Accelerator card, node status determination method and chip

Abstract

The present application discloses an accelerator card, a node state determination method and a chip, and relates to the field of artificial intelligence technology. The accelerator card includes M array-arranged lattices and M×N computing modules; each lattice includes N nodes, each node is connected to P nodes, and each computing module includes: an acquisition submodule for acquiring a preset bias value, P target weight values ​​and P initial state values; a first determination submodule for determining the probability distribution value of the first target node according to the preset bias value, P target weight values ​​and P initial state values; a second determination submodule for determining the target state value of the first target node according to the probability distribution value and the target random value. According to the embodiment of the present application, it is possible to achieve efficient calculation of the probability distribution value of the first target node, meet the requirements of efficient operation of the probability distribution value calculation on a resource-constrained hardware platform, and thus improve the efficiency of determining the target state value of the first target node.

Description

Technical Field

[0001] The present application relates to the field of artificial intelligence technology, and in particular to an accelerator card, a node status determination method, and a chip. Background Art

[0002] An accelerator card is a dedicated hardware device used to accelerate certain types of computing tasks. Compared to a general-purpose central processing unit (CPU), an accelerator card usually has more computing units and higher memory bandwidth, which can achieve higher parallel computing capabilities. The most common accelerator card is the graphics processing unit (GPU), which was originally designed for graphics rendering and was later found to be very suitable for matrix operations in deep learning. In addition to GPUs, there are other accelerator cards specifically optimized for deep learning, such as the tensor processing unit (TPU), machine learning unit (MLU), etc. These accelerator cards are specially designed in terms of computing power, power consumption, memory access mode, etc., which can greatly improve the execution efficiency of deep learning.

[0003] Probabilistic computing is a new computing model that is different from traditional deterministic computing. It uses probability distribution to represent intermediate results and uses random sampling to approximate difficult-to-calculate functions. However, traditional computing architectures are mainly used to calculate the probability distribution values ​​of nodes in dense networks, and are inefficient when processing the probability distribution values ​​of nodes in sparse networks, which in turn leads to low efficiency in determining node states.

[0004] The content of this background technology description is only for facilitating understanding of the relevant technology in this field and is not regarded as an admission of the prior art. Summary of the invention

[0005] In order to solve the above technical problems, the present application provides an accelerator card, a node status determination method and a chip. The specific solutions are as follows:

[0006] In a first aspect, an embodiment of the present application provides an accelerator card, the accelerator card comprising M array-arranged lattices and M×N computing modules;

[0007] Each lattice includes N nodes, each node is connected to P nodes, and the nodes correspond to the computing modules one by one, M, N and P are all positive integers, and P is less than or equal to M×N;

[0008] Among them, each computing module includes:

[0009] An acquisition submodule is used to acquire a preset bias value, P target weight values ​​and P initial state values, wherein the target weight value is a weight value of a node connected to a first target node, the first target node is a node corresponding to the calculation module, and the initial state value is a state value of a node connected to the first target node;

[0010] A first determination submodule, used to determine a probability distribution value of a first target node according to a preset bias value, P target weight values ​​and P initial state values;

[0011] The second determination submodule is used to determine the target state value of the first target node according to the probability distribution value and the target random value.

[0012] In some implementations of the first aspect, the first determining submodule is specifically configured to:

[0013] For each target weight value, the product of the target weight value and its corresponding initial state value is taken as the target product to obtain P target products;

[0014] In some implementations of the first aspect, the second determining submodule includes: determining the sum of the products of the preset bias value and the P targets as the probability distribution value of the first target node.

[0015] The determination unit is used to determine the target state value of the first target node according to the probability distribution value, the preset activation function and the target random value.

[0016] In some embodiments of the first aspect, the determining unit includes:

[0017] A first determining subunit, used to determine an intermediate state value corresponding to the probability distribution value according to a preset activation function;

[0018] The second determining subunit is used to determine the target state value of the first target node according to the intermediate state value and the target random value.

[0019] In some embodiments of the first aspect, the preset activation function includes at least one of a hyperbolic tangent function, a Sigmoid function, a ReLU function, a Leaky ReLU function, a Parametric ReLU function, an ELU function, a SELU function, and a Softmax function.

[0020] In some implementations of the first aspect, the target state value includes a first target state value and a second target state value, and the second determining subunit is specifically configured to:

[0021] When the intermediate state value is greater than the target random value, determining the target state value to be the first target state value;

[0022] When the intermediate state value is less than or equal to the target random value, the target state value is determined to be a second target state value.

[0023] In some embodiments of the first aspect, the computing module further comprises:

[0024] The updating submodule is used to update the initial state value of the first target node to the target state value.

[0025] In some implementations of the first aspect, the obtaining submodule is specifically used to:

[0026] When a node status update instruction is received, P target weight values ​​are obtained through a preset interface.

[0027] In a second aspect, an embodiment of the present application provides a method for determining a node state, including:

[0028] Obtain a preset bias value, P target weight values, and P initial state values, wherein the target weight value is the weight value of the node connected to the first target node, and the initial state value is the state value of the node connected to the first target node. The first target node is any one of M×N nodes, and each node is connected to P nodes respectively. M, N, and P are all positive integers, and P is less than or equal to M×N.

[0029] Determine a probability distribution value of a first target node according to a preset bias value, P target weight values, and P initial state values;

[0030] A target state value of the first target node is determined according to the probability distribution value and the target random value.

[0031] In a third aspect, an embodiment of the present application provides a field programmable gate array chip, which can be used to implement the node status determination method of the second aspect.

[0032] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0033] The accelerator card, node state determination method and chip provided in the embodiment of the present application, by setting a calculation module for each node in each lattice, can then obtain the preset bias value, P target weight values ​​and P initial state values ​​through the acquisition submodule in the calculation module, and determine the probability distribution value of the first target node according to the preset bias value, P target weight values ​​and P initial state values ​​through the first determination submodule, and then determine the target state value of the first target node according to the probability distribution value and the target random value through the second determination submodule. In this way, by designing the accelerator card that can be used for probability calculation of sparse connections, by optimizing the hardware architecture and the calculation program, it is possible to achieve efficient calculation of the probability distribution value of the first target node, meet the requirements of efficient operation of the probability distribution value calculation on a resource-constrained hardware platform, and thus improve the efficiency of determining the target state value of the first target node. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 A schematic diagram of the structure of an accelerator card provided in an embodiment of the present application;

[0036] Figure 2 A flowchart of a node status determination method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0038] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0039] Hereinafter, the terms "including", "having" and their cognates, which may be used in various embodiments of the present application, are intended only to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing items or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations of the foregoing items.

[0040] Furthermore, the terms “first”, “second”, “third”, etc. are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0041] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.

[0042] The following is an introduction to the names that may be involved in the embodiments of the present application.

[0043] Probabilistic computing is a new computing model that is different from traditional deterministic computing. It uses probability distribution to represent intermediate results and uses random sampling to approximate difficult-to-calculate functions. By introducing probability, computational errors can be tolerated, thereby achieving a balance between accuracy and efficiency. Probabilistic computing is widely used in machine learning, such as variational inference, stochastic gradient descent, and Monte Carlo sampling. These algorithms often require the generation of a large number of random numbers for sampling, integration, and other operations. Traditional hardware has limited support for such operations, and specialized probabilistic computing chips are expected to significantly speed up these operations. Figure 1 A schematic diagram of the structure of an acceleration card provided in an embodiment of the present application.

[0044] See also Figure 1 The acceleration card 10 may include M array-arranged lattices 100 and M×N computing modules 200 .

[0045] It is understandable that the acceleration card provided in the embodiment of the present application may include a sparsely connected probability calculation acceleration card, and may also include other types of acceleration cards, which are not limited here.

[0046] It should be noted that Figure 1 The values ​​of M and N are both 6 for illustration, but this is not intended to limit the present application. In actual implementation, the values ​​of M and N can be set according to actual conditions and are not limited here. For example, M is 6, N is 5, etc.

[0047] Each lattice 100 may include N nodes 110 , each node 110 is connected to P nodes 110 , and the nodes 110 correspond to the computing modules 200 one by one, M, N and P are all positive integers, and P is less than or equal to M×N.

[0048] There is a one-to-one correspondence between the nodes and the computing modules 200 , that is, each of the N nodes 110 has its own dedicated computing module 200 .

[0049] The calculation module 200 may be used to determine a target state value of the node 110 .

[0050] It should be noted that, for any two nodes 110 among the N nodes 110 , the corresponding values ​​of P may be different, and the value of P may be set according to actual conditions and is not limited here.

[0051] As an example, see Figure 1 , taking the acceleration card including a lattice 100 with six rows and six columns, each lattice 100 including four nodes 110 in the column direction and four nodes 110 in the row direction, that is, the acceleration card including 288 nodes, and the first target node being the fourth node in the column direction in the lattice of the second row and second column, that is, the node in the lower left corner, as an example, the nodes connected to the first target node include: the fourth node in the column direction in the lattice of the second row and first column, the first node, the second node, the third node and the fourth node in the row direction in the lattice of the second row and second column, and the fourth node in the column direction in the lattice of the second row and third column. At this time, the value of P corresponding to the target node is 6, that is, the connectivity is 6.

[0052] As another example, see Figure 1 , taking the acceleration card including a lattice 100 with six rows and six columns, each lattice 100 including four nodes 110 in the column direction (i.e. from top to bottom) and four nodes 110 in the row direction (i.e. from left to right), that is, the acceleration card includes 288 nodes, and the first target node is the fourth node in the column direction in the lattice of the second row and the sixth column, that is, the node in the lower left corner, as an example, the nodes connected to the first target node include: the fourth node in the column direction in the lattice of the second row and the fifth column, and the first node, the second node, the third node and the fourth node in the row direction in the lattice of the second row and the sixth column. At this time, the value of P corresponding to the target node is 5.

[0053] Wherein, each computing module 200 includes:

[0054] The acquisition submodule 210 is used to obtain a preset bias value, P target weight values ​​and P initial state values, where the target weight value is the weight value of the node connected to the first target node, the first target node is the node corresponding to the calculation module, and the initial state value is the state value of the node connected to the first target node.

[0055] For each node 110 in the N nodes, it is connected to P nodes 110 other than itself, and each of the P nodes 110 corresponds to a target weight value and an initial state value. Therefore, for each of the N nodes 110, there are P target weight values ​​and P initial state values.

[0056] Exemplarily, the preset offset value may be 10 bits of data, and the preset offset value may be set according to actual conditions and is not limited here.

[0057] Exemplarily, the target weight value may be 10-bit data.

[0058] Exemplarily, in the embodiment of the present application, the target state value may be represented as pbit.

[0059] The first determination submodule 220 is used to determine the probability distribution value of the first target node according to a preset bias value, P target weight values ​​and P initial state values.

[0060] The second determination submodule 230 is used to determine the target state value of the first target node according to the probability distribution value and the target random value.

[0061] The accelerator card provided by the present application sets a calculation module for each node in each lattice, and then can obtain the preset bias value, P target weight values ​​and P initial state values ​​through the acquisition submodule in the calculation module, and determine the probability distribution value of the first target node according to the preset bias value, P target weight values ​​and P initial state values ​​through the first determination submodule, and then determine the target state value of the first target node according to the probability distribution value and the target random value through the second determination submodule. In this way, by designing the accelerator card that can be used for probability calculation of sparse connections, by optimizing the hardware architecture and the calculation program, it is possible to achieve efficient calculation of the probability distribution value of the first target node, meet the requirements of efficient operation of the probability distribution value calculation on a resource-constrained hardware platform, and then improve the efficiency of determining the target state value of the first target node.

[0062] In some implementations, the acquisition submodule 210 may be specifically used to:

[0063] When a node status update instruction is received, P target weight values ​​are obtained through a preset interface.

[0064] The node status update instruction may be an instruction for updating the node status.

[0065] Exemplarily, the preset interface may include a PCIe (peripheral component interconnect express) interface, and may also include other interfaces except the PCIe interface, which is not limited here.

[0066] Exemplarily, a personal computer (PC) host computer sends a node status update instruction and P target weight values ​​to the acquisition submodule 210 through a PCIe interface. The acquisition submodule 210 can acquire the P target weight values ​​through the PCIe interface when receiving the node status update instruction through the PCIe interface.

[0067] Exemplarily, the preset bias value and / or initial state value may be pre-stored in the acquisition submodule 210 and may be directly called later. Alternatively, the acquisition submodule 210 may also acquire the preset bias value and / or initial state value from a PC host computer via a PCIe interface, which is not limited here.

[0068] In some implementations, the first determining submodule 220 is specifically configured to:

[0069] For each target weight value, the product of the target weight value and its corresponding initial state value is taken as the target product to obtain P target products;

[0070] The sum of the products of the preset bias value and the P targets is determined as the probability distribution value of the first target node.

[0071] The target weight value and its corresponding initial state value both correspond to the same node.

[0072] Exemplarily, the preset bias value is a, the P nodes include a first node, a second node, a third node, a fourth node, a fifth node and a sixth node, the target weight values ​​of the first node to the sixth node are b1, b2, b3, b4, b5 and b6 respectively, and the initial state values ​​of the first node to the sixth node are 1, 1, -1, 1, -1 and -1 respectively, then a+b1+b2-b3+b4-b5-b6 is determined as the probability distribution value of the first target node.

[0073] In some implementations, the second determining submodule 230 includes:

[0074] The determination unit is used to determine the target state value of the first target node according to the probability distribution value, the preset activation function and the target random value.

[0075] In some embodiments, the preset activation function may include at least one of a hyperbolic tangent function, a Sigmoid function, a ReLU function, a Leaky ReLU function, a Parametric ReLU function, an ELU function, a SELU function, and a Softmax function.

[0076] As an example, the preset activation function may include a hyperbolic tangent function tanh.

[0077] As another example, the preset activation function may include a hyperbolic tangent function and a sigmoid function.

[0078] In some embodiments, the determining unit comprises:

[0079] A first determining subunit, used to determine an intermediate state value corresponding to the probability distribution value according to a preset activation function;

[0080] The second determining subunit is used to determine the target state value of the first target node according to the intermediate state value and the target random value.

[0081] In some examples, the probability distribution value may be input into a preset activation function to calculate an intermediate state value corresponding to the probability distribution value.

[0082] In other examples, since it is difficult to determine the intermediate state value corresponding to the probability distribution value using the hyperbolic tangent function on hardware, the hyperbolic tangent function tanh(x) can be fit by a piecewise linear function, where x can represent the probability distribution value.

[0083] Exemplarily, the target random value may be a 13-bit random number.

[0084] In some implementations, the target state value includes a first target state value and a second target state value, and the second determination subunit is specifically configured to:

[0085] When the intermediate state value is greater than the target random value, determining the target state value to be the first target state value;

[0086] When the intermediate state value is less than or equal to the target random value, the target state value is determined to be a second target state value.

[0087] The first target state value may be a state that flips the current state of the first target node, and the second target state value may be a state that maintains the current state of the first target node.

[0088] Exemplarily, the initial state value of the first target node may include -1 or 1. Taking the initial state value of the first target node as -1 as an example, when the intermediate state value is greater than the target random value, the target state value is determined to be the first target state value 1; when the intermediate state value is less than the target random value, the target state value is determined to be the second target state value -1.

[0089] That is, when the intermediate state value is greater than the target random value, the initial state value of the first target node is updated; when the intermediate state value is less than the target random value, the initial state value of the first target node is maintained.

[0090] Exemplarily, the target random value may be stored in the second determination submodule 230 and may be directly called later.

[0091] It should be noted that any number of the N×M computing modules 200 corresponding to the N×M nodes can determine the target state value of the node simultaneously, or can determine the target state value of each node in sequence according to a preset order, which is not limited here.

[0092] In some examples, the computing module 200 may also include a storage module;

[0093] The storage module can be used to store the target state value of the first target node.

[0094] In some examples, the acquisition submodule 210 may also transmit the target state value of the first target node to the host computer through a preset interface.

[0095] In some embodiments, the calculation module may further include:

[0096] The updating submodule is used to update the initial state value of the first target node to the target state value.

[0097] In this way, the updated initial state value of the first target node can be used to subsequently determine the target state values ​​of other nodes except the first target node, which can improve the accuracy of determining the target state values ​​of other nodes except the first target node.

[0098] In an embodiment of the present application, first, any one of the N×M nodes is taken as the first target node, and the target state value of the first target node is determined based on the P initial state values ​​corresponding one-to-one to the P nodes connected to the first target node, and then the initial state value of the first target node is updated to the target state value; then, the other nodes among the N×M nodes except the first target node are taken as the first target nodes, and the above process is repeated until the target state values ​​corresponding one-to-one to the N×M nodes are determined.

[0099] For example, Figure 1As shown, taking the first target node as the first node in the column direction of the first row and first column lattice as an example, the target state value of the first target node is determined according to the five initial state values ​​corresponding to the first node, the second node, the third node and the fourth node in the row direction of the first row and first column lattice connected to the first target node, and the first node in the column direction of the first row and second column lattice, and then the initial state value of the first target node is updated to the target state value; then taking the first node in the row direction of the first row and first column lattice as the first target node, the target state value of the first target node is determined according to the updated initial state value of the first node in the column direction of the first row and first column lattice, the second node, the third node and the fourth node in the row direction of the first row and first column lattice connected to the first target node, and the first node in the row direction of the second row and first column lattice, and then the initial state value of the first target node is updated to the target state value, and so on, until the target state values ​​of N×M nodes corresponding to each other are determined.

[0100] The following describes the usage principle of the acceleration card provided in the embodiment of the present application in conjunction with specific application scenarios.

[0101] The principle of using the accelerator card includes the following steps:

[0102] 1. PCIe sends data

[0103] The host computer sends a node status update instruction, P target weight values ​​and P initial status values ​​to the acquisition submodule 210 through the PCIe interface.

[0104] 2. Asynchronous First In, First Out (FIFO) Cache

[0105] Write data: The write clock domain writes the data into the FIFO and updates the write pointer.

[0106] Read data: The read clock domain reads data from the FIFO and updates the read pointer.

[0107] State management: The write clock domain and the read clock domain maintain their own read and write pointers respectively, and synchronize the empty and full state signals through the Gray code counter and synchronizer.

[0108] Empty and full judgment: The empty and full status of the FIFO is judged by comparing the synchronized read and write pointers, thereby controlling the write and read operations.

[0109] 3. Data is stored in memory

[0110] The temperature sequence and weights are stored in the computing core cache (i.e., computing module).

[0111] The weight (ie, the target weight value) is stored in the dynamic random access memory (DRAM).

[0112] 4. Calculation of pbit (i.e. target state value)

[0113] When a new node state is generated, the weight value of the node is read through the Double Data Rate 3 (DDR3) interface according to the new sbit value (ie, the target state value) to update the target weight values ​​of other nodes connected to the node.

[0114] The node status data is stored in the register and after the entire temperature sequence calculation is completed, it is transmitted to the host computer through the PCIe interface as the calculation result.

[0115] 5. pbit (i.e. target status value) is transmitted back to the host computer

[0116] The new pbit value is stored in the pbit register of the accelerator card computing module and transmitted back to the host computer through the PCIe interface.

[0117] It is understandable that the workflow of the accelerator card may include: first, the host computer sends a node state update instruction and P target weight values ​​to the accelerator card; second, the accelerator card receives the node state update instruction, P target weight values ​​and P initial state values, and caches the P target weight values ​​and P initial state values; then, the accelerator card starts to update the target state values ​​of N×M nodes, for example, in accordance with a preset order, the target state values ​​of the first node to the last node are updated in sequence, and this update process does not require other instructions until the accelerator card completes the update of the target state values ​​of the N nodes, and then notifies the host computer to receive the target state values ​​of the N×M nodes one by one, and transmits the target state values ​​of the N×M nodes one by one to the host computer. It can be seen that in the entire node update process, the entire accelerator card can be considered as an independent chip, and no instructions are required to control the operation of the accelerator card. Among them, the target state values ​​of the N×M nodes one by one can be transmitted to the host computer in the form of a target state value sequence, and the target state value sequence may include the target state values ​​of the N×M nodes one by one. Based on the same inventive concept, an embodiment of the present application also provides a node status determination method. The node status determination method provided by the embodiment of the present application is described below in conjunction with the accompanying drawings.

[0118] The node status determination method provided in the embodiment of the present application can be executed by an accelerator card and an electronic device, etc.

[0119] like Figure 2 As shown, the node status determination method provided in the embodiment of the present application may include S210 to S230.

[0120] S210, obtain a preset bias value, P target weight values ​​and P initial state values, the target weight value is the weight value of the node connected to the first target node, the initial state value is the state value of the node connected to the first target node, the first target node is any one of M×N nodes, each node is connected to P nodes respectively, M, N and P are all positive integers, and P is less than or equal to M×N.

[0121] S220. Determine a probability distribution value of a first target node according to a preset bias value, P target weight values, and P initial state values.

[0122] S230. Determine a target state value of the first target node according to the probability distribution value and the target random value.

[0123] According to the node state determination method provided by the embodiment of the present application, a calculation module is set for each node in each lattice, and then the preset bias value, P target weight values ​​and P initial state values ​​can be obtained through the acquisition submodule in the calculation module, and the probability distribution value of the first target node is determined according to the preset bias value, P target weight values ​​and P initial state values ​​through the first determination submodule, and then the target state value of the first target node is determined according to the probability distribution value and the target random value through the second determination submodule. In this way, by designing the accelerator card that can be used for probability calculation of sparse connections, by optimizing the hardware architecture and the calculation program, it is possible to achieve efficient calculation of the probability distribution value of the first target node, meet the requirements of efficient operation of the probability distribution value calculation on a resource-constrained hardware platform, and thus improve the efficiency of determining the target state value of the first target node.

[0124] In some implementations, determining the probability distribution value of the first target node according to a preset bias value, P target weight values, and P initial state values ​​may include:

[0125] For each target weight value, the product of the target weight value and its corresponding initial state value is taken as the target product to obtain P target products;

[0126] The sum of the products of the preset bias value and the P targets is determined as the probability distribution value of the first target node.

[0127] In some implementations, determining the target state value of the first target node according to the probability distribution value and the target random value may include:

[0128] A target state value of the first target node is determined according to the probability distribution value, the preset activation function and the target random value.

[0129] In some implementations, determining the target state value of the first target node according to the probability distribution value, the preset activation function, and the target random value may include:

[0130] According to the preset activation function, determine the intermediate state value corresponding to the probability distribution value;

[0131] A target state value of the first target node is determined according to the intermediate state value and the target random value.

[0132] In some embodiments, the preset activation function includes at least one of a hyperbolic tangent function, a Sigmoid function, a ReLU function, a Leaky ReLU function, a Parametric ReLU function, an ELU function, a SELU function, and a Softmax function.

[0133] In some implementations, the target state value includes a first target state value and a second target state value, and determining the target state value of the first target node according to the intermediate state value and the target random value includes:

[0134] When the intermediate state value is greater than the target random value, determining the target state value to be the first target state value;

[0135] When the intermediate state value is less than or equal to the target random value, the target state value is determined to be a second target state value.

[0136] In some implementations, obtaining P target weight values ​​may include:

[0137] When a node status update instruction is received, P target weight values ​​are obtained through the PCIe interface.

[0138] In some implementations, after determining the target state value of the first target node according to the probability distribution value and the target random value, the method may further include:

[0139] Update the initial state value of the first target node to the target state value;

[0140] Update the first target node to any node among the N nodes except the first target node;

[0141] Jump to the step of "obtaining a preset bias value, P target weight values, and P initial state values" until the target state values ​​corresponding to the N×M nodes are obtained.

[0142] For ease of explanation, "updating the initial state value of the first target node to the target state value" is taken as S240, and "updating the first target node to any node among the N×M nodes except the first target node" is taken as S250. That is to say, S210 to S250 are executed in a loop until the target state values ​​of the N×M nodes corresponding one to one are obtained.

[0143] In some implementations, obtaining P target weight values ​​may include:

[0144] When receiving the node status update instruction, P target weight values ​​are obtained through the preset interface. The node status determination method provided in the embodiment of the present application can be implemented Figure 1 The functions of the accelerator card provided and its corresponding technical effects can be achieved. For the sake of brevity, they will not be described in detail here.

[0145] In addition, in combination with the node status determination method in the above embodiment, an embodiment of the present application may provide a field programmable gate array chip, which is used to implement the node status determination method in the above embodiment.

[0146] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0147] The above is only a specific implementation method of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the system, module and unit described above can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application. The methods, programs, systems, devices, etc. in the embodiments of the present application can be executed or implemented in a single or multiple networked computers, and can also be practiced in a distributed computing environment. In the embodiments of this specification, in these distributed computing environments, tasks can be performed by remote processing devices connected through a communication network.

[0148] The specific implementation process of the provided electronic device and computer-readable storage medium can refer to the specific implementation process of the acceleration card provided in the above embodiment, which will not be described in detail here.

[0149] Those skilled in the art should understand that the embodiments of the present specification can be provided as methods, systems or computer program products. Therefore, those skilled in the art can imagine that the implementation of the functional modules / units or controllers and related method steps described in the above embodiments can be implemented in software, hardware or a combination of software / hardware.

[0150] Unless explicitly stated, the actions or steps of the methods, programs, and embodiments of the present application do not have to be performed in a specific order and can still achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0151] In this article, multiple embodiments of the present application are described, but for the sake of simplicity, the description of each embodiment is not exhaustive, and the same or similar features or parts between the various embodiments may be omitted. In this article, "one embodiment", "some embodiments", "example", "specific example", or "some examples" are intended to be applicable to at least one embodiment or example according to the present application, rather than all embodiments. The above terms do not necessarily mean to refer to the same embodiment or example. In the absence of mutual contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples.

[0152] The exemplary systems and methods of the present application have been specifically shown and described with reference to the above embodiments, which are merely examples of the best modes for implementing the present systems and methods. It will be appreciated by those skilled in the art that various changes may be made to the embodiments of the systems and methods described herein when implementing the present systems and / or methods without departing from the spirit and scope of the present application as defined in the appended claims.

Claims

1. An accelerator card, characterized in that: The acceleration card includes M array-arranged lattices and M×N computing modules; Each of the lattices includes N nodes, each of the nodes is connected to P nodes respectively, and the nodes correspond to the computing modules one by one, M, N and P are all positive integers, and P is less than or equal to M×N; Wherein, each of the computing modules comprises: an acquisition submodule, used to acquire a preset bias value, P target weight values, and P initial state values, wherein the target weight value is a weight value of a node connected to a first target node, the first target node is a node corresponding to the calculation module, and the initial state value is a state value of a node connected to the first target node; A first determination submodule, used to determine a probability distribution value of the first target node according to the preset bias value, the P target weight values ​​and the P initial state values; The second determination submodule is used to determine the target state value of the first target node according to the probability distribution value and the target random value.

2. The accelerator card according to claim 1, characterized in that: The first determining submodule is specifically used for: For each of the target weight values, taking the product of the target weight value and its corresponding initial state value as the target product to obtain P target products; The sum of the products of the preset bias value and the P targets is determined as the probability distribution value of the first target node.

3. The accelerator card according to claim 1, characterized in that: The second determining submodule includes: A determination unit is used to determine a target state value of the first target node according to the probability distribution value, a preset activation function and a target random value.

4. The accelerator card according to claim 3, characterized in that: The determining unit comprises: A first determining subunit, configured to determine an intermediate state value corresponding to the probability distribution value according to the preset activation function; The second determining subunit is used to determine the target state value of the first target node according to the intermediate state value and the target random value.

5. The accelerator card according to claim 4, characterized in that: The preset activation function includes at least one of a hyperbolic tangent function, a Sigmoid function, a ReLU function, a Leaky ReLU function, a Parametric ReLU function, an ELU function, a SELU function, and a Softmax function.

6. The accelerator card according to claim 5, characterized in that: The target state value includes a first target state value and a second target state value, and the second determining subunit is specifically configured to: When the intermediate state value is greater than the target random value, determining the target state value to be the first target state value; When the intermediate state value is less than or equal to the target random value, the target state value is determined to be a second target state value.

7. The accelerator card according to claim 1, characterized in that: The calculation module also includes: An updating submodule is used to update the initial state value of the first target node to the target state value.

8. The accelerator card according to claim 1, characterized in that: The acquisition submodule is specifically used for: When a node status update instruction is received, P target weight values ​​are obtained through a preset interface.

9. A method for determining node status, characterized in that: include: Obtain a preset bias value, P target weight values, and P initial state values, wherein the target weight value is a weight value of a node connected to a first target node, and the initial state value is a state value of a node connected to the first target node, wherein the first target node is any one of M×N nodes, and each of the nodes is connected to P nodes, respectively, and M, N, and P are all positive integers, and P is less than or equal to M×N; Determine a probability distribution value of the first target node according to the preset bias value, the P target weight values ​​and the P initial state values; A target state value of the first target node is determined according to the probability distribution value and the target random value.

10. A field programmable gate array chip, characterized in that: The field programmable gate array chip is used to implement the method for determining the node status as described in claim 9.

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