A semiconductor structure and a method of fabricating the same

Abstract

The embodiments of the present disclosure disclose a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate, the substrate comprises active pillars arranged in a first direction and a second direction, the active pillars are U-shaped active pillars having two branch parts, the first direction and the second direction are parallel to the plane of the substrate, each active pillar comprises a first source / drain region at a first end of the active pillar, a second source / drain region at a second end of the active pillar, the first end and the second end are two opposite ends of the active pillar in a third direction, the third direction is perpendicular to the plane of the substrate, and a channel region between the first source / drain region and the second source / drain region, wherein the first source / drain region, the second source / drain region and the channel region have the same conductivity type.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor, and in particular, to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] With the development of the integration density of dynamic memory towards higher direction, in addition to the research on the arrangement mode of transistors in the dynamic memory array structure and how to reduce the size of a single functional device in the dynamic memory array structure, the influence of the small-size functional device on the overall electrical performance of the semiconductor structure also needs to be considered. At present, in the existing dynamic memory, the integration density of the transistor is not high, and the leakage is serious. SUMMARY

[0003] Therefore, the present disclosure provides a semiconductor structure and a preparation method thereof.

[0004] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising:

[0005] a substrate, the substrate comprising active pillars arranged in an array along a first direction and a second direction, the active pillars being U-shaped active pillars having two branch portions, the first direction and the second direction being parallel to the plane of the substrate; each of the active pillars comprising:

[0006] a first source / drain region located at a first end of the active pillar;

[0007] a second source / drain region located at a second end of the active pillar; the first end and the second end being two ends of the active pillar opposite in a third direction, the third direction being perpendicular to the plane of the substrate;

[0008] a channel region located between the first source / drain region and the second source / drain region;

[0009] wherein the first source / drain region, the second source / drain region and the channel region are of the same conductivity type.

[0010] In some embodiments, further comprising:

[0011] a plurality of word lines extending along the first direction, each of the word lines being located on a side of the channel region away from the active pillar and corresponding to the channel regions of a row of the active pillars arranged along the first direction.

[0012] In some embodiments, further comprising:

[0013] a plurality of bit lines extending along the second direction, each of the bit lines being located below the active pillar and connected to the first source / drain region or the second source / drain region of a row of the active pillars arranged along the second direction.

[0014] In some embodiments, further comprising:

[0015] a dielectric layer wrapping the U-shaped active pillar and filling a U-shaped groove between two branch portions of the U-shaped active pillar.

[0016] In some embodiments, a portion of the dielectric layer within the U-shaped groove has a void.

[0017] In some embodiments, a concentration of dopant ions of the first source / drain region and the second source / drain region is greater than a concentration of dopant ions of the channel region.

[0018] In some embodiments, the two branch portions of the U-shaped active pillar are a first active pillar and a second active pillar, and the first active pillar and the second active pillar share one of the first source / drain region or the second source / drain region.

[0019] According to a second aspect of embodiments of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising:

[0020] providing a substrate;

[0021] forming active pillars arranged in an array along a first direction and a second direction on the substrate, the active pillars being U-shaped active pillars having two branch portions, the first direction and the second direction being parallel to a plane of the substrate;

[0022] forming the active pillars, comprising:

[0023] forming a first source / drain region at a first end of the active pillar;

[0024] forming a second source / drain region at a second end of the active pillar, the first end and the second end being two ends of the active pillar opposite in a third direction, the third direction being perpendicular to the plane of the substrate;

[0025] forming a channel region between the first source / drain region and the second source / drain region;

[0026] wherein the first source / drain region, the second source / drain region, and the channel region are of the same conductivity type.

[0027] In some embodiments, further comprising:

[0028] after forming the active pillars, forming a plurality of word lines extending along the first direction, each of the word lines being located on a side of the channel region away from the active pillar and corresponding to the channel regions of a row of the active pillars arranged along the first direction.

[0029] In some embodiments, further comprising:

[0030] forming the word lines, flipping and thinning the substrate until the active pillars are exposed near one end of the substrate;

[0031] forming bit lines extending along the second direction on the end of the active pillars near the substrate, each of the bit lines being connected to the first source / drain region or the second source / drain region of a row of the active pillars arranged along the second direction.

[0032] In some embodiments, the active pillars are formed by:

[0033] forming an initial dielectric layer on the substrate;

[0034] etching the initial dielectric layer to form a plurality of first trenches arranged along the first direction and the second direction;

[0035] forming initial active pillars in the first trenches;

[0036] doping the initial active pillars to form initial first source / drain regions, initial second source / drain regions, and initial channel regions;

[0037] etching the doped initial active pillars to form the U-shaped active pillars having two branch portions.

[0038] In some embodiments, the doping the initial active pillars comprises:

[0039] performing a first doping process on an end of the initial active pillars near the substrate;

[0040] performing a second doping process on a middle region of the initial active pillars;

[0041] performing a third doping process on an end of the initial active pillars away from the substrate;

[0042] performing a fourth doping process on the end of the initial active pillars away from the substrate; wherein,

[0043] the doping ions of the first doping process, the second doping process, and the third doping process comprise phosphorus, and the doping ions of the fourth doping process comprise arsenic.

[0044] In some embodiments, the first doping process injects ions with an energy of 150KeV-190KeV and a dose of 6E13 atoms per square centimeter-8E13 atoms per square centimeter;

[0045] the second doping process injects ions with an energy of 60KeV-90KeV and a dose of 2E13 atoms per square centimeter-7E13 atoms per square centimeter;

[0046] The ion energy of the third doping process is 15KeV-25KeV, and the ion dose is 7E13 atoms per square centimeter-1E14 atoms per square centimeter;

[0047] The ion energy of the fourth doping process is 30KeV-45KeV, and the ion dose is 2E13 atoms per square centimeter-7E13 atoms per square centimeter.

[0048] In some embodiments, further comprising:

[0049] A dielectric layer is formed to wrap the U-shaped active pillar and fill the U-shaped groove between the two branches of the U-shaped active pillar.

[0050] In some embodiments, the part of the dielectric layer in the U-shaped groove has a void.

[0051] In some embodiments, the two branches of the U-shaped active pillar are a first active pillar and a second active pillar, and the first active pillar and the second active pillar share one of the first source / drain region or the second source / drain region.

[0052] In the embodiments of the present disclosure, the first source / drain region, the second source / drain region, and the channel region extend in the direction perpendicular to the plane of the substrate, so that the area occupied by a single transistor in the horizontal direction is reduced, and the active pillar has two branches, so that two transistors can be formed, the number of transistors that can be arranged in a unit area is increased, and the density of transistors in the transistor array is improved; at the same time, the first source / drain region, the second source / drain region, and the channel region have the same conductivity type, so that the structure formed is a junctionless structure, the doping process is simpler, and the leakage current is effectively reduced. BRIEF DESCRIPTION OF DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0054] Figure 1 A cross-sectional schematic diagram of a semiconductor structure provided by the embodiments of the present disclosure;

[0055] Figure 2 A perspective view of a semiconductor structure provided by the embodiments of the present disclosure;

[0056] Figure 3 A structure schematic diagram after removing the dielectric layer in the embodiments of the present disclosure; Figure 2

[0057] Figure 4 ​a concentration distribution map of the doping ions of the active pillar;

[0058] Figure 5 a structural schematic diagram of the active pillar provided by the embodiment of the present disclosure;

[0059] Figure 6 a top view of the semiconductor structure provided by the embodiment of the present disclosure;

[0060] Figure 7 a flowchart of the preparation method of the semiconductor structure provided by the embodiment of the present disclosure;

[0061] Figures 8a to 15c a structural schematic diagram of the semiconductor structure in the preparation process provided by the embodiment of the present disclosure.

[0062] Explanation of reference signs:

[0063] 10 - substrate;

[0064] 20 - active pillar; 21 - first source / drain region; 22 - channel region; 23 - second source / drain region; 24 - U-shaped groove; 201 - first active pillar; 202 - second active pillar; 200 - initial active pillar; 210 - initial first source / drain region; 220 - initial channel region; 230 - initial second source / drain region;

[0065] 30 - word line; 300 - initial word line material layer;

[0066] 40 - bit line; 41 - bit line contact plug;

[0067] 50 - dielectric layer; 500 - initial dielectric layer; 501 - void;

[0068] 60 - capacitor contact plug. DETAILED DESCRIPTION

[0069] Exemplary embodiments of the present disclosure will be described in detail with reference to the drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be completely conveyed to those skilled in the art.

[0070] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present disclosure. However, it should be apparent to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other instances, some well-known features are not described in detail in order to avoid obscuring the present disclosure. That is, all features of practical embodiments are not described here, and well-known functions and structures are not described in detail.

[0071] In the drawings, the size of layers, regions, elements, and the like can be exaggerated for clarity. Like reference numbers in different drawings can indicate like elements.

[0072] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0073] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or

[0074] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0075] For a thorough understanding of the present disclosure, detailed steps and detailed structures will be presented in the following description in order to illustrate the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail as follows, however, in addition to these detailed descriptions, the present disclosure can also have other implementation manners.

[0076] Based on this, the semiconductor structure provided by the embodiments of the present disclosure, Figure 1 The cross-sectional schematic diagram of the semiconductor structure provided by the embodiments of the present disclosure, Figure 2 The perspective view of the semiconductor structure provided by the embodiments of the present disclosure, Figure 3 The cross-sectional schematic diagram of the semiconductor structure provided by the embodiments of the present disclosure, Figure 2 The cross-sectional schematic diagram of the semiconductor structure provided by the embodiments of the present disclosure.

[0077] Referring to Figures 1 to 3 , the semiconductor structure comprises:

[0078] The substrate (not shown in the figure) comprises active pillars 20 arranged in an array along a first direction and a second direction, the active pillars 20 are U-shaped active pillars having two branch parts, the first direction and the second direction are parallel to the plane of the substrate; each active pillar 20 comprises: Figures 1 to 3 A first source / drain region 21 located at a first end of the active pillar 20;

[0079] A second source / drain region 23 located at a second end of the active pillar 20; the first end and the second end are two ends of the active pillar 20 opposite in a third direction, the third direction is perpendicular to the plane of the substrate;

[0080] A channel region 22 located between the first source / drain region 21 and the second source / drain region 23;

[0081] Wherein, the first source / drain region 21, the second source / drain region 23 and the channel region 22 have the same conductivity type.

[0082] In the embodiments of the present disclosure, the first source / drain region, the second source / drain region and the channel region extend in the direction perpendicular to the plane of the substrate, so that the area occupied by a single transistor in the horizontal direction is reduced, and the active pillar has two branches, so that two transistors can be formed, the number of transistors that can be arranged in a unit area is increased, and the density of transistors in the transistor array is improved; at the same time, the first source / drain region, the second source / drain region and the channel region have the same conductivity type, so that the structure formed is a junctionless structure, the doping process is simpler, and the leakage current is effectively reduced.

[0083]

[0084] ​In an embodiment, the substrate can be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate, or a GOI (Germanium On Insulator) substrate, etc., and can also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), and can also be a stacked structure, such as Si / SiGe, etc., and can also be other epitaxial structures, such as SGOI (Silicon Germanium On Insulator), etc.

[0085] In an embodiment, the included angle between the first direction and the second direction ranges from 0 to 90 degrees. In this embodiment, the included angle between the first direction and the second direction is 90 degrees, i.e., the first direction is perpendicular to the second direction.

[0086] In an embodiment, the active pillar 20 includes a first source / drain region 21, a channel region 22, and a second source / drain region 23, wherein the first source / drain region 21 and the second source / drain region 23 are located at opposite ends of the active pillar 20 in the third direction, and the channel region 22 is located between the first source / drain region 21 and the second source / drain region 23, i.e., at a middle position of the active pillar 20.

[0087] Specifically, as shown in FIG. 1, in the embodiment of the present disclosure, the first end is an end of the active pillar 20 close to the substrate, and the second end is an end of the active pillar 20 away from the substrate. Figure 1

[0088] In other embodiments, the first end can be an end of the active pillar away from the substrate, and the second end can be an end of the active pillar close to the substrate.

[0089] In some embodiments, the first source / drain region 21 can be a source region, and the second source / drain region 23 can be a drain region. In this embodiment, the source region is located at the first end of the active pillar, and the drain region is located at the second end of the active pillar.

[0090] In other embodiments, the first source / drain region 21 can be a drain region, and the second source / drain region 23 can be a source region. In this embodiment, the drain region is located at the first end of the active pillar, and the source region is located at the second end of the active pillar.

[0091] In an embodiment, the first source / drain region 21, the second source / drain region 23, and the channel region 22 are of N-type or P-type conductivity. In the embodiment of the present disclosure, the conductivity is of N-type, wherein the doping ions of the first source / drain region 21 and the channel region 22 are phosphorus, and the doping ions of the second source / drain region 23 are phosphorus and arsenic.

[0092] In an embodiment, the concentration of the doping ions of the first source / drain region 21 and the second source / drain region 23 is greater than the concentration of the doping ions of the channel region 22.​

[0093] The higher concentration of doped ions in the first source / drain region 21 and the second source / drain region 23 reduces contact resistance.

[0094] Figure 4 This is a concentration distribution diagram of doped ions in an active column. It should be explained that Bottom S / D in the diagram represents the source / drain region at the bottom of the active column, i.e., the first source / drain region; Channel represents the channel region; and Top S / D represents the source / drain region at the top of the active column, i.e., the second source / drain region. As represents the arsenic distribution line, P represents the phosphorus distribution line, and NetActive represents the net doping distribution line.

[0095] like Figure 4 As shown, arsenic (As) is mainly distributed in the top source / drain region of the active column, which can reduce contact resistance. Phosphorus (P) is distributed in the top source / drain region, channel region, and bottom source / drain region of the active column. Because the concentration of arsenic in the top source / drain region is insufficient, a high dose of phosphorus needs to be injected in the top source / drain region to reduce contact resistance.

[0096] In one embodiment, such as Figure 1 As shown, the two branches of the U-shaped active column 20 are the first active column 201 and the second active column 202. The first active column 201 and the second active column 202 share a first source / drain region 21 or a second source / drain region 23.

[0097] In this embodiment, the first end is the end of the active pillar closest to the substrate, so the first active pillar 201 and the second active pillar 202 share a first source / drain region 21. Specifically, when the first source / drain region 21 is a source region, the first active pillar 201 and the second active pillar 202 share a source region; when the first source / drain region 21 is a drain region, the first active pillar 201 and the second active pillar 202 share a drain region.

[0098] In the embodiments of this disclosure, the transistors share a single source or drain region, thereby reducing the space occupied by the transistors and improving the integration density.

[0099] In some other embodiments, the first active post and the second active post may also share a second source / drain region.

[0100] Figure 5 This is a schematic diagram of the structure of an active column provided in an embodiment of this disclosure.

[0101] like Figure 5 As shown, the height of the first source / drain region 21 of the active column is h1, the height of the channel region 22 is h2, the height of the second source / drain region 23 is h3, and the height of the U-shaped groove 24 of the active column is h4.

[0102] In the embodiment, the height h1 of the first source / drain region 21 is 60 nm, the height h2 of the channel region 22 is 90 nm, the height h3 of the second source / drain region 23 is 100 nm, and the height h4 of the U-shaped groove 24 is 160 nm.

[0103] In an embodiment, the semiconductor structure further comprises a plurality of word lines 30 extending along the first direction, each of the word lines 30 is located at a side of the channel region 22 away from the active pillar 20, and corresponds to the channel region 22 of a row of the active pillars 20 arranged along the first direction.

[0104] Specifically, the word line 30 is located at a side of the channel region 22 away from the U-shaped groove 24.

[0105] The material of the word line 30 includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof. In the embodiment of the present disclosure, the material of the word line 30 can be tungsten.

[0106] In an embodiment, the semiconductor structure further comprises a plurality of bit lines 40 extending along the second direction, each of the bit lines 40 is located below the active pillar 20, and is connected to the first source / drain region 21 or the second source / drain region 23 of a row of the active pillars 20 arranged along the second direction.

[0107] Specifically, in some embodiments, when the first source / drain region 21 is located at an end of the active pillar 20 close to the substrate, the bit line 40 is connected to the first source / drain region 21.

[0108] In other embodiments, when the second source / drain region 23 is located at an end of the active pillar 20 close to the substrate, the bit line 40 is connected to the second source / drain region 23.

[0109] The material of the bit line 40 includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof. In the embodiment of the present disclosure, the material of the bit line 40 can be tungsten.

[0110] In an embodiment, the semiconductor structure further comprises a bit line contact plug 41 located between the active pillar 20 and the bit line 40.

[0111] In the embodiment, the bit line is electrically connected to the first source / drain region or the second source / drain region through the bit line contact plug.

[0112] The material of the bit line contact plug 41 includes, but is not limited to, metal silicide.

[0113] In an embodiment, the semiconductor structure further comprises a dielectric layer 50 wrapping the U-shaped active pillar 20 and filling the U-shaped groove 24 between the two branch portions of the U-shaped active pillar 20.

[0114] The active pillars and the two branch portions of the active pillars are insulated by the dielectric layer, so that crosstalk between the transistors and short circuit problems can be avoided.

[0115] The material of the dielectric layer 50 includes, but is not limited to, oxide, nitride, metal oxide, and oxynitride, etc. In the embodiment of the present disclosure, the material of the dielectric layer 50 can be silicon dioxide.

[0116] The portion of the dielectric layer 50 in the U-shaped groove 24 has a gap 501.

[0117] The dielectric layer in the U-shaped groove has a gap, so that the parasitic capacitance can be reduced.

[0118] Referring to Figure 1 , the semiconductor structure further includes a gate oxide layer 51 located between the active pillar 20 and the word line 30, which provides insulation between the active pillar and the word line, and avoids crosstalk between the active pillar and the word line.

[0119] In an embodiment, the material of the gate oxide layer 51 can be the same as the material of the dielectric layer 50,

[0120] The thickness of the gate oxide layer 51 is 5.5 nm.

[0121] In an embodiment, the semiconductor structure further includes a capacitor contact plug 60 located on the active pillar 20. The capacitor contact plug can be used to electrically connect the active pillar and a capacitor (not shown).

[0122] Specifically, in some embodiments, when the first source / drain region 21 is located at the end of the active pillar 20 away from the substrate, the capacitor contact plug 60 is electrically connected to the first source / drain region 21.

[0123] In other embodiments, when the second source / drain region 23 is located at the end of the active pillar 20 away from the substrate, the capacitor contact plug 60 is electrically connected to the second source / drain region 23.

[0124] Figure 6 A top view of the semiconductor structure provided in the embodiment of the present disclosure.

[0125] As shown in Figure 6 , the width of the active pillar 20 along the first direction is h5; the distance between the word lines 30 corresponding to the two channel regions of the same active pillar 20 is h6; the distance between the U-shaped grooves of the two adjacent active pillars 20 along the second direction is h7; the distance between the two adjacent bit lines is h8; the distance between the word lines 30 corresponding to the opposite channel regions of the two adjacent active pillars 20 is h9; the word line 30 includes a protruding portion located between the adjacent active pillars 20 arranged along the first direction, and the width of the protruding portion along the second direction is h10.

[0126] Specifically, in the embodiment, the width h5 of the active pillar 20 along the first direction is 20 nm; the distance h6 between the word lines 30 corresponding to the two channel regions of the same active pillar 20 is 35 nm; the distance h7 between the U-shaped grooves of two adjacent active pillars 20 along the second direction is twice the word line pitch, that is, 70 nm; the distance h8 between the two adjacent bit lines is 35 nm; the distance h9 between the word lines 30 corresponding to the opposite channel regions of the two adjacent active pillars 20 is 7 nm; and the width h10 of the protruding part of the word line 30 along the second direction is 5 nm.

[0127] The structural size provided by the embodiment of the present disclosure is close to that of a 1C node storage unit. The word line pitch (WL pitch) of the 1C node storage unit is 33.3 nm, the bit line pitch (BL pitch) is 38.5 nm, and the area of the storage unit is 1282 nm 2 . The word line pitch of the structure provided by the embodiment of the present disclosure is 35 nm, the bit line pitch is 35 nm, and the area is 1225 nm 2 .

[0128] In addition, the medium layer in the embodiment is a shallow trench isolation structure, and the included angle between the shallow trench isolation structure and the substrate plane is 89.5°.

[0129] In the embodiment of the present disclosure, the semiconductor structure is simulated by TCAD, and the performance of the transistor is calculated. The on-state current Ion is 5.6 μA, the leakage current Ioff is less than 0.1 fA, the on / off ratio is in the range of 11-12 levels, the subthreshold swing (SS) is less than 80, and the voltage Vt is 0.2 V. The leakage and switching ratio of the semiconductor structure provided by the embodiment of the present disclosure meets the requirements of the selection transistor of the 1T1C DRAM structure.

[0130] The embodiment of the present disclosure further provides a preparation method of a semiconductor structure. For details, please refer to the accompanying Figure 7 As shown in the figure, the method comprises the following steps:

[0131] Step 701: providing a substrate;

[0132] Step 702: forming active pillars arranged in an array along a first direction and a second direction on the substrate, the active pillars being U-shaped active pillars having two branch parts, the first direction and the second direction being parallel to the plane of the substrate;

[0133] The active pillars are formed, comprising:

[0134] forming a first source / drain region at the first end of the active pillar;

[0135] a second source / drain region is formed at a second end of the active pillar; the first end and the second end are two ends of the active pillar opposite in a third direction, and the third direction is perpendicular to the plane of the substrate;

[0136] a channel region is formed between the first source / drain region and the second source / drain region;

[0137] wherein the first source / drain region, the second source / drain region and the channel region are of the same conductivity type.

[0138] The preparation method of the semiconductor structure provided by the embodiments of the present disclosure will be further described in detail below in combination with specific embodiments.

[0139] Figures 8a to 15c The structure schematic diagram of the semiconductor structure provided by the embodiments of the present disclosure in the preparation process. It should be noted that, Figure 8a 、 Figure 9a 、 Figure 12a and Figure 15a are perspective views of the semiconductor structure in the preparation process, Figure 8b 、 Figure 9b 、 Figure 12b and Figure 15b are structure schematic diagrams after removing the dielectric layer in Figure 8a 、 Figure 9a 、 Figure 12a and Figure 15a , Figure 8c 、 Figure 9c 、 Figure 12c and Figure 15c are cross-sectional schematic diagrams of Figure 8a 、 Figure 9a 、 Figure 12a and Figure 15a .

[0140] First, referring to Figures 8a to 8c , a step 701 is performed to provide a substrate 10.

[0141] In an embodiment, the substrate 10 can be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate, etc., and can also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), and can also be a laminated structure, such as Si / SiGe, etc., and can also be other epitaxial structures, such as SGOI (Silicon Germanium On Insulator), etc.

[0142] Next, referring to Figures 8a to 9cStep 702 is executed, forming active pillars 20 arranged in an array along a first direction and a second direction on the substrate 10. The active pillars 20 are U-shaped active pillars with two branches, and the first direction and the second direction are parallel to the plane of the substrate 10. Forming the active pillars 20 includes: forming a first source / drain region 21 at a first end of the active pillar 20; forming a second source / drain region 23 at a second end of the active pillar 20; the first end and the second end are the two ends of the active pillar 20 facing each other in a third direction, and the third direction is perpendicular to the plane of the substrate 10; forming a channel region 22 between the first source / drain region 21 and the second source / drain region 23; wherein the first source / drain region 21, the second source / drain region 23 and the channel region 22 have the same conductivity type.

[0143] In one embodiment, forming an active pillar 20 includes:

[0144] An initial dielectric layer 500 is formed on the substrate 10;

[0145] The initial dielectric layer 500 is etched to form multiple first trenches (not shown) arranged along the first and second directions;

[0146] An initial active column 200 is formed in the first trench;

[0147] The initial active pillar 200 is doped to form the initial first source / drain region 210, the initial second source / drain region 230 and the initial channel region 220.

[0148] The initial active pillar 200 after doping is etched to form a U-shaped active pillar 20 with two branches.

[0149] In one embodiment, the angle between the first direction and the second direction ranges from 0° to 90°. In this embodiment, the angle between the first direction and the second direction is 90°, that is, the first direction is perpendicular to the second direction.

[0150] Specifically, a mask layer (not shown) can be grown on the upper surface of the initial dielectric layer 500. This mask layer is then patterned to display the first trench pattern to be etched. This patterning can be performed using photolithography. The mask layer can be a photoresist mask or a hard mask patterned based on a photolithographic mask. When the mask layer is a photoresist mask, it is patterned through steps such as exposure, development, and resist stripping. Then, a first trench of a certain depth is etched according to the first trench pattern to be etched.

[0151] The material of the initial dielectric layer 500 includes, but is not limited to, oxides, nitrides, metal oxides and oxynitrides. In this embodiment, the material of the initial dielectric layer 500 may be silicon dioxide.

[0152] Then, as Figures 8a to 8cAs shown, an initial active column 200 is formed in the first trench.

[0153] Next, the initial active pillar 200 is doped, including:

[0154] The first doping process is performed on the end of the initial active pillar 200 near the substrate 10;

[0155] A second doping process is performed on the middle region of the initial active pillar 200;

[0156] A third doping process is performed on the end of the initial active pillar 200 that is furthest from the substrate 10.

[0157] A fourth doping process is performed on the end of the initial active pillar 200 furthest from the substrate 10; wherein,

[0158] The doping ions in the first, second, and third doping processes include phosphorus, while the doping ions in the fourth doping process include arsenic.

[0159] In some embodiments, such as Figure 8c As shown, the initial first source / drain region 210 is located at the end of the initial active pillar 200 closest to the substrate 10, and the initial second source / drain region 230 is located at the end of the initial active pillar 200 furthest from the substrate 10. Thus, in this embodiment, the initial first source / drain region 210 is formed after the first doping process, the initial channel region 220 is formed after the second doping process, and the initial second source / drain region 230 is formed after the third and fourth doping processes.

[0160] In some other embodiments, the initial first source / drain region 210 is located at the end of the initial active pillar 200 away from the substrate 10, and the initial second source / drain region 230 is located at the end of the initial active pillar 200 close to the substrate 10. Thus, in this embodiment, the initial second source / drain region 230 is formed after the first doping process, the initial channel region 220 is formed after the second doping process, and the initial first source / drain region 210 is formed after the third and fourth doping processes.

[0161] In one embodiment, the ion energy implanted in the first doping process is 150 keV to 190 keV, and the ion dose is 6E13 atoms per square centimeter to 8E13 atoms per square centimeter; the ion energy implanted in the second doping process is 60 keV to 90 keV, and the ion dose is 2E13 atoms per square centimeter to 7E13 atoms per square centimeter; the ion energy implanted in the third doping process is 15 keV to 25 keV, and the ion dose is 7E13 atoms per square centimeter to 1E14 atoms per square centimeter; the ion energy implanted in the fourth doping process is 30 keV to 45 keV, and the ion dose is 2E13 atoms per square centimeter to 7E13 atoms per square centimeter.

[0162] Next, referring to Figures 9a to 9c , the initial active pillar 200 after doping is etched to form a U-shaped active pillar 20 having two branch parts.

[0163] In actual operation, the initial dielectric layer 500 is partially etched before the initial active pillar 200 is etched, so that part of the initial active pillar 200 is exposed.

[0164] As shown in Figure 9c , the active pillar 20 formed after etching includes a first source / drain region 21, a channel region 22, and a second source / drain region 23, and a U-shaped groove 24 between the two branch parts.

[0165] In some embodiments, the first source / drain region 21 can be a source region, and the second source / drain region 23 can be a drain region. In this embodiment, the source region is located on the first end of the active pillar, and the drain region is located on the second end of the active pillar.

[0166] In other embodiments, the first source / drain region 21 can be a drain region, and the second source / drain region 23 can be a source region. In this embodiment, the drain region is located on the first end of the active pillar, and the source region is located on the second end of the active pillar.

[0167] In an embodiment, the concentration of the doping ions of the first source / drain region 21 and the second source / drain region 23 is greater than the concentration of the doping ions of the channel region 22.

[0168] The concentration of the doping ions of the first source / drain region 21 and the second source / drain region 23 is greater, which can reduce the contact resistance.

[0169] In an embodiment, as shown in Figure 9c , the two branch parts of the U-shaped active pillar 20 are a first active pillar 201 and a second active pillar 202, and the first active pillar 201 and the second active pillar 202 share a first source / drain region 21 or a second source / drain region 23.

[0170] In the embodiments of the present disclosure, the first end is the end of the active pillar close to the substrate, so the first active pillar 201 and the second active pillar 202 share a first source / drain region 21. Specifically, when the first source / drain region 21 is a source region, the first active pillar 201 and the second active pillar 202 share a source region; when the first source / drain region 21 is a drain region, the first active pillar 201 and the second active pillar 202 share a drain region.

[0171] The transistors in the embodiments of the present disclosure share a source region or a drain region, so that the space occupied by the transistors is reduced, and the integration is improved.

[0172] In some other embodiments, the first active pillar and the second active pillar can also share a second source / drain region.

[0173] With continued reference to Figure 9c After the active pillar 20 is etched, the method further includes forming a gate oxide layer 51 between the active pillar 20 and a subsequently formed word line, which provides insulation between the active pillar and the word line to avoid crosstalk between the active pillar and the word line.

[0174] In an embodiment, the gate oxide layer 51 can be made of the same material as the dielectric layer 50, and the thickness of the gate oxide layer 51 can be 5.5 nm.

[0175] Next, with reference to Figure 10 and Figure 11 After the active pillar 20 is formed, the method further includes forming a plurality of word lines 30 extending along the first direction, each of the word lines 30 being located at a side of the channel region 22 away from the active pillar 20 and corresponding to the channel region 22 of a row of the active pillars 20 arranged along the first direction.

[0176] Specifically, with reference to Figure 10 An initial word line material layer 300 extending along the first direction is formed between the adjacent active pillars 20 arranged along the second direction.

[0177] Next, with reference to Figure 11 The initial word line material layer 300 is etched to form the word lines 30.

[0178] Specifically, the word lines 30 are located at a side of the channel region 22 away from the U-shaped trench 24.

[0179] The material of the word lines 30 includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof. In the embodiments of the present disclosure, the material of the word lines 30 can be tungsten.

[0180] Next, with reference to Figures 12a to 12c The dielectric layer 50 is formed to wrap the U-shaped active pillars 20 and fill the U-shaped trenches 24 between the two branch portions of the U-shaped active pillars 20.

[0181] Specifically, the dielectric material can be deposited on the initial dielectric layer 500, and the deposited dielectric material and the initial dielectric layer 500 together form the dielectric layer 50.

[0182] The dielectric layer insulates and isolates the active pillars and the two branch portions of the active pillars, so that crosstalk between the transistors and short circuit problems can be avoided.

[0183] The portion of the dielectric layer 50 located in the U-shaped trench 24 has a gap 501.

[0184] The medium layer in the U-shaped groove has a gap, so that the parasitic capacitance can be reduced.

[0185] With reference to Figures 12a to 12c , the method further includes forming a capacitor contact plug 60 on the active pillar 20. The capacitor contact plug can be used to electrically connect the active pillar with a capacitor (not shown).

[0186] Specifically, in some embodiments, when the first source / drain region 21 is located at the end of the active pillar 20 away from the substrate, the capacitor contact plug 60 is electrically connected with the first source / drain region 21.

[0187] In other embodiments, when the second source / drain region 23 is located at the end of the active pillar 20 away from the substrate, the capacitor contact plug 60 is electrically connected with the second source / drain region 23.

[0188] Next, with reference to Figures 13 to 15c , the method further includes, after forming the word line 30, flipping and thinning the substrate 10 until the end of the active pillar 20 close to the substrate 10 is exposed.

[0189] Forming a bit line 40 extending in the second direction on the end of the active pillar 20 close to the substrate 10, each bit line 40 being connected with the first source / drain region 21 or the second source / drain region 23 of a row of active pillars 20 arranged in the second direction.

[0190] First, with reference to Figure 13 and Figure 14 , the substrate 10 is flipped and thinned until the end of the active pillar 20 close to the substrate 10 is exposed.

[0191] Next, with reference to Figures 15a to 15c , a bit line contact plug 41 and a bit line 40 on the bit line contact plug 41 are formed on the end of the active pillar 20 close to the substrate 10.

[0192] The bit line is electrically connected with the first source / drain region or the second source / drain region through the bit line contact plug.

[0193] The material of the bit line contact plug 41 includes but is not limited to metal silicide.

[0194] Specifically, in some embodiments, when the first source / drain region 21 is located at the end of the active pillar 20 close to the substrate, the bit line 40 is connected with the first source / drain region 21.

[0195] In other embodiments, when the second source / drain region 23 is located at the end of the active pillar 20 close to the substrate, the bit line 40 is connected with the second source / drain region 23.

[0196] The material of the bit line 40 includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), a metal silicide, a metal alloy, or any combination thereof. In embodiments of the present disclosure, the material of the bit line 40 can be tungsten.

[0197] The above merely provides the preferred embodiments of the present disclosure, but not for limiting the protection scope of the present disclosure. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present disclosure shall fall within the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes active pillars arranged in an array along a first direction and a second direction, wherein the active pillars are U-shaped active pillars with two branches, and the first direction and the second direction are parallel to the plane of the substrate. Each of the aforementioned active columns includes: The first source / drain region is located at the first end of the active column; The second source / drain region is located at the second end of the active pillar; the first end and the second end are the two opposite ends of the active pillar in a third direction, and the third direction is a plane perpendicular to the substrate. The channel region is located between the first source / drain region and the second source / drain region; The first source / drain region, the second source / drain region, and the channel region have the same conductivity type. Multiple word lines extending along a first direction, each word line being located on the side of the channel region away from the active post, corresponding to the channel region of a row of active posts arranged along the first direction, the word line including a protrusion located between adjacent active posts arranged along the first direction; A dielectric layer that encloses the U-shaped active post and fills the U-shaped groove between the two branches of the U-shaped active post, wherein the portion of the dielectric layer located within the U-shaped groove has voids.

2. The semiconductor structure according to claim 1, characterized in that, Also includes: Multiple bit lines extending along a second direction, each bit line located below the active pillars and connected to the first source / drain region or the second source / drain region of a row of active pillars arranged along the second direction.

3. The semiconductor structure according to claim 1, characterized in that, The concentration of doped ions in the first source / drain region and the second source / drain region is greater than the concentration of doped ions in the channel region.

4. The semiconductor structure according to claim 1, characterized in that, The two branches of the U-shaped active column are the first active column and the second active column, and the first active column and the second active column share a first source / drain region or a second source / drain region.

5. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; Active pillars are formed on the substrate in an array arranged along a first direction and a second direction. The active pillars are U-shaped active pillars with two branches. The first direction and the second direction are parallel to the plane of the substrate. Forming the active column includes: A first source / drain region is formed at the first end of the active column; A second source / drain region is formed at the second end of the active pillar; the first end and the second end are the two opposite ends of the active pillar in a third direction, which is perpendicular to the plane of the substrate; A channel region is formed between the first source / drain region and the second source / drain region; The first source / drain region, the second source / drain region, and the channel region have the same conductivity type. After the active pillar is formed, a plurality of word lines extending along the first direction are formed. Each word line is located on the side of the channel area away from the active pillar and corresponds to the channel area of ​​a row of active pillars arranged along the first direction. The word line includes a protrusion located between adjacent active pillars arranged along the first direction. A dielectric layer is formed that encloses the U-shaped active column and fills the U-shaped groove between the two branches of the U-shaped active column; the portion of the dielectric layer located within the U-shaped groove has voids.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, Also includes: After the word lines are formed, the substrate is flipped and thinned until the end of the active pillar near the substrate is exposed; Bit lines extending along the second direction are formed on one end of the active pillars near the substrate, and each bit line is connected to the first source / drain region or the second source / drain region of a row of active pillars arranged along the second direction.

7. The method for preparing a semiconductor structure according to claim 5, characterized in that, Forming the active column includes: An initial dielectric layer is formed on the substrate; The initial dielectric layer is etched to form a plurality of first trenches arranged along the first direction and the second direction; An initial active column is formed within the first trench; The initial active pillar is doped to form an initial first source / drain region, an initial second source / drain region, and an initial channel region; The initial active pillar after doping is etched to form the U-shaped active pillar with two branches.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The doping of the initial active pillar includes: A first doping process is performed on the end of the initial active pillar near the substrate; A second doping process is performed on the middle region of the initial active pillar; A third doping process is performed on the end of the initial active pillar furthest from the substrate; A fourth doping process is performed on the end of the initial active pillar furthest from the substrate; wherein... The doping ions in the first doping process, the second doping process, and the third doping process include phosphorus, and the doping ions in the fourth doping process include arsenic.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The ion energy implanted by the first doping process is 150 keV to 190 keV, and the ion dose is 6E13 atoms per square centimeter to 8E13 atoms per square centimeter. The second doping process implants ions with energies of 60 keV to 90 keV and ion doses of 2E13 atoms per square centimeter to 7E13 atoms per square centimeter. The third doping process implants ions with an energy of 15 keV to 25 keV and an ion dose of 7E13 atoms per square centimeter to 1E14 atoms per square centimeter. The fourth doping process implants ions with an energy of 30 keV to 45 keV and an ion dose of 2E13 atoms per square centimeter to 7E13 atoms per square centimeter.

10. The method for preparing a semiconductor structure according to claim 5, characterized in that, The two branches of the U-shaped active column are the first active column and the second active column, and the first active column and the second active column share a first source / drain region or a second source / drain region.

Images