Low latency driver circuit and driving device

Abstract

The application discloses a low-latency driving circuit and a driving device. The low-latency driving circuit comprises an output transistor, an output terminal of which is connected to or serves as a driving output terminal of the driving circuit; and a first control transistor, an input terminal of which is connected to a first voltage level, and an output terminal of which is connected to a control terminal of the output transistor; wherein when the driving circuit switches to an open output, the first control transistor is turned on and the first voltage level is applied to the control terminal of the output transistor to raise the voltage of the driving output terminal. The low-latency driving circuit provided by the application can reduce the delay of output response under the premise of providing adjustable driving circuit output, so as to adapt to high-precision and fast-response application scenarios.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a low-latency driving circuit and driving device. Background Technology

[0002] In drive devices, especially when used to drive loads such as motors, the output of drive signals is usually accomplished by configuring drive circuits. The drive circuits can be set to the high side and / or low side, thereby converting the control signals input from the preceding circuits into appropriate drive signals to drive the motor load to start and stop.

[0003] In existing driving circuits, to achieve a slow rise in output voltage and control the rate of voltage rise, a current source is typically used to charge the output side after controlled activation. This control of the current source then controls the voltage rise process. However, during the initial switching from on to off, the limited output current of the current source causes a significant delay before the driving circuit can generate an output, resulting in poor tracking performance. Consequently, the driving circuit is unsuitable for scenarios requiring high precision and response speed. Summary of the Invention

[0004] One of the objectives of this invention is to provide a low-delay drive circuit to solve the problem that the output delay of the drive circuit in the prior art is large and cannot meet the requirements of high precision and fast response speed.

[0005] One of the objectives of this invention is to provide a low-delay drive circuit.

[0006] One of the objectives of this invention is to provide a driving device.

[0007] To achieve one of the above-mentioned objectives, one embodiment of the present invention provides a low-delay driving circuit, comprising: an output transistor, the output terminal of which is connected to or serves as a driving output terminal of a driving circuit; a first control transistor, the first control transistor being connected to a first level through its input terminal and connected to the control terminal of the output transistor through its output terminal; wherein, when the driving circuit switches to the on output, the first control transistor is turned on and applies the first level to the control terminal of the output transistor to raise the voltage of the driving output terminal.

[0008] As a further improvement of one embodiment of the present invention, the driving circuit further includes: a first adjustment circuit, disposed between the output terminal of the first control transistor and the control terminal of the output transistor, and turned on when the voltage at the output terminal of the first control transistor is greater than the voltage at the control terminal of the output transistor, and turned off when the voltage at the control terminal of the output transistor is greater than the voltage at the output terminal of the first control transistor.

[0009] As a further improvement of one embodiment of the present invention, the first adjustment circuit includes a first adjustment transistor or a first adjustment diode; the source of the first adjustment transistor is connected to the output terminal of the first control transistor, the gate is connected to the first level, and the drain is connected to the control terminal of the output transistor; the positive terminal of the first adjustment diode is connected to the output terminal of the first control transistor, and the negative terminal is connected to the control terminal of the output transistor.

[0010] As a further improvement of one embodiment of the present invention, when the first level is applied to the control terminal of the output transistor, the output transistor operates in the saturation region; the driving circuit further includes: an on-state current source, which is connected to the control terminal of the output transistor through its output terminal, and continuously charges the control terminal of the output transistor at least when the driving circuit switches to on-state output, so as to control the rising slope of the voltage at the driving output terminal.

[0011] As a further improvement of one embodiment of the present invention, when the turn-on current source charges the control terminal of the output transistor to a first intermediate voltage, the first control transistor is turned off, and the magnitude of the turn-on current output by the turn-on current source is positively correlated with the rising slope of the voltage at the drive output terminal.

[0012] As a further improvement of one embodiment of the present invention, the driving circuit further includes a first switching transistor connected in series between the turn-on current source and the control terminal of the output transistor; the control terminal of the first control transistor is coupled to a first control signal, and the control terminal of the first switching transistor is coupled to a second control signal; the first control signal indicates, in the form of a high or low level, whether the driving circuit switches to turn-on output or the driving circuit switches to turn-off output; the second control signal is the opposite of the high or low level of the first control signal.

[0013] As a further improvement of one embodiment of the present invention, the control terminal of the first control transistor is connected to the control signal terminal to receive the first control signal; the control terminal of the first switch is connected to the control signal terminal through a first inverter and a level shifting module; the first inverter is used to output the second control signal.

[0014] As a further improvement of one embodiment of the present invention, the driving circuit further includes: a second control transistor, which is connected to a second level through its output terminal and connected to the control terminal of the output transistor through its input terminal; when the driving circuit switches to off output, the second control transistor is turned on and applies the second level to the control terminal of the output transistor to reduce the voltage of the driving output terminal.

[0015] As a further improvement of one embodiment of the present invention, the driving circuit further includes: a second adjustment circuit, disposed between the input terminal of the second control transistor and the control terminal of the output transistor, and turned on when the voltage at the input terminal of the second control transistor is less than the voltage at the control terminal of the output transistor, and turned off when the voltage at the control terminal of the output transistor is less than the voltage at the output terminal of the second control transistor.

[0016] As a further improvement of one embodiment of the present invention, the second adjustment circuit includes a second adjustment transistor or a second adjustment diode; the source of the second adjustment transistor is connected to the input terminal of the second control transistor, the gate is connected to the second level, and the drain is connected to the control terminal of the output transistor; the negative terminal of the second adjustment diode is connected to the input terminal of the second control transistor, and the positive terminal is connected to the control terminal of the output transistor.

[0017] As a further improvement of one embodiment of the present invention, when the second level is applied to the control terminal of the output transistor, the output transistor operates in the saturation region; the driving circuit further includes: a current source that is turned off and connected to the control terminal of the output transistor through its input terminal, and continuously discharges the control terminal of the output transistor at least when the driving circuit switches to the off output, so as to control the rate of decrease of the driving output voltage.

[0018] As a further improvement of one embodiment of the present invention, when the shut-off current source discharges the control terminal of the output transistor to the second intermediate voltage, the second control transistor is turned off, and the magnitude of the shut-off current output by the shut-off current source is positively correlated with the rate of decrease of the voltage at the drive output terminal.

[0019] As a further improvement of one embodiment of the present invention, the driving circuit further includes a second switching transistor connected in series between the shut-off current source and the control terminal of the output transistor; the control terminal of the second control transistor is coupled to a third control signal, and the control terminal of the second switching transistor is coupled to a fourth control signal; the third control signal indicates, in the form of a high or low level, whether the driving circuit switches to the on output or the driving circuit switches to the off output; the fourth control signal has the same high or low level as the third control signal.

[0020] As a further improvement of one embodiment of the present invention, the control terminal of the second control transistor is connected to the control signal terminal through a level shifting module to receive the third control signal; the control terminal of the second switch is connected to the control signal terminal through a second inverter; the second inverter is used to output the fourth control signal.

[0021] To achieve one of the above-mentioned objectives, one embodiment of the present invention provides a low-delay driving circuit, comprising: an output transistor, the output terminal of which is connected to or serves as a driving output terminal of a driving circuit; and a second control transistor, the output terminal of which is connected to a second voltage level, and the input terminal of which is connected to a control terminal of the output transistor; wherein, when the driving circuit switches to off output, the second control transistor is turned on and applies the second voltage level to the control terminal of the output transistor to reduce the voltage of the driving output terminal.

[0022] To achieve one of the above-mentioned objectives, one embodiment of the present invention provides a driving device, including the low-delay driving circuit described in any of the above technical solutions.

[0023] Compared with the prior art, the low-latency drive circuit provided by the present invention, by setting a control transistor, conducts and raises the voltage at the output transistor at the instant the drive circuit switches to turn on the output, so that the output transistor quickly enters the working state and controls the voltage at the drive output terminal. Under the premise of ensuring the output voltage is adjustable, the drive delay can be greatly shortened, so that the drive circuit can meet the requirements of high precision and fast response. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the driving circuit in one embodiment of the present invention.

[0025] Figure 2 This is a circuit structure diagram of the driving circuit in one embodiment of the present invention.

[0026] Figure 3 This is a waveform diagram of the voltage and current flowing through the corresponding node when the driving circuit is implemented in one embodiment of the present invention.

[0027] Figure 4 This is a circuit structure diagram of the driving circuit in another embodiment of the present invention. Detailed Implementation

[0028] The present invention will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the scope of protection of the present invention.

[0029] It should be noted that the term "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," "third," "fourth," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0030] One embodiment of the present invention provides a drive device that can be applied to large-scale equipment such as passenger cars (energy types including but not limited to gasoline, diesel, hybrid, pure electric, plug-in hybrid, and range-extended electric vehicles), trucks, buses, and urban rail vehicles, as well as smaller-scale equipment such as robots. Preferably, the drive device can be used to drive loads such as motors in any of the above-mentioned equipment to realize transmission or other functions of devices such as wheel hubs and connecting rods. Preferably, the drive device provided by the present invention includes a low-latency drive circuit, enabling rapid response to control signals and control of subsequent circuits and loads, overcoming the shortcomings of large delays and low control accuracy in the prior art. Specifically, the low-latency drive circuit can be the drive circuit provided by any of the following technical solutions.

[0031] Of course, since cars and robots have their own driving functions, the driving device defined in this invention can be interpreted as the car, robot, or other equipment itself, in addition to the specific components inside the equipment used to perform load driving.

[0032] One embodiment of the present invention provides a low-latency driving circuit, which can be disposed in any of the above-mentioned driving devices to realize the corresponding driving function. Here, "low latency" is only used to express the advantages of the present invention compared to the prior art and does not necessarily limit the present invention; the main purpose of the present invention is to provide a driving circuit.

[0033] like Figure 1 , Figure 2 and Figure 4 As shown, the driving circuit provided by the present invention includes an output transistor 10 and a first control transistor 21.

[0034] The output transistor 10 is used to implement the drive output. It can be configured as a transistor of any size and with suitable voltage resistance. When the drive circuit is set on the high-side side, the output transistor 10 can also be defined as a high-side transistor and / or configured as an N-channel field-effect transistor.

[0035] The first control transistor 21 is used to control the operating state of the output transistor 10 according to the signal input. The operating state is not limited to controlling its operation in the cutoff region, variable resistance region, and saturation region (or constant current region), but can also be used to control the voltage or current at a certain terminal. The first control transistor 21 can be configured as a transistor of any size and with suitable voltage withstand capability, preferably an N-channel field-effect transistor.

[0036] Specifically, the output transistor 10 can be configured such that its output terminal is connected to the drive output terminal OUT of the drive circuit, or its output terminal is directly used as the drive output terminal OUT of the drive circuit. In embodiments where the output transistor 10 is configured as an N-type transistor, its output terminal can be its source.

[0037] Understandably, the output terminal and input terminal defined in this invention can be interpreted as the input terminal and output terminal formed when current flows through the corresponding transistor.

[0038] The first control transistor 21 can be configured such that its input terminal is connected to a first voltage level VDD, and its output terminal is connected to the control terminal of the output transistor 10. In this way, the first control transistor 21 can adjust the voltage at the control terminal of the output transistor 10.

[0039] In this embodiment, the control terminal of the output transistor 10 can be its gate; in the embodiment where the first control transistor 21 is configured as an N-type transistor, the input terminal of the first control transistor 21 can be its drain, and the output terminal of the first control transistor 21 can be its source. The first level VDD can be any high level; preferably, the first level VDD can be a low-voltage power supply that powers the driving circuit; specifically, it can be the operating voltage of the chip in which the driving circuit is located.

[0040] When the drive circuit switches to the output state, the first control transistor 21 turns on and applies a first level VDD to the control terminal of the output transistor 10 to raise the voltage of the drive output terminal OUT. In this way, the output transistor 10 can be controlled to turn on and enter the working state the instant the drive circuit turns on, thereby shortening the drive delay and ensuring that the output voltage of the drive circuit is adjustable, thus meeting the requirements of high precision and fast response.

[0041] The switching of the drive circuit to the on output mode indicates that the drive circuit is controlled and begins to output electrical signals to the subsequent circuit. When the first level VDD is applied to the control terminal of the output transistor 10, the output transistor 10 preferably operates in the saturation region; in one embodiment, this can be achieved by adjusting the level of the first level VDD, and in another embodiment, it can be achieved by adjusting the selection of the output transistor 10 itself or the level of its opposite terminal (for example, when the control terminal is interpreted as the gate, the opposite terminal can be interpreted as the source).

[0042] In one embodiment, when a first level VDD is applied to the control terminal of the output transistor 10, the output transistor 10 operates in the saturation region. Based on this, the driving circuit may further include an on-state current source 41 for adjusting the voltage at the control terminal of the output transistor 10 to control the voltage at the drive output terminal OUT. It is understood that "the first level VDD is applied" does not necessarily indicate that the voltage at the control terminal of the output transistor 10 is equal to the first level VDD; it only indicates that the first control transistor 21 is turned on and transmits the first level VDD, or that the voltage at the control terminal of the output transistor 10 has a contribution from the first level VDD.

[0043] Preferably, the output terminal of the turn-on current source 41 is connected to the control terminal of the output transistor 10. The turn-on current source 41 can also be configured to continuously charge the control terminal of the output transistor 10 at least when the drive circuit switches to the turn-on output, so as to control the rising slope of the drive output terminal OUT voltage.

[0044] Thus, the driving circuit provided by the present invention can take into account the adjustment of the voltage rise slope at the drive output terminal OUT, and turn on the output transistor 10 to a high conduction level at the moment of turn-on, so as to avoid the problem of slow response speed of transistor in the initial stage of turn-on, which leads to output delay of the driving circuit.

[0045] Specifically, in combination Figure 3 As shown, when the control signal indicating that the drive circuit should switch to the turn-on output is triggered, the control terminal voltage Vgate of the output transistor 10 is pulled high by the first level VDD guided by the first control transistor 21, causing the control terminal current Igate of the output transistor 10 to rise instantaneously or even generate a spike. The output transistor 10 can turn on instantaneously, thereby shortening the turn-on delay td_on. Then, the turn-on current source 41 continues to charge the turn-on current Ion into the control terminal of the output transistor 10. The control terminal voltage Vgate of the output transistor 10 and the voltage at the drive output terminal OUT rise at a certain slope to achieve the effect of slowly rising the drive output side voltage.

[0046] Understandably, the implementation of the above process can further explain the relationship between the first level VDD and the control terminal voltage Vgate. That is, the first level VDD is configured such that when it is turned on to the control terminal side of the output transistor 10, it is sufficient to increase or is about to increase the conduction level of the output transistor 10, but not sufficient to fully turn on the output transistor 10.

[0047] In another embodiment, the drive circuit may further include a first regulating circuit 31. The first regulating circuit 31 is at least used to prevent voltage backflow from the first control transistor 21 to the first level VDD side, and / or to prevent damage to the first control transistor 21. In some embodiments, it may also be used to block and withstand high voltage from the control terminal of the output transistor 10, preventing it from damaging components on the output side branch (such as the second switching transistor NM2, the current shut-off source 42, etc., described later).

[0048] The first regulating circuit 31 is located between the output terminal of the first control transistor 21 and the control terminal of the output transistor 10. This primarily protects the first control transistor 21 and prevents voltage backflow. Furthermore, the first regulating circuit 31 can be configured to conduct when the voltage at the output terminal of the first control transistor 21 is greater than the voltage at the control terminal of the output transistor 10; and to turn off when the voltage at the control terminal of the output transistor 10 is greater than the voltage at the output terminal of the first control transistor 21. This prevents the control terminal current Igate of the output transistor 10 from being reverse-transmitted to the first control transistor 21, thus protecting the components and control logic of the drive circuit.

[0049] In the first embodiment of this implementation, such as Figure 2 As shown, the first adjustment circuit 31 includes a first adjustment transistor NM1. The source of the first adjustment transistor NM1 is connected to the output terminal of the first control transistor 21, the gate of the first adjustment transistor NM1 is connected to a first voltage level VDD, and the drain of the first adjustment transistor NM1 is connected to the control terminal of the output transistor 10. Thus, when the control terminal voltage Vgate of the output transistor 10 is large, the first adjustment transistor NM1 can withstand and block this large voltage through its drain, preventing the components connected to its source and gate from being affected; when the control terminal voltage Vgate of the output transistor 10 is small, the first voltage level VDD can be connected to the control terminal of the output transistor 10 through the first control transistor 21 and the body diode of the first adjustment transistor NM1, achieving the effect described above. Preferably, the first adjustment transistor NM1 is configured as an N-channel field-effect transistor.

[0050] In the second embodiment of this implementation, such as Figure 4As shown, the first regulating circuit 31 includes a first regulating diode D1. The anode of the first regulating diode D1 is connected to the output terminal of the first control transistor 21, and the cathode of the first regulating diode D1 is connected to the control terminal of the output transistor 10. Thus, at the voltage level, unidirectional conduction is achieved from the output terminal of the first control transistor 21 to the control terminal of the output transistor 10.

[0051] Of course, another embodiment provided by the present invention may include the second embodiment described above. In this other embodiment, a first regulating transistor NM1 can also be set and its connection relationship adjusted to achieve the function of circuit protection. In this embodiment, the gate of the first regulating transistor NM1 is connected to the first level VDD, the source is connected to the ground level VSS (specifically, it can be connected to the low level VSS through the second switching transistor NM2 and the shutdown current source 42), and the drain is connected to the control terminal of the output transistor 10. Thus, the first regulating transistor NM1 can not only withstand and block the high voltage on the drain side, but also discharge the control terminal current Igate based on its constant conduction.

[0052] In one embodiment, the driving circuit can also be configured such that when the turn-on current source 41 charges the control terminal of the output transistor 10 to the first intermediate voltage, the first control transistor 21 is turned off, and the magnitude of the turn-on current Ion output by the turn-on current source 41 is positively correlated with the rising slope of the voltage at the drive output terminal OUT.

[0053] by Figure 2 Taking the first embodiment shown as an example, when both the first control transistor 21 and the first regulating transistor NM1 are configured as N-channel field-effect transistors, combined with Figure 3 When the drive circuit switches to the on output, the control terminal voltage Vgate is quickly pulled up to:

[0054] Vgate = VDD - Vgs_21 - Vsd_NM1.

[0055] Wherein, Vgs_21 is the gate-source voltage of the first control transistor 21, and Vsd_NM1 is the source-drain voltage of the first regulating transistor NM1. Preferably, VDD-Vgs_21-Vsd_NM1 is configured to be greater than the threshold voltage Vth_10 of the output transistor 10.

[0056] Correspondingly, the voltage Vout at the drive output terminal OUT is rapidly pulled up to:

[0057] Vout=VDD-Vgs_21-Vsd_NM1-Vgs_10.

[0058] Where Vgs_10 is the gate-source voltage of the output transistor 10.

[0059] Since the turn-on current source 41 continuously charges the control terminal of the output transistor 10 during this process, the control terminal voltage Vgate continues to be pulled up by the turn-on current Ion until the first intermediate voltage V1 is reached. If the first intermediate voltage V1 is applied to the output terminal of the first control transistor 21 through the conducting first regulating transistor NM1, then the first control transistor 21 can be turned off. Afterwards, the control terminal voltage Vgate and the voltage at the drive output terminal OUT are only affected by the turn-on current Ion, enabling single-variable, targeted control, and further achieving controllable rise rate of the voltage at the drive output terminal OUT. Specifically, the first intermediate voltage V1 can satisfy:

[0060] V1 = Vgate' = VDD - Vth_21.

[0061] Where Vth_21 is the threshold voltage of the first control transistor; Vgate' is the current control terminal voltage.

[0062] Understandably, the magnitude of the turn-on current Ion is positively correlated with the rising slope of the voltage at the drive output terminal OUT, preferably in a proportional relationship. However, this invention does not preclude other positively correlated configurations. The larger the turn-on current Ion, the faster the voltage Vout at the drive output terminal OUT rises.

[0063] In addition, for Figure 4 The second embodiment shown here will not be described in detail here. The source-drain voltage Vsd_NM1 of the first regulating transistor NM1, which is the on-state voltage drop mentioned above, can be replaced with the on-state voltage drop of the first regulating diode D1.

[0064] In one implementation, the first control transistor 21 determines whether the driving circuit has switched to the on output mode by adjusting the level of its control terminal using a control signal. Specifically, the control terminal of the first control transistor 21 can be coupled to a first control signal; the first control signal indicates whether the driving circuit switches to the on output mode or the driving circuit switches to the off output mode in the form of a high or low level.

[0065] Furthermore, the turn-on current source 41 is not necessarily configured to always charge the control terminal of the output transistor 10. In one embodiment, the drive circuit may further include a first switching transistor PM2 connected in series between the turn-on current source 41 and the control terminal of the output transistor 10, so as to synchronously control the turn-on current source 41 to charge the control terminal of the output transistor 10 when the first control transistor 21 applies the first level VDD to the control terminal of the output transistor 10.

[0066] In an embodiment where the first control transistor 21 is configured as an N-channel MOSFET, the first switch PM2 can be configured as a P-channel MOSFET to match the charging demand on the high-side. The control terminal of the first switch PM2 can be coupled to a second control signal; the second control signal has the opposite high and low levels to the first control signal, thereby synchronizing the level pull-up with charging.

[0067] In a preferred embodiment, the control terminal of the first control transistor 21 is connected to the control signal terminal COMD to receive the first control signal. The control terminal of the first switch transistor PM2 is connected to the control signal terminal COMD via the first inverter INV1 and the level shifting module 51. The first inverter INV1 is used to output the second control signal. Thus, synchronous control of multiple components can be achieved using only the control signal terminal COMD.

[0068] In another embodiment of the present invention, the driving circuit can implement a low-latency shutdown corresponding to the low-latency enable described above. Specifically, as shown in... Figure 1 , Figure 2 and Figure 4 As shown, the driving circuit in this embodiment includes an output transistor 10 and a second control transistor 22. The output transistor 10 is configured such that its output terminal (which may be its source) is connected to the drive output terminal OUT of the driving circuit, or its output terminal (which may be its source) is directly used as the drive output terminal OUT of the driving circuit. Further explanation of the output transistor 10 can be found above and will not be repeated here.

[0069] The second control transistor 22 corresponds to the first control transistor 21 mentioned above. Specifically, it can be configured such that its output terminal is connected to the second level VCC, and its input terminal is connected to the control terminal of the output transistor 10. In this way, the second control transistor 22 can adjust the voltage at the control terminal of the output transistor 10.

[0070] The second control transistor 22 is used to control the operating state of the output transistor 10 according to the signal input. The operating state is not limited to controlling its operation in the cutoff region, variable resistance region, and saturation region (or constant current region), but can also be used to control the voltage or current at a certain terminal. The second control transistor 22 can be configured as a transistor of any size and with suitable voltage withstand capability, preferably an N-channel field-effect transistor.

[0071] In embodiments where the second control transistor 22 is configured as an N-type transistor, the input terminal of the second control transistor 22 can be its drain, and the output terminal of the second control transistor 22 can be its source. The second level VCC can be any high level; preferably, the second level VCC can be a high-voltage power supply that supplies power to the driving circuit; specifically, it can be the power supply voltage of the driving circuit.

[0072] When the drive circuit switches to the off output position, the second control transistor 22 is turned on and applies the second level VCC to the control terminal of the output transistor 10 to reduce the voltage at the drive output terminal OUT. In this way, the output transistor 10 can be controlled to enter the off process at the instant the drive circuit turns off, thereby shortening the drive delay and ensuring that the output voltage of the drive circuit is adjustable, thus meeting the requirements for high precision and fast response.

[0073] The switching of the drive circuit to the off output indicates that the drive circuit is controlled and is about to stop outputting electrical signals to the subsequent circuit. When the second level VCC is applied to the control terminal of the output transistor 10, the output transistor 10 preferably operates in the saturation region, and the voltage at the control terminal of the output transistor 10 is less than the maximum voltage during the conduction process. In one embodiment, this can be achieved by adjusting the level of the second level VCC; in another embodiment, it can be achieved by adjusting the selection of the output transistor 10 itself or the level of its opposite terminal (for example, when the control terminal is interpreted as the gate, the opposite terminal can be interpreted as the source).

[0074] Of course, this implementation method can be combined with any of the implementation methods provided above to achieve both low latency during the turn-on process (Scheme 1) and low latency during the turn-off process (Scheme 2). In other words, the further description of Scheme 2 below can be considered as an optimized embodiment of Scheme 2 itself, or as an optimized embodiment of Scheme 3 formed by combining Scheme 1 and Scheme 2.

[0075] In one embodiment, when the second level VCC is applied to the control terminal of the output transistor 10, the output transistor 10 operates in the saturation region. Based on this, the driving circuit may further include a current source 42 for adjusting the voltage at the control terminal of the output transistor 10 to control the voltage at the drive output terminal OUT. It is understood that "the second level VCC is applied" does not necessarily indicate that the voltage at the control terminal of the output transistor 10 is equal to the second level VCC; it only indicates that the second control transistor 22 is turned on and transmits the second level VCC, or that the voltage at the control terminal of the output transistor 10 has a contribution from the second level VCC.

[0076] Preferably, the input terminal of the current-shutdown source 42 is connected to the control terminal of the output transistor 10. The current-shutdown source 42 can also be configured to continuously discharge the control terminal of the output transistor 10, at least when the drive circuit switches to the off output, so as to control the rate of decline of the drive output terminal OUT voltage.

[0077] Thus, the driving circuit provided by the present invention can take into account the adjustment of the voltage drop slope at the drive output terminal OUT, and reduce the control terminal voltage of the output transistor 10 at the moment the shutdown indication is given, so as to avoid the problem of slow response speed of the transistor in the initial shutdown stage, which leads to output delay of the driving circuit.

[0078] Specifically, in combination Figure 3 As shown, when the control signal indicating that the drive circuit should switch to the off output is triggered, the control terminal voltage Vgate of the output transistor 10 is pulled low by the second level VCC guided by the second control transistor 22, causing the control terminal current Igate of the output transistor 10 to drop instantaneously or even generate a reverse spike (the reverse is relative to the process of switching to the on output). The control terminal voltage Vgate of the output transistor 10 can drop instantaneously to the state of being ready to turn off (the degree of conduction is reduced), thereby shortening the turn-off delay td_off. Then, the turn-off current source 42 continues to pull down the control terminal voltage Vgate of the output transistor 10 with the turn-off current Ioff. The control terminal voltage Vgate of the output transistor 10 and the voltage at the drive output terminal OUT drop at a certain slope to achieve the effect of a slow drop in the drive output side voltage.

[0079] Understandably, the implementation of the above process can further explain the relationship between the second level VCC and the control terminal voltage Vgate. That is, the second level VCC is configured such that when it is turned on to the control terminal side of the output transistor 10, it is sufficient to reduce or about to reduce the conduction level of the output transistor 10, but not sufficient to turn off the output transistor 10.

[0080] In another embodiment, the drive circuit may further include a second adjustment circuit 32. The second adjustment circuit 32 is at least used to prevent the second control transistor 22 from always applying the second level VCC to the control terminal of the output transistor 10, which could lead to control failure or even damage to the output transistor 10.

[0081] The second adjustment circuit 32 is located between the input terminal of the second control transistor 22 and the control terminal of the output transistor 10; thus, it mainly serves to pull the control terminal voltage of the output transistor 10 down from a high potential. Further, the second adjustment circuit 32 can be configured to conduct when the voltage at the input terminal of the second control transistor 22 is lower than the control terminal voltage of the output transistor 10; and the second adjustment circuit 32 can be configured to turn off when the voltage at the control terminal of the output transistor 10 is lower than the output terminal voltage of the second control transistor 22. This prevents the second level VCC from charging the control terminal of the output transistor 10, thereby affecting the normal operation of the output transistor 10 itself.

[0082] In the first embodiment of this implementation, such as Figure 2 As shown, the second adjustment circuit 32 includes a second adjustment transistor PM1. The source of the second adjustment transistor PM1 is connected to the input terminal of the second control transistor 22, the gate of the second adjustment transistor PM1 is connected to the second voltage level VCC, and the drain of the second adjustment transistor PM1 is connected to the control terminal of the output transistor 10. Thus, when the control terminal voltage Vgate of the output transistor 10 is low, the second adjustment transistor PM1 can isolate the control terminal voltage Vgate from the second control transistor 22 and the second voltage level VCC, preventing the operating state of the output transistor 10 from being affected; when the control terminal voltage Vgate of the output transistor 10 is high, the second voltage level VCC can be connected to the control terminal of the output transistor 10 through the body diode of the second control transistor 22 and the second adjustment transistor PM1, achieving the effect described above. Preferably, the second adjustment transistor PM1 is configured as a P-channel field-effect transistor.

[0083] In the second embodiment of this implementation, such as Figure 4 As shown, the second regulation circuit 32 includes a second regulation diode D2. The cathode of the second regulation diode D2 is connected to the input terminal of the second control transistor 22, and the anode of the second regulation diode D2 is connected to the control terminal of the output transistor 10. Thus, at the voltage level, unidirectional conduction is achieved from the control terminal of the output transistor 10 to the output terminal of the second control transistor 22.

[0084] Of course, another embodiment provided by the present invention may include the second embodiment described above. In this other embodiment, a second regulating transistor PM1 can also be set and its connection relationship adjusted to achieve the function of circuit protection. In this embodiment, the gate of the second regulating transistor PM1 is connected to the second level VCC, the source is connected to the output level VCP (specifically, it can be connected to the output level VCP through the first switching transistor PM2 and the turn-on current source 41), and the drain is connected to the control terminal of the output transistor 10. Thus, the second regulating transistor PM1 can not only stabilize the potential at the control terminal of the output transistor 10 when a lower voltage is applied, but also promptly pull down the potential at the control terminal of the output transistor 10 when a higher voltage is applied.

[0085] The output level VCP can have at least one of the following uses: (1) to power the source of the second regulating transistor PM1, specifically, to power it through the turn-on current source 41 and the first switching transistor PM2; (2) to power the turn-on current source 41 so that it generates the turn-on current Ion; (3) as the output of the charge pump 52 connected to the input terminal (or drain) of the output transistor 10, wherein the input terminal of the charge pump 52 is connected to the second level VCC and the input terminal of the output transistor 10, and the output terminal of the charge pump 52 is connected to the input terminal of the turn-on current source 41.

[0086] In one embodiment, the driving circuit can also be configured such that when the shut-off current source 42 discharges the control terminal of the output transistor 10 to the second intermediate voltage, the second control transistor 22 is turned off, and the absolute value of the shut-off current Ioff output by the shut-off current source 42 is positively correlated with the slope of the voltage drop at the drive output terminal OUT.

[0087] by Figure 2 Taking the first embodiment shown as an example, when the second control transistor 22 is configured as an N-channel field-effect transistor and the second regulating transistor PM1 is configured as a P-channel field-effect transistor, combined with Figure 3 When the drive circuit switches to the off output, the control terminal voltage Vgate is quickly pulled down to:

[0088] Vgate = VCC + Vsg_PM1.

[0089] Vsg_PM1 is the source-gate voltage of the second regulating transistor PM1. Preferably, VCC+Vsg_PM1 is configured to be approximately equal to the threshold voltage Vth_10 of the output transistor 10.

[0090] Correspondingly, the voltage Vout at the drive output terminal OUT is rapidly pulled up to:

[0091] Vout = VCC + Vsg_PM1 - Vgs_10.

[0092] Where Vgs_10 is the gate-source voltage of the output transistor 10.

[0093] As the shut-off current source 4 continuously discharges the control terminal of the output transistor 10 during this process, the control terminal voltage Vgate continues to be pulled down by the shut-off current Ioff until the second intermediate voltage V2 is reached. If the second intermediate voltage V2 is applied to the output terminal of the second control transistor 22 through the conducting second regulating transistor NM2, then the second control transistor 22 can be turned off. Afterwards, the control terminal voltage Vgate and the voltage at the drive output terminal OUT are only affected by the shut-off current Ioff, enabling single-variable, targeted control, and further achieving controllable rate of decrease of the voltage at the drive output terminal OUT. Specifically, the second intermediate voltage V2 can satisfy:

[0094] V2=Vgate”=VDD-Vth_PM1.

[0095] Where Vth_PM1 is the threshold voltage of the second regulating transistor; Vgate is the current control terminal voltage.

[0096] Understandably, the absolute value of the shutdown current Ioff is positively correlated with the rate of decrease of the voltage at the drive output terminal OUT, preferably proportionally. Of course, the present invention does not exclude other positively correlated configurations. The larger the absolute value of the shutdown current Ioff, the faster the voltage Vout at the drive output terminal OUT decreases.

[0097] In addition, for Figure 4 The second embodiment shown is not described in detail here.

[0098] In one embodiment, the second control transistor 22 determines whether the drive circuit has switched to a shutdown output by adjusting the level of its control terminal using a control signal. Specifically, the control terminal of the second control transistor 22 can be coupled to a third control signal; the third control signal indicates, in the form of a high or low level, whether the drive circuit switches to an on output or a shutdown output.

[0099] Furthermore, the current source 42 is not necessarily configured to always discharge the control terminal of the output transistor 10. In one embodiment, the drive circuit may further include a second switch NM2 connected in series between the current source 42 and the control terminal of the output transistor 10, so as to synchronously control the current source 42 to discharge the control terminal of the output transistor 10 when the second control transistor 22 applies the second level VCC to the control terminal of the output transistor 10.

[0100] In an embodiment where the second control transistor 22 is configured as an N-channel MOSFET, the second switch NM2 can also be configured as an N-channel MOSFET to match the discharge requirements of the low-side. The control terminal of the second switch NM2 can be coupled to a fourth control signal; the fourth control signal has the same high and low levels as the third control signal, thereby achieving synchronization between level pull-down and discharge.

[0101] In a preferred embodiment, the control terminal of the second control transistor 22 is connected to the control signal terminal COMD via the level shifting module 51 to receive the third control signal. The control terminal of the second switch transistor NM2 is connected to the control signal terminal COMD via the second inverter INV2. The second inverter INV2 is used to output the fourth control signal. Thus, synchronous control of multiple components can be achieved using only the control signal terminal COMD.

[0102] Preferably, in the third embodiment, the gates of the first switching transistor PM2 (via the first inverter INV1 and level shifting module 51), the second control transistor 22 (via the level shifting module), the first control transistor 21, and the second switching transistor NM2 (via the second inverter INV2) can be connected to the same control signal terminal COMD to further achieve pin multiplexing. The control signal terminal COMD can be used to switch the output signal from 0 to 1 (or from low level to high level) when instructing the driving circuit to switch from off output to on output, and / or to switch the output signal from 1 to 0 (or from high level to low level) when instructing the driving circuit to switch from on output to off output.

[0103] In a preferred embodiment of the present invention, such as Figure 1 , Figure 2 and Figure 4 As shown, the output transistor 10 is an N-channel field-effect transistor, with its output terminal being its own source, its control terminal being its own gate, and its input terminal being its own drain; the first control transistor 21 is an N-channel field-effect transistor, with its output terminal being its own source, its control terminal being its own gate, and its input terminal being its own drain; the second control transistor 22 is an N-channel field-effect transistor, with its output terminal being its own source, its control terminal being its own gate, and its input terminal being its own drain.

[0104] The level shifting module 51 provided in any of the above embodiments can be used to match the levels on the high-side and low-side; in particular, it can match the level on the control signal terminal COMD with the level on the high-side (first switch PM2, second control transistor 22), and / or match the level on the control signal terminal COMD with the level on the low-side (first control transistor 21, second switch NM2). Specifically, when the control signal terminal COMD outputs a signal 1, it outputs a level greater than or equal to the highest level connected to the high-side component (e.g., output level VCP); and / or when the control signal terminal COMD outputs a signal 0, it outputs a level less than or equal to the lowest level connected to the high-side component (e.g., second level VCC). In this way, the on / off control of the high-side component and the matching effect of the first inverter INV1 are achieved.

[0105] In a preferred first embodiment of the present invention, such as Figure 2 As shown, the drain of the first control transistor 21 is connected to the first level VDD and the gate of the first regulating transistor NM1. The gate of the first control transistor 21 is connected to the control signal terminal COMD. The source of the first control transistor 21 is connected between the source of the first regulating transistor NM1 and the drain of the second switching transistor NM2. The source of the second control transistor 22 is connected to the second level VCC and the gate of the second regulating transistor PM1. The gate of the second control transistor 22 is connected to the control signal terminal COMD through the level shifting module 51 (or two first inverters INV1). The drain of the second control transistor 22 is connected between the source of the second regulating transistor PM1 and the drain of the first switching transistor PM2.

[0106] In a preferred second embodiment of the present invention, such as Figure 4 As shown, the drain of the first control transistor 21 is connected to the first level VDD and the gate of the first regulating transistor NM1. The gate of the first control transistor 21 is connected to the control signal terminal COMD. The source of the first control transistor 21 is connected to the anode of the first regulating diode D1. The cathode of the first regulating diode D1 is connected between the first regulating transistor NM1 and the second regulating transistor PM1, and then connected to the gate of the output transistor 10. Alternatively, the cathode of the first regulating diode D1 is directly connected to the gate of the output transistor 10. The source of the second control transistor 22 is connected to the second level VCC and the gate of the second regulating transistor PM1. The gate of the second control transistor 22 is connected to the control signal terminal COMD through the level transfer module 51 (or two first inverters INV1). The drain of the second control transistor 22 is connected to the cathode of the second regulating diode D2. The anode of the second regulating diode D2 is connected between the first regulating transistor NM1 and the second regulating transistor PM1, and then connected to the gate of the output transistor 10. Alternatively, the anode of the second regulating diode D2 is directly connected to the gate of the output transistor 10.

[0107] In summary, the low-delay drive circuit provided by this invention, by setting a control transistor, conducts and raises the voltage at the output transistor at the instant the drive circuit switches to turn on the output, thereby enabling the output transistor to quickly enter the working state and controllably adjust the voltage at the drive output terminal. Under the premise of ensuring adjustable output voltage, the drive delay can be significantly shortened, allowing the drive circuit to meet the requirements of high precision and fast response.

[0108] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0109] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A low latency driver circuit, characterized by, The drive circuit comprises: an output transistor, an output terminal of which is connected to or serves as a driving output terminal of the drive circuit; a first control transistor, an input terminal of which is connected to a first voltage level, and an output terminal of which is connected to a control terminal of the output transistor; wherein the first control transistor is turned on and applies the first voltage level to the control terminal of the output transistor to raise a voltage of the driving output terminal when the drive circuit switches to an open output; the drive circuit further comprises: an open current source, an output terminal of which is connected to the control terminal of the output transistor, and which charges the control terminal of the output transistor at least when the drive circuit switches to the open output; the first control transistor is turned off when the open current source charges the control terminal of the output transistor to a first intermediate voltage, and an open current output by the open current source is positively correlated with a rising slope of the voltage of the driving output terminal; the first intermediate voltage is determined according to a difference between the first voltage level and a threshold voltage of the first control transistor.

2. The low latency drive circuit of claim 1, wherein, The drive circuit further comprises: a first regulating circuit, which is arranged between the output terminal of the first control transistor and the control terminal of the output transistor, and is turned on when a voltage at the output terminal of the first control transistor is greater than a voltage at the control terminal of the output transistor, and is turned off when the voltage at the control terminal of the output transistor is greater than the voltage at the output terminal of the first control transistor.

3. The low latency drive circuit of claim 2, wherein, The first regulating circuit comprises a first regulating transistor or a first regulating diode; a source of the first regulating transistor is connected to the output terminal of the first control transistor, a gate of the first regulating transistor is connected to the first voltage level, and a drain of the first regulating transistor is connected to the control terminal of the output transistor; a positive electrode of the first regulating diode is connected to the output terminal of the first control transistor, and a negative electrode of the first regulating diode is connected to the control terminal of the output transistor.

4. The low latency driver circuit of claim 1, wherein, The drive circuit further comprises a first switch transistor connected in series between the open current source and the control terminal of the output transistor; a control terminal of the first control transistor is coupled to a first control signal, and a control terminal of the first switch transistor is coupled to a second control signal; the first control signal indicates whether the drive circuit switches to the open output or the drive circuit switches to a closed output in the form of high and low levels; and the second control signal is opposite to the high and low levels of the first control signal.

5. The low latency driver circuit of claim 4, wherein, The control terminal of the first control transistor is connected to a control signal terminal to receive the first control signal; the control terminal of the first switch transistor is connected to the control signal terminal through a first inverter and a level shift module; and the first inverter is used to output the second control signal.

6. The low latency driver circuit of claim 1, wherein, The drive circuit further comprises: a second control transistor, an output terminal of which is connected to a second voltage level, and an input terminal of which is connected to the control terminal of the output transistor; the second control transistor is turned on and applies the second voltage level to the control terminal of the output transistor to lower the voltage of the driving output terminal when the drive circuit switches to a closed output.

7. The low latency drive circuit of claim 6, wherein, The drive circuit further comprises: A second regulating circuit is arranged between the input terminal of the second control transistor and the control terminal of the output transistor, and is turned on when the voltage at the input terminal of the second control transistor is less than the voltage at the control terminal of the output transistor, and is turned off when the voltage at the control terminal of the output transistor is less than the voltage at the output terminal of the second control transistor.

8. The low latency driver circuit of claim 7, wherein, The second regulating circuit comprises a second regulating transistor or a second regulating diode; The source of the second regulating transistor is connected to the input terminal of the second control transistor, the gate is connected to the second level, and the drain is connected to the control terminal of the output transistor. The negative electrode of the second regulating diode is connected to the input terminal of the second control transistor, and the positive electrode is connected to the control terminal of the output transistor.

9. The low latency driver circuit of claim 6, wherein, When the second level is added to the control terminal of the output transistor, the output transistor works in the saturation region; the driving circuit further comprises: A turn-off current source is connected to the control terminal of the output transistor through its input terminal, and continuously discharges the control terminal of the output transistor at least when the driving circuit switches to turn off the output, so as to control the falling slope of the driving output voltage.

10. The low latency driver circuit of claim 9, wherein, When the control terminal of the output transistor is discharged to a second intermediate voltage by the turn-off current source, the second control transistor is turned off, and the size of the turn-off current output by the turn-off current source is positively correlated with the falling slope of the driving output voltage.

11. The low latency driver circuit of claim 9, wherein, The driving circuit further comprises a second switch tube connected in series between the turn-off current source and the control terminal of the output transistor; the control terminal of the second control transistor is coupled to a third control signal, and the control terminal of the second switch tube is coupled to a fourth control signal; the third control signal indicates whether the driving circuit switches to turn on the output or the driving circuit switches to turn off the output in the form of high and low levels; and the fourth control signal has the same high and low levels as the third control signal.

12. The low latency driver circuit of claim 11, wherein, The control terminal of the second control transistor is connected to a control signal terminal through a level shifting module to receive the third control signal; the control terminal of the second switch tube is connected to the control signal terminal through a second inverter; and the second inverter is used to output the fourth control signal.

13. A low latency driver circuit, characterized by The driving circuit comprises: An output transistor, whose output terminal is connected to or serves as a driving output terminal of the driving circuit; A second control transistor, whose output terminal is connected to a second level, and whose input terminal is connected to the control terminal of the output transistor; When the driving circuit switches to turn off the output, the second control transistor is turned on and adds the second level to the control terminal of the output transistor to reduce the voltage of the driving output terminal; The driving circuit further comprises: A turn-off current source, which is connected to the control terminal of the output transistor through its input terminal, and discharges the control terminal of the output transistor at least when the driving circuit switches to turn off the output. A second regulating circuit is arranged between the input terminal of the second control transistor and the control terminal of the output transistor, and is turned on when the voltage at the input terminal of the second control transistor is less than the voltage at the control terminal of the output transistor, and is turned off when the voltage at the control terminal of the output transistor is less than the voltage at the output terminal of the second control transistor; The second regulating circuit comprises a second regulating transistor, the source of which is connected to the input terminal of the second control transistor, the gate of which is connected to the second level, and the drain of which is connected to the control terminal of the output transistor; When the off current source discharges the control terminal of the output transistor to a second intermediate voltage, the second control transistor is turned off, and the off current output by the off current source is positively correlated with the falling slope of the voltage at the driving output terminal; The second intermediate voltage is determined according to the difference between the second level and the threshold value of the second regulating transistor.

14. A drive apparatus characterized by comprising: A low latency driving circuit comprising any one of claims 1-13.

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