A wireless transceiver control circuit

Abstract

The present invention discloses a wireless transceiver control circuit, comprising a frequency matching end and an adjustment end, wherein the adjustment end comprises a controller, a demodulation unit, an adaptation unit, and a frequency-seeking unit, wherein the adaptation unit is connected to the frequency-seeking unit, the demodulation unit, and the controller, and the controller is connected to the demodulation unit and the frequency-seeking unit. The frequency matching end is used to send a current frequency-specific modulation signal to the demodulation unit, wherein the adaptation unit feeds back a received frequency signal VOUT to the demodulation unit, wherein the demodulation unit feeds back the demodulated signal to the controller for decoding and comparison, wherein the controller feeds back an interrupt signal VIN to the frequency-seeking unit, wherein the frequency-seeking unit automatically seeks frequency according to the interrupt signal state and feeds back a frequency-seeking signal Prot_1 to the adaptation unit, wherein the adaptation unit automatically corresponds to the received frequency signal VOUT based on the frequency-seeking signal Prot_1, and feeds back the received frequency signal VOUT to the demodulation circuit for re-demodulation.

Description

Technical Field

[0001] The present invention relates to the technical field of signal transmission, and in particular to a wireless transceiver control circuit. Background Art

[0002] In the field of communications, frequency matching refers to the fact that two communication devices have the same operating frequency so that they can communicate with each other. Frequency matching capability plays a vital role in communications because different frequencies may affect the quality of communication. Within the allowed frequency band, signal interference in space can be avoided by selecting different frequencies. However, in the prior art, after one end adjusts the transmitting frequency, the receiving frequency needs to be manually adjusted. In order to ensure good communication effects, this requires multiple manual adjustments. Summary of the invention

[0003] In view of the above technical problems, the purpose of the present invention is to provide a wireless transceiver control circuit, including a frequency binding end and an adjustment end, the adjustment end including a controller, a demodulation unit, an adaptation unit, and a frequency seeking unit, the adaptation unit is connected to the frequency seeking unit, the demodulation unit, and the controller, the controller is connected to the demodulation unit and the frequency seeking unit, the frequency binding end is used to send a current frequency-specific modulation signal to the demodulation unit, the adaptation unit feeds back a received frequency signal VOUT to the demodulation unit, the demodulation unit feeds back the demodulated signal to the controller for decoding and comparison, the controller feeds back an interrupt signal VIN to the frequency seeking unit, the frequency seeking unit automatically seeks frequency according to the interrupt signal state and feeds back a frequency seeking signal Prot_1 to the adaptation unit, the adaptation unit automatically corresponds to the received frequency signal VOUT based on the frequency seeking signal Prot_1, and feeds it back to the demodulation circuit for re-demodulation.

[0004] Further, the frequency-seeking unit includes a first resistor R1, a third resistor R3, a sixth resistor R6, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a sixteenth resistor R16, a first operational amplifier U1, a second operational amplifier U2, a third digital potentiometer U3, a first MOS tube Q1, a third triode Q3, a fourth thyristor Q4, and a first switch S1; one end of the first resistor R1, one end of the first switch S1, a source of the first MOS tube Q1, a first pin of the third digital potentiometer U3, a third pin of the third digital potentiometer U3, and an eighth pin of the third digital potentiometer U3 are connected to a power supply; the other end of the first resistor R1 is connected to an emitter of the third triode Q3; the collector of the third triode Q3 is connected to a seventh pin of the third digital potentiometer U3 and one end of the ninth resistor R9; the second pin of the third digital potentiometer U3 is connected to one end of the eighth resistor R8; the fifth pin of the third digital potentiometer U3, the sixth pin of the third digital potentiometer U3, and one end of the sixth resistor R6 are connected to a frequency-seeking signal Prot 1, the base of the third triode Q3 is connected to the output end of the first operational amplifier U1 and one end of the third resistor R3, the non-inverting end of the first operational amplifier U1 is connected to the cathode of the fourth thyristor Q4 and one end of the sixteenth resistor R16, the control electrode of the fourth thyristor Q4 is connected to the other end of the first switch S1, the anode of the fourth thyristor Q4 is connected to the drain of the first MOS tube Q1, the gate of the first MOS tube Q1 is connected to the output end of the second operational amplifier U2 and one end of the tenth resistor R10, the non-inverting end of the second operational amplifier U2 is connected to the interrupt signal VIN, the inverting end of the second operational amplifier U2 is connected to the interrupt reference signal VREF, the other end of the third resistor R3, the other end of the sixth resistor R6, the other end of the eighth resistor R8, the other end of the ninth resistor R9, the other end of the tenth resistor R10, the other end of the sixteenth resistor R16, and the fourth pin of the third digital potentiometer U3 are connected to the ground.

[0005] Further, the adaptation unit includes a fifteenth resistor R15, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-sixth resistor R26, a fifth trigger U5, a sixth operational amplifier U6, a seventh operational amplifier U7, an eighth operational amplifier U8, a second transistor Q2, a fifth MOS transistor Q5, a sixth transistor Q6, a seventh MOS transistor Q7, a second capacitor C2, a collector of the second transistor Q2, and a fifth trigger U5. The first pin, the fourth pin of the fifth trigger U5, and one end of the twentieth resistor R20 are connected to the power supply, the emitter of the second triode Q2 is connected to one end of the fifteenth resistor R15, the base of the second triode Q2 is connected to the fifth pin of the fifth trigger U5 and the gate of the seventh MOS tube Q7, the source of the seventh MOS tube Q7 is connected to the other end of the twentieth resistor R20, the second pin of the fifth trigger U5 is connected to the sixth pin of the fifth trigger U5, the third pin of the fifth trigger U5 is connected to the source of the fifth MOS tube Q5 and one end of the twenty-third resistor R23, the gate of the fifth MOS tube Q5 is connected to the reset signal Prot 2, the drain of the fifth MOS tube Q5 is connected to the output end of the sixth operational amplifier U6 and the output end of the seventh operational amplifier U7, the in-phase end of the sixth operational amplifier U6 is connected to one end of the seventeenth resistor R17 and one end of the eighteenth resistor R18, the inverting end of the sixth operational amplifier U6, the in-phase end of the seventh operational amplifier U7, the other end of the fifteenth resistor R15, one end of the nineteenth resistor R19, the collector of the sixth transistor Q6, one end of the second capacitor C2 and the receiving frequency signal VOUT are connected, the drain of the seventh MOS tube Q7 is connected to the base of the sixth transistor Q6, the emitter of the sixth transistor Q6 is connected to one end of the twenty-sixth resistor R26, the inverting end of the seventh operational amplifier U7 is connected to the other end of the seventeenth resistor R17 and one end of the twenty-first resistor R21, the other end of the twenty-first resistor R21 is connected to one end of the twenty-second resistor R22, and the output end of the eighth operational amplifier U8, the inverting end of the eighth operational amplifier U8 is connected to the other end of the twenty-second resistor R22, the in-phase end of the eighth operational amplifier U8 is connected to the frequency search signal Prot 1, the other end of the eighteenth resistor R18, the other end of the nineteenth resistor R19, the other end of the twenty-third resistor R23, the other end of the twenty-sixth resistor R26, the other end of the second capacitor C2 and the ground terminal are connected.

[0006] Furthermore, it also includes a reset unit, which is connected to the adaptation unit, and includes a fourth resistor R4, a fifth resistor R5, a seventh resistor R7, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourth operational amplifier U4, and a first capacitor C1. One end of the fourth resistor R4 and one end of the eleventh resistor R11 are connected to the power supply, the other end of the fourth resistor R4 is connected to one end of the first capacitor C1, the in-phase end of the fourth operational amplifier U4, and one end of the seventh resistor R7, the inverting end of the fourth operational amplifier U4 is connected to the other end of the eleventh resistor R11 and one end of the twelfth resistor R12, the output end of the fourth operational amplifier U4, one end of the thirteenth resistor R13 are connected to the reset signal Prot 2, one end of the fifth resistor R5 is connected to the base of the second transistor Q2, and the other end of the fifth resistor R5, the other end of the seventh resistor R7, the other end of the twelfth resistor R12, the other end of the thirteenth resistor R13, and the other end of the first capacitor C1 are connected to the ground end.

[0007] Furthermore, the frequency-seeking unit also includes a second resistor R2 and a fourteenth resistor R14, one end of the second resistor R2 is connected to the power supply, the other end of the second resistor R2 is connected to the inverting end of the first operational amplifier U1 and one end of the fourteenth resistor R14, and the other end of the fourteenth resistor R14 is connected to the ground.

[0008] Furthermore, the adaptation unit further includes a twenty-fourth resistor R24, one end of the twenty-fourth resistor R24 ​​is connected to the source of the seventh MOS tube Q7, and the other end of the twenty-fourth resistor R24 ​​is connected to the ground.

[0009] Furthermore, the adaptation unit further includes a twenty-fifth resistor R25, one end of the twenty-fifth resistor R25 is connected to the drain of the fifth MOS tube Q5, and the other end of the twenty-fifth resistor R25 is connected to the ground.

[0010] The beneficial effects of the present invention compared with the prior art are:

[0011] The present invention can automatically match the receiving frequency with the transmitting frequency, avoiding the need to manually match the frequencies of both ends after adjustment within the allowed frequency band. It can automatically reset during the initial power-on period, avoiding manual control and failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1The present invention provides an overall structural diagram.

[0014] Figure 2 This is a schematic diagram of the circuit structure of the adaptation unit, frequency-seeking unit and reset unit provided by the present invention. DETAILED DESCRIPTION

[0015] In order to make the objects and advantages of the present invention more clearly understood, the present invention is specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or several specific implementations of the present invention, and does not strictly limit the scope of protection specifically requested by the present invention.

[0016] The present invention discloses a wireless transceiver control circuit, comprising a frequency matching end and an adjustment end, wherein the adjustment end comprises a controller, a demodulation unit, an adaptation unit, and a frequency-seeking unit, wherein the adaptation unit is connected to the frequency-seeking unit, the demodulation unit, and the controller, and the controller is connected to the demodulation unit and the frequency-seeking unit. The frequency matching end is used to send a current frequency-specific modulation signal to the demodulation unit, wherein the adaptation unit feeds back a received frequency signal VOUT to the demodulation unit, wherein the demodulation unit feeds back the demodulated signal to the controller for decoding and comparison, wherein the controller feeds back an interrupt signal VIN to the frequency-seeking unit, wherein the frequency-seeking unit automatically seeks frequency according to the interrupt signal state and feeds back a frequency-seeking signal Prot_1 to the adaptation unit, wherein the adaptation unit automatically corresponds to the received frequency signal VOUT based on the frequency-seeking signal Prot_1, and feeds back the received frequency signal VOUT to the demodulation circuit for re-demodulation.

[0017] Specifically, the frequency-seeking unit includes a first resistor R1, a third resistor R3, a sixth resistor R6, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a sixteenth resistor R16, a first operational amplifier U1, a second operational amplifier U2, a third digital potentiometer U3, a first MOS tube Q1, a third triode Q3, a fourth thyristor Q4, and a first switch S1. One end of the first resistor R1, one end of the first switch S1, a source of the first MOS tube Q1, a first pin of the third digital potentiometer U3, a third pin of the third digital potentiometer U3, and an eighth pin of the third digital potentiometer U3 are connected to a power supply. The other end of the first resistor R1 is connected to the emitter of the third triode Q3, the collector of the third triode Q3 is connected to the seventh pin of the third digital potentiometer U3, and one end of the ninth resistor R9 is connected. The second pin of the third digital potentiometer U3 is connected to one end of the eighth resistor R8, and the fifth pin of the third digital potentiometer U3, the sixth pin of the third digital potentiometer U3, and one end of the sixth resistor R6 are connected to a frequency-seeking signal Prot. 1, the base of the third triode Q3 is connected to the output end of the first operational amplifier U1 and one end of the third resistor R3, the non-inverting end of the first operational amplifier U1 is connected to the cathode of the fourth thyristor Q4 and one end of the sixteenth resistor R16, the control electrode of the fourth thyristor Q4 is connected to the other end of the first switch S1, the anode of the fourth thyristor Q4 is connected to the drain of the first MOS tube Q1, the gate of the first MOS tube Q1 is connected to the output end of the second operational amplifier U2 and one end of the tenth resistor R10, the non-inverting end of the second operational amplifier U2 is connected to the interrupt signal VIN, the inverting end of the second operational amplifier U2 is connected to the interrupt reference signal VREF, the other end of the third resistor R3, the other end of the sixth resistor R6, the other end of the eighth resistor R8, the other end of the ninth resistor R9, the other end of the tenth resistor R10, the other end of the sixteenth resistor R16, and the fourth pin of the third digital potentiometer U3 are connected to the ground.

[0018] Specifically, the adaptation unit includes a fifteenth resistor R15, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-sixth resistor R26, a fifth trigger U5, a sixth operational amplifier U6, a seventh operational amplifier U7, an eighth operational amplifier U8, a second transistor Q2, a fifth MOS transistor Q5, a sixth transistor Q6, a seventh MOS transistor Q7, a second capacitor C2, a collector of the second transistor Q2, and a fifth trigger U5. The first pin, the fourth pin of the fifth trigger U5, and one end of the twentieth resistor R20 are connected to the power supply, the emitter of the second triode Q2 is connected to one end of the fifteenth resistor R15, the base of the second triode Q2 is connected to the fifth pin of the fifth trigger U5 and the gate of the seventh MOS tube Q7, the source of the seventh MOS tube Q7 is connected to the other end of the twentieth resistor R20, the second pin of the fifth trigger U5 is connected to the sixth pin of the fifth trigger U5, the third pin of the fifth trigger U5 is connected to the source of the fifth MOS tube Q5 and one end of the twenty-third resistor R23, the gate of the fifth MOS tube Q5 is connected to the reset signal Prot 2, the drain of the fifth MOS tube Q5 is connected to the output end of the sixth operational amplifier U6 and the output end of the seventh operational amplifier U7, the in-phase end of the sixth operational amplifier U6 is connected to one end of the seventeenth resistor R17 and one end of the eighteenth resistor R18, the inverting end of the sixth operational amplifier U6, the in-phase end of the seventh operational amplifier U7, the other end of the fifteenth resistor R15, one end of the nineteenth resistor R19, the collector of the sixth transistor Q6, one end of the second capacitor C2 and the receiving frequency signal VOUT are connected, the drain of the seventh MOS tube Q7 is connected to the base of the sixth transistor Q6, the emitter of the sixth transistor Q6 is connected to one end of the twenty-sixth resistor R26, the inverting end of the seventh operational amplifier U7 is connected to the other end of the seventeenth resistor R17 and one end of the twenty-first resistor R21, the other end of the twenty-first resistor R21 is connected to one end of the twenty-second resistor R22, and the output end of the eighth operational amplifier U8, the inverting end of the eighth operational amplifier U8 is connected to the other end of the twenty-second resistor R22, the in-phase end of the eighth operational amplifier U8 is connected to the frequency search signal Prot 1, the other end of the eighteenth resistor R18, the other end of the nineteenth resistor R19, the other end of the twenty-third resistor R23, the other end of the twenty-sixth resistor R26, the other end of the second capacitor C2 and the ground terminal are connected.

[0019] Specifically, the reset unit includes a fourth resistor R4, a fifth resistor R5, a seventh resistor R7, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourth operational amplifier U4, and a first capacitor C1. One end of the fourth resistor R4 and one end of the eleventh resistor R11 are connected to the power supply, the other end of the fourth resistor R4 is connected to one end of the first capacitor C1, the in-phase end of the fourth operational amplifier U4, and one end of the seventh resistor R7, the inverting end of the fourth operational amplifier U4 is connected to the other end of the eleventh resistor R11 and one end of the twelfth resistor R12, the output end of the fourth operational amplifier U4, one end of the thirteenth resistor R13 and the reset signal Prot 2 are connected, one end of the fifth resistor R5 is connected to the base of the second transistor Q2, and the other end of the fifth resistor R5, the other end of the seventh resistor R7, the other end of the twelfth resistor R12, the other end of the thirteenth resistor R13, and the other end of the first capacitor C1 are connected to the ground end.

[0020] Specifically, the frequency-seeking unit also includes a second resistor R2 and a fourteenth resistor R14, one end of the second resistor R2 is connected to the power supply, the other end of the second resistor R2 is connected to the inverting end of the first operational amplifier U1 and one end of the fourteenth resistor R14, and the other end of the fourteenth resistor R14 is connected to the ground.

[0021] Specifically, the adaptation unit further includes a twenty-fourth resistor R24, one end of the twenty-fourth resistor R24 ​​is connected to the source of the seventh MOS tube Q7, and the other end of the twenty-fourth resistor R24 ​​is connected to the ground.

[0022] Specifically, the adaptation unit further includes a twenty-fifth resistor R25, one end of the twenty-fifth resistor R25 is connected to the drain of the fifth MOS tube Q5, and the other end of the twenty-fifth resistor R25 is connected to the ground.

[0023] The frequency matching end and the adjustment end both include a controller, a demodulation unit, an adaptation unit, a frequency-seeking unit, and a reset unit. The frequency matching end is used to send a current frequency-specific modulation signal to the demodulation unit. The adaptation unit also feeds back a received frequency signal VOUT to the demodulation unit. The demodulation unit demodulates the current frequency-specific signal, and the demodulation result is sent to the controller for decoding and comparison. The controller sets a specific demodulation signal corresponding to the specific modulation signal. When there is inconsistency, the frequency-seeking unit is controlled to automatically seek frequency. The frequency-seeking unit sends the currently adjusted frequency-seeking signal Prot_1 to the adaptation unit in real time. The adaptation unit performs adaptive adjustment and feeds back a received frequency signal VOUT corresponding to the current frequency-seeking signal Prot_1 to the demodulation unit for re-demodulation. When the demodulated specific modulation signal is consistent with the specific demodulation signal, the controller sends an interrupt signal VIN to the frequency-seeking unit to stop seeking frequency. Among them, when the first switch S1 is closed, the automatic frequency search is started. When VIN has no input, the output end of the second operational amplifier U2 has no output. The source power supply signal of the first MOS tube Q1 passes through the drain of the first MOS tube Q1, the anode of the fourth thyristor Q4, the sixteenth resistor R16, and the ground end loop, and the signal is fed back to the in-phase end of the first operational amplifier U1. When there is an output at the in-phase end of the first operational amplifier U1, the output signal of the output end of the first operational amplifier U1 is fed back to the base of the third transistor Q3, and the third transistor Q3 is cut off. The seventh pin of the third digital potentiometer U3 passes through the ninth resistor R9 and the ground end loop, and the direction of the fifth pin of the third digital potentiometer U3 is adjusted from the sixth pin. The voltage of the sixth resistor R6 connected to the fifth pin and the sixth pin of the third digital potentiometer U3 feeds back the frequency search signal Prot_1 to the in-phase end of the eighth operational amplifier U8. The output end of the eighth operational amplifier U8 in the adaptation unit follows the output, and the output signal passes through the twenty-first resistor R21, the seventeenth resistor R17, the eighteenth resistor R18, and the ground end loop. Among them, the The voltage at the connection end of the twenty-first resistor R21 and the seventeenth resistor R17 is fed back to the inverting end of the seventh operational amplifier U7, and the voltage at the connection end of the eighteenth resistor R18 and the seventeenth resistor R17 is fed back to the non-inverting end of the sixth operational amplifier U6. When initially powered on, the voltage at the second capacitor C2 is zero. The output signal at the output end of the seventh operational amplifier U7 is fed back through the fifth MOS tube Q5 and the twenty-third resistor R23 loop. The voltage at the twenty-third resistor R23 is fed back to the third pin of the fifth trigger U5. The output signal of the fifth pin of the fifth trigger U5 is fed back to the gate of the seventh MOS tube Q7 in one way, and is input to the base of the second triode Q2 in another way. The source to drain of the seventh MOS tube Q7 is positive voltage or lower than the negative voltage for conduction and is cut off, and the second triode Q2 is turned on. The power supply is integrated through the collector and emitter of the second triode Q2, the fifteenth resistor R15 and the second capacitor C2 and is input to the inverting end of the sixth operational amplifier U6 and the non-inverting end of the seventh operational amplifier U7. When the sixth operational amplifier U6 is cut off and the seventh operational amplifier U7 outputs after the voltage of the second capacitor C2 rises,The output signal of the seventh operational amplifier U7 is input to the third pin of the fifth trigger U5 through the drain and source of the fifth MOS tube Q5, the fifth pin of the fifth trigger U5 is cut off, the second transistor Q2 is cut off, and the seventh MOS tube Q7 is turned on, the power supply signal at the twentieth resistor R20 is input to the base of the sixth transistor Q6 through the source of the seventh MOS tube Q7 and the drain of the seventh MOS tube Q7, the sixth transistor Q6 is turned on, the second capacitor C2 is looped through the twenty-sixth resistor R26, the seventh operational amplifier U7 is cut off, and then the sixth operational amplifier U6 is turned on, and the signal is input to the seventh through the fifth MOS tube Q5 again. The third pin of the fifth trigger U5 allows the third digital potentiometer U3 to adjust the frequency during frequency search. VOUT can output the receiving frequency VOUT corresponding to the frequency search signal Prot_1 currently input to the in-phase terminal of the eighth operational amplifier U8. When the receiving frequency VOUT is consistent with the transmitting frequency, the specific modulation signal sent is decoded and compared by the controller, and then the controller outputs the interrupt signal VIN to the frequency search unit. VREF sets the corresponding reference signal according to different interrupt signal output sources. When the interrupt signal VIN is input, the second operational amplifier U2 outputs, and the signal is fed back to the gate of the first MOS tube Q1. , the first MOS tube Q1 and the fourth thyristor Q4 are turned off, the first operational amplifier U1 has no output, the power supply signal at the end of the first resistor R1 passes through the emitter, base, third resistor R3 and ground loop of the third transistor Q3, and the collector terminal voltage of the third transistor Q3 is input to the seventh pin of the third digital potentiometer U3. The third digital potentiometer U3 is turned off to complete the automatic frequency matching. When power is on, the third pin of the fifth trigger U5 needs to be pulled down to avoid uncontrollable pin state failure. The fifth MOS tube Q5 in the reset unit is used for automatic reset when power is on, and there is no need to pull down the third pin of the fifth trigger U5. Initial When powered on, the power is fed back to the first capacitor C1 through the fourth resistor R4, the eleventh resistor R11 and the twelfth resistor R12 set the reset time, the fourth operational amplifier U4 has no output, the fifth MOS tube Q5 is cut off, and when the first pin and the fourth pin of the fifth trigger U5 are powered on, the fourth operational amplifier U4 outputs the reset signal Prot_2 to the gate of the fifth MOS tube Q5, the fifth MOS tube Q5 is turned on, and the seventh operational amplifier U7 can normally input the signal to the third pin of the fifth trigger U5 until the first capacitor C1 is powered off and resets after the seventh resistor R7 loop is turned on again. The reference signal amplitude set at the inverting end of the first operational amplifier U1 is greater than the leakage current of the fourth thyristor Q4 when powered on, and the signal can be fixedly set or divided by the power supply. ,

[0024] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations within the meaning and scope of the equivalent elements of the claims be included in the invention. Any marking in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A wireless transceiver control circuit, characterized in that: It includes a frequency-binding end and an adjustment end, the adjustment end includes a controller, a demodulation unit, an adaptation unit, and a frequency-seeking unit, the adaptation unit is connected to the frequency-seeking unit, the demodulation unit, and the controller, the controller is connected to the demodulation unit and the frequency-seeking unit, the frequency-binding end is used to send a current frequency-specific modulation signal to the demodulation unit, the adaptation unit feeds back a received frequency signal VOUT to the demodulation unit, the demodulation unit feeds back the demodulation signal to the controller for decoding and comparison, the controller feeds back an interrupt signal VIN to the frequency-seeking unit, the frequency-seeking unit automatically seeks frequency according to the interrupt signal state and feeds back a frequency-seeking signal Prot_1 to the adaptation unit, the adaptation unit automatically corresponds to the received frequency signal VOUT based on the frequency-seeking signal Prot_1, and feeds back to the demodulation circuit for re-demodulation; The frequency-seeking unit comprises a first resistor, a third resistor, a sixth resistor, an eighth resistor, a ninth resistor, a tenth resistor, a sixteenth resistor, a first operational amplifier, a second operational amplifier, a third digital potentiometer, a first MOS tube, a third triode, a fourth thyristor, and a first switch; one end of the first resistor, one end of the first switch, a source of the first MOS tube, a first pin of the third digital potentiometer, a third pin of the third digital potentiometer, and an eighth pin of the third digital potentiometer are connected to a power supply; the other end of the first resistor is connected to an emitter of the third triode; the collector of the third triode is connected to a seventh pin of the third digital potentiometer and one end of the ninth resistor; the second pin of the third digital potentiometer is connected to one end of the eighth resistor; the fifth pin of the third digital potentiometer, the sixth pin of the third digital potentiometer, and one end of the sixth resistor are connected to a frequency-seeking signal Prot 1, the base of the third triode is connected to the output end of the first operational amplifier and one end of the third resistor, the non-inverting end of the first operational amplifier is connected to the cathode of the fourth thyristor and one end of the sixteenth resistor, the control electrode of the fourth thyristor is connected to the other end of the first switch, the anode of the fourth thyristor is connected to the drain of the first MOS tube, the gate of the first MOS tube is connected to the output end of the second operational amplifier and one end of the tenth resistor, the non-inverting end of the second operational amplifier is connected to the interrupt signal VIN, the inverting end of the second operational amplifier is connected to the interrupt reference signal VREF, the other end of the third resistor, the other end of the sixth resistor, the other end of the eighth resistor, the other end of the ninth resistor, the other end of the tenth resistor, the other end of the sixteenth resistor, the fourth pin of the third digital potentiometer and the ground terminal are connected.

2. The wireless transceiver control circuit according to claim 1, characterized in that: The adaptation unit includes a fifteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a twenty-third resistor, a twenty-sixth resistor, a fifth trigger, a sixth operational amplifier, a seventh operational amplifier, an eighth operational amplifier, a second triode, a fifth MOS tube, a sixth triode, a seventh MOS tube, and a second capacitor. The collector of the second triode, the first pin of the fifth trigger, the fourth pin of the fifth trigger, and one end of the twentieth resistor are connected to the power supply, the emitter of the second triode is connected to one end of the fifteenth resistor, the base of the second triode is connected to the fifth pin of the fifth trigger and the gate of the seventh MOS tube, the source of the seventh MOS tube is connected to the other end of the 20th resistor, the second pin of the fifth trigger is connected to the sixth pin of the fifth trigger, the third pin of the fifth trigger is connected to the source of the fifth MOS tube and one end of the twenty-third resistor, and the gate of the fifth MOS tube is connected to the reset signal Prot 2, the drain of the fifth MOS tube is connected to the output end of the sixth operational amplifier and the output end of the seventh operational amplifier, the non-inverting end of the sixth operational amplifier is connected to one end of the seventeenth resistor and one end of the eighteenth resistor, the inverting end of the sixth operational amplifier, the non-inverting end of the seventh operational amplifier, the other end of the fifteenth resistor, one end of the nineteenth resistor, the collector of the sixth transistor, one end of the second capacitor and the receiving frequency signal VOUT are connected, the drain of the seventh MOS tube is connected to the base of the sixth transistor, the emitter of the sixth transistor is connected to one end of the twenty-sixth resistor, the inverting end of the seventh operational amplifier is connected to the other end of the seventeenth resistor and one end of the twenty-first resistor, the other end of the twenty-first resistor is connected to one end of the twenty-second resistor and the output end of the eighth operational amplifier, the inverting end of the eighth operational amplifier is connected to the other end of the twenty-second resistor, the non-inverting end of the eighth operational amplifier is connected to the frequency search signal Prot 1, and the other end of the eighteenth resistor, the other end of the nineteenth resistor, the other end of the twenty-third resistor, the other end of the twenty-sixth resistor, the other end of the second capacitor and the ground are connected.

3. The wireless transceiver control circuit according to claim 1, characterized in that: The present invention also includes a reset unit, which is connected to the adaptation unit. The reset unit includes a fourth resistor, a fifth resistor, a seventh resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourth operational amplifier, and a first capacitor. One end of the fourth resistor and one end of the eleventh resistor are connected to a power supply, the other end of the fourth resistor is connected to one end of the first capacitor, the in-phase end of the fourth operational amplifier, and one end of the seventh resistor, the inverting end of the fourth operational amplifier is connected to the other end of the eleventh resistor and one end of the twelfth resistor, the output end of the fourth operational amplifier, one end of the thirteenth resistor are connected to a reset signal Prot 2, one end of the fifth resistor is connected to the base of the second transistor, and the other ends of the fifth resistor, the seventh resistor, the twelfth resistor, the thirteenth resistor, and the first capacitor are connected to the ground.

4. The wireless transceiver control circuit according to claim 1, characterized in that: The frequency-seeking unit also includes a second resistor and a fourteenth resistor, wherein one end of the second resistor is connected to the power supply, the other end of the second resistor is connected to the inverting end of the first operational amplifier and one end of the fourteenth resistor, and the other end of the fourteenth resistor is connected to the ground.

5. The wireless transceiver control circuit according to claim 2, characterized in that: It also includes an adaptation unit, which includes a twenty-fourth resistor, one end of the twenty-fourth resistor is connected to the source of the seventh MOS tube, and the other end of the twenty-fourth resistor is connected to the ground end.

6. The wireless transceiver control circuit according to claim 2, characterized in that: It also includes an adaptation unit, and the adaptation unit also includes a twenty-fifth resistor, one end of the twenty-fifth resistor is connected to the drain of the fifth MOS tube, and the other end of the twenty-fifth resistor is connected to the ground end.

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