Semiconductor structure, method for preparing semiconductor structure, and memory

Abstract

The present disclosure provides a semiconductor structure, a method for preparing a semiconductor structure, and a memory, relating to the field of semiconductor technology. The semiconductor structure includes: a substrate; at least one active region formed in the substrate; a bitline structure located on the substrate; a contact window located in the substrate and located on at least one side of the bitline structure; a conductive layer located above the contact window and adjacent to the bitline structure; wherein the bitline structure includes a bitline, a first isolation layer, and an air gap, wherein the first isolation layer and the air gap are located on one or both sides of the bitline where the conductive layer exists, the first isolation layer covers the sidewalls of the bitline, and the air gap is located within the first isolation layer; the bitline is electrically connected to one of the drain region and the source region of the active region, and the contact window is electrically connected to the other. The present disclosure increases the difficulty for oxygen-containing small molecules and oxygen free radicals in the air gap to be liberated to the contact window, thereby improving the problem of contact window oxidation.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for preparing the semiconductor structure, and a memory. Background Art

[0002] In semiconductor memory devices, a contact window structure is typically used to connect the active area to the storage node capacitor (or bit line) to control the charging and discharging of the capacitor through a transistor. However, during the semiconductor manufacturing process, the contact window may undergo unexpected oxidation, affecting the performance of the memory device. For example, if the contact window is made of polysilicon material, if the polysilicon oxidizes, the resulting oxide will reduce the conductivity of the contact window, causing adverse phenomena such as SBIT (single bit initiation) failure. Summary of the Invention

[0003] The present disclosure provides a semiconductor structure, a method for manufacturing the semiconductor structure, and a memory, which can solve the problem of contact window oxidation at least to a certain extent.

[0004] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising: a substrate; at least one active region formed in the substrate; a bit line structure located on the substrate; a contact window located in the substrate and located on at least one side of the bit line structure; a conductive layer located above the contact window and adjacent to the bit line structure; wherein the bit line structure comprises a bit line, a first isolation layer, and an air gap, wherein the first isolation layer and the air gap are located on one side or both sides of the bit line where the conductive layer exists, the first isolation layer covers the sidewalls of the bit line, and the air gap is located in the first isolation layer; the bit line is electrically connected to one of the drain region or the source region of the active region, and the contact window is electrically connected to the other.

[0005] Optionally, an upper surface of the contact window is flush with an upper surface of the substrate.

[0006] Optionally, an upper surface of the contact window is lower than an upper surface of the substrate, and a height difference between the upper surface of the contact window and the upper surface of the substrate is 20% to 30% of the height of the contact window.

[0007] Optionally, the semiconductor structure further includes a metal silicide layer located between the contact window and the conductive layer.

[0008] Optionally, the lower surface of the conductive layer is higher than the upper surface of the substrate.

[0009] Optionally, contact windows are provided on both sides of the bit line structure, and are electrically connected to the two source regions or the two drain regions of the active region respectively.

[0010] Optionally, the semiconductor structure includes a plurality of bit lines arranged in parallel, and the contact windows are located between two adjacent bit lines and in contact with the source region or the drain region of the active region, and are arranged in an array.

[0011] Optionally, the bit line structure further includes a second isolation layer covering a sidewall of the first isolation layer, and the conductive layer is adjacent to the second isolation layer.

[0012] Optionally, the upper surface of the conductive layer forms a pattern of landing pads.

[0013] According to a second aspect of the present disclosure, a method for preparing a semiconductor structure is provided, comprising: providing a substrate, wherein at least one active area is formed in the substrate, and a bit line structure is formed on the substrate; a groove adjacent to the bit line structure exists on at least one side of the bit line structure; the bit line structure comprises a bit line, a first isolation layer, and a third isolation layer, wherein the first isolation layer and the third isolation layer are located on one side or both sides of the groove where the bit line exists, the first isolation layer covers the sidewall of the bit line, and the third isolation layer is located within the first isolation layer; the bit line is electrically connected to one of the drain region and the source region of the active area, and the groove is in contact with the other; filling the groove with a contact material so that the upper surface of the contact material does not exceed the upper surface of the substrate to form a contact window; forming a conductive layer above the contact window; and removing the third isolation layer to form an air gap.

[0014] Optionally, filling the groove with contact material so that the upper surface of the contact material does not exceed the upper surface of the substrate to form a contact window includes: depositing contact material to fill the groove and cover the upper part of the bit line structure; and using etching to remove the contact material above the bit line structure, so that the upper surface of the contact material in the groove does not exceed the upper surface of the substrate to form the contact window.

[0015] Optionally, before or after forming the contact window, the method further includes: forming a second isolation layer on the sidewall of the first isolation layer.

[0016] Optionally, the second isolation layer is formed on the sidewalls of the first isolation layer, including: depositing a bit line protection material to cover the sidewalls of the first isolation layer and partially filling the groove to cover the bottom of the groove or the upper surface of the contact window; etching the bit line protection material to expose the bottom of the groove or the upper surface of the contact window, and the bit line protection material remaining on the sidewalls of the first isolation layer forms the second isolation layer.

[0017] Optionally, before forming the conductive layer, the method further includes: forming a metal silicide layer on top of the contact window.

[0018] According to a third aspect of the present disclosure, a memory is provided, comprising the semiconductor structure according to the first aspect.

[0019] The technical solution disclosed in this disclosure has the following beneficial effects:

[0020] On the one hand, the contact window is located within the substrate, with its upper surface not exceeding the upper surface of the substrate, while the air gap in the bitline structure is located above the substrate. This increases the distance between the air gap and the contact window, making it more difficult for oxygen-containing small molecules and oxygen free radicals in the air gap to migrate to the contact window (especially to the interface between the contact window and the conductive layer, or the interface between the contact window and the metal silicide layer). This improves the oxidation problem of the contact window (such as polysilicon), ensures the conductivity of the contact window, and reduces the occurrence of adverse conditions such as SBIT failure. On the other hand, by reducing the height of the contact window and increasing the height of the conductive layer, the conductivity of the connection structure between the active area and the storage node capacitor is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 shows a top view of a cell array region of a semiconductor memory device in this exemplary embodiment;

[0022] Figure 2 A schematic diagram of a semiconductor structure according to this exemplary embodiment is shown;

[0023] Figure 3 A schematic diagram of a semiconductor structure according to this exemplary embodiment is shown;

[0024] Figure 4 A schematic diagram of a semiconductor structure according to this exemplary embodiment is shown;

[0025] Figure 5 A schematic diagram of a semiconductor structure according to this exemplary embodiment is shown;

[0026] Figure 6 A schematic diagram of a semiconductor structure according to this exemplary embodiment is shown;

[0027] Figure 7 A flow chart showing a method for preparing a semiconductor structure in this exemplary embodiment is shown;

[0028] Figures 8 to 16 A schematic diagram illustrating a process of a method for preparing a semiconductor structure in this exemplary embodiment is shown;

[0029] Figures 17 to 23 A schematic diagram of a process for preparing a semiconductor structure in this exemplary embodiment is shown.

[0030] The reference numerals are as follows:

[0031] 101: substrate; 102: active area; 103: bit line structure; 1031: bit line; 1032: first isolation layer; 1033: air gap; 1034: second isolation layer; 1035: third isolation layer; 1036: bit line contact; 1037: bit line barrier layer; 104: contact window; 105: conductive layer; 1051: first metal layer; 1052: metal barrier layer; 1053: second metal layer; 106: metal silicide layer; 107: isolation channel; 108: word line; 109: groove. DETAILED DESCRIPTION

[0032] Exemplary embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings.

[0033] The accompanying drawings are schematic illustrations of the present disclosure and are not necessarily drawn to scale. The technical solutions of the present disclosure can be implemented in various forms and should not be construed as being limited to the examples set forth herein. The features, structures, or characteristics described in the present disclosure may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full description of the embodiments of the present disclosure. However, those skilled in the art will appreciate that one or more specific details may be omitted when implementing the technical solutions of the present disclosure, or that other methods, components, structures, etc. may be used to replace one or more specific details.

[0034] In semiconductor manufacturing, the goal is to increase the sensing margin, boosting the capacitance of memory cells while reducing the parasitic capacitance of bit lines. This is why the air gap process was introduced. Typically, a specific gas chemically reacts with the isolation material (such as SiO2) between the bit line and the node contact (NC), producing gaseous reactants that are then expelled through heat treatment or other methods, forming an air gap.

[0035] For example, NH3 / HF gas can be used to remove SiO2. A wafer can be placed in a chamber and NH3 / HF gas is introduced, causing it to adsorb onto the wafer surface and diffuse into the interior of the wafer. The wafer is heated to 20-80°C, and the following reaction occurs:

[0036] SiO2+4HF+4NH3→SiF4+2H2O+4NH3

[0037] SiF4+2HF+2NH3→(NH4)2SiF6

[0038] After the above reaction is completed, heat treatment is performed, such as heating to 100-250°C, so that the above reactants further undergo the following reactions:

[0039] (NH4)2SiF6→SiF4+2NH3+2HF

[0040] After the above treatment, SiO2 is completely converted into gas and evaporates from the wafer surface to form an air gap.

[0041] The inventors discovered that air gaps can cause oxidation of the contact window. Specifically, the aforementioned reaction produces byproducts containing reactive oxygen, such as small oxygen molecules (e.g., H2O) and oxygen free radicals, which may be adsorbed and retained in the gaps surrounding the air gap. These byproducts are gradually released over time, or released during subsequent high-temperature processes, and then liberated to the nearby contact window, where oxidation reactions occur. For example, these small oxygen molecules and oxygen free radicals can pass through the SiN layer on the sidewalls of the bit line from the air gap and liberate to the interface between the polysilicon and cobalt silicide (or metal) of the contact window, causing oxidation of the polysilicon and leading to SBIT failure.

[0042] In view of the above problems, exemplary embodiments of the present disclosure first provide a semiconductor structure, which can be a local structure in a semiconductor memory device, such as a DRAM (Dynamic Random Access Memory). A semiconductor memory device generally includes a cell array area and a peripheral area. Figure 1 shows a top view of a cell array region of a semiconductor memory device, Figure 2 Shows a cross-sectional view of the Ι-Ι' section. Figure 1 and Figure 2 As shown, the semiconductor structure in this exemplary embodiment may include: a substrate 101; at least one active area (AA) 102 formed in the substrate 101; a bit line structure 103 located on the substrate 101; a contact window 104 located in the substrate 101 and on at least one side of the bit line structure 103; and a conductive layer 105 located above the contact window 104 and adjacent to the bit line structure 103. The bit line structure 103 includes a bit line 1031, a first isolation layer 1032, and an air gap 1033. The first isolation layer 1032 and the air gap 1033 are located on one side or both sides of the bit line 1031 where the conductive layer 105 exists. The first isolation layer 1032 covers the sidewalls of the bit line 1031, and the air gap 1033 is located in the first isolation layer 1032. The bit line 1031 is electrically connected to one of the drain region and the source region of the active area 102, and the contact window 104 is electrically connected to the other.

[0043] Substrate 101 can be made of materials such as silicon (e.g., single crystal silicon, polycrystalline silicon, or amorphous silicon), germanium, a silicon-germanium compound, or a Group III-V compound (e.g., gallium arsenide). Substrate 101 can include an epitaxial layer or a silicon-on-insulator (SOI) substrate. Active regions 102 can be formed in substrate 101. Active regions 102 can include source regions, drain regions, and channel regions. Active regions 102 can be distributed in an array in substrate 101 and separated by isolation trenches 107. Isolation trenches 107 can be made of an insulating material such as SiO2.

[0044] The bitline 1031 is electrically connected to the drain or source region in the active area 102 to read the charge state of the memory cell. The bitline 1031 is made of a conductive material, such as a metal, such as tungsten, titanium, cobalt, copper, aluminum, or alloys thereof. In one embodiment, the bitline structure further includes a bitline contact (BLC) 1036, through which the bitline 1031 is electrically connected to the drain or source region in the active area 102. The bitline contact 1036 can be made of polysilicon or doped polysilicon. The bitline 1031 and the bitline contact 1036 can be in direct contact, or a bitline barrier layer 1037 can be disposed therebetween. The bitline barrier layer 1037 can prevent interdiffusion between the bitline 1031 and the bitline contact 1036 and improve the adhesion of the bitline 1031 material to the bitline contact 1036, thereby providing an adhesive bond. Exemplarily, a titanium nitride film can be used as the bitline barrier layer 1037.

[0045] Figure 1 The semiconductor memory device also shows word lines 108. The bit lines 1031 and word lines 108 extend in directions that intersect, such as being perpendicular to each other. The word lines 108 may be located within the substrate 101 to form buried word lines (BWLs).

[0046] The first isolation layer 1032 covers the sidewalls of the bit line 1031 and is used to isolate the bit line 1031 from other surrounding structures. For example, it can prevent a short circuit between the bit line 1031 and the contact window 104, and it can also prevent the bit line 1031 from reacting with other materials or being corroded. The first isolation layer 1032 can be made of an insulating material, such as silicon nitride, silicon oxide, etc. In one embodiment, the first isolation layer 1032 can also cover the top of the bit line 1031, so that the bit line 1031 is isolated from the structure above it, thereby protecting the top structure of the bit line 1031. For example, a landing pad (LP) can be formed above the bit line structure 103, and a storage node capacitor can be further formed on the landing pad. The first isolation layer 1032 separates the bit line 1031 from the landing pad and the storage node capacitor.

[0047] The air gap 1033 is located inside the first isolation layer 1032 and may be parallel to the sidewall of the bit line 1031 , so as to reduce the parasitic capacitance between the bit line 1031 and the conductive layer 105 (or the contact window 104 ).

[0048] The contact window 104 is located within the substrate 101, with its upper surface not exceeding the upper surface of the substrate 101. The contact window 104 is located on at least one side of the bitline structure 103. If the bitline 1031 is electrically connected to the drain region in the active region 102, the contact window 104 is electrically connected to the source region. If the bitline 1031 is electrically connected to the source region, the contact window 104 is electrically connected to the drain region. In one embodiment, each active region 102 includes a source region and a drain region. The contact window 104 can be formed on one side of the bitline structure 103. If the bitline 1031 is electrically connected to the drain region, the contact window 104 can be located on the side where the source region is located. In one embodiment, each active region 102 includes two source regions or two drain regions, and contact windows 104 can be formed on both sides of the bit line structure 103, electrically connected to the two source regions or the two drain regions, respectively. For example, if the bit line structure 103 is electrically connected to the drain region in the middle of the active region 102, the contact windows 104 can be located on both sides of the bit line structure 103, electrically connected to the two source regions at both ends of the active region 102. The contact windows 104 can be made of a conductive material, such as polysilicon or doped polysilicon.

[0049] In one embodiment, reference Figure 1 As shown, the semiconductor structure includes multiple parallel bit lines 1031. Contact windows 104 can be located between two adjacent bit lines 1031, contacting the source or drain region of the active area 102, and arranged in an array. Thus, one active area 102 corresponds to two memory cells, and the two memory cells share a bit line 1031, which helps to increase the density of the memory cells.

[0050] Conductive layer 105 is located above contact window 104, that is, on at least one side of bitline structure 103. Contact window 104 and conductive layer 105 form a connection structure between the active region and the storage node capacitor, used to connect the source region or drain region in active region 102 to the storage node capacitor, such as the bottom electrode of the capacitor, to achieve control of the charging and discharging of the capacitor. It should be understood that if contact window 104 is formed on both sides of bitline structure 103, conductive layer 105 is also formed on both sides of bitline structure 103. Conductive layer 105 can be made of metal, such as tungsten, titanium, cobalt, copper, aluminum, or alloys thereof, or a non-metallic conductive material. In this exemplary embodiment, the contact window 104 is controlled within the substrate 101, and its height is greatly reduced, and the height of the corresponding conductive layer 105 is greatly increased. That is, the proportion of the contact window 104 in the connection structure between the active area 102 and the storage node capacitor is reduced, and the proportion of the conductive layer 105 is increased. The resistivity of the conductive layer 105 is generally lower than that of the contact window 104, thereby improving the conductive performance of the entire connection structure.

[0051] The parasitic capacitance between the bit line 1031 and the conductive layer 105 (or the parasitic capacitance between the bit line 1031 and the contact window 104, which will not be described in detail below) can be calculated by referring to the following formula:

[0052]

[0053] Wherein, C(BL_NC) represents the parasitic capacitance between the bit line 1031 and the conductive layer 105. ε represents the dielectric constant of the medium between the bit line 1031 and the conductive layer 105. The dielectric may include a first isolation layer 1032 and an air gap 1033. Spacer THK represents the thickness of the sidewall isolation layer (i.e., the dielectric) of the bit line 1031, which may be the thickness of the first isolation layer 1032. BL THK represents the thickness (or height) of the bit line 1031, and BL Length represents the length of the bit line 1031. The product of the thickness and length of the bit line 1031 is the sidewall area of ​​the bit line 1031. Introducing the air gap 1033 can reduce the dielectric constant ε of the dielectric, thereby reducing C(BL_NC), thereby controlling the parasitic capacitance between the bit line 1031 and the conductive layer 105.

[0054] Based on the semiconductor structure of this exemplary embodiment, on the one hand, the contact window 104 is located within the substrate 101, and its upper surface does not extend beyond the upper surface of the substrate 101, while the air gap 1033 in the bitline structure 103 is located above the substrate 101. This increases the distance between the air gap 1033 and the contact window 104, making it more difficult for oxygen-containing small molecules and oxygen free radicals in the air gap 1033 to migrate to the contact window 104 (particularly to the interface between the contact window 104 and the conductive layer 105, or the interface between the contact window 104 and the metal silicide layer 106 described below). This improves the oxidation of the contact window 104 (e.g., polysilicon), ensures the conductivity of the contact window 104, and reduces the occurrence of adverse conditions such as SBIT failure. On the other hand, by reducing the height of the contact window 104 and increasing the height of the conductive layer 105, the conductivity of the connection structure between the active area 102 and the storage node capacitor is improved.

[0055] The first isolation layer 1032 and the air gap 1033 are located on one side or both sides of the bit line 1031 where the conductive layer 105 exists. That is, if the contact window 104 and the conductive layer 105 exist on one side of the bit line 1031, the first isolation layer 1032 and the air gap 1033 exist on that side of the bit line 1031; if the contact window 104 and the conductive layer 105 exist on both sides of the bit line 1031, the first isolation layer 1032 and the air gap 1033 exist on both sides of the bit line 1031. In one embodiment, the air gap 1033 can be located between the bit line 1031 and the conductive layer 105. For example, Figure 1 In the embodiment, along the sidewall of the bit line 1031, if there is a contact window 104 nearby (the presence of the contact window 104 indicates that there is a conductive layer 105 above), an air gap 1033 can be provided on the sidewall at that location. If there is no contact window 104 nearby (usually, the isolation trench 107 between the active areas 102), the air gap 1033 is not required on the sidewall at that location. This reduces the volume of the air gap 1033 along the entire sidewall of the bit line 1031, thereby alleviating the adverse effects of the air gap 1033 on the mechanical structure, electrical performance, etc.

[0056] The lower surface of the air gap 1033 can be flush with the lower surface of the bit line 1031 or the upper surface of the substrate 101, and its upper surface can be flush with the upper surface of the bit line 1031 or the upper surface of the first isolation layer 1032 to fully reduce the parasitic capacitance between the bit line 1031 and the conductive layer 105 (or the contact window 104).

[0057] In one embodiment, reference Figure 3As shown, the bitline structure 103 may further include a second isolation layer 1034. The second isolation layer 1034 covers the sidewalls of the first isolation layer 1032. The second isolation layer 1034 is located on the sidewall of the first isolation layer 1032 away from the bitline 1031 and is adjacent to the conductive layer 105. The second isolation layer 1034 functions similarly to the first isolation layer 1032. Together, the second isolation layer 1034 forms an isolation structure on the side of the bitline 1031, increasing the thickness of the sidewall isolation layer of the bitline 1031. The materials of the first isolation layer 1032 and the second isolation layer 1034 may be the same or different. For example, the materials of the first isolation layer 1032 and the second isolation layer 1034 may both be silicon nitride.

[0058] In the presence of second isolation layer 1034, the dielectric between bit line 1031 and conductive layer 105 includes first isolation layer 1032, air gap 1033, and second isolation layer 1034. In formula (1), Spacer THK is the sum of first isolation layer 1032 and second isolation layer 1034. Increasing Spacer THK further reduces C(BL_NC), thereby more effectively controlling the parasitic capacitance between bit line 1031 and conductive layer 105. Second isolation layer 1034 can also reduce short circuits between bit line 1031 and conductive layer 105.

[0059] In addition, the second isolation layer 1034 further increases the distance between the air gap 1033 and the contact window 104 , thereby further increasing the difficulty for oxygen-containing small molecules and oxygen free radicals in the air gap 1033 to be liberated to the contact window 104 , which can more effectively improve the problem of oxidation of the contact window 104 .

[0060] It should be noted that the addition of the second isolation layer 1034 reduces the width of the conductive layer 105, which generally affects the conductivity of the conductive layer 105. However, in this exemplary embodiment, reducing the height of the contact window 104 and increasing the height of the conductive layer 105 can improve the conductivity of the connection structure and compensate for the adverse effects caused by the reduced width of the conductive layer 105.

[0061] In one embodiment, reference Figure 4 As shown, the semiconductor structure may further include a metal silicide layer 106 located between the contact window 104 and the conductive layer 105, which can reduce the contact resistance between the contact window 104 and the conductive layer 105 and prevent unintended reaction or diffusion between the contact window 104 and the conductive layer 105. The metal silicide layer 106 may be made of cobalt silicide (CoSi x) and other materials. In the presence of the metal silicide layer 106, oxygen-containing small molecules and oxygen free radicals within the air gap 1033 are more likely to be liberated at the interface where the bitline structure 103, the metal silicide layer 106, and the contact window 104 meet. This is because metal atoms diffuse into the first isolation layer 1032 or the second isolation layer 1034 at this interface, reducing the compactness of the first isolation layer 1032 or the second isolation layer 1034, making it easier for oxygen-containing small molecules and oxygen free radicals to be liberated, and making the contact window 104 more susceptible to oxidation. In this exemplary embodiment, the interface where the bitline structure 103, the metal silicide layer 106, and the contact window 104 meet is located at or below the upper surface of the substrate 101. The distance between the air gap 1033 and this interface is relatively large, which increases the difficulty for oxygen-containing small molecules and oxygen free radicals to be liberated at this interface, thereby reducing the occurrence of oxidation of the contact window 104. In addition, when the second isolation layer 1034 is present, the distance between the air gap 1033 and the interface can be further increased, thereby more effectively preventing the contact window 104 from being oxidized.

[0062] In one embodiment, the upper surface of the contact window 104 may be flush with the upper surface of the substrate 101. In this way, the conductive layer 105 and other structures above the contact window 104 are located above the substrate 101, which can reduce the diffusion of materials such as the conductive layer 105 within the substrate 101 and reduce adverse effects such as short circuits between the contact window 104 or the conductive layer 105 and other structures (such as the bit line 1031 or the bit line contact).

[0063] In one embodiment, the upper surface of the contact window 104 may be lower than the upper surface of the substrate 101, and the height difference between the upper surface of the contact window 104 and the upper surface of the substrate 101 may be 20% to 30% of the height of the contact window 104. This increases the distance between the air gap 1033 and the contact window 104, while ensuring that a smaller portion of the conductive layer 105 is below the upper surface of the substrate 101. This also reduces diffusion of the conductive layer 105 within the substrate 101 and reduces the risk of short circuits between the contact window 104 or the conductive layer 105 and the bit line 1031.

[0064] In one embodiment, in the presence of the metal silicide layer 106, the lower surface of the conductive layer 105 can be higher than the upper surface of the substrate 101. The upper surface of the contact window 104 is flush with or lower than the upper surface of the substrate 101. The presence of the metal silicide layer 106 above the contact window 104 elevates the lower surface of the conductive layer 105 above the upper surface of the substrate 101. This effectively reduces diffusion into the substrate 101 and reduces the risk of short circuits between the contact window 104 or the conductive layer 105 and the bit line 1031.

[0065] In one embodiment, reference Figure 5As shown, a landing pad pattern may be formed on the upper surface of the conductive layer 105. This facilitates further forming a lower electrode of a storage node capacitor on the conductive layer 105 and forming a storage node capacitor.

[0066] In one embodiment, the conductive layer 105 may include a first metal layer 1051 at the bottom, a metal barrier layer 1052 covering the first metal layer 1051, and a second metal layer 1053 covering the metal barrier layer 1052. The first metal layer 1051, the metal barrier layer 1052, and the second metal layer 1053 may form a sandwich structure of the conductive layer 105. The materials of the first metal layer 1051 and the second metal layer 1053 may be different. The provision of these two metal layers may improve the overall conductivity of the conductive layer 105. The metal barrier layer 1052 is used to prevent interdiffusion between the first metal layer 1051 and the second metal layer 1053. For example, the first metal layer 1051 may be made of titanium, the metal barrier layer 1052 may be made of titanium nitride, and the second metal layer 1053 may be made of tungsten.

[0067] In one embodiment, the semiconductor structure may be as Figure 6 As shown, an isolation trench 107 is formed in the substrate 101 to isolate the active area 102. Materials such as SiO2 can be used. A bitline structure 103 is located on the substrate 101. In the bitline structure 103, a bitline 1031 is electrically connected to the drain (or source) in the active area 102 via a bitline contact 1036 thereunder. A bitline barrier layer 1037 is formed between the bitline structure 103 and the bitline contact 1036. The bitline 1031 can be made of tungsten, the bitline contact 1036 can be made of polysilicon, and the bitline barrier layer 1037 can be made of titanium nitride. A first isolation layer 1032 can cover the sidewalls and top of the bitline 1031, as well as the sidewalls of the bitline barrier layer 1037 and the bitline contact 1036. A second isolation layer 1034 is also formed on the sidewalls of the first isolation layer 1032. The first isolation layer 1032 and the second isolation layer 1034 can be made of the same material, such as silicon nitride. The present disclosure does not specifically limit the structure of the first isolation layer 1032. For example, its top may form a step structure during the etching process of the conductive layer 105. An air gap 1033 exists inside the first isolation layer 1032. Its upper surface may be flush with or higher than the upper surface of the bit line 1031, and its lower surface may be flush with the lower surface of the substrate 101 or the lower surface of the bit line contact 1036. Of course, the height of the lower surface of the bit line contact 1036 is different at different positions in the substrate 101. As shown in the figure, the lower surface of the air gap 1033 may be flush with the lower surface of the bit line contact 1036 above the isolation channel 107, and higher than the lower surface of the bit line contact 1036 above the active area. Figure 1, between adjacent bit lines 1031 and between adjacent isolation trenches 107, contacting both ends of the active area 102, and this area can form a groove structure. The contact window 104, the metal silicide layer 106, and the conductive layer 105 can be located in this groove structure in sequence. The contact window 104 can be made of polysilicon, and the metal silicide layer 106 can be made of cobalt silicide. The conductive layer 105 is a sandwich structure consisting of a first metal layer 1051, a metal barrier layer 1052, and a second metal layer 1053. It extends to the top of the first isolation layer 1032 and has a landing pad pattern. The first metal layer 1071 is made of titanium, the metal barrier layer 1072 is made of titanium nitride, and the second metal layer 1073 is made of tungsten.

[0068] The exemplary embodiment of the present disclosure also provides a method for preparing a semiconductor structure. Figure 7 、 Figures 8 to 16 This method will be described. Figure 7 The process of the method for preparing a semiconductor structure is shown, which may include the following steps S710 to S750:

[0069] Step S710, providing a substrate 101, wherein at least one active area 102 is formed in the substrate 101, and a bit line structure 103 is formed on the substrate 101; a groove 109 adjacent to the bit line structure 103 exists on at least one side of the bit line structure 103; the bit line structure 103 includes a bit line 1031, a first isolation layer 1032, and a third isolation layer 1035, wherein the first isolation layer 1032 and the third isolation layer 1035 are located on one side or both sides of the bit line 1031 where the groove 109 exists, the first isolation layer 1032 covers the sidewall of the bit line 1031, and the third isolation layer 1035 is located in the first isolation layer 1032; the bit line 1031 is electrically connected to one of the drain region and the source region of the active area 102, and the groove 109 is in contact with the other.

[0070] refer to Figure 8 , the active region 102 in the substrate 101 can be isolated by the isolation trench 107. The third isolation layer 1035 can be parallel to the sidewalls of the bit line 1031, that is, parallel to the sidewalls of the groove 109. The third isolation layer 1035 is used to form the air gap 1033 in the subsequent steps. Its position is the same as the position of the air gap 1033 described above. Therefore, the position of the third isolation layer 1035 is not further described. For example, its upper surface can be flush with or higher than the upper surface of the bit line 1031, and its lower surface can be flush with the lower surface of the bit line 1031 or the upper surface of the substrate 101. The third isolation layer 1035 can be made of a material that can be completely converted into a gas through a gas-phase reaction, and this material is different from the material of the first isolation layer 1032. For example, the first isolation layer 1032 is made of silicon nitride, and the third isolation layer 1035 is made of silicon oxide.

[0071] The recess 109 adjacent to the bitline structure 103 is used for the subsequent formation of the contact window 104 and the conductive layer 105. If the bitline 1031 is electrically connected to the drain region in the active region 102, the recess 109 contacts the source region. If the bitline 1031 is electrically connected to the source region, the recess 109 contacts the drain region. In one embodiment, each active region 102 includes a source region and a drain region. The recess 109 may be located on one side of the bitline structure 103. For example, if the bitline 1031 is electrically connected to the drain region, the recess 109 may be located on the side where the source region is located, contacting the source region. In one embodiment, each active region 102 includes two source regions or two drain regions. The recess 109 may be located on both sides of the bitline structure 103, contacting the two source regions or the two drain regions respectively. For example, if the bitline structure 103 is electrically connected to the drain region in the middle portion of the active region 102, the recess 109 may be located on both sides of the bitline structure 103, contacting the two source regions at both ends of the active region 102.

[0072] Figure 8 FIG1 shows that the first isolation layer 1032 only covers the sidewalls of the bit line 1031. In one embodiment, the first isolation layer 1032 may also cover the upper surface of the bit line 1031. The bit line structure 103 may refer to FIG1. Figure 9 shown.

[0073] In one embodiment, the semiconductor structure includes a plurality of parallel bit lines 1031, as described above. Figure 1 As shown, the grooves 109 can be located between two adjacent bit lines 1031 and in contact with the source region or drain region of the active area 102, and can be arranged in an array. For example, along the extension direction of the word line 108, the grooves 109 can be located between adjacent bit lines 1031, and along the extension direction of the bit line 1031, the grooves 109 can be located between adjacent isolation trenches 107.

[0074] In one embodiment, the bit line 1031 can be electrically connected to the drain region or source region in the active region 102 through the bit line contact portion 1036, and a bit line barrier layer 1037 can be provided between the two. Figure 6 shown.

[0075] The process of forming the bit line structure 103 is exemplarily described below.

[0076] In one embodiment, when forming a bitline contact hole that contacts the source or drain region of the active area 102, a conductive material such as polysilicon can be filled into the bitline contact hole to form a bitline contact portion 1036. A bitline barrier material (e.g., titanium nitride), a bitline material (e.g., tungsten), an isolation material (e.g., silicon nitride), an anti-reflective layer (e.g., carbon), and a mask layer (e.g., silicon oxynitride) can then be sequentially deposited. Photolithography and etching are then performed to retain the isolation material, bitline material, and bitline barrier material having a bitline pattern, thereby forming a first isolation layer 1032 covering the upper surface of the bitline 1031, the bitline 1031, and a bitline barrier layer 1037, respectively. Subsequently, the material for the first isolation layer 1032, the material for the third isolation layer 1035, and the material for the first isolation layer 1032 are sequentially deposited, and the material outside the sidewalls of the bitline 1031 is etched back to form a sandwich structure of the first isolation layer 1032, the third isolation layer 1035, and the first isolation layer 1032 on the sidewalls of the bitline 1031.

[0077] In step S720 , a contact material is filled in the groove 109 so that the upper surface of the contact material does not exceed the upper surface of the substrate 101 , thereby forming a contact window 104 .

[0078] The contact material refers to the material of the contact window 104, which can be polysilicon or doped polysilicon. The contact material is partially filled into the recess 109, ensuring that the upper surface of the contact material does not protrude beyond the upper surface of the substrate 101. The contact material within the recess 109 forms the contact window 104. The upper surface of the contact window 104 can be flush with or lower than the upper surface of the substrate 101. The height difference between the upper surface and the upper surface of the substrate 101 can be 20% to 30% of the height of the contact window 104.

[0079] In one embodiment, the step of filling the groove 109 with a contact material so that the upper surface of the contact material does not exceed the upper surface of the substrate 101 to form the contact window 104 may include the following steps:

[0080] Depositing a contact material to fill the groove 109 and cover the bit line structure 103;

[0081] The contact material above the bit line structure 103 is removed by etching, and the upper surface of the contact material in the groove 109 is ensured not to exceed the upper surface of the substrate 101 , so as to form a contact window 104 .

[0082] Before depositing the contact material, the upper surface of the bit line 1031 may be covered by the first isolation layer 1032 or may be exposed. Figure 9 and Figure 10As shown, contact material is deposited to completely fill recess 109 and extend beyond recess 109 to cover the entire bitline structure 103. Etching is then performed to expose the upper surface of bitline structure 103. The upper surface of the contact material within recess 109 is then leveled with or lower than the upper surface of substrate 101, forming contact window 104. This increases the distance between third isolation layer 1035 and contact window 104 and leaves sufficient space within recess 109 for the subsequently formed conductive layer 105. The etching depth of the contact material within recess 109 can be controlled by controlling etching process parameters (e.g., process time) to achieve the desired height for contact window 104. This process ensures that the upper surface of bitline structure 103 is not covered by contact material, while also facilitating control of the thickness of contact window 104 within recess 109 (i.e., the height of contact window 104).

[0083] It should be understood that Figure 10 For illustration only, the process of etching the contact material may affect other structures. For example, a portion of the first isolation layer 1032 or the third isolation layer 1035 may be etched away, thereby reducing the top width of the bit line structure 103 or thinning the first isolation layer 1032 on the side wall of the bit line 1031.

[0084] In step S730 , a conductive layer 105 is formed above the contact window 104 .

[0085] The conductive layer 105 may fill the remaining space of the groove 109 above the contact window 104 and may also extend to the area outside the groove 109 , such as covering the top of the bit line structure 103 , to form a specific pattern.

[0086] In one embodiment, the process of forming the conductive layer 105 may include: depositing a conductive material to cover the space above the contact window 104 within the recess 109 and above the bitline structure 103; and patterning the conductive material into a landing pad using photolithography and etching to obtain the conductive layer 105. The conductive material refers to the material of the conductive layer 105, and may be tungsten, titanium, cobalt, copper, aluminum, or alloys thereof. The conductive material within the recess 109 forms a connection structure with the contact window 104, and the conductive material above the bitline structure 103 may form an upper conductive structure. The conductive material may be patterned into a landing pad using photolithography and etching processes to obtain the conductive layer 105, which may be the M0 layer for subsequent formation of storage node capacitors.

[0087] In one embodiment, before forming the conductive layer 105, a metal silicide layer 106 may be formed on top of the contact window 104. The metal silicide layer 106 may be made of a material such as cobalt silicide. For example, if the contact window 104 is polycrystalline silicon, metal particles may be deposited on the upper surface of the contact window 104, and the metal and the contact window 104 may react by heat treatment to form a film layer of metal silicide, thereby obtaining the metal silicide layer 106. Alternatively, a chemical vapor deposition process may be used to directly generate metal silicide by a vapor phase reaction and deposit it on the upper surface of the contact window 104 to obtain the metal silicide layer 106. Thus, in step S730, the conductive layer 105 will be formed on the upper surface of the metal silicide layer 106. The metal silicide layer 106 can reduce the contact resistance between the contact window 104 and the conductive layer 105, and can also prevent unintended reactions or diffusion between the contact window 104 and the conductive layer 105.

[0088] Figure 11 Schematic diagram of the semiconductor structure after forming a metal silicide layer 106 and a conductive layer 105 above the contact window 104. Of course, a specific pattern such as a landing pad can also be formed on the top of the conductive layer 105.

[0089] In step S740 , the third isolation layer 1035 is removed to form an air gap 1033 .

[0090] The air gap 1033 can be formed by a gas phase reaction. For example, the third isolation layer 1035 is made of SiO2. NH3 / HF reaction gas is used to adsorb the NH3 / HF onto the SiO2 surface due to the concentration gradient and interface interaction, generating silicate-based substances. The silicate is then decomposed and desorbed by a high-temperature heat treatment, thereby forming the air gap 1033 at the location of the third isolation layer 1035. Figure 11 After the air gap 1033 is formed in the semiconductor structure, reference can be made to Figure 12 As shown, the position of the air gap 1033 is the same as that of the third isolation layer 1035 .

[0091] based on Figure 7 The illustrated method, on the one hand, controls the upper surface of contact window 104 so that it does not extend beyond the upper surface of substrate 101 during the formation of air gap 1033 on the sidewalls of contact window 104 and bit line 1031. This increases the distance between air gap 1033 and contact window 104, making it more difficult for oxygen-containing small molecules and oxygen free radicals in the air gap to migrate to the contact window (particularly to the interface between the contact window and the conductive layer, or the interface between the contact window and the metal silicide layer). This improves oxidation of the contact window (e.g., polysilicon), ensures the conductivity of the contact window, and reduces the occurrence of adverse conditions such as SBIT failure. Furthermore, the presence of air gap 1033 can reduce parasitic capacitance between bit line 1031 and conductive layer 105.

[0092] In one embodiment, before or after forming the contact window 104, the method for preparing the semiconductor structure may further include the following steps:

[0093] A second isolation layer 1034 is formed on the sidewalls of the first isolation layer 1032 .

[0094] That is, the present disclosure does not limit the order of forming the contact window 104 and forming the second isolation layer 1034. Two solutions are described below.

[0095] Solution 1: First form the contact window 104, then form the second isolation layer 1034

[0096] refer to Figure 10 or Figure 13 As shown, without forming the second isolation layer 1034, the groove 109 is filled with a contact material to form a contact window 104. Then, the second isolation layer 1034 covering the sidewall of the first isolation layer 1032 is formed. Figure 13 Further forming a second isolation layer 1034 on the basis of Figure 14 Therefore, when forming the contact window 104, due to the absence of the second isolation layer 1034, the aperture of the groove 109 is not reduced, which can ensure that the contact window 104 has a relatively sufficient contact area, improve the problem of easy open circuit between the contact window 104 and the active area 102, and facilitate the improvement of the conductive contact of the contact window 104 and the subsequent formation of an ideal interconnection structure.

[0097] From the above Figure 9 and Figure 10 As can be seen, when forming the contact window 104, the contact material in the groove 109 can be etched to control the height of the contact window 104. This etching process may also etch away the first isolation layer 1032 on the sidewall of the bit line 1031, thinning the first isolation layer 1032. This may subsequently increase the parasitic capacitance between the bit line 1031 and the conductive layer 105, or even cause a short circuit between the bit line 1031 and the contact window 104 or the conductive layer 105. The presence of the second isolation layer 1034 can compensate for the thinning of the first isolation layer 1032, thereby avoiding an increase in parasitic capacitance or a short circuit caused by the thinning of the first isolation layer 1032.

[0098] Solution 2: First form the second isolation layer 1034, then form the contact window 104

[0099] refer to Figure 15As shown, a second isolation layer 1034 may be formed on the sidewall of the first isolation layer 1032. Since there is no obstruction of the contact window 104, the bottom of the second isolation layer 1034 may extend to a lower position, for example, the lower surface of the second isolation layer 1034 may be lower than the upper surface of the substrate 101. Figure 16 As shown, the groove 109 is then partially filled with contact material to form a contact window 104. This further increases the distance between the third isolation layer 1035 and the contact window 104, that is, increases the distance between the subsequent air gap 1033 and the contact window 104, making the contact window 104 less susceptible to oxidation.

[0100] In one embodiment, forming the second isolation layer 1034 on the sidewall of the first isolation layer 1032 may include the following steps:

[0101] Depositing a bit line protection material to cover the sidewalls of the first isolation layer 1032 and partially fill the groove 109 to cover the bottom of the groove 109 or the upper surface of the contact window 104;

[0102] The bit line protection material is etched to expose the bottom of the groove 109 or the upper surface of the contact window 104 , and the bit line protection material remaining on the sidewall of the first isolation layer 1032 forms a second isolation layer 1034 .

[0103] The bit line protection material refers to the material of the second isolation layer 1034 , which may be the same as the material of the first isolation layer 1032 . For example, the bit line protection material may be silicon nitride, which serves as the material of both the first isolation layer 1032 and the second isolation layer 1034 .

[0104] During the formation of the second isolation layer 1034, the deposited bit line protection material may not only cover the sidewalls of the first isolation layer 1032, but may also cover other structures. In the first solution, when the second isolation layer 1034 is formed, the recess 109 may already be filled with the contact window 104. In this case, the deposited bit line protection material may cover the upper surface of the contact window 104. In the second solution, when the second isolation layer 1034 is formed, the recess 109 may be unfilled. In this case, the deposited bit line protection material may cover the bottom of the recess 109.

[0105] The bit line protection material covering the upper surface of the contact window 104 or the bottom of the recess 109 may affect the conductive contact of the contact window 104. Etching can be used to completely or partially remove this portion of the bit line protection material, exposing the upper surface of the contact window 104 or the bottom of the recess 109 in whole or in part. This ensures the conductive contact of the contact window 104 and subsequent interconnect structures. During the etching process, a portion of the bit line protection material located on the sidewalls of the first isolation layer 1032 may be etched away. By controlling the etching direction (e.g., increasing longitudinal etching and reducing lateral etching) or other process parameters (e.g., process time), the bit line protection material on the sidewalls of the first isolation layer 1032 is less etched, and the remaining bit line protection material forms the second isolation layer 1034.

[0106] Whether it is the above-mentioned solution one or solution two, when the second isolation layer 1034 is added, the distance from the air gap 1033 to the contact window 104 / metal silicide layer 106 interface or the contact window 104 / conductive layer 105 interface can be further increased, so that the difficulty of oxygen-containing small molecules and oxygen free radicals in the air gap 1033 to be freed to the interface is further increased, thereby more effectively improving the problem of oxidation of the contact window 104.

[0107] In one embodiment, the method for preparing the semiconductor structure can refer to Figures 17 to 23 as well as Figure 6 As shown, it includes the following processes:

[0108] refer to Figure 17 A substrate 101 is provided. An isolation trench 107 is formed in the substrate 101 to separate the active area 102. A bitline structure 103 is formed on the substrate 101. The bitline structure 103 includes a bitline 1031, a first isolation layer 1032, a third isolation layer 1035, a bitline contact 1036, and a bitline barrier layer 1037. The bitline 1031 is electrically connected to the drain (or source) in the active area 102 via the bitline contact 1036 thereunder. The bitline barrier layer 1037 is located between the bitline 1031 and the bitline contact 1036. The first isolation layer 1032 covers the sidewalls and top of the bitline 1031. The third isolation layer 1035 is located within the first isolation layer 1032 and is parallel to the sidewalls of the bitline 1031. A groove 109 is formed between adjacent bitline structures 103. The first isolation layer 1032 is made of silicon nitride, and the third isolation layer 1035 is made of silicon oxide.

[0109] refer to Figure 18 , depositing contact material to fill the groove 109 and cover the top of the bit line structure 103. Chemical mechanical polishing can be used to polish the top of the contact material flat.

[0110] refer to Figure 19, the contact material is etched so that the top of the upper surface of the contact material in the groove 109 is flush with the upper surface of the substrate 101, forming a contact window 104, and completely removing the contact material on the top of the bit line structure 103. At the same time, a portion of the first isolation layer 1032 and the third isolation layer 1035 may also be etched away, making the etched position narrower, for example Figure 19 The upper portion of the bit line structure 103 is shown to be etched and narrowed.

[0111] refer to Figure 20 Silicon nitride is deposited on the sidewalls of the first isolation layer 1032 to form a silicon nitride layer, i.e., the second isolation layer 1034. This layer thickens the first isolation layer 1032, and the two can be considered as a whole. At the same time, silicon nitride is also deposited in the groove 109, covering the top of the contact window 104.

[0112] refer to Figure 21 In order to ensure the conductive contact of the contact window 104, the silicon nitride on the top of the contact window 104 is etched to fully or partially expose the upper surface of the contact window 104, and by controlling the etching direction, the silicon nitride of the second isolation layer 1034 is etched as little as possible.

[0113] refer to Figure 22 A metal silicide layer 106 is formed on top of the contact window 104, and a conductive layer 105 is formed, which is composed of a first metal layer 1051, a metal barrier layer 1052, and a second metal layer 1053. The conductive layer 105 fills the recess 109 above the contact window 104 and extends outside the recess 109 to cover the top of the bit line structure 103. Chemical mechanical polishing can be used to polish the upper surface of the conductive layer 105 to make it smooth.

[0114] refer to Figure 23 A landing pad pattern is formed in the conductive layer 105 using photolithography and etching processes to obtain the M0 layer. This step etches away a portion of the first metal layer 1051, the metal barrier layer 1052, and the second metal layer 1053 located at the top of the conductive layer 105, and may also etch away a portion of the first isolation layer 1032 or the second isolation layer 1034.

[0115] exist Figure 23 Based on the structure, gas is introduced to react with the third isolation layer 1035, so that the third isolation layer 1035 is completely converted into gas and discharged to the outside through desorption, forming an air gap 1033 at the position of the third isolation layer 1035. Thus, the preparation of the semiconductor structure is completed. The final structure can be referred to Figure 6 Subsequently, dielectric materials such as silicon nitride may be filled between the conductive layers 105, and structures such as storage node capacitors on the upper layer may be further prepared.

[0116] The exemplary embodiment of the present disclosure further provides a memory, which may include the semiconductor structure of the exemplary embodiment, such as Figures 2 to 6 The memory may be a volatile memory such as DRAM, or a non-volatile memory such as NAND Flash (NAND Flash).

[0117] It should be understood that the present disclosure is not limited to the specific structures or methods described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof. This application is intended to cover any variations, uses, or adaptations of the technical solutions that follow the general principles of this disclosure and include common knowledge or customary technical means in the art that are not disclosed herein. The contents of this specification are to be regarded as exemplary only, and the scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate having at least one active region formed therein; a bit line structure located on the substrate; a contact window located in the substrate and on at least one side of the bit line structure; a conductive layer, located above the contact window and adjacent to the bit line structure; The bit line structure includes a bit line, a first isolation layer, and an air gap, wherein the first isolation layer and the air gap are located on one side or both sides of the bit line where the conductive layer is located, the first isolation layer covers the sidewall of the bit line, and the air gap is located within the first isolation layer; The bit line is electrically connected to one of the drain region and the source region of the active region, and the contact window is electrically connected to the other; the bit line structure also includes a second isolation layer, which covers the side wall of the first isolation layer and part of the side wall of the isolation channel, and the conductive layer is adjacent to the second isolation layer.

2. The semiconductor structure according to claim 1, wherein: An upper surface of the contact window is flush with an upper surface of the substrate.

3. The semiconductor structure according to claim 1, wherein: An upper surface of the contact window is lower than an upper surface of the substrate, and a height difference between the upper surface of the contact window and an upper surface of the substrate is 20% to 30% of a height of the contact window.

4. The semiconductor structure according to claim 1, wherein: It also includes a metal silicide layer located between the contact window and the conductive layer.

5. The semiconductor structure according to claim 4, wherein: The lower surface of the conductive layer is higher than the upper surface of the substrate. The semiconductor structure according to claim 1 , wherein: The contact windows are located on both sides of the bit line structure and are electrically connected to the two source regions or the two drain regions of the active region respectively.

7. The semiconductor structure according to claim 6, wherein: The semiconductor structure includes a plurality of bit lines arranged in parallel, and the contact windows are located between two adjacent bit lines and in contact with the source region or the drain region of the active region, and are arranged in an array.

8. The semiconductor structure according to claim 1, wherein: The upper surface of the conductive layer forms a pattern of landing pads.

9. A method for preparing a semiconductor structure, characterized in that: include: A substrate is provided, wherein at least one active area is formed in the substrate, and a bit line structure is formed on the substrate; a groove adjacent to the bit line structure exists on at least one side of the bit line structure; the bit line structure includes a bit line, a first isolation layer, and a third isolation layer, wherein the first isolation layer and the third isolation layer are located on one side or both sides of the bit line where the groove exists, the first isolation layer covers the sidewall of the bit line, and the third isolation layer is located within the first isolation layer; The bit line is electrically connected to one of the drain region and the source region of the active region, and the groove is in contact with the other one; Filling the groove with a contact material so that the upper surface of the contact material does not exceed the upper surface of the substrate to form a contact window; Before or after forming the contact window, the method further includes: depositing a bit line protection material to cover the sidewalls of the first isolation layer and partially fill the groove to cover the bottom of the groove; etching the bit line protection material to expose the bottom of the groove, and the bit line protection material remaining on the sidewalls of the first isolation layer to form a second isolation layer; forming a conductive layer above the contact window; The third isolation layer is removed to form an air gap.

10. The method according to claim 9, characterized in that Filling the groove with a contact material so that the upper surface of the contact material does not exceed the upper surface of the substrate to form a contact window includes: depositing a contact material to fill the groove and cover the bit line structure; The contact material above the bit line structure is removed by etching, and the upper surface of the contact material in the groove does not exceed the upper surface of the substrate, so as to form the contact window.

11. The method according to claim 9, characterized in that Before forming the conductive layer, the method further includes: A metal silicide layer is formed on top of the contact window.

12. A memory, characterized in that: Comprising the semiconductor structure according to any one of claims 1 to 8.

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