A rapid testing method for mass production of stamp hole modules

Abstract

The present invention discloses a mass production rapid testing method for a stamp hole module. The present invention supplies power and tests the stamp hole module through a module test base plate. The test fixture is provided with a start dial and a start button respectively electrically connected to the module test circuit. The module test circuit determines the start mode through the combination of the start dial and the start button. The start mode of the stamp hole module is quickly switched by changing the combination of the start dial and the start button. The module test circuit tests the IO signal of the stamp hole module through a test pin or a test interface. The test process of the present invention does not require welding of the stamp hole module. The present invention supplies power and connects signals to the stamp hole module through a probe of a fixture, which does not affect the final delivered appearance and circuit of the stamp hole module. The present invention realizes semi-automatic testing of the stamp hole module. The test fixture has a streamlined structure and is easy to operate. It is applied and deployed in the shipping and customer acceptance environment to meet the test use of mass production.

Description

Technical Field

[0001] The invention relates to the technical field of pre-welding testing of stamp hole modules, and in particular to a mass production rapid testing method for stamp hole modules. Background Art

[0002] Modules that integrate high-performance MPU, memory, storage and other chips often use stamp hole packaging, which ultimately needs to be welded to the product base plate. Before welding, the module must be subjected to functional, signal and electrical tests, and the test process requires switching the startup mode. A large number of external leads are required before testing. Currently, the testing of modules using stamp hole packaging is more troublesome, so it is necessary to improve it. Summary of the invention

[0003] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a mass production rapid testing method for stamp hole modules, which does not require additional wiring and is simple, convenient and fast to test and meet the requirements of mass production testing.

[0004] In order to achieve the above object, the technical solution adopted by the present invention is: a mass production rapid testing method for stamp hole modules,

[0005] Fix the stamp hole module by means of a clip set on the test fixture;

[0006] The test fixture is provided with a module test base plate. After the stamp hole module is fixed by a clip, each pin of the stamp hole module is electrically connected to the module interface of the module test base plate, and the stamp hole module is electrically connected to the module test base plate.

[0007] The stamp hole module is powered by a module test base plate, and a module test circuit is set on the module test base plate;

[0008] The test fixture is provided with a start dial and a start button, which are electrically connected to the module test circuit respectively. The module test circuit determines the start mode by the combination of the start dial and the start button, and the start mode of the stamp hole module is quickly switched by changing the combination of the start dial and the start button.

[0009] The stamp hole module is tested by a module test circuit, a plurality of test pins and test interfaces are arranged on the module test base plate, the test pins and the test interfaces are electrically connected to the module test circuit respectively, and the module test circuit tests the IO signal of the stamp hole module through the test pins or the test interface;

[0010] The test results are output through the buzzer response set on the test circuit board and the screen.

[0011] Furthermore, the module test baseboard is provided with a main control chip and a plurality of startup interfaces electrically connected to the module test circuit for accessing a storage medium, and the main control chip receives a program through the startup interface.

[0012] The module test circuit is electrically connected to the main control chip and each start-up interface respectively;

[0013] Further, it includes a power supply circuit DC_IN, through which the test fixture is powered, and a power supply conversion source is provided through a power supply pin 5V_SYS of the power supply circuit DC_IN;

[0014] The stamp hole module and the test circuit are powered by the pin 3V3_IN of the power supply circuit DC_IN. When the pin POWER_EN level is high, the pin 3V3_IN outputs a 3.3V level.

[0015] When the pin POWER_EN level is low, the pin 3V3_IN output level is 0; the MCU chip U12 of the monitoring circuit is powered through the pin CHECK_3V3.

[0016] Further, the startup dial code includes a startup signal pin group consisting of BOOT_MODE0 pin, BOOT_MODE1 pin, LCD_DATA4 pin, LCD_DATA5 pin, LCD_DATA6 pin, LCD_DATA7 pin, LCD_DATA11 pin and LCD_DATA13 pin respectively electrically connected to the buffer chip U13 of model 74LCX244MTCX;

[0017] The start button includes button SW4, button SW5, button SW6 and button SW7. The level value of the start signal pin group is preset by the SW4 dial code.

[0018] The buffer chip U13 receives switch signals from the buttons SW4, SW5, SW6 and SW7, and the buffer chip U13 determines the start mode according to the combination of the switch signals from the start buttons.

[0019] Further, it includes a self-locking switch SW6 of model SW_6P,

[0020] Before the test or in the initial state, the button SW4 is set to OFF, and the level of the start signal pin group is set to 0;

[0021] When the self-locking switch SW6 is in the released state, pin 2 and pin 3 are connected, and pin 5 and pin 6 are connected. When the self-locking switch SW6 is in the pressed state, pin 1 and pin 2 are connected, and pin 4 and pin 5 are connected.

[0022] The buffer chip U13 receives the switch signal of the self-locking switch SW6 and automatically sets,

[0023] When the pin 1G of the buffer chip U13 is at a low level, the levels of its pins 1A1 to 1A4 are synchronized to pins 1Y1 to 1Y4 respectively.

[0024] When the pin 2G of the buffer chip U13 is at a low level, the levels of its pins 2A1 to 2A4 are synchronized to the pins 2Y1 to 2Y4 respectively.

[0025] Furthermore, after the self-locking switch SW6 is pressed, its pin 4 and pin 5 are turned on, the level of the pin 4 of the button SW6 is 0, and the level of the pin 5 connected to the button SW7 is 0;

[0026] After the button SW7 is pressed, its pin 4 and pin 5 are connected, and the level of the 4th pin of the button SW7 is 0;

[0027] The pin 2G level of the buffer chip U13 is set to 0, the high levels of pins 2A1, 2A2 and 2A3 are synchronized to pins 2Y1, 2Y2 and 2Y3 respectively, the levels of pins BOOT_MODE1, LCD_DATA6 and LCD_DATA13 are set to 1, and the levels of the remaining startup signal pin groups are 0. The buffer chip U13 compares the truth table of the startup mode and concludes that the startup mode is SD card startup.

[0028] Furthermore, the module test circuit includes a monitoring circuit, in which a low-end DC current sampling circuit is provided. The current on the sampling resistor R20 of the low-end DC current sampling circuit is used as the total current consumed by the power supply input. When the power supply is normal, the current flowing through the sampling resistor is set to current, in units of A. The current flowing through the sampling resistor R20 will generate a corresponding voltage.

[0029] According to the operational amplifier virtual disconnection analysis principle, Ib-=Ib+=0,

[0030] According to the operational amplifier virtual short principle, we can get: V+=V-; (Vdgnd-V-) / R52=(V--Vout) / R76, (Vgnd-V+) / R54=V+ / R73;

[0031] Solution: Vout = (R76 / R52)*(Vgnd-Vdgnd) = (30K / 1K)*Vr20 = (30 / 1)*(R20*current), i.e. current_ADC = (30 / 1)*0.2*current;

[0032] It includes the MCU chip U12 of model PY32F002B, which converts the values ​​of voltage_ADC and current_ADC back to the values ​​of DC_IN and current, and drives the digital tube to display in real time through the relevant pins;

[0033] When the fixture is initially powered, if the converted DC_IN value is within the preset range, the MCU chip U12 controls the POWER_EN level of the pin to be high, and the pin 3V3_IN outputs normally, and the module and test-related circuits are powered and running;

[0034] When the converted DC_IN or current value exceeds the preset range, the MCU chip U12 controls the pin POWER_EN level to be low and the pin 3V3_IN output is turned off.

[0035] Further, the module test circuit includes a plurality of chips MC74HC595, and the pins BOOT_MODE0, SNVS_TAMPER7, BOOT_MODE1 and SNVS_TAMPER8 of each chip MC74HC595 or any pin suitable for level control are used as module control pins, and the remaining pins to be tested are connected from QA to QH;

[0036] The signals of pins 595_SER of multiple chips MC74HC595 are expanded into multiple signals, and the signals are read as uniformly high or uniformly low by the module pins to be tested that are electrically connected to the corresponding IO pins of the stamp hole module, that is, the IO pin test passes, and the IO signal test of the stamp hole module is completed.

[0037] Furthermore, when the module control pin SNVS_TAMPER8 of each chip MC74HC595 is at a low level, the OE pin of each chip MC74HC595 is enabled at a low level, so that the corresponding chip MC74HC595 outputs;

[0038] The pin 595_SRCLK signal level of the control chip MC74HC595 changes periodically, and serves as the SCLK pin clock of multiple chips MC74HC595;

[0039] During the rising period of the SCLK pin clock of the chip MC74HC595, the chip MC74HC595 samples its own A pin level, and the level sampled eight times is recorded as an 8-bit value. When the pin 595_RCLK signal gives the LCLK pin a high level, its own eight pins QA to QH output the 8-bit value level in parallel;

[0040] When the number of samples exceeds eight, the new sample value is output from the SQH pin of the first chip MC74HC595; the signal from the module control pin 595_SER of the first chip MC74HC595 is output to the A pin of the first chip MC74HC595, and the first chip MC74HC595 continuously samples the level of its A pin. The sample values ​​exceeding eight times are output from the SQH pin of the first chip MC74HC595 as the SQH1 signal, and the SQH1 signal is output to the A pin of the second chip MC74HC595. The second chip MC74HC595 continuously samples the level of its own A pin. The sample values ​​exceeding eight times are output from the SQH pin as the SQH2 signal to the A pin of the next chip MC74HC595, and so on.

[0041] When the signals read at all the module pins to be tested are uniformly high or uniformly low, the IO pin test passes, and the IO signal test of the stamp hole module is completed.

[0042] Compared with the prior art, the advantages of the present invention are as follows: during testing, the stamp hole module is placed in a clip, the clip automatically electrically connects the power supply pin and the signal pin of the stamp hole module, and the base plate expands multiple IO signals to test the module pins without the need for additional wiring. The start mode is quickly switched using a combination of a dial and a button without the need to modify the circuit, and the test is simple, convenient and fast.

[0043] The test process of the present invention does not require welding of the stamp hole module. The present invention supplies power and connects signals to the stamp hole module through the probe of the fixture, which does not affect the final delivered appearance and circuit of the stamp hole module. The present invention realizes semi-automatic testing of the stamp hole module, the structure of the test fixture is streamlined, the operation is simple, and it can be applied and deployed in the shipping and customer acceptance environment to meet the test use of mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a schematic diagram of the structure of the test fixture of the present invention.

[0045] Figure 2 It is a flow chart of the switching start method of the present invention.

[0046] Figure 3 It is a flow chart of the operation of the jig of the present invention.

[0047] Figure 4 It is a flow chart of the fixture of the present invention for monitoring voltage and current.

[0048] Figure 5 It is a flow chart of the module testing procedure of the present invention.

[0049] Figure 6 The invention is a circuit schematic diagram including a start-up dialing part.

[0050] Figure 7 It is a circuit schematic diagram of the present invention including a button start part. DETAILED DESCRIPTION

[0051] A mass production rapid testing method for stamp hole modules. Figures 1 to 7 As shown,

[0052] The stamp hole module is fixed by means of a clip set on the test fixture; the module test base plate is provided with a main control chip and a plurality of startup interfaces electrically connected to the module test circuit for accessing the storage medium; the main control chip receives the program through the startup interface, and the module test circuit is electrically connected to the main control chip and each startup interface respectively.

[0053] The test fixture is provided with a module test base plate. After the stamp hole module is fixed by a clip, each pin of the stamp hole module is electrically connected to the module interface of the module test base plate, and the stamp hole module is electrically connected to the module test base plate; the stamp hole module is powered by the module test base plate, and the module test base plate is provided with a module test circuit.

[0054] The module test circuit is provided with a power supply circuit DC_IN, which powers the test fixture through the power supply circuit DC_IN, and provides a power conversion source through the power supply pin 5V_SYS of the power supply circuit DC_IN; the stamp hole module and the test circuit are powered through the pin 3V3_IN of the power supply circuit DC_IN, and when the pin POWER_EN level is high, the pin 3V3_IN outputs a 3.3V level, and when the pin POWER_EN level is low, the pin 3V3_IN outputs a level of 0; the MCU chip U12 of the monitoring circuit is powered through the pin CHECK_3V3.

[0055] The test fixture is provided with a start dial and a start button, which are electrically connected to the module test circuit respectively. The module test circuit determines the start mode by the combination of the start dial and the start button, and the start mode of the stamp hole module is quickly switched by changing the combination of the start dial and the start button.

[0056] The startup dial code includes a startup signal pin group consisting of a BOOT_MODE0 pin, a BOOT_MODE1 pin, an LCD_DATA4 pin, an LCD_DATA5 pin, an LCD_DATA6 pin, an LCD_DATA7 pin, an LCD_DATA11 pin and an LCD_DATA13 pin respectively electrically connected to a buffer chip U13 of model 74LCX244MTCX;

[0057] The start button includes button SW4, button SW5, button SW6 and button SW7. The level value of the start signal pin group is preset through the SW4 dial code.

[0058] The buffer chip U13 receives switch signals from the buttons SW4, SW5, SW6 and SW7, and the buffer chip U13 determines the start mode according to the combination of the switch signals from the start buttons.

[0059] For example, Figure 1 As shown, USB or NAND startup is selected through button SW5, that is, USB startup is when released, and NAND startup is when pressed; EMMC startup or SD card startup is selected through button SW7, that is, EMMC startup is when released, and SD card startup is when pressed; button SW6 is used to select to use button SW5 or button SW7, and selecting button SW5 is effective when released, and selecting button SW7 is effective when pressed.

[0060] The module test circuit is provided with a reset button and a MODE button which are respectively electrically connected to the module test circuit. The module is reset and restarted by the reset button, and the USB startup mode is directly entered by cooperating with the reset button.

[0061] For example, the module test circuit is provided with a self-locking switch SW6 of model SW_6P.

[0062] Before testing or in the initial state, set the button SW4 to OFF, and the level of the start signal pin group is set to 0;

[0063] When the self-locking switch SW6 is in the released state, pin 2 and pin 3 are connected, and pin 5 and pin 6 are connected. When the self-locking switch SW6 is in the pressed state, pin 1 and pin 2 are connected, and pin 4 and pin 5 are connected.

[0064] The buffer chip U13 receives the switch signal of the self-locking switch SW6 and automatically sets,

[0065] When the buffer chip U13 pin is low level, the levels of pins 1A1 to 1A4 are synchronized to pins 1Y1 to 1Y4 respectively.

[0066] When the buffer chip U13 pin is low level, and the levels of its pins 2A1 to 2A4 are synchronized to pins 2Y1 to 2Y4 respectively.

[0067] After the self-locking switch SW6 is pressed, its pin 4 and pin 5 are turned on, the level of the 4th pin of the button SW6 is 0, and the level of the 5th pin connected to the button SW7 is 0;

[0068] After the button SW7 is pressed, its pin 4 and pin 5 are connected, and the level of the 4th pin of the button SW7 is 0;

[0069] Pinout of buffer chip U13 The level is set to 0, the high levels of pin 2A1, pin 2A2 and pin 2A3 are synchronized to pin 2Y1, pin 2Y2 and pin 2Y3 respectively, the levels of pin BOOT_MODE1, pin LCD_DATA6 and pin LCD_DATA13 are set to 1, and the levels of the other startup signal pin groups are 0. The buffer chip U13 compares the truth table of the startup mode and concludes that the startup mode is SD card startup.

[0070] The present invention tests the stamp hole module through a module test circuit, a module test base plate is provided with a plurality of test pins and a test interface, the test pins and the test interface are respectively electrically connected to the module test circuit, and the module test circuit tests the IO signal of the stamp hole module through the test pins or the test interface;

[0071] The test results are output through the buzzer response set on the test circuit board and the screen.

[0072] The module test circuit includes a monitoring circuit, in which a low-end DC current sampling circuit is provided. The current on the sampling resistor R20 of the low-end DC current sampling circuit is used as the total current consumed by the power supply input. When the power supply is normal, the current flowing through the sampling resistor is set to current, in A. The current flowing through the sampling resistor R20 will generate a corresponding voltage.

[0073] According to the operational amplifier virtual disconnection analysis principle, Ib-=Ib+=0,

[0074] According to the operational amplifier virtual short principle, we can get: V+=V-; (Vdgnd-V-) / R52=(V--Vout) / R76, (Vgnd-V+) / R54=V+ / R73;

[0075] Solution: Vout = (R76 / R52)*(Vgnd-Vdgnd) = (30K / 1K)*Vr20 = (30 / 1)*(R20*current), i.e. current_ADC = (30 / 1)*0.2*current;

[0076] It includes the MCU chip U12 of model PY32F002B, which converts the values ​​of voltage_ADC and current_ADC back to the values ​​of DC_IN and current, and drives the digital tube to display in real time through the relevant pins;

[0077] When the fixture is initially powered, if the converted DC_IN value is within the preset range, the MCU chip U12 controls the POWER_EN level of the pin to be high, and the pin 3V3_IN outputs normally, and the module and test-related circuits are powered and running;

[0078] When the converted DC_IN or current value exceeds the preset range, the MCU chip U12 controls the pin POWER_EN level to be low and the pin 3V3_IN output is turned off.

[0079] The module test circuit includes multiple chips MC74HC595, and the pins BOOT_MODE0, SNVS_TAMPER7, BOOT_MODE1 and SNVS_TAMPER8 of each chip MC74HC595 or any pin suitable for level control are used as module control pins, and the remaining pins to be tested are connected from QA to QH;

[0080] The signals of pins 595_SER of multiple chips MC74HC595 are expanded into multiple signals, and the signals are read as uniformly high or uniformly low by the module pins to be tested that are electrically connected to the corresponding IO pins of the stamp hole module, that is, the IO pin test passes, and the IO signal test of the stamp hole module is completed.

[0081] When the module control pin SNVS_TAMPER8 level of each chip MC74HC595 is low, The low level of the pin enables the corresponding chip MC74HC595 to output;

[0082] The pin 595_SRCLK signal level of the control chip MC74HC595 changes periodically, and serves as the SCLK pin clock of multiple chips MC74HC595;

[0083] During the rising period of the SCLK pin clock of the chip MC74HC595, the chip MC74HC595 samples its own A pin level, and the level sampled eight times is recorded as an 8-bit value. When the pin 595_RCLK signal gives the LCLK pin a high level, its own eight pins QA to QH output the 8-bit value level in parallel;

[0084] When the number of samples exceeds eight, the new sample value is output from the SQH pin of the first chip MC74HC595; the signal from the module control pin 595_SER of the first chip MC74HC595 is output to the A pin of the first chip MC74HC595, and the first chip MC74HC595 continuously samples the level of its A pin. The sample values ​​exceeding eight times are output from the SQH pin of the first chip MC74HC595 as the SQH1 signal, and the SQH1 signal is output to the A pin of the second chip MC74HC595. The second chip MC74HC595 continuously samples the level of its own A pin. The sample values ​​exceeding eight times are output from the SQH pin as the SQH2 signal to the A pin of the next chip MC74HC595, and so on.

[0085] When the signals read at all the module pins to be tested are uniformly high or uniformly low, the IO pin test passes, and the IO signal test of the stamp hole module is completed.

[0086] The fixture can monitor voltage and current. If overvoltage or overcurrent occurs, the power supply to the module and related circuits will be automatically disconnected. The test results will be responded by a buzzer and displayed on the screen.

[0087] The test process of the present invention does not require welding of the stamp hole module. The present invention supplies power and connects signals to the stamp hole module through the probe of the fixture, which does not affect the final delivered appearance and circuit of the stamp hole module. The present invention realizes semi-automatic testing of the stamp hole module, the structure of the test fixture is streamlined, the operation is simple, and it can be applied and deployed in the shipping and customer acceptance environment.

Claims

1. A mass production rapid testing method for stamp hole modules, characterized in that: Fix the stamp hole module by means of a clip set on the test fixture; The test fixture is provided with a module test base plate. After the stamp hole module is fixed by a clip, each pin of the stamp hole module is electrically contacted with the module interface of the module test base plate, and the stamp hole module is electrically connected to the module test base plate. The stamp hole module is powered by a module test base plate, and a module test circuit is set on the module test base plate; The test fixture is provided with a start dial and a start button, which are electrically connected to the module test circuit respectively. The module test circuit determines the start mode by the combination of the start dial and the start button, and the start mode of the stamp hole module is quickly switched by changing the combination of the start dial and the start button. The stamp hole module is tested by a module test circuit, a plurality of test pins and test interfaces are arranged on the module test base plate, the test pins and the test interfaces are electrically connected to the module test circuit respectively, and the module test circuit tests the IO signal of the stamp hole module through the test pins or the test interface; The test results are output through the buzzer response set on the test circuit board and the screen; The startup dial code includes a startup signal pin group consisting of a BOOT_MODE0 pin, a BOOT_MODE1 pin, an LCD_DATA4 pin, an LCD_DATA5 pin, an LCD_DATA6 pin, an LCD_DATA7 pin, an LCD_DATA11 pin and an LCD_DATA13 pin respectively electrically connected to a buffer chip U13 of model 74LCX244MTCX; The start button includes button SW4, button SW5, button SW6 and button SW7. The level value of the start signal pin group is preset through the SW4 dial code. The buffer chip U13 receives switch signals from the buttons SW4, SW5, SW6 and SW7, and the buffer chip U13 determines the start mode according to the combination of the switch signals from the start buttons.

2. A mass production rapid testing method for stamp hole modules according to claim 1, characterized in that: The module test baseboard is provided with a main control chip and a plurality of startup interfaces electrically connected to the module test circuit for accessing a storage medium. The main control chip receives a program through the startup interface. The module test circuit is electrically connected to the main control chip and each start-up interface respectively.

3. The mass production rapid testing method of stamp hole modules according to claim 1, characterized in that: It includes a power supply circuit DC_IN, which supplies power to the test fixture through the power supply circuit DC_IN, and provides a power conversion source through a power supply pin 5V_SYS of the power supply circuit DC_IN; The stamp hole module and the test circuit are powered by the pin 3V3_IN of the power supply circuit DC_IN. When the pin POWER_EN level is high, the pin 3V3_IN outputs a 3.3V level. When the pin POWER_EN level is low, the pin 3V3_IN output level is 0; the MCU chip U12 of the monitoring circuit is powered through the pin CHECK_3V3.

4. The mass production rapid testing method of stamp hole modules according to claim 1, characterized in that: Including self-locking switch SW6 model SW_6P, Before the test or in the initial state, the button SW4 is set to OFF, and the level of the start signal pin group is set to 0; When the self-locking switch SW6 is in the released state, pin 2 and pin 3 are connected, and pin 5 and pin 6 are connected. When the self-locking switch SW6 is in the pressed state, pin 1 and pin 2 are connected, and pin 4 and pin 5 are connected. The buffer chip U13 receives the switch signal of the self-locking switch SW6 and automatically sets, When the buffer chip U13 pin is low level, the levels of pins 1A1 to 1A4 are synchronized to pins 1Y1 to 1Y4 respectively. When the buffer chip U13 pin is low level, and the levels of its pins 2A1 to 2A4 are synchronized to pins 2Y1 to 2Y4 respectively.

5. The mass production rapid testing method of stamp hole modules according to claim 4, characterized in that: After the self-locking switch SW6 is pressed, its pin 4 and pin 5 are turned on, the level of the pin 4 of the button SW6 is 0, and the level of the pin 5 connected to the button SW7 is 0; After the button SW7 is pressed, its pin 4 and pin 5 are connected, and the level of the 4th pin of the button SW7 is 0; The pins of the buffer chip U13 The level is set to 0, the high levels of pin 2A1, pin 2A2 and pin 2A3 are synchronized to pin 2Y1, pin 2Y2 and pin 2Y3 respectively, the levels of pin BOOT_MODE1, pin LCD_DATA6 and pin LCD_DATA13 are set to 1, and the levels of the other startup signal pin groups are 0. The buffer chip U13 compares the truth table of the startup mode and concludes that the startup mode is SD card startup.

6. A mass production rapid testing method for stamp hole modules according to claim 5, characterized in that: The module test circuit includes a monitoring circuit, in which a low-end DC current sampling circuit is provided. The current on the sampling resistor R20 of the low-end DC current sampling circuit is used as the total current consumed by the power supply input. When the power supply is normal, the current flowing through the sampling resistor is set to current, in A. The current flowing through the sampling resistor R20 will generate a corresponding voltage. It also includes an MCU chip U12 with model number PY32F002B, which converts the values ​​of voltage_ADC and current_ADC back to the values ​​of DC_IN and current, and drives the digital tube to display in real time through the relevant pins; When the fixture is initially powered, if the converted DC_IN value is within the preset range, the MCU chip U12 controls the POWER_EN level of the pin to be high, and the pin 3V3_IN outputs normally, and the module and test-related circuits are powered and running; When the converted DC_IN or current value exceeds the preset range, the MCU chip U12 controls the pin POWER_EN level to be low and the pin 3V3_IN output is turned off.

7. A mass production rapid testing method for stamp hole modules according to any one of claims 1 to 6, characterized in that: The module test circuit includes a plurality of chips MC74HC595, and the pins BOOT_MODE0, SNVS_TAMPER7, BOOT_MODE1 and SNVS_TAMPER8 of each chip MC74HC595 or any pin suitable for level control are used as module control pins, and the remaining pins to be tested are connected from QA to QH; The signals of pins 595_SER of multiple chips MC74HC595 are expanded into multiple signals, and the signals are read as uniformly high or uniformly low by the module pins to be tested that are electrically connected to the corresponding IO pins of the stamp hole module, that is, the IO pin test passes, and the IO signal test of the stamp hole module is completed.

8. A mass production rapid testing method for stamp hole modules according to claim 7, characterized in that: When the module control pin SNVS_TAMPER8 level of each chip MC74HC595 is low, The low level of the pin enables the corresponding chip MC74HC595 to output; The pin 595_SRCLK signal level of the control chip MC74HC595 changes periodically, and serves as the SCLK pin clock of multiple chips MC74HC595; During the rising period of the SCLK pin clock of the chip MC74HC595, the chip MC74HC595 samples its own A pin level, and the level sampled eight times is recorded as an 8-bit value. When the pin 595_RCLK signal gives the LCLK pin a high level, its own eight pins QA to QH output the 8-bit value level in parallel; When the number of samples exceeds eight, the new sample value is output from the SQH pin of the first chip MC74HC595; the signal from the module control pin 595_SER of the first chip MC74HC595 is output to the A pin of the first chip MC74HC595, and the first chip MC74HC595 continuously samples the level of its A pin. The sample values ​​exceeding eight times are output from the SQH pin of the first chip MC74HC595 as the SQH1 signal, and the SQH1 signal is output to the A pin of the second chip MC74HC595. The second chip MC74HC595 continuously samples the level of its own A pin. The sample values ​​exceeding eight times are output from the SQH pin as the SQH2 signal to the A pin of the next chip MC74HC595, and so on. When the signals read at all the module pins to be tested are uniformly high or uniformly low, the IO pin test passes, and the IO signal test of the stamp hole module is completed.

Images