Infrared image processing optimization method and system for embedded systems

Abstract

The present invention discloses an infrared image processing optimization method and system for embedded systems, which relates to the field of infrared image processing optimization technology, and includes the following steps: using a configured monitoring tool to collect cache-related performance data in real time, storing the collected data in a data storage system, and preprocessing; analyzing the trend of cache performance data, and performing anomaly detection on the cache performance data. The present invention establishes an automated anomaly detection mechanism by collecting and analyzing cache performance data in real time to promptly discover cache coordination problems. When an anomaly is detected, a potential hidden danger signal is generated to notify relevant personnel to ensure system performance, especially in high-resolution infrared image processing. Cache coordination anomalies are divided into high-level and low-level failures. Through transmission frequency high-frequency index analysis, targeted optimization measures are taken, such as adjusting cache strategies, optimizing pre-fetching or increasing capacity, to improve system performance and efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of infrared image processing optimization, and in particular to an infrared image processing optimization method and system for embedded systems. Background Art

[0002] Infrared image processing optimization for embedded systems refers to designing and improving infrared image processing algorithms and technologies based on the hardware characteristics and resource limitations of embedded systems to improve image processing efficiency and effectiveness. Embedded systems usually have limited computing power and storage resources, so they need to be optimized when processing infrared images to ensure the real-time and stability of the system. This optimization method includes many aspects, such as algorithm optimization, hardware acceleration, and resource management. For example, the speed and effect of infrared image processing can be improved by simplifying image processing algorithms, using specific hardware accelerators (such as DSP or FPGA), and optimizing memory usage. These optimization measures can not only improve system performance, but also extend the battery life of the device, making embedded systems more efficient and reliable in practical applications.

[0003] When processing infrared images, embedded systems usually use multi-level cache strategies to reduce the delay and frequency of data transmission and make full use of cache resources. However, if the different levels of cache (L1, L2, L3) cannot be effectively coordinated, the existing technology cannot detect this abnormality. When this happens, data will be frequently transferred between caches, which will increase data access latency. As a result, the cache is not effectively utilized and the overall system performance will drop sharply. Especially when processing high-resolution infrared images, the frame processing speed will be significantly slowed down, and ultimately the real-time processing capability will be lost.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute the prior art that is already known to one of ordinary skill in the art. Summary of the invention

[0005] The purpose of the present invention is to provide an infrared image processing optimization method and system for embedded systems, which can collect and analyze cache performance data in real time, establish an automated anomaly detection mechanism, and promptly discover coordination problems between caches of different levels. When the system detects that there is a cache coordination anomaly when the embedded system processes infrared images, it will generate a potential hidden danger signal to notify relevant personnel to take measures to prevent system performance from degrading, especially when processing high-resolution infrared images, to ensure that the real-time processing capability of the system is not affected. In addition, the present invention divides cache coordination anomaly problems into high-level cache coordination failure and low-level cache coordination failure, and analyzes them according to the high-frequency index of transmission frequency. Through hierarchical processing and precise optimization, targeted optimization measures are taken, such as adjusting the cache replacement strategy, optimizing the pre-fetch strategy, or increasing the cache capacity, thereby improving the overall system performance and processing efficiency to solve the problems in the above-mentioned background technology.

[0006] In order to achieve the above object, the present invention provides the following technical solution: an infrared image processing optimization method for embedded systems, comprising the following steps:

[0007] Use the configured monitoring tools to collect cache-related performance data in real time, store the collected data in the data storage system, and perform preprocessing;

[0008] Analyze the trend of cache performance data, perform anomaly detection on cache performance data, establish an automated anomaly detection mechanism based on the data after anomaly detection, monitor cache performance in real time, and promptly discover potential problems where caches at different levels cannot be effectively coordinated;

[0009] After identifying the potential problems of ineffective coordination between caches at different levels, the potential problems are divided into high-level cache coordination failure and low-level cache coordination failure based on the results of the anomaly detection mechanism analysis;

[0010] For high-level cache coordination failure, a high-level cache coordination failure warning prompt is issued to notify relevant personnel to avoid further impact on system performance caused by the inability to effectively coordinate between caches. For low-level cache coordination failure, the frequency of data transmission between caches is used to determine whether the problem of cache coordination failure exists. If the problem of cache coordination failure also exists in the case of low-level cache coordination failure, a low-level cache coordination failure warning prompt is issued to notify relevant personnel to further avoid further impact on system performance caused by the inability to effectively coordinate between caches.

[0011] Preferably, the cache performance data includes cache hit rate and cache bandwidth occupancy rate. The cache hit rate refers to the ratio of the number of times the required data is successfully obtained from the cache to the total number of accesses when the processor accesses the data. The cache bandwidth occupancy rate refers to the ratio of the data transmission bandwidth between the cache and the main memory that is used. After performing anomaly detection on the cache hit rate and the cache bandwidth occupancy rate, a cache hit rate decrease index and a cache bandwidth occupancy rate increase index are generated. An automated anomaly detection mechanism is established through the cache hit rate decrease index and the cache bandwidth occupancy rate increase index, and a cache coordination anomaly coefficient is generated. The cache coordination anomaly coefficient is used to intelligently evaluate the coordination between caches of different levels.

[0012] Preferably, the cache coordination anomaly coefficient generated within a fixed detection window when the embedded system uses a multi-level cache strategy to process infrared images is compared and analyzed with a pre-set cache coordination anomaly coefficient reference threshold. If the cache coordination anomaly coefficient is greater than or equal to the cache coordination anomaly coefficient reference threshold, a potential hidden danger signal is generated, indicating that when the embedded system uses a multi-level cache strategy to process infrared images, there is a potential hidden danger that different levels of caches cannot be effectively coordinated. If the cache coordination anomaly coefficient is less than the cache coordination anomaly coefficient reference threshold, an efficient coordination signal is generated, indicating that when the embedded system uses a multi-level cache strategy to process infrared images, different levels of caches can be efficiently coordinated.

[0013] Preferably, after identifying the potential problem that the caches cannot be effectively coordinated, that is, when the embedded system uses a multi-level cache strategy to process infrared images to generate potential hidden danger signals, the generated cache coordination anomaly coefficient is compared and analyzed with the gradient reference threshold, wherein the cache coordination anomaly coefficient reference threshold is less than the gradient reference threshold, and the cache coordination situations at different levels are divided, and the specific division process is as follows:

[0014] If the cache coordination anomaly coefficient is greater than or equal to the cache coordination anomaly coefficient reference threshold and less than the gradient reference threshold, the potential problem of ineffective coordination between caches at different levels is classified as low-level cache coordination failure;

[0015] If the cache coordination anomaly coefficient is greater than or equal to the gradient reference threshold, the potential problem of ineffective coordination between caches at different levels is classified as high-level cache coordination failure.

[0016] Preferably, for low-level cache coordination failure, the specific steps of generating a transmission frequency high frequency index according to the transmission frequency of data between caches are as follows:

[0017] Collect cache transfer frequency data within a specified time window. Suppose the specified time window is T seconds, and record the number of transfers between the L1 cache and the L2 cache during this period, expressed as ,in represents the number of transmissions in the tth second;

[0018] The collected transmission frequency data Apply discrete Fourier transform (DFT) to transform to the frequency domain to detect high-frequency components. The formula for discrete Fourier transform is: , where Indicates the frequency The Fourier transform result of , p represents the imaginary unit, represents the frequency index, ranging from 0 to T−1;

[0019] Calculate the energy density of each frequency component in the frequency domain. The calculation expression is: , where Indicates frequency The energy density, Represents the amplitude of the Fourier transform result;

[0020] Calculate the total energy density in the high-frequency range separately and the total energy density of the entire frequency range , the calculation expression is: , , where Represents the frequency index threshold, which defines the starting point of high-frequency components, where The frequency is regarded as high-frequency component;

[0021] Calculate the transmission frequency high frequency index, the calculation expression is: , where Indicates the high frequency index of transmission frequency.

[0022] Preferably, for low-level cache coordination failure, the transmission frequency high-frequency index generated when the embedded system processes infrared images using a multi-level cache strategy is compared and analyzed with a preset transmission frequency high-frequency index reference threshold to determine whether there is a coordination failure problem. The determination process is as follows:

[0023] If the transmission frequency high frequency index is greater than or equal to the transmission frequency high frequency index reference threshold, a high frequency transmission signal is generated, and it is determined that there is a cache coordination failure problem when the embedded system uses a multi-level cache strategy to process infrared images under low-level cache coordination failure, and a low-level cache coordination failure warning prompt is issued to notify relevant personnel;

[0024] If the high-frequency index of the transmission frequency is less than the reference threshold of the high-frequency index of the transmission frequency, a low-frequency transmission signal is generated to determine that there is no cache coordination failure problem when the embedded system uses a multi-level cache strategy to process infrared images under low-level cache coordination failure.

[0025] Preferably, after performing anomaly detection on the cache hit rate, the steps of generating a cache hit rate reduction index are as follows:

[0026] The fixed detection window is divided into N small time periods, and each small time period is recorded as a time slice. The total number of cache accesses and cache hits within the time slice t are collected in real time, and the total number of cache accesses within the time slice t is recorded as , the number of cache hits in time slice t is recorded as , calculate the cache hit rate of each time slice, the calculation expression is: , where Indicates the cache hit rate within time slice t;

[0027] The standard deviation of cache hit rate is calculated within a fixed detection window. The calculation expression is: , where represents the standard deviation of cache hit rate within a fixed detection window, represents the mean cache hit rate within a fixed detection window, , N represents the total number of time slices within the fixed detection window;

[0028] Calculate the change in cache hit rate in each time slice. The calculation expression is: , Indicates the change in cache hit rate of time slice t relative to the previous time slice;

[0029] The cache hit rate decrease index is calculated by the cache hit rate change. The calculation expression is: , where Indicates the cache hit rate decrease index, Represents an indicator function, which is 1 when the cache hit rate change is lower than the negative value of the standard deviation, otherwise it is 0.

[0030] Preferably, after performing abnormal detection on the cache bandwidth occupancy, the steps of generating a cache bandwidth occupancy increase index are as follows:

[0031] Get the cache bandwidth occupancy data within the fixed detection window, denoted as , where i represents the i-th time point, i=1, 2, 3, 4, ..., M, and M is a positive integer;

[0032] The weighted moving average method is used to smooth the cache bandwidth usage data to reduce the impact of short-term fluctuations. The smoothing formula is: , where Indicates the smoothed cache bandwidth usage, is the weight, j represents the offset of the neighboring data points relative to the current time point i, and k represents the window size, which refers to the number of data points considered when calculating the smoothed value;

[0033] Calculate the change rate of the smoothed cache bandwidth occupancy rate. The calculation expression is: , represents the rate of change of cache bandwidth occupancy at the i-th time point;

[0034] The mean and standard deviation of the change rate of cache bandwidth occupancy are calibrated as and , use the standard score (Z-score) method to calculate the standard score at the i-th time point, and the calculation expression is: , where represents the standard score at the i-th time point;

[0035] The standard score is used to identify whether the change rate of the cache bandwidth usage at this point in time is abnormal. The identification process is as follows: , then the time point is identified as an abnormal point. , then the time point is identified as a normal point, where represents the standard score reference threshold;

[0036] Calculate the cache bandwidth usage increase index. The calculation expression is: ,in, represents the indicator function, when The value is 1 when , otherwise it is 0. Indicates the cache bandwidth usage increase index, Indicates the change in bandwidth usage of all caches within a fixed detection window The maximum value in To standardize.

[0037] Infrared image processing optimization method for embedded systems, including data acquisition and preprocessing module, anomaly detection module, potential problem classification module and cache coordination failure warning module;

[0038] The data collection and preprocessing module uses the configured monitoring tools to collect cache-related performance data in real time, stores the collected data in the data storage system, and performs preprocessing;

[0039] The anomaly detection module analyzes the trend of cache performance data, performs anomaly detection on cache performance data, establishes an automated anomaly detection mechanism based on the data after anomaly detection, monitors cache performance in real time, and promptly discovers potential problems that cannot be effectively coordinated between caches at different levels;

[0040] The potential problem classification module, after identifying the potential problems of ineffective coordination between caches at different levels, divides the potential problems into high-level cache coordination failure and low-level cache coordination failure based on the results of the anomaly detection mechanism analysis;

[0041] The cache coordination failure warning module issues a high-level cache coordination failure warning prompt to notify relevant personnel for high-level cache coordination failure, thereby avoiding further impact on system performance caused by ineffective coordination between caches. For low-level cache coordination failure, the frequency of data transmission between caches is used to determine whether the problem of cache coordination failure exists. If the problem of cache coordination failure also exists in the case of low-level cache coordination failure, a low-level cache coordination failure warning prompt is issued to notify relevant personnel, thereby further avoiding further impact on system performance caused by ineffective coordination between caches.

[0042] In the above technical solution, the technical effects and advantages provided by the present invention are:

[0043] The present invention can timely discover potential problems of ineffective coordination between caches at different levels by collecting and analyzing cache-related performance data in real time and establishing an automated anomaly detection mechanism. When the system detects that there is a potential hidden danger of ineffective coordination between caches at different levels in the process of processing infrared images by the embedded system using a multi-level cache strategy, a potential hidden danger signal will be generated to notify relevant personnel to take measures to avoid further impact on system performance caused by ineffective coordination between caches, thereby improving the stability and reliability of the system, especially when processing high-resolution infrared images, ensuring that the real-time processing capability of the system is not affected by cache coordination failure.

[0044] The present invention divides the cache coordination anomaly problem when the embedded system uses a multi-level cache strategy to process infrared images into high-level cache coordination failure and low-level cache coordination failure, and further analyzes it according to the transmission frequency high-frequency index. It can take precise optimization measures for cache coordination problems at different levels. For low-level cache coordination failure, the transmission frequency high-frequency index is generated by the transmission frequency of data between caches, and compared and analyzed with the reference threshold of the transmission frequency high-frequency index to determine whether there is a cache coordination failure problem, and issue an early warning prompt to ensure that the problem is handled in time. This hierarchical processing and precise optimization method can not only effectively solve the performance problems caused by cache coordination failure, but also take targeted measures for different types of cache failure problems, such as adjusting the cache replacement strategy, optimizing the prefetch strategy or increasing the cache capacity, thereby improving the overall performance and processing efficiency of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0046] Figure 1 The present invention is a method flow chart of the infrared image processing optimization method for embedded systems.

[0047] Figure 2 The module diagram of the infrared image processing optimization system for embedded systems of the present invention is shown in FIG. DETAILED DESCRIPTION

[0048] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that the description of the present disclosure will be more comprehensive and complete, and the concept of the example embodiments will be fully conveyed to those skilled in the art.

[0049] The present invention provides Figure 1 The infrared image processing optimization method for embedded systems shown in the figure includes the following steps:

[0050] Use the configured monitoring tools to collect cache-related performance data in real time, store the collected data in the data storage system, and perform preprocessing;

[0051] Select monitoring tools suitable for embedded systems, such as Perf, VTune, or customized embedded monitoring modules, and configure them to ensure that performance data such as the hit rate, replacement times, data transfer frequency, and write-back times of the L1, L2, and L3 caches can be collected. Configure the parameters and frequency of the monitoring tool to ensure the accuracy and timeliness of data collection. Deploy the monitoring tool to the embedded system and perform necessary tests to ensure its normal operation and the stability of data collection.

[0052] Preprocess the collected performance data, including data cleaning, formatting, aggregation, and smoothing, to remove noise and outliers and ensure data accuracy and consistency. Convert the data into a structured format, such as CSV, JSON, or SQL table, and group and summarize the data to generate performance indicator reports of various granularities. Through data smoothing, remove short-term fluctuations and highlight long-term trends for subsequent analysis.

[0053] Analyze the trend of cache performance data, perform anomaly detection on cache performance data, establish an automated anomaly detection mechanism based on the data after anomaly detection, monitor cache performance in real time, and promptly discover potential problems where caches at different levels cannot be effectively coordinated;

[0054] Cache performance data includes cache hit rate and cache bandwidth occupancy rate. The cache hit rate refers to the ratio of the number of times the required data is successfully obtained from the cache to the total number of accesses when the processor accesses the data. The cache bandwidth occupancy rate refers to the ratio of the data transmission bandwidth between the cache and the main memory that is used. After anomaly detection of the cache hit rate and cache bandwidth occupancy rate, a cache hit rate decrease index and a cache bandwidth occupancy rate increase index are generated. An automated anomaly detection mechanism is established through the cache hit rate decrease index and the cache bandwidth occupancy rate increase index, and a cache coordination anomaly coefficient is generated. The cache coordination anomaly coefficient is used to intelligently evaluate the coordination between caches of different levels.

[0055] When embedded systems use multi-level cache strategies to process infrared images, the cache hit rate of the processor when accessing data decreases significantly, indicating that there is a potential risk of ineffective coordination between caches at different levels. A decrease in cache hit rate usually means that the processor cannot find the required data in the efficient cache hierarchy, resulting in more data requests being satisfied by the slower memory hierarchy. This may be due to a variety of reasons, including improper cache replacement strategies, invalid data prefetching strategies, insufficient cache capacity, or cache line conflicts. When these factors cause critical data to stay in the cache for a shorter time or be replaced frequently, the fast access advantage of the cache is weakened and system performance is significantly reduced. Especially when processing high-load tasks such as high-resolution infrared images, this coordination failure can lead to significant processing delays and undermine the real-time processing capabilities of the system. Therefore, a decrease in cache hit rate is an important warning signal.

[0056] After performing anomaly detection on the cache hit rate, the steps to generate the cache hit rate drop index are as follows:

[0057] The fixed detection window is divided into N small time periods, and each small time period is recorded as a time slice. The total number of cache accesses and cache hits within the time slice t are collected in real time, and the total number of cache accesses within the time slice t is recorded as , the number of cache hits in time slice t is recorded as , calculate the cache hit rate of each time slice, the calculation expression is: , where Indicates the cache hit rate within time slice t;

[0058] The standard deviation of cache hit rate is calculated within a fixed detection window. The calculation expression is: , where represents the standard deviation of cache hit rate within a fixed detection window, represents the mean cache hit rate within a fixed detection window, , N represents the total number of time slices within the fixed detection window;

[0059] Calculate the change in cache hit rate in each time slice. The calculation expression is: , Indicates the change in cache hit rate of time slice t relative to the previous time slice;

[0060] The cache hit rate decrease index is calculated by the cache hit rate change. The calculation expression is: , where Indicates the cache hit rate decrease index, Represents an indicator function, which is 1 when the cache hit rate change is lower than the negative value of the standard deviation, otherwise it is 0.

[0061] When an embedded system uses a multi-level cache strategy to process infrared images, within a fixed detection window, the greater the performance value of the cache hit rate reduction index when the processor accesses data, the greater the potential hidden danger of ineffective coordination between caches at different levels. A large cache hit rate reduction index indicates that the cache hit rate is frequently and significantly reduced, indicating that the effectiveness and stability of cached data are poor, causing the processor to rely more on slower memory access, which in turn causes performance bottlenecks. Conversely, the smaller the performance value of the cache hit rate reduction index, the more stable the cache hit rate, the better the coordination between cache levels, and the higher the residence time and availability of data in the cache, indicating that the potential coordination problems between caches at different levels are smaller, and the overall system performance is relatively stable and efficient.

[0062] When the embedded system uses a multi-level cache strategy to process infrared images, the proportion of data transmission bandwidth used between the cache and the main memory increases significantly, indicating that there may be potential risks of ineffective coordination between caches at different levels. The reason is that the purpose of cache design is to reduce frequent access to the main memory, thereby reducing data access latency and improving system performance. If the data transmission bandwidth occupancy rate between the cache and the main memory increases significantly, it means that the cache fails to effectively store and hit the required data, resulting in frequent access to the main memory by the system. This situation is usually caused by low cache hit rate, improper cache replacement strategy or insufficient cache capacity, reflecting that the multi-level cache fails to work in coordination, thus failing to give full play to the advantages of the cache, resulting in a decrease in the overall performance of the system. This performance degradation is particularly obvious when processing high-resolution infrared images, because a large amount of data needs to be frequently processed and accessed, and cache failure will seriously affect the real-time processing capability. Therefore, the increase in data transmission bandwidth occupancy rate is an important early warning signal.

[0063] After performing anomaly detection on the cache bandwidth usage, the steps to generate the cache bandwidth usage increase index are as follows:

[0064] Get the cache bandwidth occupancy data within the fixed detection window, denoted as , where i represents the i-th time point, i=1, 2, 3, 4, ..., M, and M is a positive integer;

[0065] The weighted moving average method is used to smooth the cache bandwidth usage data to reduce the impact of short-term fluctuations. The smoothing formula is: , where Indicates the smoothed cache bandwidth usage, is the weight, j represents the offset of the adjacent data point relative to the current time point i, and k represents the window size, which refers to the number of data points considered when calculating the smoothing value. Generally, k is selected between 2 and 5;

[0066] Calculate the change rate of the smoothed cache bandwidth occupancy rate. The calculation expression is: , represents the rate of change of cache bandwidth occupancy at the i-th time point;

[0067] The mean and standard deviation of the change rate of cache bandwidth occupancy are calibrated as and , use the standard score (Z-score) method to calculate the standard score at the i-th time point, and the calculation expression is: , where represents the standard score at the i-th time point;

[0068] The standard score is used to identify whether the change rate of the cache bandwidth usage at this point in time is abnormal. The identification process is as follows: , then the time point is identified as an abnormal point. , then the time point is identified as a normal point, where represents the standard score reference threshold;

[0069] Calculate the cache bandwidth usage increase index. The calculation expression is: ,in, represents the indicator function, when The value is 1 when , otherwise it is 0. Indicates the cache bandwidth usage increase index, Indicates the change in bandwidth usage of all caches within a fixed detection window The maximum value in To standardize.

[0070] When an embedded system uses a multi-level cache strategy to process infrared images, within a fixed detection window, the greater the cache bandwidth occupancy, the greater the potential risk of ineffective coordination between caches at different levels. A high cache bandwidth occupancy means that the system frequently needs to obtain data from the main memory instead of the cache, indicating a low cache hit rate or improper cache management strategy, resulting in the ineffective cache operation. Conversely, a smaller cache bandwidth occupancy indicates good coordination between caches at different levels, and the cache can effectively store and provide data, thereby reducing access to the main memory, showing that the system performance is well optimized.

[0071] The anomaly detection mechanism, which is not specifically limited here, can reduce the cache hit rate by an exponential amount. and cache bandwidth utilization rate increase index Perform comprehensive analysis to generate cache coordination anomaly coefficients In order to realize the technical solution of the present invention, the present invention provides a specific implementation method;

[0072] Cache coordination anomaly coefficient The resulting calculation formula is: , where , They are cache hit rate decrease index and cache bandwidth utilization rate increase index The preset scaling factor of , Both are greater than 0.

[0073] According to the cache coordination anomaly coefficient, within a fixed detection window, the larger the performance value of the cache hit rate decrease index and the cache bandwidth occupancy rate increase index generated when the embedded system uses a multi-level cache strategy to process infrared images, that is, the larger the performance value of the cache coordination anomaly coefficient generated within the fixed detection window, the greater the potential hidden danger of ineffective coordination between caches of different levels, and vice versa.

[0074] The cache coordination anomaly coefficient generated in a fixed detection window when the embedded system uses a multi-level cache strategy to process infrared images is compared and analyzed with the pre-set cache coordination anomaly coefficient reference threshold. If the cache coordination anomaly coefficient is greater than or equal to the cache coordination anomaly coefficient reference threshold, a potential hidden danger signal is generated, indicating that there is a potential hidden danger that different levels of caches cannot be effectively coordinated when the embedded system uses a multi-level cache strategy to process infrared images. If the cache coordination anomaly coefficient is less than the cache coordination anomaly coefficient reference threshold, an efficient coordination signal is generated, indicating that different levels of caches can be efficiently coordinated when the embedded system uses a multi-level cache strategy to process infrared images.

[0075] After identifying the potential problems of ineffective coordination between caches at different levels, the potential problems are divided into high-level cache coordination failure and low-level cache coordination failure based on the results of the anomaly detection mechanism analysis;

[0076] After identifying the potential problem that the caches cannot be effectively coordinated, that is, when the embedded system uses a multi-level cache strategy to process infrared images to generate potential hidden danger signals, the generated cache coordination anomaly coefficient is compared and analyzed with the gradient reference threshold, where the cache coordination anomaly coefficient reference threshold is less than the gradient reference threshold, and the cache coordination situations at different levels are divided. The specific division process is as follows:

[0077] If the cache coordination anomaly coefficient is greater than or equal to the cache coordination anomaly coefficient reference threshold and less than the gradient reference threshold, the potential problem of ineffective coordination between caches at different levels is classified as low-level cache coordination failure;

[0078] If the cache coordination anomaly coefficient is greater than or equal to the gradient reference threshold, the potential problem of ineffective coordination between caches at different levels is classified as high-level cache coordination failure.

[0079] For high-level cache coordination failure, a high-level cache coordination failure warning is issued to notify relevant personnel to avoid further impact on system performance caused by ineffective coordination between caches. For low-level cache coordination failure, the frequency of data transmission between caches is used to determine whether the cache coordination failure problem exists. If the cache coordination failure problem also exists in the case of low-level cache coordination failure, a low-level cache coordination failure warning is issued to notify relevant personnel to further avoid further impact on system performance caused by ineffective coordination between caches.

[0080] In response to the failure of advanced cache coordination, an advanced cache coordination failure warning is issued to inform relevant personnel to avoid further impact on system performance caused by the inability to effectively coordinate between caches. Relevant personnel can take the following measures:

[0081] First, optimize the cache replacement strategy and adopt more efficient algorithms such as the adaptive replacement algorithm (ARC) to improve the cache hit rate; second, adjust and optimize the data prefetch strategy, analyze the data access pattern, improve the prefetch algorithm, and improve the effectiveness of prefetched data; third, increase the capacity of the advanced cache (L2, L3 cache) to accommodate more data and reduce cache overflow and replacement frequency; in addition, improve data consistency management and adopt more efficient cache consistency protocols (such as MESI protocol) to ensure the consistency and synchronization of cache data; finally, monitor and adjust the cache line mapping strategy to reduce cache line conflicts and optimize cache utilization efficiency. The comprehensive implementation of these measures can effectively solve the problem of advanced cache coordination failure and improve system performance.

[0082] When embedded systems use multi-level cache strategies to process infrared images, there are potential anomalies between caches at different levels that cannot be effectively coordinated, which will cause the frequency of data transmission between caches to increase. The reason is that the goal of cache design is to reduce the frequency of access to main memory and increase the speed of data access. When caches at different levels fail to coordinate effectively, the cache hit rate decreases, and the data in the cache is frequently replaced and reloaded, causing the system to continuously transfer data between caches at different levels to meet the needs of the processor. This frequent data transmission not only increases transmission latency, but also occupies a large amount of bandwidth resources, further reducing the overall performance and real-time processing capabilities of the system.

[0083] For low-level cache coordination failure, the specific steps of generating a transmission frequency high-frequency index based on the data transmission frequency between caches are as follows:

[0084] Collect cache transfer frequency data within a specified time window. Suppose the specified time window is T seconds, and record the number of transfers between the L1 cache and the L2 cache during this period, expressed as ,in represents the number of transmissions in the tth second;

[0085] The collected transmission frequency data Apply discrete Fourier transform (DFT) to transform to the frequency domain to detect high-frequency components. The formula for discrete Fourier transform is: , where Indicates the frequency The Fourier transform result of , p represents the imaginary unit, represents the frequency index, ranging from 0 to T−1;

[0086] Calculate the energy density of each frequency component in the frequency domain. The calculation expression is: , where Indicates frequency The energy density, Represents the amplitude of the Fourier transform result;

[0087] Calculate the total energy density in the high-frequency range separately and the total energy density of the entire frequency range , the calculation expression is: , , where Indicates the frequency index threshold, which defines the starting point of the high-frequency component. The frequency index threshold is usually selected within the upper quarter of the total frequency. The specific value can be determined based on experience or system characteristics. The frequency is regarded as high-frequency component;

[0088] Calculate the transmission frequency high frequency index, the calculation expression is: , where Indicates the high frequency index of transmission frequency.

[0089] The higher the frequency of data transfer between caches, the more serious the potential problem of ineffective coordination between caches at different levels. Frequent data transfer means low cache hit rate, and the cache fails to effectively keep the required data, causing the processor to frequently obtain data from low-level cache or main memory. This not only increases data access latency, but also increases the bandwidth burden of cache and main memory, ultimately leading to a decrease in overall system performance, especially when processing high-resolution infrared images, where real-time processing capabilities are significantly weakened. Therefore, high transmission frequency is an important indicator of cache coordination failure.

[0090] In view of the low-level cache coordination failure, the transmission frequency high-frequency index generated when the embedded system uses the multi-level cache strategy to process infrared images is compared and analyzed with the preset transmission frequency high-frequency index reference threshold to determine whether there is a coordination failure problem. The judgment process is as follows:

[0091] If the transmission frequency high frequency index is greater than or equal to the transmission frequency high frequency index reference threshold, a high frequency transmission signal is generated, and it is determined that there is a cache coordination failure problem when the embedded system uses a multi-level cache strategy to process infrared images under low-level cache coordination failure, and a low-level cache coordination failure warning prompt is issued to notify relevant personnel;

[0092] If the high-frequency index of the transmission frequency is less than the reference threshold of the high-frequency index of the transmission frequency, a low-frequency transmission signal is generated to determine that there is no cache coordination failure problem when the embedded system uses a multi-level cache strategy to process infrared images under low-level cache coordination failure.

[0093] In view of the problem of cache coordination failure when the embedded system uses a multi-level cache strategy to process infrared images due to low-level cache coordination failure, the relevant personnel are informed to further avoid further impact on system performance caused by the inability to effectively coordinate between caches. The relevant personnel can take the above measures, which are not described in detail here.

[0094] The present invention can timely discover potential problems of ineffective coordination between caches at different levels by collecting and analyzing cache-related performance data in real time and establishing an automated anomaly detection mechanism. When the system detects that there is a potential hidden danger of ineffective coordination between caches at different levels in the process of processing infrared images by the embedded system using a multi-level cache strategy, a potential hidden danger signal will be generated to notify relevant personnel to take measures to avoid further impact on system performance caused by ineffective coordination between caches, thereby improving the stability and reliability of the system, especially when processing high-resolution infrared images, ensuring that the real-time processing capability of the system is not affected by cache coordination failure.

[0095] The present invention divides the cache coordination anomaly problem when the embedded system uses a multi-level cache strategy to process infrared images into high-level cache coordination failure and low-level cache coordination failure, and further analyzes it according to the transmission frequency high-frequency index. It can take precise optimization measures for cache coordination problems at different levels. For low-level cache coordination failure, the transmission frequency high-frequency index is generated by the transmission frequency of data between caches, and compared and analyzed with the reference threshold of the transmission frequency high-frequency index to determine whether there is a cache coordination failure problem, and issue an early warning prompt to ensure that the problem is handled in time. This hierarchical processing and precise optimization method can not only effectively solve the performance problems caused by cache coordination failure, but also take targeted measures for different types of cache failure problems, such as adjusting the cache replacement strategy, optimizing the prefetch strategy or increasing the cache capacity, thereby improving the overall performance and processing efficiency of the system.

[0096] The present invention provides Figure 2 The infrared image processing optimization method for embedded systems shown includes a data acquisition and preprocessing module, an anomaly detection module, a potential problem division module, and a cache coordination failure warning module;

[0097] The data collection and preprocessing module uses the configured monitoring tools to collect cache-related performance data in real time, stores the collected data in the data storage system, and performs preprocessing;

[0098] The anomaly detection module analyzes the trend of cache performance data, performs anomaly detection on cache performance data, establishes an automated anomaly detection mechanism based on the data after anomaly detection, monitors cache performance in real time, and promptly discovers potential problems that cannot be effectively coordinated between caches at different levels;

[0099] The potential problem classification module, after identifying the potential problems of ineffective coordination between caches at different levels, divides the potential problems into high-level cache coordination failure and low-level cache coordination failure based on the results of the anomaly detection mechanism analysis;

[0100] The cache coordination failure warning module issues a high-level cache coordination failure warning prompt to inform relevant personnel for high-level cache coordination failure, so as to avoid further impact on system performance caused by ineffective coordination between caches. For low-level cache coordination failure, the frequency of data transmission between caches is used to determine whether the cache coordination failure problem exists. If the cache coordination failure problem also exists in the case of low-level cache coordination failure, a low-level cache coordination failure warning prompt is issued to inform relevant personnel, so as to further avoid further impact on system performance caused by ineffective coordination between caches.

[0101] The infrared image processing optimization method for embedded systems provided in an embodiment of the present invention is implemented by the above-mentioned infrared image processing optimization system for embedded systems. The specific methods and processes of the infrared image processing optimization system for embedded systems are detailed in the embodiment of the infrared image processing optimization method for embedded systems, which will not be repeated here.

[0102] The above formulas are all dimensionless and numerical calculations. The formula is a formula for the most recent real situation obtained by collecting a large amount of data and performing software simulation. The preset parameters in the formula are set by technicians in this field according to actual conditions.

[0103] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0104] The above description is only by way of illustration of certain exemplary embodiments of the present invention. It is undoubted that those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. An infrared image processing optimization method for embedded systems, characterized in that: The following steps are involved: Use the configured monitoring tools to collect cache-related performance data in real time, store the collected data in the data storage system, and perform preprocessing; Analyze the trend of cache performance data, perform anomaly detection on cache performance data, establish an automated anomaly detection mechanism based on the data after anomaly detection, monitor cache performance in real time, and promptly discover potential problems that cannot be effectively coordinated between caches at different levels; After identifying the potential problems of ineffective coordination between caches at different levels, the potential problems are divided into high-level cache coordination failure and low-level cache coordination failure based on the results of the anomaly detection mechanism analysis; For high-level cache coordination failure, a high-level cache coordination failure warning is issued to notify relevant personnel to avoid further impact on system performance caused by ineffective coordination between caches. For low-level cache coordination failure, the frequency of data transmission between caches is used to determine whether the cache coordination failure problem exists. If the cache coordination failure problem also exists in the case of low-level cache coordination failure, a low-level cache coordination failure warning is issued to notify relevant personnel to further avoid further impact on system performance caused by ineffective coordination between caches. Cache performance data includes cache hit rate and cache bandwidth occupancy rate. Cache hit rate refers to the ratio of the number of times the required data is successfully obtained from the cache to the total number of accesses when the processor accesses the data. Cache bandwidth occupancy rate refers to the ratio of the data transmission bandwidth between the cache and the main memory that is occupied. After performing anomaly detection on the cache hit rate and cache bandwidth occupancy rate, a cache hit rate decrease index and a cache bandwidth occupancy rate increase index are generated. An automated anomaly detection mechanism is established through the cache hit rate decrease index and the cache bandwidth occupancy rate increase index, and a cache coordination anomaly coefficient is generated. The cache coordination anomaly coefficient is used to intelligently evaluate the coordination between caches at different levels. The cache coordination anomaly coefficient generated in a fixed detection window when the embedded system uses a multi-level cache strategy to process infrared images is compared and analyzed with a preset cache coordination anomaly coefficient reference threshold. If the cache coordination anomaly coefficient is greater than or equal to the cache coordination anomaly coefficient reference threshold, a potential hidden danger signal is generated, indicating that there is a potential hidden danger that different levels of caches cannot be effectively coordinated when the embedded system uses a multi-level cache strategy to process infrared images. If the cache coordination anomaly coefficient is less than the cache coordination anomaly coefficient reference threshold, an efficient coordination signal is generated, indicating that different levels of caches can be efficiently coordinated when the embedded system uses a multi-level cache strategy to process infrared images. After identifying the potential problem that the caches cannot be effectively coordinated, that is, when the embedded system uses a multi-level cache strategy to process infrared images to generate potential hidden danger signals, the generated cache coordination anomaly coefficient is compared and analyzed with the gradient reference threshold, where the cache coordination anomaly coefficient reference threshold is less than the gradient reference threshold, and the cache coordination situations at different levels are divided. The specific division process is as follows: If the cache coordination anomaly coefficient is greater than or equal to the cache coordination anomaly coefficient reference threshold and less than the gradient reference threshold, the potential problem of ineffective coordination between caches at different levels is classified as low-level cache coordination failure; If the cache coordination anomaly coefficient is greater than or equal to the gradient reference threshold, the potential problem of ineffective coordination between caches at different levels is classified as high-level cache coordination failure; For low-level cache coordination failure, the specific steps of generating a transmission frequency high-frequency index based on the data transmission frequency between caches are as follows: Collect cache transfer frequency data within a specified time window. Suppose the specified time window is T seconds, and record the transfer frequency between the L1 cache and the L2 cache during this period, expressed as ,in represents the transmission frequency at the tth second; The collected transmission frequency data Apply discrete Fourier transform and convert to frequency domain to detect high-frequency components. The formula of discrete Fourier transform is: , where Indicates the frequency The Fourier transform result of , p represents the imaginary unit, represents the frequency index, ranging from 0 to T−1; Calculate the energy density of each frequency component in the frequency domain. The calculation expression is: , where Indicates frequency The energy density, Represents the amplitude of the Fourier transform result; Calculate the total energy density in the high-frequency range separately and the total energy density of the entire frequency range , the calculation expression is: , , where Represents the frequency index threshold, which defines the starting point of high-frequency components, where The frequency is regarded as high-frequency component; Calculate the transmission frequency high frequency index, the calculation expression is: , where Indicates the high frequency index of transmission frequency.

2. The infrared image processing optimization method for embedded systems according to claim 1, characterized in that: In view of the low-level cache coordination failure, the transmission frequency high-frequency index generated when the embedded system uses the multi-level cache strategy to process infrared images is compared and analyzed with the preset transmission frequency high-frequency index reference threshold to determine whether there is a coordination failure problem. The judgment process is as follows: If the transmission frequency high frequency index is greater than or equal to the transmission frequency high frequency index reference threshold, a high frequency transmission signal is generated, and it is determined that there is a cache coordination failure problem when the embedded system uses a multi-level cache strategy to process infrared images under low-level cache coordination failure, and a low-level cache coordination failure warning prompt is issued to notify relevant personnel; If the high-frequency index of the transmission frequency is less than the reference threshold of the high-frequency index of the transmission frequency, a low-frequency transmission signal is generated to determine that there is no cache coordination failure problem when the embedded system uses a multi-level cache strategy to process infrared images under low-level cache coordination failure.

3. The infrared image processing optimization method for embedded systems according to claim 1, characterized in that: After performing anomaly detection on the cache hit rate, the steps to generate the cache hit rate drop index are as follows: The fixed detection window is divided into N small time periods, and each small time period is recorded as a time slice. The total number of cache accesses and cache hits within the time slice t are collected in real time, and the total number of cache accesses within the time slice t is recorded as , the number of cache hits in time slice t is recorded as , calculate the cache hit rate of each time slice, the calculation expression is: , where Indicates the cache hit rate within time slice t; The standard deviation of cache hit rate is calculated within a fixed detection window. The calculation expression is: , where represents the standard deviation of cache hit rate within a fixed detection window, represents the mean cache hit rate within a fixed detection window, , N represents the total number of time slices within the fixed detection window; Calculate the change in cache hit rate in each time slice. The calculation expression is: , Indicates the change in cache hit rate of time slice t relative to the previous time slice; The cache hit rate decrease index is calculated by the cache hit rate change. The calculation expression is: , where Indicates the cache hit rate decrease index, Represents an indicator function, which is 1 when the cache hit rate change is lower than the negative value of the standard deviation, otherwise it is 0.

4. The infrared image processing optimization method for embedded systems according to claim 1, characterized in that: After performing anomaly detection on the cache bandwidth usage, the steps to generate the cache bandwidth usage increase index are as follows: Get the cache bandwidth occupancy data within the fixed detection window, denoted as , where i represents the i-th time point, i=1, 2, 3, 4, ..., M, and M is a positive integer; The weighted moving average method is used to smooth the cache bandwidth usage data to reduce the impact of short-term fluctuations. The smoothing formula is: , where Indicates the smoothed cache bandwidth occupancy, is the weight, j represents the offset of the neighboring data points relative to the current time point i, and k represents the window size, which refers to the number of data points considered when calculating the smoothed value; Calculate the change rate of the smoothed cache bandwidth occupancy rate. The calculation expression is: , represents the rate of change of cache bandwidth occupancy at the i-th time point; The mean and standard deviation of the change rate of cache bandwidth occupancy are calibrated as and , use the standard score method to calculate the standard score at the i-th time point, the calculation expression is: , where represents the standard score at the i-th time point; The standard score is used to identify whether the change rate of the cache bandwidth usage at this point in time is abnormal. The identification process is as follows: , then the time point is identified as an abnormal point. , then the time point is identified as a normal point, where represents the standard score reference threshold; Calculate the cache bandwidth usage increase index. The calculation expression is: ,in, represents the indicator function, when The value is 1 when , otherwise it is 0. Indicates the cache bandwidth usage increase index, Indicates the change in bandwidth usage of all caches within a fixed detection window The maximum value in To standardize.

5. An infrared image processing optimization system for embedded systems, used to implement the infrared image processing optimization method for embedded systems as described in any one of claims 1 to 4, characterized in that: It includes data collection and preprocessing module, anomaly detection module, potential problem classification module and cache coordination failure warning module; The data collection and preprocessing module uses the configured monitoring tools to collect cache-related performance data in real time, stores the collected data in the data storage system, and performs preprocessing; The anomaly detection module analyzes the trend of cache performance data, performs anomaly detection on cache performance data, establishes an automated anomaly detection mechanism based on the data after anomaly detection, monitors cache performance in real time, and promptly discovers potential problems that cannot be effectively coordinated between caches at different levels; The potential problem classification module, after identifying the potential problems of ineffective coordination between caches at different levels, divides the potential problems into high-level cache coordination failure and low-level cache coordination failure based on the results of the anomaly detection mechanism analysis; The cache coordination failure warning module issues a high-level cache coordination failure warning prompt to notify relevant personnel for high-level cache coordination failure, thereby avoiding further impact on system performance caused by ineffective coordination between caches. For low-level cache coordination failure, the frequency of data transmission between caches is used to determine whether the problem of cache coordination failure exists. If the problem of cache coordination failure also exists in the case of low-level cache coordination failure, a low-level cache coordination failure warning prompt is issued to notify relevant personnel, thereby further avoiding further impact on system performance caused by ineffective coordination between caches.

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