Power device and preparation method, power module, power conversion circuit and vehicle

Abstract

The present invention discloses a power device and a preparation method, a power module, a power conversion circuit and a vehicle. The power device comprises: a substrate of a first doping type; an epitaxial layer is located on one side of the substrate, and the epitaxial layer has the same doping type as the substrate; a first doping type region and a well region are located on the surface of the epitaxial layer away from the substrate; the well region comprises a first sub-region and a second sub-region connected to each other, the first sub-region is located on a side of the first doping type region adjacent to the substrate, the first doping type region has a first side and a second side opposite in a first direction, and the second sub-region is located on the second side of the first doping type region; the well region is of a second doping type; a gate oxide layer is located on a side of the well region away from the substrate, and the gate oxide layer covers the second sub-region and part of the first doping type region; a gate is located on a side of the gate oxide layer away from the substrate, and the gate oxide covers part of the gate oxide layer, and the vertical projection of the gate on the substrate coincides with the vertical projection of the second sub-region on the substrate. The present invention can reduce parasitic capacitance and improve device performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] In common power devices, in conventional metal oxide semiconductor field effect transistors (MOSFETs), the gate arrangement will increase the parasitic capacitance between the gate and the JFET region and the N+ region, causing overshoot during high frequency, resulting in increased losses. The current improvement method is to use a self-aligned design for the MOSFET, with the gate divided into two parts for design, to reduce the parasitic capacitance with the JFET region. In this structure, the parasitic capacitance between the gate and the N+ region is still large, which will increase the parasitic capacitance between the source and the drain. Summary of the invention

[0003] The present invention provides a power device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, which can reduce parasitic capacitance and improve device performance.

[0004] According to one aspect of the present invention, there is provided a power device, comprising:

[0005] A substrate, the substrate being of a first doping type;

[0006] An epitaxial layer, the epitaxial layer is located on one side of the substrate, and the epitaxial layer and the substrate have the same doping type; a first doping type region and a well region are located on the surface of the epitaxial layer away from the substrate; the well region includes a first sub-region and a second sub-region connected to each other, the first sub-region is located on a side of the first doping type region adjacent to the substrate; the first doping type region has a first side and a second side opposite to each other in a first direction, the first direction is the direction from the first doping type region to the second sub-region, and is perpendicular to the direction from the substrate to the epitaxial layer; the second sub-region is located on the second side of the first doping type region; the well region is of the second doping type;

[0007] A gate oxide layer, the gate oxide layer is located at a side of the well region away from the substrate, and the gate oxide layer covers the second sub-region and a portion of the first doping type region;

[0008] The gate is located at a side of the gate oxide layer away from the substrate, the gate covers a portion of the gate oxide layer, and a vertical projection of the gate on the substrate coincides with a vertical projection of the second sub-region on the substrate.

[0009] Optionally, the power device further includes:

[0010] A second doping type region, the second doping type region is located on a surface of the epitaxial layer away from the substrate; the second doping type region is located on a first side of the first doping type region, and the second doping type region and the first doping type region are in contact with each other;

[0011] A vertical projection of the first sub-region on the substrate coincides with a vertical projection of the second doping type region and the first doping type region on the substrate.

[0012] Optionally, the number of the second doping type region, the first doping type region and the well region is two; and the region between the two well regions is a JFET region;

[0013] The gate oxide layer includes a first gate oxide layer and a second gate oxide layer; the first gate oxide layer covers the second sub-region of a well region and a partial region of a first doping type region, and the second gate oxide layer covers the second sub-region of another well region and a partial region of another first doping type region;

[0014] The gate includes a first gate and a second gate, the first gate is located on a side of the first gate oxide layer away from the substrate, and the vertical projection of the first gate on the substrate coincides with the vertical projection of the second sub-region of a well region on the substrate; the second gate is located on a side of the second gate oxide layer away from the substrate, and the vertical projection of the second gate on the substrate coincides with the vertical projection of the second sub-region of another well region on the substrate.

[0015] Optionally, the power device further includes:

[0016] The mask layer is located on a side of the epitaxial layer away from the substrate, the mask layer is located between the first gate oxide layer and the second gate oxide layer, and the mask layer is located between the first gate electrode and the second gate electrode.

[0017] Optionally, the power device further includes:

[0018] A planarization layer, the planarization layer is located on a side of the gate away from the substrate;

[0019] When the power device does not include a mask layer, the planarization layer covers the gate, the gate oxide layer not covered by the gate, and the area between the first gate oxide layer and the second gate oxide layer and the area between the first gate and the second gate;

[0020] When the power device includes a mask layer, the planarization layer covers the gate, the mask layer and the gate oxide layer not covered by the gate.

[0021] Optionally, the power device further includes:

[0022] a first electrode and a second electrode;

[0023] The first electrode is located on a side of the substrate away from the epitaxial layer, and covers the substrate; the second electrode is located on a side of the planarization layer away from the substrate, and covers the planarization layer, the second doping type region and part of the first doping type region.

[0024] Optionally, the power device further includes:

[0025] A packaging structure, the packaging structure comprising a passivation layer and a protective layer;

[0026] The passivation layer is located on a side of the second electrode away from the substrate, and a vertical projection of the passivation layer on the substrate does not overlap with a vertical projection of the planarization layer on the substrate;

[0027] The protection layer is located on a side of the passivation layer away from the substrate, and covers the passivation layer and a side wall of the passivation layer away from the edge.

[0028] According to another aspect of the present invention, a power module is provided, comprising a substrate and a power device according to any embodiment of the present invention, wherein the substrate is used for supporting the power device.

[0029] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0030] The power conversion circuit includes a circuit board and a power device according to any embodiment of the present invention, and the power device is electrically connected to the circuit board.

[0031] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit according to any embodiment of the present invention, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0032] According to another aspect of the present invention, there is provided a method for preparing a power device, comprising:

[0033] An epitaxial layer is formed on one side of a substrate; the substrate is of a first doping type; the epitaxial layer and the substrate have the same doping type;

[0034] A well region is formed on the surface of the epitaxial layer away from the substrate; the well region includes a first sub-region and a second sub-region connected to each other; the well region is of the second doping type;

[0035] forming a gate oxide sublayer on a side of the well region away from the substrate; the gate oxide sublayer covers the well region;

[0036] forming a gate sublayer on a side of the gate oxide sublayer away from the substrate;

[0037] A first doping type region is formed on a surface of the epitaxial layer away from the substrate; wherein the first sub-region is located on a side of the first doping type region adjacent to the substrate; the first doping type region has a first side and a second side opposite to each other in a first direction, the first direction being a direction from the first doping type region to the second sub-region and being perpendicular to a direction from the substrate to the epitaxial layer; the second sub-region is located on a second side of the first doping type region;

[0038] Removing part of the gate sublayer to form a gate; the gate covers part of the gate oxide sublayer, and a vertical projection of the gate on the substrate coincides with a vertical projection of the second subregion on the substrate;

[0039] The gate oxide sublayer is etched to form a gate oxide layer; the gate oxide layer covers the second sub-region and a portion of the first doping type region.

[0040] Optionally, before forming a well region on a surface of the epitaxial layer away from the substrate, the method includes:

[0041] forming a first mask plate on a side of the epitaxial layer away from the substrate;

[0042] patterning a first mask;

[0043] Performing ion implantation of a second doping type into the epitaxial layer through the patterned first mask plate to form a second doping type region;

[0044] removing the first mask plate;

[0045] A well region is formed on a surface of the epitaxial layer away from the substrate, including:

[0046] forming a second mask plate on a side of the epitaxial layer away from the substrate;

[0047] Patterning the second mask plate; wherein the patterned second mask plate is the mask layer;

[0048] Ions of the second doping type are implanted into the epitaxial layer through the patterned second mask plate to form a well region.

[0049] Optionally, forming a first doping type region on a surface of the epitaxial layer away from the substrate includes:

[0050] Using the gate sublayer and the mask layer as mask plates, ions of the first doping type are implanted into the epitaxial layer to form a first doping type region.

[0051] Optionally, before etching the gate oxide sublayer to form the gate oxide layer, the method further includes:

[0052] removing the patterned second mask;

[0053] A planarization sublayer is formed on a side of the gate away from the substrate; the planarization sublayer covers the gate, the gate oxide sublayer not covered by the gate, and the area of ​​the removed second mask;

[0054] Etching the gate oxide sublayer to form a gate oxide layer includes:

[0055] The planarization sublayer and the gate oxide sublayer are etched simultaneously to form a planarization layer and a gate oxide layer; the gate oxide layer covers the second subregion and part of the first doping type region, and the planarization layer covers the gate, the gate oxide layer not covered by the gate, and the area of ​​the removed second mask.

[0056] Optionally, before etching the gate oxide sublayer to form the gate oxide layer, the method further includes:

[0057] A planarization sublayer is formed on a side of the gate away from the substrate; the planarization sublayer covers the gate, the mask layer, and the gate oxide sublayer not covered by the gate;

[0058] Etching the gate oxide sublayer to form a gate oxide layer includes:

[0059] The planarization sublayer and the gate oxide sublayer are etched simultaneously to form a planarization layer and a gate oxide layer; the gate oxide layer covers the second subregion and part of the first doping type region, and the planarization layer covers the gate, the mask layer and the gate oxide layer not covered by the gate.

[0060] The technical solution of the embodiment of the present invention provides a power device comprising: a substrate, the substrate is of a first doping type; an epitaxial layer, the epitaxial layer is located on one side of the substrate, and the epitaxial layer and the substrate have the same doping type; a first doping type region and a well region are located on a surface of the epitaxial layer away from the substrate; the well region comprises a first sub-region and a second sub-region connected to each other, the first sub-region is located on a side of the first doping type region adjacent to the substrate; the first doping type region has a first side and a second side opposite to each other in a first direction, the first direction is a direction from the first doping type region to the second sub-region, and is perpendicular to a direction from the substrate to the epitaxial layer; the second sub-region is located in the first doping type region, The second side of the impurity type region; the well region is of the second doping type; the gate oxide layer, the gate oxide layer is located on the side of the well region away from the substrate, the gate oxide layer covers the second sub-region and part of the first doping type region; the gate, the gate is located on the side of the gate oxide layer away from the substrate, the gate covers part of the gate oxide layer, the vertical projection of the gate on the substrate coincides with the vertical projection of the second sub-region on the substrate, so that the vertical projection of the gate on the substrate does not overlap with the vertical projections of the first doping type region and the JFET region on the substrate, which can reduce the parasitic capacitance between the gate and the JFET region and the first doping type region to the greatest extent, reduce device loss, and improve device performance.

[0061] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0063] Figure 1 It is a schematic diagram of a power device provided by an embodiment of the present invention.

[0064] Figure 2 It is a schematic diagram of another power device provided by an embodiment of the present invention.

[0065] Figure 3 It is a flow chart of a method for preparing a power device provided by an embodiment of the present invention.

[0066] Figure 4 It is a schematic diagram of an intermediate structure of a power device provided by an embodiment of the present invention.

[0067] Figure 5 It is an intermediate flow chart of a method for preparing a power device provided by an embodiment of the present invention.

[0068] Figure 6 It is a schematic diagram of an intermediate structure of another power device provided by an embodiment of the present invention.

[0069] Figure 7 It is a detailed flow chart in S120.

[0070] Figure 8 It is a schematic diagram of an intermediate structure of another power device provided by an embodiment of the present invention.

[0071] Fig. 9 It is a schematic diagram of an intermediate structure of another power device provided by an embodiment of the present invention.

[0072] Fig.10 It is a schematic diagram of an intermediate structure of another power device provided by an embodiment of the present invention.

[0073] Fig.11 It is a schematic diagram of an intermediate structure of another power device provided by an embodiment of the present invention.

[0074] Fig.12 It is an intermediate flow chart of another method for preparing a power device provided in an embodiment of the present invention.

[0075] Fig.13 It is a schematic diagram of an intermediate structure of another power device provided by an embodiment of the present invention.

[0076] Fig.14 It is a schematic diagram of an intermediate structure of another power device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0077] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0078] It should be noted that the terms "first", "second", etc. in the present invention are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0079] An embodiment of the present invention provides a power device, Figure 1 is a schematic diagram of a power device provided by an embodiment of the present invention, with reference to Figure 1 , power devices include:

[0080] The substrate 10 is of the first doping type; the epitaxial layer 20 is located on one side of the substrate 10, and the epitaxial layer 20 has the same doping type as the substrate 10; the first doping type region 40 and the well region 30 are located on the surface of the epitaxial layer 20 away from the substrate 10; the well region 30 includes a first sub-region 31 and a second sub-region 32 connected to each other, and the first sub-region 31 is located on a side of the first doping type region 40 adjacent to the substrate 10; the first doping type region 40 has a first side and a second side opposite to each other in a first direction, and the first direction is the direction from the first doping type region 40 to the second sub-region The second sub-region 32 is located in the direction of the first doping type region 40, and is perpendicular to the direction of the substrate 10 pointing to the epitaxial layer 20; the second sub-region 32 is located on the second side of the first doping type region 40; the well region 30 is of the second doping type; the gate oxide layer 60 is located on the side of the well region 30 away from the substrate 10, and the gate oxide layer 60 covers the second sub-region 32 and a portion of the first doping type region 40; the gate 70 is located on the side of the gate oxide layer 60 away from the substrate 10, and the gate 70 covers a portion of the gate oxide layer 60, and the vertical projection of the gate 70 on the substrate 10 coincides with the vertical projection of the second sub-region 32 on the substrate 10.

[0081] The power device may be a MOSFET device. If the device is an N-type device, the first doping type is N-type, and the second doping type is P-type; if the device is a P-type device, the first doping type is P-type, and the second doping type is N-type. Exemplarily, if the device is an N-type device, the substrate 10 is an N+ substrate, such as an N+ silicon carbide substrate; the epitaxial layer 20 is an N-epitaxial layer, such as an N-silicon carbide epitaxial layer; the well region 30 may be a P-type well region (PW region), and the PW region may be formed by injecting P-type ions into the well region 30. The P-type ions may be aluminum (Al) ions or boron (B) ions, and the concentration may be 10 14 ~10 18 / cm3 The region between the two well regions 30 is the JFET region 21; the first doping type region 40 is an N+ region, and the N+ region can be formed by injecting N-type ions into the first doping type region 40, and the N-type ions can be phosphorus (P) ions or nitrogen (N) ions, and the concentration can be 10 17 ~10 21 / cm 3 If the device is a P-type device, the substrate 10 is a P+ substrate, and the epitaxial layer 20 is a P-epitaxial layer. The gate oxide layer 60 may be a silicon dioxide layer, and the gate 70 may be made of molybdenum (Mo) or tungsten (W).

[0082] In the prior art, since the vertical projection of the gate 70 on the substrate 10 covers the vertical projections of the first doping type region 40 and the JFET region 21 on the substrate 10, the parasitic capacitance between the gate 70 and the first doping type region 40 and the JFET region 21 is relatively large, which causes overshoot during high-frequency processing, resulting in increased losses; while in the embodiment of the present invention, since the vertical projection of the gate 70 on the substrate 10 coincides with the vertical projection of the second sub-region 32 of the well region 30 on the substrate 10, the vertical projection of the gate 70 on the substrate 10 does not overlap with the vertical projections of the first doping type region 40 and the JFET region 21 on the substrate 10, the parasitic capacitance between the gate and the JFET region 21 and the first doping type region 40 can be minimized, the device loss can be reduced, and the device performance can be improved.

[0083] The technical solution of the embodiment of the present invention provides a power device including: a substrate 10, the substrate 10 is of a first doping type; an epitaxial layer 20, the epitaxial layer 20 is located on one side of the substrate 10, and the epitaxial layer 20 has the same doping type as the substrate 10; a first doping type region 40 and a well region 30 are located on the surface of the epitaxial layer 20 away from the substrate 10; the well region 30 includes a first sub-region 31 and a second sub-region 32 connected to each other, the first sub-region 31 is located on a side of the first doping type region 40 adjacent to the substrate 10; the first doping type region 40 has a first side and a second side opposite to each other in a first direction, the first direction is the direction from the first doping type region 40 to the second sub-region 32, and is perpendicular to the direction from the substrate 10 to the epitaxial layer 20; the second sub-region 32 is located in the first doping type region 40. The second side of the region 40; the well region 30 is of the second doping type; the gate oxide layer 60, the gate oxide layer 60 is located on the side of the well region 30 away from the substrate 10, and the gate oxide layer 60 covers the second sub-region 32 and a portion of the first doping type region 40; the gate 70, the gate 70 is located on the side of the gate oxide layer 60 away from the substrate 10, the gate 70 covers a portion of the gate oxide layer 60, and the vertical projection of the gate 70 on the substrate 10 coincides with the vertical projection of the second sub-region 32 on the substrate 10, so that the vertical projection of the gate 70 on the substrate 10 does not overlap with the vertical projections of the first doping type region 40 and the JFET region 21 on the substrate 10, which can reduce the parasitic capacitance between the gate and the JFET region 21 and the first doping type region 40 to the greatest extent, reduce device loss, and improve device performance.

[0084] Optional, reference Figure 1 The power device also includes: a second doping type region 50, the second doping type region 50 is located on the surface of the epitaxial layer 20 away from the substrate 10; the second doping type region 50 is located on the first side of the first doping type region 40, and the second doping type region 50 and the first doping type region 40 are in contact with each other; the vertical projection of the first sub-region 31 on the substrate 10 coincides with the vertical projection of the second doping type region 50 and the first doping type region 40 on the substrate 10.

[0085] If the device is an N-type device, the second doping type region 50 may be a P+ region, and the P-type ions doped in the second doping type region 50 may be aluminum (Al) ions or boron (B) ions, and the concentration may be 10 17 ~10 21 / cm 3 The second doping type region 50 is used to improve the conductivity of the device, form a good contact area, and improve the performance of the device.

[0086] Optional, reference Figure 1, the number of the second doping type region 50, the first doping type region 40 and the well region 30 is two; the region between the two well regions 30 is the JFET region 21; the gate oxide layer 60 includes a first gate oxide layer 61 and a second gate oxide layer 62; the first gate oxide layer 61 covers the second sub-region 32 of one well region 30 and a partial region of the first doping type region 40, and the second gate oxide layer 62 covers the second sub-region 32 of another well region 30 and a partial region of the other first doping type region 40; the gate 70 includes a first gate 71 and a second gate 72, the first gate 71 is located on a side of the first gate oxide layer 61 away from the substrate 10, and the vertical projection of the first gate 71 on the substrate 10 coincides with the vertical projection of the second sub-region 32 of one well region 30 on the substrate 10; the second gate 72 is located on a side of the second gate oxide layer 62 away from the substrate 10, and the vertical projection of the second gate 72 on the substrate 10 coincides with the vertical projection of the second sub-region 32 of another well region 30 on the substrate 10.

[0087] Among them, the first gate 71 is located on the side of the first gate oxide layer 61 away from the substrate 10, and the vertical projection of the first gate 71 on the substrate 10 coincides with the vertical projection of the second sub-region 32 of a well region 30 on the substrate 10; the second gate 72 is located on the side of the second gate oxide layer 62 away from the substrate 10, and the vertical projection of the second gate 72 on the substrate 10 coincides with the vertical projection of the second sub-region 32 of another well region 30 on the substrate 10, so that the vertical projections of the first gate 71 and the second gate 72 on the substrate 10 do not overlap with the vertical projections of the first doping type region 40 and the JFET region on the substrate 10, which can reduce the parasitic capacitance between the gate and the JFET region and the first doping type region 40 to the greatest extent, reduce device loss, and improve device performance.

[0088] Optional, Figure 2 is a schematic diagram of another power device provided by an embodiment of the present invention, with reference to Figure 2 The power device further includes: a mask layer 110 , the mask layer 110 is located on a side of the epitaxial layer 20 away from the substrate 10 , the mask layer 110 is located between the first gate oxide layer 61 and the second gate oxide layer 62 , and the mask layer 110 is located between the first gate 71 and the second gate 72 .

[0089] The material of the mask layer 110 may be silicon nitride (SiNx) material, and the mask layer 110 may be used as a mask plate for forming the well region 30 . There is no need to remove the mask layer 110 later, which can simplify the process flow. Figure 1 For the structure after removing the mask layer 110 , it is possible to prevent hydrogen (H) ions in the mask layer 110 from diffusing into the epitaxial layer 20 , thereby preventing the electrical properties of the device from being affected and improving the reliability of the device.

[0090] Optional, reference Figure 1 and Figure 2The power device further includes: a planarization layer 80, the planarization layer 80 is located on a side of the gate 70 away from the substrate 10; Figure 1 , when the power device does not include the mask layer 110, the planarization layer 80 covers the gate 70, the gate oxide layer 60 not covered by the gate 70, and the area between the first gate oxide layer 61 and the second gate oxide layer 62 and the area between the first gate 71 and the second gate 72; Figure 2 When the power device includes the mask layer 110 , the planarization layer 80 covers the gate 70 , the mask layer 60 , and the gate oxide layer 60 not covered by the gate 70 .

[0091] The material of the planarization layer 80 may be silicon dioxide, and the planarization layer may play a role of insulation and isolation.

[0092] Optional, reference Figure 1 and Figure 2 The power device also includes: a first electrode 91 and a second electrode 92; the first electrode 91 is located on a side of the substrate 10 away from the epitaxial layer 20, and the first electrode 91 covers the substrate 10; the second electrode 92 is located on a side of the planarization layer 80 away from the substrate 10, and the second electrode 92 covers the planarization layer 80, the second doping type region 50 and a portion of the first doping type region 40.

[0093] The first electrode may be a drain electrode, and the second electrode may be a source electrode; the materials of the first electrode 91 and the second electrode 92 may be titanium, titanium nitride or aluminum; the thickness of the first electrode 91 and the second electrode 92 may be set thicker to reduce resistance.

[0094] Optionally, the power device also includes: a packaging structure 100, the packaging structure 100 includes a passivation layer 101 and a protective layer 102; the passivation layer 101 is located on the side of the second electrode 92 away from the substrate 10, and the vertical projection of the passivation layer 101 on the substrate 10 does not overlap with the vertical projection of the planarization layer 80 on the substrate 10; the protective layer 102 is located on the side of the passivation layer 101 away from the substrate 10, and the protective layer 102 covers the passivation layer 101 and covers the side wall of the passivation layer 101 away from the edge.

[0095] The area not encapsulated by the encapsulation structure 100 is the lead area of ​​the gate 70, and the lead area is used to connect the gate 70 to the outside. The material of the passivation layer 101 includes silicon dioxide (SiO 2 ) and / or silicon nitride (SiN), which may be silicon dioxide (SiO 2 ) and silicon nitride (SiN) stacked structure, or it can be a separate silicon dioxide layer or silicon nitride layer; the material of the protective layer 102 can be polyimide (PI); the packaging structure 100 can protect the device.

[0096] An embodiment of the present invention further provides a power module based on the above embodiment, comprising a substrate and the power device described in any embodiment of the present invention, wherein the substrate is used to carry the power device.

[0097] The power module provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the power device described in any embodiment of the present invention.

[0098] An embodiment of the present invention further provides a power conversion circuit based on the above embodiments, and the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and the power device described in any embodiment of the present invention, and the power device is electrically connected to the circuit board.

[0099] The power conversion circuit provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the power device described in any embodiment of the present invention.

[0100] An embodiment of the present invention further provides a vehicle based on the above embodiments, including a load and the power conversion circuit described in any embodiment of the present invention, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0101] The vehicle provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the power device described in any embodiment of the present invention.

[0102] The embodiment of the present invention further provides a method for preparing a power device based on the above embodiment. Figure 3 is a flow chart of a method for preparing a power device provided by an embodiment of the present invention, with reference to Figure 3 , the preparation method comprises:

[0103] S110, forming an epitaxial layer on one side of a substrate; the substrate is of a first doping type; the epitaxial layer and the substrate have the same doping type.

[0104] in, Figure 4 is a schematic diagram of an intermediate structure of a power device provided by an embodiment of the present invention, with reference to Figure 4 , an epitaxial layer 20 may be grown on the substrate 10 by epitaxy.

[0105] S120, forming a well region on a surface of the epitaxial layer away from the substrate; the well region includes a first sub-region and a second sub-region connected to each other; the well region is of the second doping type.

[0106] If the second doping type is P-type, P-type ions are injected into the surface of the epitaxial layer 20 away from the substrate 10 to form a well region. The P-type ions may be aluminum (Al) ions or boron (B) ions, and the concentration may be 1014 ~10 18 / cm 3 .

[0107] S130, forming a gate oxide sublayer on a side of the well region away from the substrate; the gate oxide sublayer covers the well region.

[0108] Wherein, a gate oxide sublayer may be formed on a side of the well region away from the substrate by high temperature dry oxygen.

[0109] S140 , forming a gate sublayer on a side of the gate oxide sublayer away from the substrate.

[0110] A gate sublayer may be formed on a side of the gate oxide sublayer away from the substrate by physical vapor deposition (PVD), and the metal of the gate sublayer needs to have a melting point higher than 1700°C.

[0111] S150. Form a first doping type region on the surface of the epitaxial layer away from the substrate; wherein the first sub-region is located on a side of the first doping type region adjacent to the substrate; the first doping type region has a first side and a second side opposite to each other in a first direction, the first direction is the direction from the first doping type region to the second sub-region, and is perpendicular to the direction from the substrate to the epitaxial layer; the second sub-region is located on the second side of the first doping type region.

[0112] Wherein, ions of the first doping type are implanted into the epitaxial layer to form a first doping type region.

[0113] S160, removing part of the gate sublayer to form a gate; the gate covers part of the gate oxide sublayer, and a vertical projection of the gate on the substrate coincides with a vertical projection of the second sub-region on the substrate.

[0114] Part of the gate sublayer is removed by an etching process to form a gate.

[0115] S170, etching the gate oxide sublayer to form a gate oxide layer; the gate oxide layer covers the second sub-region and a portion of the first doping type region.

[0116] The gate oxide sublayer is etched by etching and photolithography processes to form a gate oxide layer.

[0117] Optional, Figure 5 is an intermediate flow chart of a method for preparing a power device provided by an embodiment of the present invention, with reference to Figure 5 , before forming a well region on the surface of the epitaxial layer away from the substrate, including:

[0118] S210 , forming a first mask plate on a side of the epitaxial layer away from the substrate.

[0119] The material of the first mask plate may be silicon dioxide, and the first mask plate covers the epitaxial layer.

[0120] S220 , patterning a first mask plate.

[0121] The pattern of the photomask is transferred to the first mask plate by using plasma enhanced chemical vapor deposition (PECVD) and photolithography technology, and the first mask plate on the area where the second doping type is to be formed is removed.

[0122] S230 , implanting ions of a second doping type into the epitaxial layer through the patterned first mask plate to form a second doping type region.

[0123] in, Figure 6 is a schematic diagram of an intermediate structure of another power device provided by an embodiment of the present invention, with reference to Figure 6 The second doping type region 50 may be doped with P-type ions, and the doped P-type ions may be aluminum (Al) ions or boron (B) ions, and the concentration may be 10 17 ~10 21 / cm 3 .

[0124] S240: removing the first mask plate.

[0125] in, Figure 6 This is the structure after the first mask plate is removed, and the mask plate can be removed by conventional processes.

[0126] Figure 7 This is a detailed flow chart in S120, refer to Figure 7 , S120, forming a well region on a surface of the epitaxial layer away from the substrate, including:

[0127] S121 . Form a second mask on a side of the epitaxial layer away from the substrate.

[0128] The second mask is deposited by plasma enhanced chemical vapor deposition (PECVD), and the second mask covers the epitaxial layer and the second doping type region; the material of the second mask may be silicon nitride (SiNx).

[0129] S122, patterning the second mask plate; wherein the patterned second mask plate is the mask layer.

[0130] in, Figure 8 is a schematic diagram of an intermediate structure of another power device provided by an embodiment of the present invention, with reference to Figure 8 , using photolithography technology to transfer the pattern of the mask to the second mask plate, Figure 8 The mask layer 110 in FIG. 1 is a structure after the second mask plate is patterned.

[0131] S123 , implanting ions of a second doping type into the epitaxial layer through the patterned second mask plate to form a well region.

[0132] The P-type well region can be formed by injecting P-type ions into the well region. The P-type ions can be aluminum (Al) ions or boron (B) ions, and the concentration can be 10 14 ~10 18 / cm 3 .

[0133] Optionally, forming a first doping type region on a surface of the epitaxial layer away from the substrate includes: using the gate sublayer and the mask layer as mask plates, performing ion implantation of the first doping type into the epitaxial layer to form the first doping type region.

[0134] in, Fig. 9 is a schematic diagram of an intermediate structure of another power device provided by an embodiment of the present invention, with reference to Fig. 9 After the well region 30 is formed, a gate oxide sublayer 61 is formed on the side of the epitaxial layer 20 away from the substrate 10 , and the gate oxide sublayer 61 covers the well region 30 and the second doping type region 50 . Fig.10 is a schematic diagram of an intermediate structure of another power device provided by an embodiment of the present invention, with reference to Fig.10 The gate sublayer 61 can be formed by physical vapor deposition (PVD), and the pattern of the mask is transferred to the gate sublayer 61 by photolithography. The gate sublayer 61 on the second doping type region 50 is the mask pattern, and the gate sublayer on the well region 40 is in contact with the sidewall of the mask layer 110. A gate sublayer 71 is formed on the side of the gate oxide sublayer 61 away from the substrate 10. Fig.11 is a schematic diagram of an intermediate structure of another power device provided by an embodiment of the present invention, with reference to Fig.11 , the gate sublayer 71 and the mask layer 110 can be used as a mask plate to perform ion implantation of the first doping type on the epitaxial layer 20 to form a first doping type region. The first doping type region can be an N+ region, and the implanted ions are N-type ions, which can be phosphorus (P) ions or nitrogen (N) ions, and the concentration can be 10 17 ~10 21 / cm 3 Then, the gate sublayer on the second doping type region 50 is removed to form a gate 70, and then a carbon film is sputtered, and high-temperature activation annealing is performed to activate carriers, and finally the carbon film is removed, which can avoid carbon precipitation in the silicon carbide epitaxial layer 20 and improve device performance.

[0135] Optional, Fig.12 is an intermediate flow chart of another method for preparing a power device provided by an embodiment of the present invention, with reference to Fig.12 , before etching the gate oxide sublayer to form a gate oxide layer, the method further includes:

[0136] S310 , removing the patterned second mask.

[0137] In order to finally form Figure 1In order to obtain the structure in the embodiment of the present invention, it is necessary to remove the patterned second mask plate, that is, it is necessary to remove the mask layer.

[0138] S320, forming a planarization sublayer on a side of the gate away from the substrate; the planarization sublayer covers the gate, the gate oxide sublayer not covered by the gate, and the removed area of ​​the second mask.

[0139] Among them, the deposition process can be Fig.11 A planarization sublayer is deposited on the basis of the

[0140] Etching the gate oxide sublayer to form a gate oxide layer includes:

[0141] The planarization sublayer and the gate oxide sublayer are etched simultaneously to form a planarization layer and a gate oxide layer; the gate oxide layer covers the second subregion and part of the first doping type region, and the planarization layer covers the gate, the gate oxide layer not covered by the gate, and the area of ​​the removed second mask.

[0142] in, Fig.13 is a schematic diagram of an intermediate structure of another power device provided by an embodiment of the present invention, with reference to Fig.13 , and the planarization sublayer and the gate oxide sublayer are etched at the same time to form a planarization layer 80 and a gate oxide layer 60. Aluminum metal can be deposited thereafter to form a first electrode 91 and a second electrode 92. The first electrode 91 and the second electrode 92 can be thickened to reduce resistance. Subsequently, the packaging structure 100 can be deposited by PECVD. Finally, back thinning, metal deposition, laser annealing, and back gold thickening are performed to improve device performance.

[0143] Optionally, before etching the gate oxide sublayer to form the gate oxide layer, the method further includes:

[0144] A planarization sublayer is formed on a side of the gate away from the substrate; the planarization sublayer covers the gate, the mask layer, and the gate oxide sublayer not covered by the gate;

[0145] Etching the gate oxide sublayer to form a gate oxide layer includes:

[0146] The planarization sublayer and the gate oxide sublayer are etched simultaneously to form a planarization layer and a gate oxide layer; the gate oxide layer covers the second subregion and part of the first doping type region, and the planarization layer covers the gate, the mask layer and the gate oxide layer not covered by the gate.

[0147] in, Fig.14 is a schematic diagram of an intermediate structure of another power device provided by an embodiment of the present invention, with reference to Fig.14 , in order to form Figure 2The structure in FIG. 1 does not need to remove the mask layer 110, which can simplify the process flow. After the planarization sublayer and the gate oxide sublayer are etched simultaneously to form the planarization layer 80 and the gate oxide layer 60, aluminum metal can be deposited to form the first electrode 91 and the second electrode 92, and the first electrode 91 and the second electrode 92 can be thickened to reduce the resistance. Subsequently, the packaging structure 100 can be deposited by PECVD. Finally, back thinning, metal deposition, laser annealing, and back gold thickening are performed to improve device performance.

[0148] The method for preparing a power device provided in an embodiment of the present invention has the same beneficial effects as the power device described in any embodiment of the present invention.

[0149] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0150] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a power device, characterized in that: include: forming an epitaxial layer on one side of a substrate; the substrate being of a first doping type; The epitaxial layer and the substrate have the same doping type; A well region is formed on the surface of the epitaxial layer away from the substrate; the well region comprises a first sub-region and a second sub-region connected to each other; the well region is of a second doping type; forming a gate oxide sublayer on a side of the well region away from the substrate; the gate oxide sublayer covers the well region; forming a gate sublayer on a side of the gate oxide sublayer away from the substrate; A first doping type region is formed on a surface of the epitaxial layer away from the substrate; wherein the first sub-region is located on a side of the first doping type region adjacent to the substrate; the first doping type region has a first side and a second side opposite to each other in a first direction, the first direction being a direction from the first doping type region to the second sub-region and being perpendicular to a direction from the substrate to the epitaxial layer; the second sub-region is located on a second side of the first doping type region; Removing part of the gate sublayer to form a gate; the gate covers part of the gate oxide sublayer, and a vertical projection of the gate on the substrate coincides with a vertical projection of the second sub-region on the substrate; Etching the gate oxide sublayer to form a gate oxide layer; the gate oxide layer covers the second sub-region and a portion of the first doping type region; Forming a well region on a surface of the epitaxial layer away from the substrate comprises: forming a second mask plate on a side of the epitaxial layer away from the substrate; Patterning the second mask plate; wherein the patterned second mask plate is a mask layer; Performing ion implantation of a second doping type into the epitaxial layer through the patterned second mask plate to form a well region; Forming a first doping type region on a surface of the epitaxial layer away from the substrate comprises: Using the gate sublayer and the mask layer as mask plates, ions of a first doping type are implanted into the epitaxial layer to form a first doping type region.

2. The preparation method according to claim 1, characterized in that: Before forming a well region on a surface of the epitaxial layer away from the substrate, the method comprises: forming a first mask plate on a side of the epitaxial layer away from the substrate; patterning the first mask; Performing ion implantation of a second doping type into the epitaxial layer through the patterned first mask plate to form a second doping type region; The first mask is removed.

3. The preparation method according to claim 2, characterized in that: Before etching the gate oxide sublayer to form a gate oxide layer, the method further includes: removing the second patterned mask; forming a planarization sublayer on a side of the gate away from the substrate; the planarization sublayer covers the gate, the gate oxide sublayer not covered by the gate, and the removed area of ​​the second mask; Etching the gate oxide sublayer to form a gate oxide layer comprises: The planarization sublayer and the gate oxide sublayer are etched simultaneously to form a planarization layer and a gate oxide layer; so that the gate oxide layer covers the second sub-region and a portion of the first doping type region, and the planarization layer covers the gate, the gate oxide layer not covered by the gate, and the removed area of ​​the second mask plate.

4. The preparation method according to claim 2, characterized in that: Before etching the gate oxide sublayer to form a gate oxide layer, the method further includes: forming a planarization sublayer on a side of the gate away from the substrate; the planarization sublayer covers the gate, the mask layer, and the gate oxide sublayer not covered by the gate; Etching the gate oxide sublayer to form a gate oxide layer comprises: The planarization sublayer and the gate oxide sublayer are etched simultaneously to form a planarization layer and a gate oxide layer; so that the gate oxide layer covers the second sub-region and a portion of the first doping type region, and the planarization layer covers the gate, the mask layer and the gate oxide layer not covered by the gate.

5. A power device, characterized in that: The method according to any one of claims 1 to 4 is used for preparation, comprising: a substrate having a first doping type; An epitaxial layer, the epitaxial layer is located on one side of the substrate, and the epitaxial layer and the substrate have the same doping type; a first doping type region and a well region are located on the surface of the epitaxial layer away from the substrate; the well region includes a first sub-region and a second sub-region connected to each other, the first sub-region is located on a side of the first doping type region adjacent to the substrate; the first doping type region has a first side and a second side opposite to each other in a first direction, the first direction is the direction from the first doping type region to the second sub-region, and is perpendicular to the direction from the substrate to the epitaxial layer; the second sub-region is located on the second side of the first doping type region; the well region is of the second doping type; a gate oxide layer, the gate oxide layer being located at a side of the well region away from the substrate, the gate oxide layer covering the second sub-region and a portion of the first doping type region; A gate is located at a side of the gate oxide layer away from the substrate, the gate covers a portion of the gate oxide layer, and a vertical projection of the gate on the substrate coincides with a vertical projection of the second sub-region on the substrate.

6. The power device according to claim 5, characterized in that: Also includes: A second doping type region, wherein the second doping type region is located on a surface of the epitaxial layer away from the substrate; the second doping type region is located on a first side of the first doping type region, and the second doping type region and the first doping type region are in contact with each other; A vertical projection of the first sub-region on the substrate coincides with vertical projections of the second doping type region and the first doping type region on the substrate.

7. The power device according to claim 6, characterized in that: The number of the second doping type region, the first doping type region and the well region is two; the region between the two well regions is a JFET region; The gate oxide layer comprises a first gate oxide layer and a second gate oxide layer; the first gate oxide layer covers the second sub-region of one well region and a partial region of the first doping type region, and the second gate oxide layer covers the second sub-region of another well region and a partial region of another first doping type region; The gate includes a first gate and a second gate, the first gate is located on a side of the first gate oxide layer away from the substrate, and a vertical projection of the first gate on the substrate coincides with a vertical projection of a second sub-region of one of the well regions on the substrate; the second gate is located on a side of the second gate oxide layer away from the substrate, and a vertical projection of the second gate on the substrate coincides with a vertical projection of a second sub-region of another of the well regions on the substrate.

8. The power device according to claim 7, characterized in that: Also includes: A mask layer, wherein the mask layer is located on a side of the epitaxial layer away from the substrate, the mask layer is located between the first gate oxide layer and the second gate oxide layer, and the mask layer is located between the first gate electrode and the second gate electrode.

9. The power device according to claim 8, characterized in that: Also includes: A planarization layer, the planarization layer is located on a side of the gate away from the substrate; When the power device does not include a mask layer, the planarization layer covers the gate, the gate oxide layer not covered by the gate, and the area between the first gate oxide layer and the second gate oxide layer and the area between the first gate and the second gate; When the power device includes a mask layer, the planarization layer covers the gate, the mask layer and the gate oxide layer not covered by the gate.

10. The power device according to claim 9, characterized in that: Also includes: a first electrode and a second electrode; The first electrode is located at a side of the substrate away from the epitaxial layer, and the first electrode covers the substrate; The second electrode is located at a side of the planarization layer away from the substrate, and the second electrode covers the planarization layer, the second doping type region and a portion of the first doping type region.

11. The power device according to claim 10, characterized in that: Also includes: A packaging structure, the packaging structure comprising a passivation layer and a protective layer; The passivation layer is located on a side of the second electrode away from the substrate, and a vertical projection of the passivation layer on the substrate does not overlap with a vertical projection of the planarization layer on the substrate; The protection layer is located on a side of the passivation layer away from the substrate, and the protection layer covers the passivation layer and a side wall of the passivation layer away from the edge.

12. A power module, characterized in that: It comprises a substrate and at least one power device according to any one of claims 5 to 11, wherein the substrate is used to support the power device.

13. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one power device as claimed in any one of claims 5 to 11, wherein the power device is electrically connected to the circuit board.

14. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 13, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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