A semiconductor laser structure with dual-gate control and preparation method

Abstract

The present invention provides a semiconductor laser structure with dual-gate control and a preparation method thereof. The structure comprises a substrate, a buffer layer, a nitride epitaxial DBR, and an N-type semiconductor transmission layer. A multi-quantum well layer is arranged on the upper part of the N-type semiconductor transmission layer. A ferroelectric material and an N-type ohmic electrode are arranged on the upper part of the exposed N-type semiconductor transmission layer. A ferroelectric material electrode is arranged on the upper part of the ferroelectric material. A P-type current blocking layer and a P-type semiconductor transmission layer are arranged in sequence on the upper part of the multi-quantum well layer. A current limiting hole structure layer is arranged on the upper surface of the P-type semiconductor transmission layer. A current expansion layer covers the P-type semiconductor transmission layer and the current limiting hole structure layer. A dielectric DBR and a P-type ohmic electrode are arranged on the upper side of the current expansion layer. The present application can enhance the current control capability of a VCSEL, effectively prevent reverse leakage of the device and suppress leakage level of an active area, and improve the reliability and stability of the device.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor lasers, and in particular to a semiconductor laser structure with dual-gate control and a preparation method thereof. Background Art

[0002] Since the concept was proposed in 1977, Vertical Cavity Surface Emitting Laser (VCSEL) has attracted close attention from researchers due to its advantages such as small threshold current, excellent beam quality and strong directionality, and has been widely used in laser display, lidar, optical communication and other fields. At present, the development of GaAs-based VCSEL has gradually matured and has been successfully commercialized. However, the short-wave VCSEL technology based on GaN wide-bandgap semiconductors still has many shortcomings and there is still a long way to go before commercial application and promotion.

[0003] Research shows that electron leakage is an important reason for the deterioration of GaN-based VCSEL luminous efficiency. First, due to lattice mismatch and thermal expansion coefficient mismatch, GaN-based VCSEL devices have a large number of defects such as threading dislocations inside the device. These defects will form leakage channels to a certain extent, increasing the leakage level of the device. Second, since the mobility of electrons is much greater than the mobility of holes, and the p-type doping efficiency in GaN materials is much lower than the n-type doping efficiency, this leads to extremely uneven distribution of electron and hole concentrations in the active region. Most electrons tend to undergo non-radiative recombination or escape from the active region and leak into the p-region, resulting in a deterioration of VCSEL luminous efficiency. It is worth noting that the above problems will become more prominent due to the self-heating effect and polarization effect of the device, which seriously restricts the development of GaN-based VCSEL devices.

[0004] In order to alleviate the electron leakage phenomenon in the active area, current VCSEL devices usually adopt a p-type electron blocking layer (EBL) design, which uses the barrier energy difference in the conduction band to prevent electrons from escaping the active area. However, the p-EBL design will also increase the barrier height that hinders hole injection in the valence band, resulting in a large number of holes being unable to be efficiently transported to the active area. Therefore, the composition and thickness of the p-EBL have always been the focus of researchers' optimization. For this reason, superlattice p-EBL, component gradient p-EBL and other architectures have been proposed to balance the problems of electron leakage and hole injection. However, the operational space of this measure is limited, and the optimal window value of the variable requires a lot of exploration.

[0005] The applicant has conducted a detailed search of the prior art and has not found any patent application related to the present application; therefore, effectively preventing the reverse leakage of the device and suppressing the leakage level in the active area are still urgent issues to be resolved.

[0006] Therefore, it is necessary to provide a new technical solution to solve the above technical problems. Summary of the invention

[0007] The present invention provides a semiconductor laser structure with dual-gate control, wherein the dual gates refer to two layers of AlGaN with different components as polarization gates and a ferroelectric material as another gate; even if one of the gates is controlled by a ferroelectric material electrode, the other gate is formed by two N-type semiconductor transmission layers with specific components forming polarized negative charges at the interface between the two, which plays a role in depleting electrons.

[0008] The semiconductor laser comprises a substrate, a buffer layer, a nitride epitaxial DBR, and an N-type semiconductor transmission layer in sequence along the epitaxial growth direction; a multi-quantum well layer is arranged on the upper part of the N-type semiconductor transmission layer; a ferroelectric material and an N-type ohmic electrode are arranged on the upper part of the exposed N-type semiconductor transmission layer; a ferroelectric material electrode is arranged on the upper part of the ferroelectric material; a P-type current blocking layer and a P-type semiconductor transmission layer are arranged in sequence on the upper part of the multi-quantum well layer; the outer side of the upper surface of the P-type semiconductor transmission layer is an annular insulating layer as a current limiting hole structure layer; a current expansion layer covers the P-type semiconductor transmission layer and the current limiting hole structure layer; a dielectric DBR and a P-type ohmic electrode are arranged on the upper side of the current expansion layer; and the projection area of ​​the dielectric DBR is smaller than that of the current expansion layer.

[0009] As a preferred solution, the projection area of ​​the dielectric DBR is 0.5-0.9 of the area of ​​the current spreading layer.

[0010] As a preferred solution, the material of the substrate is sapphire, SiC, Si, AlN, GaN or quartz glass.

[0011] As a preferred solution, the buffer layer is made of Al x1 Ga y1 In 1-x1-y1 N; wherein 0≤x1≤1, 0≤y1≤1, 0≤1-x1-y1≤1, and the thickness is 10—500nm.

[0012] As a preferred solution, the nitride epitaxial DBR is composed of Al x2 Ga y2 In 1-x2-y2 N and Al x3 Ga y3 In 1-x3-y3 N alternately composed of Al x2 Ga y2 In 1-x2-y2 N and Al x3 Ga y3 In1-x3-y3 The thickness of N is one quarter of the wavelength of the required light-emitting wavelength in the medium, and the number of periods is greater than or equal to 1; among them, 0≤x2≤1, 0≤y2≤1, 0≤1-x2-y2≤1; 0≤x3≤1, 0≤y3≤1, 0≤1-x3-y3≤1.

[0013] As a preferred solution, the N-type semiconductor transport layer is composed of Al x4 Ga y4 In 1-x4-y4 N and Al x5 Ga y5 In 1-x5-y5 N, wherein 0≤x4≤1, 0≤y4≤1, 0≤1-x4-y4≤1, 0≤x5≤1, 0≤y5≤1, 0≤1-x5-y5≤1 and x4>x5; the Al x5 Ga y5 In 1-x5-y5 A multi-quantum well layer, a ferroelectric material, and an N-type ohmic electrode are arranged above the N layer.

[0014] As a preferred embodiment, the Al x4 Ga y4 In 1-x4-y4 The thickness of N is 50nm-5μm, and the thickness of Al x5 Ga y5 In 1-x5-y5 N thickness is 50nm-2μm.

[0015] As a preferred solution, the ferroelectric material is AlScN.

[0016] As a preferred solution, the thickness of the ferroelectric material is 5-100 nm.

[0017] As a preferred solution, the multi-quantum well layer is composed of quantum well Al x6 In y6 Ga 1-x6-y6 N and quantum barrier Al x7 In y7 Ga 1-x7-y7 N, wherein 0≤x6≤1, 0≤y6≤1, 0≤1-x6-y6≤1, 0≤x7≤1, 0≤y7≤1, 0≤1-x7-y7≤1, the bandgap width of the quantum barrier should be higher than the bandgap width of the quantum well, and the number of the quantum wells is greater than or equal to 1.

[0018] As a preferred embodiment, the quantum well Al x6 In y6 Ga 1-x6-y6 The thickness of N is 1-10nm, and the quantum barrier Al x7 In y7Ga 1-x7-y7 The thickness of N is 5-50nm.

[0019] As a preferred solution, the material of the N-type ohmic electrode is Al / Au or Cr / Au.

[0020] As a preferred solution, the material of the P-type current blocking layer is Al x8 In y8 Ga 1-x8-y8 N, where 0≤x8≤1, 0≤y8≤1, 0≤1-x8-y8≤1.

[0021] As a preferred solution, the thickness of the P-type current blocking layer is 10-100 nm.

[0022] As a preferred solution, the material of the P-type semiconductor transport layer is Al x9 In y9 Ga 1-x9-y9 N, where 0≤x9≤1, 0≤y9≤1, 0≤1-x9-y9≤1.

[0023] As a preferred solution, the thickness of the P-type semiconductor transport layer is 50-300 nm.

[0024] As a preferred solution, the material of the current limiting hole structure layer is SiO2.

[0025] As a preferred solution, the current limiting pore structure layer has a thickness of 10-100 nm.

[0026] As a preferred solution, the material of the current spreading layer is one of ITO, Ni / Au, zinc oxide, graphene, aluminum or metal nanowires.

[0027] As a preferred solution, the thickness of the current spreading layer is 10-100 nm.

[0028] As a preferred solution, the material of the dielectric DBR is Ta2O5 / SiO2 or TiO2 / SiO2.

[0029] As a preferred solution, the thickness of Ta2O5 / SiO2 or TiO2 / SiO2 is one quarter of the wavelength of the desired luminous wavelength in the medium, and the number of periods is greater than or equal to 1.

[0030] As a preferred solution, the material of the P-type ohmic electrode is one of Ni / Au, Cr / Au, Pt / Au, and Ni / Al.

[0031] A method for preparing a semiconductor laser structure with dual-gate control comprises the following steps:

[0032] S1, in an MOCVD reactor, growing a buffer layer, a nitride epitaxial DBR, an N-type semiconductor transport layer, a quantum well layer, a P-type current blocking layer, and a P-type semiconductor transport layer on the surface of the substrate respectively;

[0033] S2, forming a step on the P-type semiconductor transmission layer by photolithography and etching processes to expose the N-type semiconductor transmission layer;

[0034] S3, depositing and growing a current limiting hole structure layer on the P-type semiconductor transport layer;

[0035] S4, evaporating a current spreading layer on the current limiting hole structure layer;

[0036] S5, atomic layer deposition of dielectric DBR on the current spreading layer;

[0037] S6, based on S5, depositing ferroelectric material on the exposed N-type semiconductor transport layer through photolithography and etching technology;

[0038] S7, evaporating and photolithography to form a ferroelectric material electrode on the ferroelectric material; and evaporating and photolithography to form a P-type ohmic electrode and an N-type ohmic electrode on the exposed current spreading layer and the N-type semiconductor transmission layer, respectively.

[0039] As a preferred solution, in S2, 60%-80% of the N-type semiconductor transport layer is exposed.

[0040] As a preferred solution, the N-type semiconductor transport layer is composed of Al x4 Ga y4 In 1-x4-y4 N and Al x5 Ga y5 In 1-x5-y5 N, wherein 0≤x4≤1, 0≤y4≤10, 0≤1-x4-y4≤1, 0≤x5≤1, 0≤y5≤1, 0≤1-x5-y5≤1 and x4>x5; the Al x5 Ga y5 In 1-x5-y5 A multi-quantum well layer, a ferroelectric material, and an N-type ohmic electrode are arranged above the N layer.

[0041] As a preferred embodiment, the Al x4 Ga y4 In 1-x4-y4 The thickness of N is 50nm-5μm, and the thickness of Al x5 Ga y5 In 1-x5-y5 N thickness is 50nm-2μm.

[0042] As a preferred solution, the ferroelectric material is AlScN.

[0043] As a preferred solution, the thickness of the ferroelectric material is 5-100 nm.

[0044] The present application deposits a layer of ferroelectric material on the surface of the N-semiconductor transmission layer of the VCSEL, and adopts an N-region composition with a specific component gradient, making full use of the piezoelectric properties and polarization effect of the ferroelectric material to act as a double-gate effect to control the opening and closing of the conductive channel; the current control capability of the VCSEL can be enhanced, the reverse leakage of the device can be effectively prevented, the leakage level of the active area can be suppressed, and the reliability and stability of the device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a schematic diagram of the device current when no bias is applied to the ferroelectric material;

[0046] Figure 2 Schematic diagram of device current when reverse bias is applied to ferroelectric material;

[0047] Figure 3 Schematic diagram of device current when a forward bias is applied to a ferroelectric material;

[0048] Figure 4 A schematic diagram of a semiconductor laser structure with dual-gate control according to the present application;

[0049] Figure 5 This is a schematic diagram of the epitaxial wafer structure in which a step is made on a P-type semiconductor transmission layer by photolithography and etching processes to expose an N-type semiconductor transmission layer in the present invention;

[0050] Figure 6 This is a schematic diagram of the epitaxial wafer structure in which an insulating layer is grown by deposition on a P-type semiconductor transmission layer, and a current limiting hole structure layer is photoetched;

[0051] Figure 7 This is a schematic diagram of the structure of an epitaxial wafer for making a patterned current spreading layer by photolithography and etching in the present invention;

[0052] Figure 8 In the present invention, a schematic diagram of the structure of an epitaxial wafer of a patterned ferroelectric material is produced by photolithography and etching;

[0053] Among them, 101, substrate; 102, buffer layer; 103, nitride epitaxial DBR; 104, N-type semiconductor transport layer; 106, ferroelectric material; 107, multi-quantum well layer; 108, P-type current blocking layer; 109, P-type semiconductor transport layer; 110, current limiting pore structure layer; 111, current spreading layer; 112, dielectric DBR; 113, P-type ohmic electrode; 114, N-type ohmic electrode; 115, ferroelectric material electrode. DETAILED DESCRIPTION

[0054] The following is combined with Figure 1 To Attachment Figure 8 The specific implementation of the present invention is described in detail. It should be noted that the specific implementation described here is only used to illustrate and explain the present invention, and is not used to limit the present invention.

[0055] Embodiment 1:

[0056] The present invention provides a semiconductor laser structure with dual-gate control, wherein the dual gates refer to two layers of AlGaN with different components constituting an N-type semiconductor transport layer as polarization gates, and another gate of a ferroelectric material 106; that is, one of the gates is controlled by a ferroelectric material electrode 115, and the other gate is formed by polarization negative charges formed at the interface between the two specific components of the two N-type semiconductor transport layers, which plays a role in depleting electrons.

[0057] The semiconductor laser includes a circular substrate 101, a buffer layer 102, a nitride epitaxial DBR 103, and an N-type semiconductor transmission layer 104 in sequence along the epitaxial growth direction. Preferably, the material of the substrate 101 is sapphire, SiC, Si, AlN, GaN or quartz glass. The substrate 101 can be divided into a polar surface substrate and a semi-polar surface substrate along the epitaxial growth direction; the material of the buffer layer 102 is Al x1 Ga y1 In 1-x1-y1 N, wherein 0≤x1≤1, 0≤y1≤1, 0≤1-x1-y1≤1, and the thickness is 10-500nm; the material of the nitride epitaxial DBR 103 is Al x2 Ga y2 In 1-x2-y2 N and Al x3 Ga y3 In 1-x3-y3 N alternately composed of Al x2 Ga y2 In 1-x2-y2 N and Al x3 Ga y3 In 1-x3-y3The thickness of N is one quarter of the wavelength of the desired luminous wavelength in the medium, and the number of periods is greater than or equal to 1; wherein, 0≤x2≤1, 0≤y2≤1, 0≤1-x2-y2≤1; 0≤x3≤1, 0≤y3≤1, 0≤1-x3-y3≤1;

[0058] A multi-quantum well layer 107 is disposed on the upper portion of the N-type semiconductor transport layer 104. Preferably, the multi-quantum well layer 107 is composed of quantum well Al x6 In y6 Ga 1-x6-y6 N and quantum barrier Al x7 In y7 Ga 1-x7-y7 N, wherein 0≤x6≤1, 0≤y6≤1, 0≤1-x6-y6≤1, 0≤x7≤1, 0≤y7≤1, 0≤1-x7-y7≤1, the bandgap width of the quantum barrier should be higher than the bandgap width of the quantum well, and the number of quantum wells is greater than or equal to 1; the quantum well Al x6 In y6 Ga 1-x6-y6 The thickness of N is 1-10nm, and the quantum barrier Al x7 In y7 Ga 1-x7-y7 The thickness of N is 5-50nm;

[0059] The exposed N-type semiconductor transmission layer 104 is provided with a ferroelectric material 106 and an N-type ohmic electrode 114 on the upper part. The ferroelectric material 106 is AlScN, and the thickness of the ferroelectric material 106 is 5-100nm; the annular N-type ohmic electrode 114 is located outside the exposed part of the N-type semiconductor transmission layer 104, and the width is preferably 0.1-1μm. The material of the N-type ohmic electrode is Al / Au or Cr / Au; the ferroelectric material 106 is provided with a ferroelectric material electrode 115 on the upper part, and the P-type current blocking layer 108 and the P-type semiconductor transmission layer 109 are provided on the upper part of the multi-quantum well layer 107 in sequence. Preferably, the material of the P-type current blocking layer 108 is Al x8 In y8 Ga 1-x8-y8 N, wherein 0≤x8≤1, 0≤y8≤1, 0≤1-x8-y8≤1; the thickness of the P-type current blocking layer 108 is 10-100 nm, and the material of the P-type semiconductor transmission layer 109 is Al x9 In y9 Ga 1-x9-y9N, wherein 0≤x9≤1, 0≤y9≤1, 0≤1-x9-y9≤1, the thickness of the P-type semiconductor transmission layer 109 is 50-300nm; the outer side of the upper surface of the P-type semiconductor transmission layer 109 is a ring-shaped insulating layer, which serves as a current limiting hole structure layer 110. The current limiting hole structure layer 110 is a high dielectric constant insulating layer, and the material is preferably SiO2. The thickness of the current limiting hole structure layer 110 is 10-100nm; the width of the ring is 2-200μm; the current expansion layer 111 covers the P-type semiconductor transmission layer 109 and the current limiting hole structure layer 110; preferably, the material of the current expansion layer 111 is one of ITO, Ni / Au, zinc oxide, graphene, aluminum or metal nanowires, and the thickness of the current expansion layer 111 is 10-100nm; a dielectric DBR is arranged on the upper side of the current expansion layer 111 112 and a P-type ohmic electrode 113, the projection area of ​​the dielectric DBR 112 is smaller than the area of ​​the current spreading layer 111, preferably, the projection area of ​​the dielectric DBR 112 is 0.5-0.9 of the area of ​​the current spreading layer 111; the material of the dielectric DBR 112 is Ta2O5 / SiO2 or TiO2 / SiO2; when Ta2O5 / SiO2 is used, the thickness of Ta2O5 and SiO2 is respectively one-fourth of the wavelength of the required luminous wavelength in the medium, and the number of periods is greater than or equal to 1; when TiO2 / SiO2 is used, the thickness of TiO2 and SiO2 is respectively one-fourth of the wavelength of the required luminous wavelength in the medium, and the number of periods is greater than or equal to 1; the annular P-type ohmic electrode 113 is located outside the current spreading layer 111, has a width of 0.1-2μm, and the material of the P-type ohmic electrode 113 is one of Ni / Au, Cr / Au, Pt / Au, and Ni / Al.

[0060] The N-type semiconductor transport layer 100 is composed of Al x4 Ga y4 In 1-x4-y4 N and Al x5 Ga y5 In 1-x5-y5 N composition, wherein 0≤x4≤1, 0≤y4≤1, 0≤1-x4-y4≤1; 0≤x5≤1, 0≤y5≤1, 0≤1-x5-y5≤1 and x4>x5, Al x4 Ga y4 In 1-x4-y4 N thickness is 50nm-5μm, Al x5 Ga y5 In 1-x5-y5 N thickness is 50nm-2μm; Al x5 Ga y5 In 1-x5-y5A 5-100 nm ferroelectric material 106 is deposited on the N layer. The ferroelectric material 106 is preferably AlScN. This composition gradient will cause Al x4 Ga y4 In 1-x4-y4 N / A x5 Ga y5 In 1-x5-y5 There are a lot of negatively polarized interface charges at the N interface, which leads to space depletion of electrons. Secondly, the ferroelectric material 106 and Al x5 Ga y5 In 1-x5-y5 The type and concentration of the N-layer interface charge vary with the direction and intensity of the applied electric field.

[0061] The device in this embodiment deposits a layer of ferroelectric material 106 on the N-type semiconductor transmission layer 104. On the one hand, Al x4 Ga y4 In 1-x4-y4 N acts as a polarization gate, forming a negative interface charge at the interface through composition differences, thereby forming a depletion effect on electrons, such as Figure 1 As shown; on the other hand, in the case of low Al components x5 Ga y5 In 1-x5-y5 The N layer is etched and a layer of ferroelectric material 106 is deposited. The ferroelectric material 106 has special piezoelectric properties, which makes its interface polarization charge and polarization intensity change with the direction and intensity of the external electric field, thereby affecting the accumulation and depletion of electrons below it. Figure 2 As shown; therefore, under the joint action of the upper and lower dual gate electrodes, the opening and closing control effect of the N-side electron transport channel can be achieved, thereby regulating the electron transport efficiency, which can not only suppress the electron leakage problem in the active area, but also greatly reduce the reverse leakage of the device.

[0062] Embodiment 2:

[0063] This embodiment provides a method for preparing a semiconductor laser structure with dual-gate control, comprising the following steps:

[0064] S1, in a MOCVD reactor, baking the substrate 101 at 1250° C.-1350° C., removing foreign matter on the surface of the substrate 101, and then growing a buffer layer 102, a nitride epitaxial DBR 103, an N-type semiconductor transport layer 104, a multi-quantum well layer 107, a P-type current blocking layer 108, and a P-type semiconductor transport layer 109 on the surface of the substrate 101;

[0065] S2, on the P-type semiconductor transmission layer 109, a step is formed by photolithography and etching process to expose the N-type semiconductor transmission layer 104, preferably, 60% to 80% of the N-type semiconductor transmission layer 104 is exposed;

[0066] S3, depositing and growing a current limiting hole structure layer 110 on the P-type semiconductor transmission layer 109; preferably, the thickness of the current limiting hole structure layer 110 is 10-100 nm, and the insulating material used for the current limiting hole structure layer 110 is SiO2, and then etching a ring pattern on the insulating material using photolithography technology, the pattern covers along the edge of the P-type semiconductor transmission layer 109, and the width of the ring is 2-200 μm;

[0067] S4, evaporating a current spreading layer 111 on the current limiting hole structure layer 110; forming a patterned current spreading layer 111 by photolithography and wet etching, the patterned current spreading layer 111 is located above the P-type semiconductor transmission layer 109 and the current limiting hole structure layer 110;

[0068] S5, atomic layer deposition (ALD) of dielectric DBR 112 on the current spreading layer 111;

[0069] S6, based on S5, depositing a ferroelectric material 106 on the exposed N-type semiconductor transmission layer 104 through a photolithography process and an etching technology, wherein the ferroelectric material 106 is AlScN, and stripping off the remaining photoresist;

[0070] S7, evaporating and photolithography to form a ferroelectric material electrode 115 on the ferroelectric material 106; and evaporating and photolithography to form a P-type ohmic electrode 113 and an N-type ohmic electrode 114 on the exposed current spreading layer 111 and the N-type semiconductor transport layer 104, respectively.

[0071] According to the above method, a semiconductor laser structure with a dual-gate control function is obtained.

[0072] Embodiment three:

[0073] The present invention provides a specific structure of a semiconductor laser structure with dual-gate control and a preparation method thereof, specifically:

[0074] A semiconductor laser structure with double-gate control, wherein the double gates are composed of Al 0.8 Ga 0.2 N、Al 0.6 Ga 0.4N, and another gate made of ferroelectric material AlScN; the device includes a circular substrate 101, a buffer layer 102, a nitride epitaxial DBR 103 and an N-type semiconductor transmission layer 104 in the epitaxial growth direction; wherein the N-type semiconductor transmission layer 104 has two layers, Al 0.8 Ga 0.2 N、Al 0.6 Ga 0.4 N, in Al 0.6 Ga 0.4 A layer of ferroelectric material 106 is inserted in N, and the ferroelectric material 106 is AlScN;

[0075] The Al 0.6 Ga 0.4 The upper layer of N is a multi-quantum well layer 107, a P-type current blocking layer 108, and a P-type semiconductor transmission layer 109 in sequence; the outer side of the upper surface of the P-type semiconductor transmission layer 109 is a ring-shaped high dielectric constant insulating layer, which serves as a current limiting hole structure layer 110. The material of the current limiting hole structure layer 110 is SiO2, the thickness is 20nm, and the width of the ring is 2.5μm;

[0076] The current spreading layer 111 covers the P-type semiconductor transmission layer 109 and the insulating current limiting aperture structure layer 110; the dielectric DBR 112 is located on the current spreading layer 111, and its projected area is 0.6 of the area of ​​the current spreading layer 111; the annular P-type ohmic electrode 113 is located on the outside of the current spreading layer 111, and has a width of 0.5 μm; the annular N-type ohmic electrode 114 is located on the outside of the exposed portion of the N-type semiconductor transmission layer 104, and has a width of 0.5 μm; the annular ferroelectric material electrode 115 is located on the ferroelectric material 106, and has a width of 0.5 μm.

[0077] The preparation method of the semiconductor laser structure with dual-gate control is as follows:

[0078] S1, in an MOCVD reactor, the substrate 101 is baked at a high temperature of 1300°C, foreign matter on the surface of the substrate 101 is removed, and then a buffer layer 102, a nitride epitaxial DBR 103, an N-type semiconductor transmission layer 104, a multi-quantum well layer 107, a P-type current blocking layer 108, and a P-type semiconductor transmission layer 109 are grown respectively; wherein the buffer layer 102 is made of GaN, the nitride epitaxial DBR 103 is made of AlN / GaN, the N-type semiconductor transmission layer 104 is made of GaN, and the multi-quantum well layer 107 is made of ten pairs of In 0.21 Ga 0.79 N / GaN; the P-type current blocking layer 108 is made of Al 0.1 Ga 0.9N; the material of the P-type semiconductor transmission layer 109 is GaN;

[0079] S2, based on the P-type semiconductor transmission layer 109 obtained in S1, a step is made by photolithography and etching process to expose the N-type semiconductor transmission layer 104;

[0080] S3, depositing and growing a current limiting hole structure layer 110 on the P-type semiconductor transmission layer 109 obtained in S1, wherein the insulating material used in the current limiting hole structure layer 110 is SiO2 with a thickness of 20 nm; then etching a ring pattern on the insulating material using photolithography technology, wherein the pattern covers the edge of the P-type semiconductor transmission layer 109 and has a width of 2.5 μm;

[0081] S4, based on the current limiting hole structure layer 110 obtained in S3, a current spreading layer 111 is evaporated, the material of the current spreading layer 111 is ITO, and the thickness is 40nm; and a patterned current spreading layer 111 is manufactured by photolithography and wet etching, and is located above the P-type semiconductor transmission layer 109 and the current limiting hole structure layer 110;

[0082] S5, based on the current spreading layer 111 obtained in S3, an atomic layer deposition (ALD) dielectric DBR 112 is formed, and the thickness of the dielectric DBR 112 is 1.27 μm; the dielectric DBR 112 uses 10 pairs of Ta2O5 / SiO2;

[0083] S6, depositing a layer of ferroelectric material 106 on the N-type semiconductor transmission layer 104 through photolithography and etching processes, wherein the ferroelectric material 106 is made of AlScN with a thickness of 5-10 nm, and stripping off the remaining photoresist;

[0084] S7 , evaporating and photolithography to form a P-type ohmic electrode 113 , an N-type ohmic electrode 114 and a ferroelectric material electrode 115 .

[0085] The implementation of the present invention is based on the basic design idea of ​​VCSEL laser, combining the polarization properties of III-V nitride materials with the piezoelectric properties of ferroelectric materials, and synergistically regulating the accumulation and depletion of electrons, thereby achieving good results; specifically, a specific component gradient is used to generate negative interface charges at the interface of the N-type semiconductor transport layer, thereby repelling and depleting negatively charged electrons; at the same time, the charge of the interface charge between the ferroelectric material and the N-type semiconductor transport layer is selectively adjusted by regulating the external electric field, thereby achieving the accumulation and depletion of electrons, controlling the opening and closing of the conductive channel, and thus suppressing the leakage current phenomenon of the device; the present application deposits a layer of ferroelectric material on the surface of the N-semiconductor transport layer of the VCSEL, and adopts an N-region composition with a specific component gradient, fully utilizing the piezoelectric characteristics and polarization effect of the ferroelectric material to act as a double-gate effect, and controlling the opening and closing of the conductive channel; the current control capability of the VCSEL can be enhanced, the reverse leakage of the device can be effectively prevented, the leakage level of the active area can be suppressed, and the reliability and stability of the device can be improved.

[0086] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

[0087] The preferred embodiments of the present application are described in detail above in conjunction with the accompanying drawings; however, the present application is not limited to the specific details in the above embodiments. Within the technical concept of the present application, a variety of simple modifications can be made to the technical solution of the present application, and these simple modifications all fall within the protection scope of the present application.

[0088] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the various possible combinations of this application will not be described separately.

[0089] In addition, the various implementation modes of the present application may be arbitrarily combined, and as long as they do not violate the concept of the present application, they should also be regarded as the contents disclosed in the present application.

Claims

1. A semiconductor laser structure with dual-gate control, the semiconductor laser comprising a substrate (101), a buffer layer (102), a nitride epitaxial DBR (103), and an N-type semiconductor transmission layer (104) in sequence along the epitaxial growth direction, characterized in that: A multi-quantum well layer (107) is arranged on the upper part of the N-type semiconductor transmission layer (104); a ferroelectric material (106) and an N-type ohmic electrode (114) are arranged on the upper part of the exposed N-type semiconductor transmission layer (104); a ferroelectric material electrode (115) is arranged on the upper part of the ferroelectric material (106); a P-type current blocking layer (108) and a P-type semiconductor transmission layer (109) are arranged in sequence on the upper part of the multi-quantum well layer (107); a current limiting hole structure layer (110) is arranged on the upper surface of the P-type semiconductor transmission layer (109); a current expansion layer (111) covers the P-type semiconductor transmission layer (109) and the current limiting hole structure layer (110); a dielectric DBR (112) and a P-type ohmic electrode (113) are arranged on the upper side of the current expansion layer (111); and the projection area of ​​the dielectric DBR (112) is smaller than the area of ​​the current expansion layer (111).

2. A semiconductor laser structure with dual-gate control according to claim 1, characterized in that: The projection area of ​​the dielectric DBR (112) is 0.5-0.9 of the area of ​​the current spreading layer (111).

3. A semiconductor laser structure with dual-gate control according to claim 1, characterized in that: The material of the nitride epitaxial DBR (103) is Al x2 Ga y2 In 1-x2-y2 N and Al x3 Ga y3 In 1-x3-y3 N alternately composed of Al x2 Ga y2 In 1-x2- y2 N and Al x3 Ga y3 In 1-x3-y The thickness of N is one quarter of the wavelength of the required light-emitting wavelength in the medium, and the number of periods is greater than or equal to 1; among them, 0≤x2≤1, 0≤y2≤1, 0≤1-x2-y2≤1; 0≤x3≤1, 0≤y3≤1, 0≤1-x3-y3≤1.

4. A semiconductor laser structure with dual-gate control according to claim 1, characterized in that: The N-type semiconductor transport layer (104) is composed of Al x4 Ga y4 In 1-x4-y4 N and Al x5 Ga y5 In 1-x5-y5 N, where 0≤x4≤1, 0≤y4≤1, 0≤1-x4-y4≤1, 0≤x5 ≤1, 0≤y5≤1, 0≤1-x5-y5≤1 and x4>x5; the Al x5 Ga y5 In 1-x5-y5 A multi-quantum well layer (107), a ferroelectric material (106), and an N-type ohmic electrode (114) are arranged above the N layer.

5. A semiconductor laser structure with dual-gate control according to claim 4, characterized in that: The Al x4 Ga y4 In 1-x4-y4 The thickness of N is 50nm-5μm, and Al x5 Ga y5 In 1-x5-y5 N thickness is 50nm-2μm.

6. The semiconductor laser structure with dual-gate control according to claim 1, characterized in that: The multi-quantum well layer (107) is composed of quantum well Al x6 In y6 Ga 1-x6-y6 N and quantum barrier Al x7 In y7 Ga 1-x7-y7 N, wherein 0≤x6≤1, 0≤y6≤1, 0≤1-x6-y6≤1, 0≤x7≤1, 0≤y7≤1, 0≤1-x7-y7≤1, the bandgap width of the quantum barrier should be higher than the bandgap width of the quantum well, and the number of the quantum wells is greater than or equal to 1.

7. The semiconductor laser structure with dual-gate control according to claim 1, characterized in that: The ferroelectric material (106) is AlScN.

8. A method for preparing a semiconductor laser structure with dual-gate control according to any one of claims 1 to 7, characterized in that: The following steps are involved: S1, in an MOCVD reactor, growing a buffer layer (102), a nitride epitaxial DBR (103), an N-type semiconductor transmission layer (104), a multi-quantum well layer (107), a P-type current blocking layer (108), and a P-type semiconductor transmission layer (109) on the surface of a substrate (101); S2, forming a step on the P-type semiconductor transmission layer (109) by photolithography and etching processes to expose the N-type semiconductor transmission layer (104); S3, depositing and growing a current limiting aperture structure layer (110) on the P-type semiconductor transport layer (109); S4, evaporating a current spreading layer (111) on the current limiting aperture structure layer (110); S5, atomically depositing a dielectric DBR (112) on the current spreading layer (111); S6, based on S5, depositing a ferroelectric material (106) on the exposed N-type semiconductor transport layer (104) through a photolithography process and an etching technique; S7, evaporating and photolithography to form a ferroelectric material electrode (115) on the ferroelectric material (106); and evaporating and photolithography to form a P-type ohmic electrode (113) and an N-type ohmic electrode (114) on the exposed current spreading layer (111) and the N-type semiconductor transmission layer (104), respectively.

9. The method for preparing a semiconductor laser structure with dual-gate control according to claim 8, characterized in that: In the step S2, 60%-80% of the N-type semiconductor transport layer (104) is exposed.

10. The method for preparing a semiconductor laser structure with dual-gate control according to claim 8, characterized in that: The N-type semiconductor transport layer (104) is composed of Al x4 Ga y4 In 1-x4-y4 N and Al x5 Ga y5 In 1-x5-y5 N, wherein 0≤x4≤1, 0≤y4≤10, 0≤1-x4-y4≤1, 0≤x5≤1, 0≤y5≤1, 0≤1-x5-y5≤1 and x4>x5; the Al x5 Ga y5 In 1-x5-y5 A multi-quantum well layer (107), a ferroelectric material (106), and an N-type ohmic electrode (114) are arranged above the N layer.

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