A data synchronization circuit and a data processing circuit

Abstract

The embodiment of the present application discloses a data synchronization circuit and a data processing circuit. The data synchronization circuit includes: a clock module for outputting a source reference signal; a plurality of analog-to-digital conversion modules, respectively electrically connected to the clock module, including an analog-to-digital conversion module in a master mode and an analog-to-digital conversion module in a slave mode; the analog-to-digital conversion module in the master mode generates a data synchronization control signal according to the source reference signal, and sends the data synchronization control signal to the analog-to-digital conversion module in the slave mode, so that each analog-to-digital conversion module performs synchronous transmission of data to be processed according to the data synchronization control signal. The circuit can improve the synchronization of data transmission.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a data synchronization circuit and a data processing circuit. Background Art

[0002] Analog-Digital Converter (ADC) chip is used to convert analog signals into digital signals. Due to the low data conversion rate of ADC chip, the ADC data in the ADC chip will be sent to Field Programmable Gate Array (FPGA) for processing. In order to ensure more accurate analysis of the ADC data of multiple ADC chips, the ADC data of multiple ADC chips need to be sent to FPGA synchronously.

[0003] In the related art, FPGA will actively generate a synchronization signal and send it to multiple ADC chips, so that each ADC chip can send its ADC data to FPGA based on the synchronization signal. However, FPGA cannot know the internal state of each ADC chip. If the sending time or pulse width of the synchronization signal is not appropriate, some or all ADC chips will not be able to send ADC data to FPGA synchronously, resulting in reduced synchronization of data transmission.

[0004] Therefore, how to improve the synchronization of data transmission is an urgent problem to be solved. Summary of the invention

[0005] In order to solve the above technical problems, an embodiment of the present application provides a data synchronization circuit and a data processing circuit.

[0006] According to one aspect of an embodiment of the present application, a data synchronization circuit is provided, including: a clock module for outputting a source reference signal; a plurality of analog-to-digital conversion modules, respectively electrically connected to the clock module, including a master mode analog-to-digital conversion module and a slave mode analog-to-digital conversion module; the master mode analog-to-digital conversion module generates a data synchronization control signal according to the source reference signal, and sends the data synchronization control signal to the slave mode analog-to-digital conversion module, so that each analog-to-digital conversion module performs synchronous transmission of data to be processed according to the data synchronization control signal.

[0007] In some embodiments of the present application, each analog-to-digital conversion module includes a register configuration module; the register configuration module is used to configure the corresponding model converter module to a master mode or a slave mode according to a received mode configuration instruction.

[0008] In some embodiments of the present application, a first reference signal generating module is used to generate a first reference signal according to the source reference signal sent by the clock module; and a control signal generating module is used to generate the data synchronization control signal according to a high level interval in the first reference signal.

[0009] In some embodiments of the present application, the control signal generating module determines the interval between the falling edge of the first high level interval and the falling edge of the second high level interval in the first reference signal as the high level interval of the data synchronization control signal; wherein the first high level interval is located before the second high level interval.

[0010] In some embodiments of the present application, the first high level interval and the second high level interval are adjacent high level intervals.

[0011] In some embodiments of the present application, the first reference signal generating module also determines the moment when the data synchronization control signal is in a high level interval and a rising edge appears in the first reference signal as the sending moment of sending the data to be processed to the data processing module, and the data processing module is used to perform processing on the data to be processed sent synchronously by each analog-to-digital conversion module.

[0012] In some embodiments of the present application, a second reference signal generating module is used to generate a second reference signal according to the source reference signal sent by the clock module, and determine the time to send the data to be processed to the data processing module based on the second reference signal and the data synchronization control signal.

[0013] In some embodiments of the present application, the second reference signal generating module determines the moment when the data synchronization control signal is in a high level interval and a rising edge appears in the second reference signal as the moment when the data to be processed is sent.

[0014] According to another aspect of an embodiment of the present application, a data processing circuit is provided, comprising a data synchronization circuit and a data processing module as described above; the data synchronization circuit is electrically connected to the data processing module, and the data processing module is used to process the data to be processed sent synchronously by each analog-to-digital conversion module in the data synchronization circuit.

[0015] In the above technical solution: the multiple analog-to-digital conversion modules may include an analog-to-digital conversion module in a master mode and an analog-to-digital conversion module in a slave mode, and the analog-to-digital conversion module in the master mode may generate a data synchronization control signal according to a source reference signal output by a clock module, and may send the data synchronization control signal to the analog-to-digital conversion module in the slave mode. In this way, the multiple analog-to-digital conversion modules may synchronously send the data to be processed based on the data synchronization control signal, so that each analog-to-digital conversion module may simultaneously send its own data to be processed, thereby improving the synchronization of data transmission.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0018] Figure 1 is a schematic diagram of a data synchronization circuit shown in an exemplary embodiment of the present application;

[0019] Figure 2 is a signal timing diagram of a sysref signal involved in the present application;

[0020] Figure 3 It is a schematic diagram of the internal structure of an analog-to-digital conversion module involved in the present application;

[0021] Figure 4 It is a signal timing diagram in an analog-to-digital conversion module of a main mode of the present application;

[0022] Figure 5 It is a signal timing diagram in an analog-to-digital conversion module of a slave mode of the present application;

[0023] Figure 6 It is a schematic diagram of a data processing circuit shown in an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0024] Here, exemplary embodiments will be described in detail, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments that are the same as the present application. Instead, they are only examples of devices and methods that are the same as some aspects of the present application as detailed in the attached claims.

[0025] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0026] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, while some operations / steps can be integrated or partially integrated, so the actual execution order may change according to actual conditions.

[0027] It should be noted that the "multiple" mentioned in this application refers to two or more than two. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship.

[0028] Before introducing the technical solutions of the embodiments of the present application, the technical terms involved in the embodiments of the present application are first introduced here.

[0029] Analog-to-Digital Converter (ADC) is an electronic device used to convert analog signals (such as voltage, current, etc.) into digital signals. Analog signals are continuous, while digital signals are discrete. ADC represents the amplitude of analog signals as digital values ​​through the process of sampling and quantization for subsequent digital processing. ADC is widely used in various applications that require analog signals to be converted into digital form, such as audio processing, data acquisition, sensor data reading, etc. For example, in a digital audio system, the sound (analog signal) collected by the microphone needs to be converted into a digital signal by ADC before it can be processed in a computer or digital device.

[0030] Field-Programmable Gate Array (FPGA) is a semiconductor device that contains a large number of programmable logic units and programmable interconnect resources. Users can program FPGAs through hardware description languages ​​(HDL) such as VHDL or Verilog to implement customized digital circuit designs. FPGAs are used to implement a variety of complex digital circuit functions and are commonly used in high-speed data processing, digital signal processing (DSP), computer vision, encryption algorithms, and signal processing in communication systems. Because FPGAs can be reprogrammed in the field (that is, when the system is already deployed), they are particularly suitable for applications that require high flexibility and fast development cycles.

[0031] In the related art, FPGA will actively generate a synchronization signal and send it to multiple ADC chips, so that each ADC chip sends its ADC data to FPGA based on the synchronization signal. However, FPGA cannot know the internal status of each ADC chip. If the sending time or pulse width of the synchronization signal is not appropriate, some or all of the ADC chips will not be able to send ADC data to FPGA synchronously, causing FPGA to be unable to synchronously receive ADC data sent by multiple ADC chips, reducing the synchronization of data transmission.

[0032] Based on this, the embodiments of the present application respectively propose a data synchronization circuit and a data processing circuit. Multiple analog-to-digital conversion modules can be configured in mode, one of the analog-to-digital conversion modules is configured as a master mode, and the remaining analog-to-digital conversion modules are configured as slave modes. The analog-to-digital conversion module in the master mode can generate a data synchronization control signal based on the source reference signal output by the clock module, and can be sent to the analog-to-digital conversion module in the slave mode. In this way, the multiple analog-to-digital conversion modules can perform synchronous transmission of the data to be processed based on the data synchronization control signal, so that each analog-to-digital conversion module can send its own data to be processed at the same time, thereby improving the synchronization of data transmission.

[0033] Figure 1 FIG. 1 is a schematic diagram of a data synchronization circuit according to an exemplary embodiment of the present application. Figure 1 As shown, the data synchronization circuit 100 of the present application includes a clock module 110 and a plurality of analog-to-digital conversion modules, wherein: Figure 1 The analog-to-digital conversion module 120, the analog-to-digital conversion module 130, the analog-to-digital conversion module 140 and the analog-to-digital conversion module 150 are exemplarily shown. It should be noted that the number of analog-to-digital conversion modules in the data synchronization circuit 100 can be 2 to 3, or can be 4 or more. This application takes 4 analog-to-digital conversion modules as an example for description, and does not limit the number of analog-to-digital conversion modules.

[0034] In addition, the data synchronization circuit 100 can be connected to the data processing module 160, and the combination of the two can form a data processing circuit.

[0035] Each part is described in detail one by one through the following embodiments.

[0036] The clock module 110 in the data synchronization circuit 100 can output a source reference signal, which can be a system reference signal, denoted as sysref. Figure 2 The figure shows a signal timing diagram of a sysref signal involved in the present application. Figure 2 In the embodiment, the clock module 110 generates a sysref based on the clock signal (clk), and the sysref may have a high level interval and a low level interval in a specific period. Figure 2 The sysref shown in contains three complete high-level intervals and two complete low-level intervals. Among them, the clock signal is a periodically changing electronic signal used to synchronize the operation of various parts in the digital circuit. It usually appears in the form of a square wave, alternating between high and low levels at a fixed frequency.

[0037] In actual application scenarios, those skilled in the art may also change the period, high level interval length, low level interval length, etc. of sysref according to actual needs, which is not limited in the embodiments of the present application.

[0038] The clock module 110 may send the source reference signal to the analog-to-digital conversion module 120, the analog-to-digital conversion module 130, the analog-to-digital conversion module 140, and the analog-to-digital conversion module 150. The analog-to-digital conversion module 120 is connected to the analog-to-digital conversion module 130, the analog-to-digital conversion module 130 is connected to the analog-to-digital conversion module 140, and the analog-to-digital conversion module 140 is connected to the analog-to-digital conversion module 150. Each two connected analog-to-digital conversion modules may be connected via a general purpose input and output port (GPIO), for example, the GPIO of the analog-to-digital conversion module 120 is connected to the GPIO of the analog-to-digital conversion module 130.

[0039] The multiple analog-to-digital conversion modules in the data synchronization circuit 100 are electrically connected to the clock module respectively, including an analog-to-digital conversion module in a master mode and an analog-to-digital conversion module in a slave mode.

[0040] The master mode analog-to-digital conversion module generates a data synchronization control signal according to the source reference signal, and sends the data synchronization control signal to the slave mode analog-to-digital conversion module, so that each analog-to-digital conversion module synchronously sends the data to be processed according to the data synchronization control signal.

[0041] Through this circuit, multiple analog-to-digital conversion modules can include an analog-to-digital conversion module in a master mode and an analog-to-digital conversion module in a slave mode. The analog-to-digital conversion module in the master mode can generate a data synchronization control signal according to a source reference signal output by a clock module, and can send the data synchronization control signal to the analog-to-digital conversion module in the slave mode. In this way, the multiple analog-to-digital conversion modules can synchronously send the data to be processed based on the data synchronization control signal. Each analog-to-digital conversion module can send its own data to be processed at the same time, thereby improving the synchronization of data transmission.

[0042] It should be noted that for any analog-to-digital conversion module, you can refer to Figure 3 , Figure 3 Schematic diagram of the internal structure of an analog-to-digital conversion module involved in this application. It should be noted that the analog-to-digital conversion module in this application may be an ADC module. Figure 3In the SPI, each analog-to-digital conversion module can include a full-duplex synchronous serial (Serial Peripheral Interface, SPI) bus (Bus), a register configuration module (SPI cfg), a reference signal generation module (sysref_capture), a control signal generation module (sysref_ctrl_gen) and an input and output port (gpio).

[0043] The register configuration module is used to configure the corresponding model converter module to the master mode or the slave mode according to the received mode configuration instruction.

[0044] The mode configuration instruction may be sent by a technician via the SPI bus, and may be a program file, so that the modes of different analog-to-digital conversion modules can be set. In the embodiment of the present application, one of the multiple analog-to-digital conversion modules may be set to a master mode, and the remaining analog-to-digital conversion modules may be set to a slave mode.

[0045] For example, Figure 1 In the embodiment, the analog-to-digital conversion module 120 can be set to the master mode, and the other analog-to-digital conversion modules can be set to the slave mode.

[0046] By configuring the analog-to-digital conversion module as a master mode and a slave mode, the data synchronization control signal is uniformly generated by the analog-to-digital conversion module in the master mode, and all analog-to-digital conversion modules in the slave mode can rely on the data synchronization control signal of the analog-to-digital conversion module in the master mode, thereby ensuring that each analog-to-digital conversion module in the slave mode can send the data to be processed based on the same data synchronization control signal, reducing the complexity of data synchronization and improving the accuracy of data synchronization.

[0047] The data synchronization control signal can be recorded as sysref_ctrl. Figure 3 In the process of receiving sysref_ctrl_in, the analog-to-digital conversion module in the master mode sends sysref_ctrl through gpio, and there is a delay. The delayed signal can be called the data synchronization control output signal (recorded as sysref_ctrl_out). Correspondingly, the analog-to-digital conversion module in the slave mode receives sysref_ctrl_out through gpio, and there is also a delay in the receiving process. The delayed signal can be called the data synchronization control input signal (recorded as sysref_ctrl_in).

[0048] The reference signal generating module is used to receive the source reference signal sent by the clock module, and generate reference signal modules of each analog-to-digital conversion module based on the source reference signal.

[0049] For ease of distinction, the reference signal generating module in the analog-to-digital conversion module of the master mode may be referred to as a first reference signal generating module, the reference signal generating module in the analog-to-digital conversion module of the slave mode may be referred to as a second analog reference signal generating module, and so on.

[0050] For the analog-to-digital conversion module in the master mode, the first reference signal generation module therein can be used to generate the first reference signal according to the source reference signal sent by the clock module.

[0051] like Figure 4 The figure shows a signal timing diagram in an analog-to-digital conversion module of a main mode of the present application. Figure 4 In the first reference signal generation module, the first reference signal generation module receives sysref (source reference signal) and performs synchronous tapping on sysref to obtain the first reference signal (sysref_local). Among them, sysref_local is obtained after delaying sysref. The synchronous tapping will have a certain delay, and the synchronous tapping can also eliminate the burrs in the sysref signal, making the obtained sysref_local more straight and stable.

[0052] Next, the control signal generating module of the analog-to-digital conversion module in the main mode can be used to generate a data synchronization control signal according to the high level interval in the first reference signal.

[0053] Specifically, the control signal generating module of the analog-to-digital conversion module of the main mode can determine the interval between the falling edge of the first high level interval and the falling edge of the second high level interval in the first reference signal as the high level interval of the data synchronization control signal; wherein the first high level interval is located before the second high level interval.

[0054] Optionally, the first high level interval may be adjacent to the second high level interval. Figure 4 In the example, the first high level interval and the second high level interval are adjacent to each other, and there is a low level interval between them. In this case, the control signal generation module of the analog-to-digital conversion module of the main mode can determine the high level interval of the data synchronization control signal (sysref_ctrl) based on the interval between the falling edge of the first high level interval and the falling edge of the second high level interval.

[0055] By generating the data synchronization control signal through the analog-to-digital conversion module of the main mode, it is possible to avoid the FPGA generating the data synchronization control signal in the related art. On the one hand, the task of generating the data synchronization control signal is moved from the FPGA to the analog-to-digital conversion module of the main mode, which reduces the computing burden of the FPGA, allowing the FPGA to focus on data processing and other key tasks, and improves the overall processing efficiency of the system. On the other hand, the analog-to-digital conversion module of the main mode will generate the data synchronization control signal according to the internal state of each analog-to-digital conversion module, which helps to reduce the delay and jitter in the signal transmission process, reduce the probability of error, and ensure that the data synchronization accuracy of each analog-to-digital conversion module is higher.

[0056] After the data synchronization control signal is generated, the first reference signal generation module will also determine the moment when the data synchronization control signal is in the high level interval and the first reference signal has a rising edge as the sending moment of sending the data to be processed to the data processing module. The data processing module is used to process the data to be processed synchronously sent by each analog-to-digital conversion module, which can be a FPAG module, and the data to be processed can be ADC data.

[0057] That is to say, at the sending moment, each analog-to-digital conversion module will synchronously send its own data to be processed to the data processing module respectively.

[0058] like Figure 4 As shown, the first reference signal generation module determines the time when the sysref_ctrl is valid and the sysref_local has a rising edge as the sending time of the to-be-processed data to the data processing module. In addition, the first reference signal generation module determines the second high level interval of the sysref_local as the reference signal capture signal sysref_capture, that is, the second high level interval of the sysref_local is captured and its rising edge time is used as the sending time.

[0059] from Figure 4 It can be seen that the second high level interval of sysref_capture is synchronized with that of sysref_local, so the analog-to-digital conversion module in the main mode will start sending the data to be processed to the data processing module at the rising edge of the second high level interval of sysref_local (or sysref_capture). The rising edge of the second high level interval of sysref_local and the rising edge of sysref_capture are the same time.

[0060] At the same time, the master mode analog-to-digital conversion module will also send the data synchronization control signal to the slave mode analog-to-digital conversion module. Figure 3As can be seen, after the control signal generation module (sysref_ctrl_gen) generates sysref_ctrl, it will be sent to the slave mode analog-to-digital converter through gpio. Among them, the gpio of the master mode analog-to-digital conversion module is connected to the gpio of other analog-to-digital conversion modules. Considering that there is a delay in data transmission between sysref_ctrl_gen and gpio, when sysref_ctrl reaches gpio, it has become sysref_ctrl_out. Figure 4 It can be seen that sysref_ctrl_out will have a certain delay compared to sysref_ctrl.

[0061] For the analog-to-digital conversion module in slave mode, the second reference signal generation module therein can be used to generate a second reference signal according to the source reference signal sent by the clock module, and determine the time to send the data to be processed to the data processing module based on the second reference signal and the data synchronization control signal.

[0062] like Figure 5 The figure shows a signal timing diagram in a slave mode analog-to-digital conversion module of the present application. Figure 5 In the second reference signal generation module, the second reference signal generation module receives sysref (source reference signal) and performs synchronous tapping on sysref to obtain the second reference signal (sysref_local). Among them, sysref_local is obtained after delaying sysref. The synchronous tapping will have a certain delay, and the synchronous tapping can also eliminate the burrs in the sysref signal, making the obtained sysref_local more stable.

[0063] It can be understood that in the embodiment of the present application, the sysref and sysref_local corresponding to the analog-to-digital conversion modules in the master mode and the slave mode can be synchronized.

[0064] Next, the second reference signal generation module will receive the data synchronization control signal (sysref_ctrl_in) through the general purpose input and output port (gpio). Because the data synchronization control signal will also have a delay during the transmission process, the sysref_ctrl_in of the analog-to-digital conversion module in the slave mode will also have a certain delay compared to the sysref_ctrl_out sent by the analog-to-digital conversion module in the master mode.

[0065] Figure 5 The first high level interval and the second high level interval in are adjacent high level intervals. Figure 5 and Figure 4, it can be seen that sysref_ctrl_in is delayed from sysref_ctrl_out.

[0066] In order to ensure that the rising edge of sysref_ctrl_in is before the second high level of sysref_local is the rising edge, those skilled in the art need to reasonably set the length of the sysref high level interval and the length of the low level interval, etc., to ensure that the rising edge of sysref_ctrl_in will not be after the second high level of sysref_local is the rising edge. The second high level refers to the next high level of the high level of sysref_local based on which sysref_ctrl is based. In this way, potential timing conflicts can be avoided, thereby ensuring the synchronization of data transmission.

[0067] Next, the second reference signal generating module determines the time when the data synchronization control signal is in the high level interval and the second reference signal has a rising edge as the time to send the data to be processed.

[0068] like Figure 5 As shown, the second reference signal generation module uses sysref_ctrl_in as the data synchronization control signal, and determines the moment when sysref_ctrl_in is in the high level interval and sysref_local has a rising edge as the sending moment of sending the data to be processed to the data processing module. Among them, the sysref_local belongs to the analog-to-digital conversion module of the slave mode corresponding to the second reference signal generation module. In addition, the second reference signal generation module determines the second high level interval of the sysref_local as the reference signal capture signal sysref_capture, that is, the second high level interval of the sysref_local is captured, and its rising edge moment is used as the sending moment.

[0069] In the analog-to-digital conversion module of the slave mode, sysref_capture is synchronized with the second high level interval of sysref_local, so the analog-to-digital conversion module of the slave mode will start sending the data to be processed to the data processing module at the rising edge of the second high level interval of sysref_local (or sysref_capture). The rising edge of the second high level interval of sysref_local and the rising edge of sysref_capture are the same time.

[0070] By Figure 5 and Figure 4By comparison, it can be seen that since the sysref_local of the analog-to-digital conversion module in the master mode and the analog-to-digital conversion module in the slave mode are synchronized, and both use the rising edge of the second high level interval of sysref_local as the sending time, they both synchronously send the data to be processed at the same time.

[0071] Through this circuit, the analog-to-digital conversion module in the master mode and the analog-to-digital conversion module in the slave mode can synchronously send the data to be processed at the same sending time, thereby improving the synchronization of data transmission.

[0072] In some embodiments of this application, see Figure 6 , Figure 6 A schematic diagram of a data processing circuit provided in this application. Figure 6 In the embodiment, the data processing circuit comprises the data synchronization circuit and the data processing module as described above. The data synchronization circuit is electrically connected to the data processing module, and the data processing module is used to process the to-be-processed data synchronously sent by each analog-to-digital conversion module in the data synchronization circuit.

[0073] Similarly, in the data processing circuit, the number of analog-to-digital conversion modules may be 2, 3, or more than 4. The number of analog-to-digital conversion modules may be determined based on different usage scenarios, and is not limited in the embodiments of the present application.

[0074] That is to say, the data processing module can be connected with the data synchronization circuit to form a data processing circuit. In this data processing circuit, the data synchronization circuit is used so that the data to be processed of each analog-to-digital conversion module can be synchronously sent to the data processing module, so that the data processing module can synchronously process the multiple data to be processed, so that the phases between the various data to be processed are the same, thereby ensuring that all data received by the data processing module are sampled and processed at the same time point, avoiding phase differences caused by inconsistent timing. Therefore, the data processing module can process multiple data to be processed more accurately, thereby improving the accuracy of data processing.

[0075] In addition, since there is no need to use the data processing module to send data synchronization control signals to each analog-to-digital conversion module, the relevant configuration operations of the data processing module are eliminated. When the same data synchronization operation needs to be performed on multiple data processing modules, it is only necessary to replace the data processing module without the need for additional configuration operations, thereby improving the flexibility and efficiency of data synchronization.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0077] For the convenience of explanation, the above description has been made in conjunction with specific embodiments. However, the above exemplary discussion is not intended to be exhaustive or limit the embodiments to the specific forms disclosed above. Based on the above teachings, various modifications and variations can be obtained. The selection and description of the above embodiments are to better explain the principles and practical applications, so that those skilled in the art can better use the embodiments and various different variations of the embodiments suitable for specific use considerations.

Claims

1. A data synchronization circuit, characterized in that: include: A clock module, used for outputting a source reference signal; A plurality of analog-to-digital conversion modules are electrically connected to the clock module respectively, including an analog-to-digital conversion module in a master mode and an analog-to-digital conversion module in a slave mode; The analog-to-digital conversion module in the master mode generates a data synchronization control signal according to the source reference signal, and sends the data synchronization control signal to the analog-to-digital conversion module in the slave mode, so that each analog-to-digital conversion module performs synchronous transmission of the data to be processed according to the data synchronization control signal; The analog-to-digital conversion module of the main mode includes a first reference signal generation module, which is used to generate a first reference signal according to the source reference signal sent by the clock module; The analog-to-digital conversion module of the main mode further includes a control signal generation module, which is used to generate the data synchronization control signal according to the high level interval in the first reference signal; The control signal generating module determines the interval between the falling edge of the first high level interval and the falling edge of the second high level interval in the first reference signal as the high level interval of the data synchronization control signal; wherein the first high level interval is located before the second high level interval; The analog-to-digital conversion module of the slave mode includes a second reference signal generating module, which is used to generate a second reference signal according to the source reference signal sent by the clock module, and determine the time to send the data to be processed to the data processing module based on the second reference signal and the data synchronization control signal.

2. The data synchronization circuit according to claim 1, characterized in that: Each analog-to-digital conversion module includes a register configuration module; The register configuration module is used to configure the corresponding model converter module to a master mode or a slave mode according to a received mode configuration instruction.

3. The data synchronization circuit according to claim 1, characterized in that: The first high level interval and the second high level interval are adjacent high level intervals.

4. The data synchronization circuit according to claim 1, characterized in that: The first reference signal generating module also determines the moment when the data synchronization control signal is in a high level interval and a rising edge appears in the first reference signal as the sending moment of sending the data to be processed to the data processing module. The data processing module is used to process the data to be processed sent synchronously by each analog-to-digital conversion module.

5. The data synchronization circuit according to claim 1, characterized in that: The second reference signal generating module determines the time when the data synchronization control signal is in a high level interval and the second reference signal has a rising edge as the time when the data to be processed is sent.

6. A data processing circuit, characterized in that: comprising a data synchronization circuit and a data processing module as claimed in any one of claims 1 to 5; The data synchronization circuit is electrically connected to the data processing module, and the data processing module is used to process the to-be-processed data synchronously sent by each analog-to-digital conversion module in the data synchronization circuit.

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