Software radio communication method, apparatus and system for SoC heterogeneous platform

Abstract

The application discloses a software radio communication method and device for an SoC heterogeneous platform and a software radio communication system. The method is applied to the software radio communication system, shared memory is used for data transmission between an application node and a transmission node, and the application node sends a data read-write address to the transmission node in advance. When data is written into the transmission node, the application node sends to-be-written data packaged into a standard interface format to a storage node and simultaneously sends a data read signal to the transmission node, and the transmission node reads the to-be-written data from the storage node based on a read address. When data is written into the application node, the transmission node sends target data packaged into a standard interface format to the storage node based on a write address and simultaneously sends a data read signal to the application node, and the application node reads the target data from the storage node, thereby realizing communication between different nodes suitable for the SoC heterogeneous platform and effectively improving the communication efficiency of a componentized reconfigurable system such as the software radio.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, and in particular to a software radio communication method and device for a SoC heterogeneous platform and a software radio communication system. BACKGROUND

[0002] Software Defined Radio (SDR) is a new type of wireless architecture, which combines hardware, software and wireless technology together to form a flexible and multi-functional system. The basic idea of software defined radio is to rely on a general, standard and modular hardware platform, and to realize various functions of radio through software programming, so that the developers are released from the hardware-based and purpose-oriented radio design method. Software defined radio has achieved great results in both military and civilian fields, and various software platform architectures have emerged as the times require.

[0003] From the current application situation, the Software Communication Architecture (SCA) proposed in the Joint Tactical Radio System (JTRS) program is the earliest, most mature, most supported globally and most widely applied standard specification, and other platform architectures are modified and improved on the basis of the SCA. The SCA specifies that the software platform is designed using the componentization idea and component interface standards, and has good universality, openness and scalability, and meets the reusability of software platform components and the portability of waveform components. Therefore, the entire software radio waveform is essentially a logical link of various components in a certain relationship, and the communication of the software platform is essentially the communication between various components, and the communication mode between components directly affects the communication performance of the entire software radio.

[0004] Traditional software radio communication platform, the whole system is large in size, high cost, work scene and work system are limited, hardware platform is complex, and the real-time and high-speed of the platform are difficult to guarantee. With the popularization and application of Internet of Things, intelligent terminal and other small devices, wireless communication devices tend to be small, intelligent, low power consumption, low cost, flexibility, high integration. At the present stage, the SoC (System on Chip) heterogeneous platform using general processor + special processor such as GPP (General-Purpose Processor) + DSP (Digital Signal Process) or GPP + FPGA (Field Programmable Gate Array) or GPP + DSP + FPGA architecture is more and more widely used in small software radio devices. Small software radio devices such as single man backpack radio, single hand-held radio, etc. have almost strict requirements on data communication, data transmission time, power consumption and other indicators of software radio system. The software radio communication system based on traditional complex radio is not suitable for small SoC heterogeneous platform. In addition, the SCA (Software Communication Architecture) suggests that the software radio uses CORBA (Common Object Request Broker Architecture) middleware for communication, but this suggestion is only suitable for general processor GPP. Because of the limitation of hardware device resources, it is difficult to realize the CORBA interface for special processor DSP and FPGA. Therefore, the CORBA middleware is not suitable for SoC heterogeneous platform with general processor and special processor architecture, and the communication mode of SoC heterogeneous platform directly affects the performance of the whole software radio communication.

[0005] Therefore, how to realize the communication between different nodes suitable for SoC heterogeneous platform and improve the communication efficiency of the componentized reconfigurable system such as software radio is a technical problem to be solved by those skilled in the art. SUMMARY

[0006] The application provides a software radio communication method and device for SoC heterogeneous platform and a software radio communication system, which realizes the communication between different nodes suitable for SoC heterogeneous platform and effectively improves the communication efficiency of the componentized reconfigurable system such as software radio.

[0007] To solve the above technical problems, the embodiments of the application provide the following technical solutions:

[0008] The embodiments of the application provide a software radio communication method for SoC heterogeneous platform,

[0009] The application is applied to a software radio communication system including a dedicated processor as a transmission node, a general processor as an application node and a memory as a storage node, the application node and the transmission node perform data transmission in a shared memory mode; the application node sends data read-write address to the transmission node in advance; the method comprises:

[0010] When receiving a data write transmission node request, the application node sends the data to be written encapsulated into a standard interface format to the storage node, and sends a data read signal to the transmission node, so that the transmission node reads the data to be written from the storage node based on the read address;

[0011] When receiving a data write application node request, the transmission node sends target data encapsulated into the standard interface format to the storage node based on the write address, and sends a data read signal to the application node, so that the application node reads the target data from the storage node.

[0012] Optionally, the method further comprises:

[0013] reading configuration information from the storage node;

[0014] obtaining read configuration information and / or write configuration information and / or control information by analyzing the configuration information;

[0015] sending the read configuration information to a read module, so that the read module performs a data read operation based on a read start address in the read configuration information;

[0016] sending the write configuration information to a write module, so that the write module performs a data write operation based on a write start address in the write configuration information;

[0017] generating a control instruction based on the control information, and sending the control instruction to a target module to complete a reset operation.

[0018] Optionally, the data read operation based on the read start address in the read configuration information comprises:

[0019] reading target actual data from the storage node based on the read start address;

[0020] performing packet detection on the target actual data based on a data format of the target actual data, to obtain a start packet and / or an end packet and / or an address information packet;

[0021] generating a start flag based on the start packet, the start flag is used to trigger an address resolution operation on the address information packet, and serves as an enable flag bit of the read module or the write module.

[0022] An end flag is generated based on the end packet, the end flag is used to trigger the parsing operation of the end packet and as an enable flag bit of the read module or the write module.

[0023] Optionally, further comprising:

[0024] The hardware abstraction layer interface and the corresponding configuration package file are configured in advance for the waveform component processing the waveform data of the software wireless communication system, so that the waveform component receives or transmits the extensible signal through the hardware abstraction layer interface and the configuration package file.

[0025] The read signal and / or the write signal are received from the waveform component.

[0026] If there are multiple read signals and write signals in the enable state at the same time, arbitration is performed on each read signal and each write signal, so that the read operation and the write operation cannot be performed at the same time.

[0027] Optionally, if there are multiple read signals and write signals in the enable state at the same time, arbitration is performed on each read signal and each write signal, so that the read operation and the write operation cannot be performed at the same time, comprising:

[0028] It is judged whether the first enable signal exists.

[0029] If the first enable signal exists, after waiting for the first enable operation transmission to end, it is judged whether the second enable signal exists; if the first enable signal does not exist, it is directly judged whether the second enable signal exists.

[0030] If the second enable signal does not exist, the step of judging whether the first enable signal exists is returned.

[0031] If the second enable signal exists, it is judged whether the configuration package file is configured with a feedback signal; if the feedback signal is configured, the received data is transmitted to a module that performs an operation type different from the first enable signal, and the feedback signal is generated at the same time; if the feedback signal is not configured, the received data is transmitted to a module that performs an operation type different from the first enable signal.

[0032] The first enable signal and the second enable signal are read enable signals or write enable signals, and the first enable signal and the second enable signal correspond to read operation and write operation.

[0033] Another aspect of the embodiment of the application provides a software radio communication device for a SoC heterogeneous platform, which is applied to a software radio communication system including a special-purpose processor as a transmission node, a general-purpose processor as an application node and a memory as a storage node, and comprises:

[0034] The application node includes a general waveform component, a general hardware abstraction layer, and a general driver adaptation layer; the transmission node includes a dedicated waveform component, a dedicated hardware abstraction layer, and a dedicated driver adaptation layer; the application node and the transmission node transmit data using a shared memory method, and the general hardware abstraction layer of the application node pre-sends the data read / write address to the dedicated hardware abstraction layer of the transmission node;

[0035] The general hardware abstraction layer is used to encapsulate the data to be written into a standard interface format when there is a data write transmission node request, and send it to the memory through the general driver adaptation layer. At the same time, it sends a data read signal to the dedicated hardware abstraction layer so that the dedicated waveform component can read the data to be written from the storage node through the dedicated driver adaptation layer based on the read address.

[0036] The dedicated hardware abstraction layer is used to send the target data, encapsulated in the standard interface format, to the storage node based on the write address through the dedicated driver adaptation layer when there is a data write request to the application node. At the same time, it sends a data read signal to the general hardware abstraction layer so that the target data can be read from the storage node through the general hardware abstraction layer and the general driver adaptation layer.

[0037] Optionally, the dedicated hardware abstraction layer includes a read module, a write module, a configuration module, and an extension interface module;

[0038] The extended interface module is used to provide data interaction ports and configuration package files for the dedicated waveform component and the dedicated hardware abstraction layer;

[0039] The write module is used to obtain the data to be written from the dedicated waveform component and write the data to be written to the memory through the dedicated driver adapter layer;

[0040] The read module is used to read waveform data from the memory and transmit the waveform data to the dedicated waveform component;

[0041] The configuration module is used to read configuration information from the storage node; parse the configuration information to obtain read configuration information and / or write configuration information and / or control information; send the read configuration information to the read module to perform a data read operation based on the read start address in the read configuration information; send the write configuration information to the write module to perform a data write operation based on the write start address in the write configuration information; generate control instructions based on the control information, and send the control instructions to the target module to complete the reset operation.

[0042] Optionally, the extension interface module comprises a capacity sending module, a read arbitration module, a write arbitration module and a target interface module; the read arbitration module and the write arbitration module are not in working state at the same time;

[0043] The capacity sending module is configured to send the spatial capacity value of the transmission data of the dedicated waveform component to the read module or the write module;

[0044] The read arbitration module is configured to receive read enable signals and write enable signals from the dedicated waveform component, and when there are multiple read signals and write signals in the enabled state, arbitration is performed to determine whether the read module or the write module is currently in working state;

[0045] The write arbitration module is configured to receive read enable signals and write enable signals from the dedicated waveform component, and when there are multiple read signals and write signals in the enabled state, arbitration is performed to determine whether the read module or the write module is currently in working state.

[0046] Optionally, the write module is instantiated as a plurality of sub-write modules, each sub-write module having the same logical architecture, and each sub-write module comprising a sending module and a data packet module; the data packet module is configured to group the data generated by the dedicated waveform component into data packets according to a preset packet format to generate write data packets, and the sending module is configured to send write signals to the corresponding drive interface and write the received write data packets to the memory;

[0047] The read module is instantiated as a plurality of sub-read modules, each sub-read module having the same logical architecture, and each sub-read module comprising a receiving module and an analysis module; the analysis module is configured to obtain read address information after determining that the received grouped data meets the requirements; and the receiving module is configured to read the grouped data from the read address information and send a data enable signal to the dedicated waveform component.

[0048] The embodiment of the present application also provides an electronic device comprising a processor, wherein the processor is configured to implement the steps of the method for software radio communication of a SoC heterogeneous platform according to any one of the preceding embodiments when executing a computer program stored in a memory.

[0049] The embodiment of the present application also provides a readable storage medium, wherein the readable storage medium stores a computer program, and the computer program is configured to implement the steps of the method for software radio communication of a SoC heterogeneous platform according to any one of the preceding embodiments when executed by a processor.

[0050] Finally, the embodiment of the present application also provides a software radio communication system comprising a dedicated processor, a general-purpose processor, a memory and an electronic device;

[0051] The special-purpose processor and the general-purpose processor perform data transmission in a shared memory mode through the memory;

[0052] The electronic device comprises a processor configured to implement the steps of the method for software radio communication for SoC heterogeneous platform when executing a computer program stored in the memory.

[0053] The technical scheme provided by the application has the advantages that the underlying communication mechanism related to the heterogeneous hardware platform can be shielded to complete data routing. By encapsulating a standard communication interface, the data communication mode between waveform components and the specific hardware platform are separated, the consistency of the underlying communication access interface of the waveform components is maintained, the cross-platform portability of the waveform application in the software radio system is improved, the shared memory mode is used for data transmission between the application nodes and the transmission nodes, the transmission delay is reduced, the communication between different nodes suitable for the SoC heterogeneous platform is realized, and the communication efficiency of the componentized reconfigurable system such as the software radio is effectively improved.

[0054] In addition, the embodiments of the application also provide corresponding implementation devices, electronic devices, readable storage media and software radio communication systems for the method for software radio communication for SoC heterogeneous platform, so that the method is more practical, and the devices, the electronic devices, the readable storage media and the software radio communication systems have corresponding advantages.

[0055] It should be understood that the foregoing general description and the following detailed description are only exemplary and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0056] In order to more clearly illustrate the technical schemes of the embodiments of the application or the related art, the drawings needed to be used in the embodiment or related art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0057] Figure 1 A flowchart of a method for software radio communication for SoC heterogeneous platform provided by the embodiments of the application;

[0058] Figure 2 A framework structure diagram of a software radio communication system in an exemplary application scenario provided by the embodiments of the application;

[0059] Figure 3 A specific implementation structure diagram of a software radio communication device for SoC heterogeneous platform provided by the embodiments of the application;

[0060] Figure 4 A framework structure schematic diagram of a hardware abstraction layer provided for an exemplary application scenario of an embodiment of the present application is shown in FIG. 1.

[0061] Figure 5 A framework structure schematic diagram of a configuration module provided for an exemplary application scenario of an embodiment of the present application is shown in FIG. 2.

[0062] Figure 6 A framework structure schematic diagram of an extension interface module provided for an exemplary application scenario of an embodiment of the present application is shown in FIG. 3.

[0063] Figure 7 A working principle schematic diagram of a read arbitration module provided for an embodiment of the present application is shown in FIG. 4.

[0064] Figure 8 A working principle schematic diagram of a write arbitration module provided for an embodiment of the present application is shown in FIG. 5.

[0065] Figure 9 A framework structure schematic diagram of a write module provided for an exemplary application scenario of an embodiment of the present application is shown in FIG. 6.

[0066] Figure 10 A framework structure schematic diagram of a read module provided for an exemplary application scenario of an embodiment of the present application is shown in FIG. 7.

[0067] Figure 11 A structure diagram of a specific implementation of an electronic device provided for an embodiment of the present application is shown in FIG. 8.

[0068] Figure 12 A structure diagram of a specific implementation of a software radio communication system provided for an embodiment of the present application is shown in FIG. 9. DETAILED DESCRIPTION

[0069] In order to make the personnel in the art better understand the present application scheme, the present application is further explained in detail below in combination with the drawings and specific embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person of ordinary skill in the art without making creative efforts, fall within the scope of protection of the present application.

[0070] The terms "first", "second", "third", "fourth" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish different objects, but are not used to describe a specific sequence. In addition, the terms "include" and "have" and their any variations, are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can include steps or units not listed.

[0071] After introducing the technical solutions of the embodiments of the present invention, the various non-limiting embodiments of this application will be described in detail below.

[0072] First see Figure 1 , Figure 1 This is a flowchart illustrating a software-defined radio communication method for a SoC heterogeneous platform provided in an embodiment of the present invention. The SoC heterogeneous platform is a platform composed of a dedicated processor and a general-purpose processor. Examples of SoC heterogeneous platforms include GPP+DSP architecture, GPP+FPGA architecture, and GPP+DSP+FPGA architecture. This embodiment is applied to a software-defined radio communication system, such as... Figure 2 As shown, the software-defined radio communication system may include a dedicated processor as a transmission node, a general-purpose processor as an application node, and a memory as a storage node. This embodiment of the invention implements data communication between the dedicated processor and the general-purpose processor at the software level, without relying on hardware. Therefore, it can shield the underlying communication mechanism, and the entire data communication occurs within the same SoC heterogeneous platform, resulting in significantly higher communication efficiency than cross-platform communication. The application node and transmission node use shared memory for data transmission; that is, the two sides of the SoC heterogeneous platform communicate through the storage node. Compared to the packet-switched data communication method in the prior art, this obviously improves communication timeliness. The application node pre-sends its data read / write address to the transmission node, and subsequent data read / write operations between the application node and the transmission node are based on this data read / write address. The software-defined radio communication process may include the following:

[0073] S101: When a data write request is received from the transmission node, the application node will send the data to be written, which is encapsulated in a standard interface format, to the storage node. At the same time, it will send a data read signal to the transmission node so that the transmission node can read the data to be written from the storage node based on the read address.

[0074] In this embodiment, the standard interface format is an encapsulated standard communication interface. Encapsulating the data sent out by the waveform component into a standard interface format enables data transmission across the entire SoC heterogeneous platform. This can shield the underlying communication mechanisms related to heterogeneous hardware platforms and improve the cross-platform portability of waveform applications in software radio systems.

[0075] S102: When a data write request is received to the application node, the transmission node sends the target data, encapsulated in a standard interface format, to the storage node based on the write address, and at the same time sends a data read signal to the application node so that the application node can read the target data from the storage node.

[0076] The communication process between the application node and the transmission node of the embodiment is as follows: the application node sends the address of the storage node reading and writing data to the transmission node; the transmission node replies to the application node that the reading and writing address has been received; the application node sends data to the writing area of the storage node, then reads data from the reading area of the storage node, and transmits the read data to the waveform component of the application node; the waveform component of the transmission node reads data from the storage node, and sends the read data to the storage node.

[0077] In the technical scheme provided by the embodiment, the isomorphic hardware platform related underlying communication mechanism can be shielded, data routing can be completed, a standard communication interface can be packaged, the separation of the data communication mode between the waveform components and the specific hardware platform can be realized, the consistency of the underlying communication access interface of the waveform component can be maintained, the cross-platform portability of the waveform application in the software radio system can be improved, the shared memory mode is used for data transmission between the application node and the transmission node, the transmission delay is reduced, the communication between different nodes suitable for the SoC isomorphic platform is realized, and the communication efficiency of the componentized reconfigurable system such as the software radio is effectively improved.

[0078] It should be noted that there is no strict execution order between the steps in the present application, as long as the logical order is met, the steps can be executed simultaneously, or executed in a certain preset order, Figure 1 It is only an illustrative mode, and does not mean that only such an execution order can be represented.

[0079] It is inevitable that the entire software wireless communication system needs to be configured, based on the above embodiment, the present embodiment further provides a configuration implementation mode of the software wireless communication system, which can include:

[0080] The transmission node reads the configuration information from the storage node; the read configuration information and / or the write configuration information and / or the control information are obtained by analyzing the configuration information; the read configuration information is sent to the reading module, so that the reading module performs a data reading operation based on the read start address in the read configuration information; the write configuration information is sent to the writing module, so that the writing module performs a data writing operation based on the write start address in the write configuration information; the control instruction is generated based on the control information, and the control instruction is sent to the target module to complete the reset operation.

[0081] In the present embodiment, different configuration information has different data formats, the type of the configuration information can be known through the corresponding data format, and the configuration information type can be identified by comparing the data format with the format of the obtained configuration information.

[0082] In order to further improve the data security and ensure the integrity of the parsed data, the present embodiment further provides a triggering mechanism, that is, the process of performing a data reading operation based on the read start address in the read configuration information can include:

[0083] read target actual data from the storage node based on the read start address; perform packet detection on the target actual data based on a data format of the target actual data to obtain a start packet and / or an end packet and / or an address information packet; generate a start flag based on the start packet, the start flag being used to trigger an address resolution operation on the address information packet and serving as an enable flag bit of the read module or the write module; generate an end flag based on the end packet, the end flag being used to trigger an analysis operation on the end packet and serving as an enable flag bit of the read module or the write module.

[0084] In the embodiment, the target actual data has a specific format, which can be flexibly selected according to an actual application scenario and is pre-agreed. The target actual data is actual transmitted data. The format of the target actual data may, for example, be LD+length+data, where LD represents a data type, the LD may, for example, fixedly occupy two bytes, the length may, for example, fixedly occupy 2 bytes, and the remaining data after removing the LD and the length is the read address or the write address. That is, only the length bytes starting from the fifth byte of the target actual data need to be read to obtain the useful data, that is, the read / write address. For example, a certain LD represents a start-end packet, and a certain LD represents an address information packet. If the start-end packet, the data is the start flag or the end flag, for example, 1 represents the start, and 0 represents the end. If the address information packet, the data is the address information, and the analysis packet module sends the address to the matching module after resolving the address. The packet detection module extracts the fixed LD and the data length. The start-end data and the payload are a manifestation of different data formats of the useful data. The start flag and the end flag are two different flags, and thus correspond to two frames of packet data. The process is to process according to the specific format, and the results are different for different formats and numbers of each packet. The start flag and the end flag can also be extracted in the above manner.

[0085] It can be understood that, because the signal lines specified in the specification are relatively large in number, a common signal line may appear, that is, the read module and the write module share the same signal line for feedback, and thus the read module and the write module cannot work at the same time, which may cause the output information of the signal line to be chaotic. In order to ensure the stability of the system reading and writing, based on the above embodiment, the method can further include:

[0086] pre-configuring a hardware abstraction layer interface and a corresponding configuration package file for a waveform component processing waveform data of a software wireless communication system, so that the waveform component receives or sends an extensible signal through the hardware abstraction layer interface and the configuration package file;

[0087] receiving a read signal and / or a write signal from the waveform component;

[0088] If there are multiple read signals and write signals in the enabled state at the same time, arbitration is performed on each read signal and each write signal so that the read operation and the write operation cannot be performed at the same time.

[0089] The configuration package file is a separate file defined in the SCA specification, and all parameter information is written in the configuration package file. The configuration package file needs to configure many parameters, such as configurable optional signal related parameters and extensible signal interface related parameters. The configuration package file also includes parameter configuration information, which is used as an enabling signal of the signal. The enabling signal is a signal that is working or not working, such as 1 working and 0 not working. In short, the content of the configuration package file determines which module of the extensible interface module is working, that is, the working module is different when the parameter configuration is different.

[0090] As an optional implementation, the arbitration execution process of the above embodiment can be as follows:

[0091] It is determined whether the first enabling signal exists;

[0092] If the first enabling signal exists, it is determined whether the second enabling signal exists after the first enabling operation transmission ends; if the first enabling signal does not exist, it is directly determined whether the second enabling signal exists;

[0093] If the second enabling signal does not exist, the step of determining whether the first enabling signal exists is returned to;

[0094] If the second enabling signal exists, it is determined whether the configuration package file is configured with a feedback signal; if the feedback signal is configured, the received data is transmitted to a module that performs an operation type different from the operation type corresponding to the first enabling signal, and a feedback signal is generated; if the feedback signal is not configured, the received data is transmitted to a module that performs an operation type different from the operation type corresponding to the first enabling signal;

[0095] The first enable signal and the second enable signal are read enable signals or write enable signals, that is, the first enable signal and the second enable signal are not the same and can only be one of the read enable signal or the write enable signal, if the first enable signal is the read enable signal, the second enable signal is the write enable signal, if the first enable signal is the write enable signal, the second enable signal is the read enable signal. The first enable signal and the second enable signal correspond to the operation types of read operation and write operation, for example, if the first enable signal is the read enable signal, the corresponding operation type is the read operation, and the module corresponding to the operation type different from the first enable signal is the write module for executing the write operation, if the first enable signal is the write enable signal, the corresponding operation type is the write operation, and the module corresponding to the operation type different from the first enable signal is the read module for executing the read operation. The feedback signal can be configured in advance for the waveform component of the application node or the transmission node through the configuration package file.

[0096] The embodiment of the present application also provides a corresponding device for the software radio communication method of the SoC heterogeneous platform, further making the method more practical. Wherein, the device can be explained from the perspective of functional modules and hardware. The following describes the device for the software radio communication of the SoC heterogeneous platform provided by the embodiment of the present application, and the device for the software radio communication of the SoC heterogeneous platform described in the following can be correspondingly referred to the method for the software radio communication of the SoC heterogeneous platform described in the above.

[0097] Based on the perspective of functional modules, see Figure 3 , Figure 3 The structure diagram of the device for the software radio communication of the SoC heterogeneous platform provided by the embodiment of the present application in a specific embodiment, applied to a software radio communication system, the software radio communication system includes a special-purpose processor as a transmission node 32, a general-purpose processor as an application node 31 and a memory as a storage node 33. The device can also include:

[0098] The application node 31 includes a general-purpose waveform component 311, a general-purpose hardware abstraction layer 312 and a general-purpose driver adaptation layer 313; the transmission node 32 includes a special-purpose waveform component 321, a special-purpose hardware abstraction layer 322 and a special-purpose driver adaptation layer 323; the application node 31 and the transmission node 32 adopt a shared memory mode for data transmission, and the general-purpose hardware abstraction layer 312 of the application node 31 sends the data read-write address to the special-purpose hardware abstraction layer 322 of the transmission node 32 in advance. The special-purpose processor and the general-purpose processor directly communicate through the general-purpose hardware abstraction layer 312 and the special-purpose hardware abstraction layer 322, and the general-purpose hardware abstraction layer 312 and the special-purpose hardware abstraction layer 322 are both software functional modules packaged by computer programs realizing corresponding functions.

[0099] In the embodiment, the communication process between the application node and the transmission node is as follows: the general hardware abstraction layer 312 of the application node 31 sends the address of the read-write data of the storage node 32 to the special hardware abstraction layer 322 of the transmission node 32; the special hardware abstraction layer 322 of the transmission node 32 replies to the general hardware abstraction layer 312 of the application node 31 that the read-write address has been received; the general waveform component 311 of the application node 31 sends data to the write area of the storage through the general hardware abstraction layer 312 and the general drive adaptation layer 313 of the application node 31, reads data from the read area of the storage, and transmits the data to the general waveform component 311 of the application node 31 through the general drive adaptation layer 313 and the general hardware abstraction layer 312 of the application node 31; the special waveform component 321 of the transmission node 32 reads data from the storage through the special hardware abstraction layer 322 and the special drive adaptation layer 323 of the transmission node 31, and sends the data to the storage node through the special hardware abstraction layer 322 and the special drive adaptation layer 323 of the transmission node 32.

[0100] The general hardware abstraction layer 312 is configured to, when there is a data write-in transmission node request, encapsulate the data to be written in a standard interface format, and send the data to the storage 33 through the general drive adaptation layer 313, and send a data read signal to the special hardware abstraction layer 322, so that the special waveform component 321 reads the data to be written from the storage node 33 based on the read address through the special drive adaptation layer 323. The special hardware abstraction layer 322 is configured to, when there is a data write-in application node request, send the target data encapsulated in the standard interface format to the storage node 33 based on the write address through the special drive adaptation layer 323, and send a data read signal to the general hardware abstraction layer 312, so that the target data is read from the storage node 33 through the general hardware abstraction layer 312 and the general drive adaptation layer 313. The hardware abstraction layer, including the general hardware abstraction layer 312 and the special hardware abstraction layer 322, is an important component of the software radio communication system, can shield the bottom layer drive, complete data routing, and extend the interface and waveform component, i.e., the general waveform component 311 and the special waveform component 321, specified by the standard hardware abstraction layer, to interact. The data communication mode between the waveform components is separated from the specific hardware platform, the consistency of the bottom layer communication access interface of the waveform component is maintained, and the cross-platform portability of the waveform application is improved.

[0101] The functions of the functional modules of the software radio communication device for the SoC heterogeneous platform in the embodiment can be specifically implemented according to the methods in the method embodiments, and the specific implementation process can be referred to the related description of the method embodiments, which will not be described here.

[0102] From the above, the embodiment can realize the software radio communication suitable for the SoC heterogeneous platform, and effectively improve the communication efficiency of the software radio communication system.

[0103] Optionally, in some embodiments of the embodiment, referring to Figure 4 , the application also limits the specific structure of the special hardware abstraction layer 322, Figure 4 is a structural diagram of the special hardware abstraction layer 322. The special hardware abstraction layer 322 can include a read module, a configuration module, a write module, and an expansion interface module. In the embodiment, Figure 4 The dashed box in the configuration control part is responsible for reading and parsing hardware abstraction layer configuration data from the memory, and distributing the parsed configuration data to different modules. Through the configuration information, each module is informed of the read-write starting address or controls other modules to complete the reset function; the read module, the write module, and the expansion interface module are the main part of the special hardware abstraction layer, which is used to realize the data read and write and data routing of the special hardware abstraction layer. The waveform component and the special hardware abstraction layer interact data using a unified port. Hardware abstraction layer developers and driver developers can negotiate the hardware abstraction layer and driver interaction port according to the actual application scenario. Payload refers to the actual information to be transmitted in data transmission, which is also commonly referred to as actual data or data body.

[0104] In the embodiment, the expansion interface module is used to provide a data interaction port and a configuration package file for the special waveform component 321 and the special hardware abstraction layer 322. The write module is used to obtain the to-be-written data from the special waveform component 321, and write the to-be-written data into the storage node 33 through the special driver adapter layer 323. The read module is used to read waveform data from the storage node 33 and transmit the waveform data to the special waveform component 321. The configuration module is used to read configuration information from the storage node 33, and obtain read configuration information and / or write configuration information and / or control information by parsing the configuration information. Specifically, the configuration module sends the read configuration information to the read module to perform a data read operation based on the read starting address in the read configuration information. It sends the write configuration information to the write module to perform a data write operation based on the write starting address in the write configuration information; generates a control instruction based on the control information, and sends the control instruction to the target module to complete the reset operation.

[0105] As an optional embodiment of the embodiment, the configuration module is responsible for reading the configuration data of a specified storage space through the driver interface and parsing it. The parsed configuration data is written to the matching module for distribution. The configuration module can also control other modules to complete the reset through the configuration instruction. After the reset, the message can be reconfigured. The configuration module can include a message detection module, a start-end flag module, a parsed message module, a read message module, and a matching module. The structure can be as follows Figure 5As shown, the direction indicated by the arrow is the basic data flow direction, the configuration data enters from the reading message module, and the data is sent out by the matching module after being processed by each module. The main function is to send the read / write starting address to the reading and writing modules. The reading message module reads the data and sends it to the message detection module. The message detection module analyzes the data. If it is a start message and an end message, it is sent to the start-end flag module. If it is an address message, it is sent to the parsed message module. The start-end flag module sends the specific flag data parsed to the parsed message module. The parsed message module analyzes the message sent by the message detection module after receiving the start flag and sends the parsed address information to the matching module. If the end flag is received, the message parsing is ended. The matching module sends the read / write address to the reading and writing modules. Specifically, when the external module, i.e., the reading module or the writing module, needs to obtain the parsed data from the matching module, it will send a request to the matching module and provide configuration data. The matching data will be matched with the matching module. If the matching is successful, the data is sent out. Otherwise, it is not sent out. In order to ensure the reliability of the configuration data and reduce the possibility of unnecessary errors caused by configuration messages, the embodiment also uses a trigger mechanism, i.e., the execution message parsing operation and the end message parsing operation are triggered by the identification information. The reading message module reads the target actual data from the storage node based on the read starting address. The message detection module detects the target actual data based on the data format of the target actual data to obtain a start message and / or an end message and / or an address information message. It sends the start message and / or the end message to the start-end flag module and sends the address information message to the parsed message module. The start-end flag module generates a start flag based on the start message. The start flag is used to trigger the address parsing operation on the address information message and as an enable flag for the reading module or the writing module. An end flag is generated based on the end message. The end flag is used to trigger the parsing operation of the end message and as an enable flag for the reading module or the writing module. The general parsed message module receives the start flag to execute the message parsing operation and receives the end flag to end the message parsing operation. The matching module is used to send the address information obtained by the parsed message module to the corresponding functional module. It can be understood that the reading module and the writing module have a link relationship with the configuration module. Since the reading module and the writing module work after the configuration module, the configuration module needs to transmit the work end flag signal to the outside and use it as the enable of the reading module and the writing module. Correspondingly, the parsed message module needs to work and end according to the start flag and the end flag. The external reading module and the writing module also need the flag to determine whether to work or stop.

[0106] Optionally, in some other embodiments of the present embodiment, the structure of the extension interface module is also defined, and the main function of the extension interface module is to receive or send the extensible signal to the waveform component. Whether receiving the waveform component signal or sending the signal to the waveform component, the corresponding function module can process the signal according to the content of the configuration package file. In this way, the phenomenon that the function cannot be implemented due to the inconsistency of the extensible signal of the waveform component or the hardware abstraction layer can be avoided. The extension interface module exposes the standard hardware abstraction layer interface to the waveform component, and these interfaces are the optional signal interfaces and the extensible signal interfaces specified in the specification. The specification stipulates whether these interfaces are used by the developers of the hardware abstraction layer and the waveform component, and the specification also stipulates a configuration package file, so that the developers can configure the optional signal related parameters or other parameters in the configuration package file. Therefore, the extension interface module is set under the premise of the specification, and the coupling between the extension interface and each module is classified, and finally the extension interface is divided into four categories and four modules, please refer to Figure 6 The above-mentioned extension interface module can include a capacity sending module, a read arbitration module, a write arbitration module and a target interface module; the read arbitration module and the write arbitration module are not in working state at the same time.

[0107] In the configuration package, the signals that enable these function modules, i.e. the capacity sending module, the read arbitration module, the write arbitration module and the target interface module, need to be pre-configured. The capacity sending module is used to send the space capacity value of the corresponding waveform component transmission data to the corresponding read module or write module. The read arbitration module is used to receive the read enable signal and the write enable signal from the corresponding waveform component, and when there are multiple read signals and write signals in the enabled state, arbitration is performed to determine whether the corresponding read module or the corresponding write module is in working state. The write arbitration module is used to receive the read enable signal and the write enable signal from the corresponding waveform component, and when there are multiple read signals and write signals in the enabled state, arbitration is performed to determine whether the corresponding read module or the corresponding write module is in working state. The so-called enable signal is the signal that enables it to work. The read / write arbitration function of the read arbitration module and the write arbitration module is basically the same, and the read / write arbitration module receives the read / write enable signal from the waveform component and arbitrates it. When multiple read / write signals are enabled at the same time, the arbitration takes effect. Whether the waveform component uses the feedback signal can be configured through the configuration package. If the feedback signal is configured, a feedback signal will be sent to the waveform component after confirming the reception of the read or write signal. The read / write arbitration determines whether the read module or the write module works. The target interface module is an optional interface module, which is composed of interfaces that are not closely related to the read module and the write module.

[0108] It can be understood that, due to the relatively large number of signal lines specified in the specification, the common signal line will appear, that is, the read and write modules share the same signal line for feedback, so the read and write modules cannot work at the same time, which will lead to the output information of the signal line being chaotic. Therefore, the read arbitration module and the write arbitration module are used to restrict each other in the embodiment, when the read arbitration module works, the work of the write arbitration module is restricted until the read arbitration work is finished, and vice versa. The working procedures of the two are described below in combination with the read arbitration module flowchart shown in Figure 7 and the write arbitration module flowchart shown in Figure 8 .

[0109] For the read arbitration module: it is judged whether the write enable signal exists; if the write enable signal exists, it is waited until the write enable operation transmission is finished, and then it is judged whether the read enable signal exists; if the write enable signal does not exist, it is directly judged whether the read enable signal exists; if the read enable signal does not exist, it is returned to judge whether the write enable signal exists; if the read enable signal exists, it is judged whether the configuration package file is configured with a feedback signal; if the feedback signal is configured, the received data is transmitted to the read module, and a feedback signal is generated at the same time; if the feedback signal is not configured, the received data is transmitted to the read module.

[0110] For the write arbitration module: it is judged whether the read enable signal exists; if the read enable signal exists, it is waited until the read enable operation transmission is finished, and then it is judged whether the write enable signal exists; if the read enable signal does not exist, it is directly judged whether the write enable signal exists; if the write enable signal does not exist, it is returned to judge whether the read enable signal exists; if the write enable signal exists, it is judged whether the configuration package file is configured with a feedback signal; if the feedback signal is configured, the received data is transmitted to the write module, and a feedback signal is generated at the same time; if the feedback signal is not configured, the received data is transmitted to the write module;

[0111] The function of the write module of the embodiment is to obtain the write data and signals from the waveform component, and to write the data into the memory through driving. In this process, the address information transmitted from the configuration module needs to be received to ensure that the data information of the corresponding waveform component is written into the corresponding storage space. At the same time, after writing the waveform component information, the write module packages the related information and writes it into the planned memory information space. The function of the read module is to read the waveform data from the memory through driving, and to transmit the read waveform data to the waveform component. Optionally, in some other embodiments of the embodiment, the structure of the write module and the read module is limited, please refer to Figure 9 and Figure 10 , which can include:

[0112] The write module can be instantiated as a plurality of sub-write modules, each of which has the same logical architecture, and each of which includes a sending module and a data packet module. The data packet module is configured to package data generated by a corresponding waveform component according to a preset packet format to generate a write data packet. The sending module is configured to send a write signal to a corresponding drive interface and write the received write data packet to a storage node. The sending module and the data packet module send different data. The sending module is configured to write payload data, which is obtained by the waveform component. The data packet module is configured to package and send configuration data. The preset packet format is a data packet format that is flexibly determined according to an actual application scenario. For example, the preset packet format can be composed of LD + sending times + data length + end flag. The data packet module packages data according to the format, and then the sending module sends the service data. After the sending of the service data is completed, the sending module sends an end signal to the data packet module. The data packet module sends the packaged data to the sending module, and the sending module sends the packaged data, and the entire write module ends.

[0113] The working process of the entire write module is as follows. First, the waveform component initiates a write enable to the expansion interface module. The expansion interface module generates an enable signal after processing and transmits the enable signal to the write module. The data packet module packages data, and the sending module initiates a write signal to the drive after a handshake. The address and data are transmitted to the drive, and the drive writes the data to the storage. After the data transmission of the sending module is completed, the sending module informs the data packet module of the end of transmission. The data packet module transmits the packaged data to the sending module and transmits the packaged data to the drive by the sending module. When the drive writes the data to the storage, the write module ends the transmission. Specifically, the data packet module is configured to package data generated by a dedicated waveform component according to a preset packet format to generate a write data packet. The sending module is configured to send a write signal to a drive interface of a dedicated drive adaptation layer.

[0114] In this embodiment, the read module is instantiated as a plurality of sub-read modules, each of which has the same logical architecture, and each of which includes a receiving module and an analysis module. The analysis module analyzes the received data and parses the data packet content according to a specific data format for use by the receiving module. The specific data format is the same as the preset packet format of the write module described above. If the data format of the received data is the same as the preset packet format, the analysis operation is performed. If the data format of the received data is different from the preset packet format, the data is discarded. The analysis module is configured to obtain read address information after determining that the received packaged data meets the requirements. The receiving module is configured to read the packaged data from the read address information and send a data enable signal to a corresponding waveform component.

[0115] The working process of the reading module is as follows: first, the receiving module reads the packaged data from a certain specific address in a cycle, and transmits the read data to the analysis module for analysis. The analysis module judges whether the packaged data meets the requirements, and if the requirements are met, requests the data reading address information from the matching module, and then the receiving module reads the data from a certain address, and the reading address at this time is the reading address information issued by the matching module. The receiving module initiates a data enable to the waveform component, which simply means that the general processor waveform component is told that the data is ready and can take the data. Then the general processor waveform component will take the data from the reading module. The whole reading module work is finished. Specifically, the receiving module is used to read the packaged data from the reading address information, and send a data enable signal to the special waveform component 321.

[0116] The software radio communication device for the SoC heterogeneous platform mentioned above is described from the perspective of functional modules, and further, the present application also provides an electronic device, which is described from the perspective of hardware. Figure 11 The structure schematic diagram of the electronic device provided by the embodiment of the present application in an implementation manner is shown in the figure. Figure 11 As shown in the figure, the electronic device includes a memory 110 for storing a computer program, and a processor 111 for executing the computer program to implement the steps of the software radio communication method for the SoC heterogeneous platform mentioned in any of the above embodiments.

[0117] The processor 111 can include one or more processing cores, such as a 4-core processor, an 8-core processor, and the processor 111 can also be a controller, a microcontroller, a microprocessor, or other data processing chips, etc. The processor 111 can be implemented in at least one of the hardware forms of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 111 can also include a main processor and a coprocessor. The main processor is a processor for processing data in the wake-up state, also known as CPU (Central Processing Unit). The coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 111 can be integrated with a GPU (Graphics Processing Unit) for rendering and drawing the content required to be displayed by the display screen. In some embodiments, the processor 111 can also include an AI (Artificial Intelligence) processor for processing machine learning-related computing operations.

[0118] The memory 110 can include one or more computer-readable storage media. The computer-readable storage media can be non-transitory. The memory 110 can also include high-speed random access memory and non-volatile memory, such as one or more magnetic disk storage devices, flash memory devices. The memory 110 can be an internal storage unit of an electronic device in some embodiments, such as a hard disk of a server. The memory 110 can also be an external storage device of an electronic device in other embodiments, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. Further, the memory 110 can include both an internal storage unit and an external storage device of an electronic device. The memory 110 can be used not only to store application software and various data installed in an electronic device, such as code of a program for performing a vulnerability processing method, but also to temporarily store data that has been output or will be output. In the present embodiment, the memory 110 is used at least to store a computer program 1101, wherein the computer program is loaded and executed by the processor 111, and can implement the related steps of the software radio communication method for a SoC heterogeneous platform disclosed in any of the preceding embodiments. In addition, the resources stored in the memory 110 can also include an operating system 1102 and data 1103, etc., and the storage mode can be temporary storage or permanent storage. The operating system 1102 can include Windows, Unix, Linux, etc. The data 1103 can include, but is not limited to, data corresponding to the software radio communication result for a SoC heterogeneous platform, etc.

[0119] In some embodiments, the electronic device described above can further include a display screen 112, an input / output interface 113, a communication interface 114, or a network interface, a power supply 115, and a communication bus 116. Among them, the display screen 112 and the input / output interface 113 such as a keyboard belong to a user interface, and the optional user interface can further include a standard wired interface, a wireless interface, and the like. Optionally, in some embodiments, the display can be an LED display, a liquid crystal display, a touch liquid crystal display, an OLED (Organic Light-Emitting Diode) touch, and the like. The display can also be appropriately referred to as a display screen or a display unit, which is used to display information processed in the electronic device and to display a visualized user interface. The communication interface 114 can optionally include a wired interface and / or a wireless interface, such as a WI-FI interface, a Bluetooth interface, and the like, which is usually used to establish a communication connection between the electronic device and other electronic devices. The communication bus 116 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, or the like. The bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, Figure 11 In the figure, only one thick line is used to represent the bus, but it does not mean that there is only one bus or only one type of bus.

[0120] Those skilled in the art can understand that Figure 11 The structure shown in the figure does not constitute a limitation on the electronic device, and can include more or fewer components than the figure, for example, it can further include sensors 117 for implementing various functions.

[0121] The functions of the functional modules of the electronic device of the embodiments of the present application can be specifically implemented according to the methods in the above method embodiments, and the specific implementation process can refer to the related description of the above method embodiments, which will not be described here.

[0122] As can be seen from the above, the present embodiment can realize the communication between different nodes suitable for the SoC heterogeneous platform, and effectively improve the communication efficiency of the componentized reconfigurable system such as the software radio.

[0123] It can be understood that if the software radio communication method for the SoC heterogeneous platform in the above embodiments is implemented in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and performs all or part of the steps of the methods of the various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), an electrically erasable programmable ROM, a register, a hard disk, a multimedia card, a card-type memory (such as an SD or DX memory), a magnetic storage, a removable magnetic disk, a CD-ROM, a magnetic disk or an optical disk, and various media that can store program codes.

[0124] Based on this, the embodiment of the present application also provides a readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps of the software radio communication method for the SoC heterogeneous platform according to any one of the above embodiments are performed.

[0125] The embodiment of the present application also provides a software radio communication system for an SoC heterogeneous platform, which is shown in Figure 12 The software radio communication system can include a special processor 121, a general processor 122, a memory 123 and an electronic device 124.

[0126] In the embodiment, the special processor 121 and the general processor 122 perform data transmission in a shared memory mode through the memory 123. The electronic device 124 can include a processor, which is used to perform the steps of the software radio communication method for the SoC heterogeneous platform according to any one of the above embodiments when executing a computer program stored in the memory. Since the electronic device 124 is related to the control of the special processor 121 and the general processor 122, the electronic device 124 can be embedded into the general processor 122, or embedded into the special processor 121, or the electronic device 124 is divided into two parts, the part for controlling the special processor 121 is embedded into the special processor 121, and the part for controlling the general processor 122 is embedded into the general processor 122, which does not affect the implementation of the present application.

[0127] The functions of the functional modules of the software radio communication system of the embodiment of the present application can be implemented according to the specific implementation in the above embodiments, and the specific implementation process can be referred to the related description of the above embodiments, which will not be described here.

[0128] From the above, the embodiment can realize the communication between different nodes suitable for the SoC heterogeneous platform, and effectively improve the communication efficiency of the componentized reconfigurable system such as the software radio.

[0129] The various embodiments are described in the present specification in progressive order, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be mutually referred to. The hardware disclosed by the embodiments includes devices and electronic equipment, and the hardware is relatively simple because it corresponds to the method disclosed by the embodiments. The relevant parts can be referred to the method part.

[0130] The skilled person can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed in the present specification can be realized by electronic hardware, computer software or combination of the two. In order to clearly show the interchangeability of hardware and software, the composition and steps of the examples have been described in general in the above description. Whether the functions are realized by hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0131] The above describes in detail the method, device and system for the software radio communication of the SoC heterogeneous platform. The principle and implementation mode of the present application are described by using specific examples. The above embodiment is only used to help understand the method of the present application and its core idea. It should be pointed out that the ordinary skilled person in the art can make some improvements and modifications to the present application without departing from the principle of the present application. These improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A software defined radio communication method for a SoC heterogeneous platform, characterized in that, The application is applied to a software radio communication system including a dedicated processor as a transmission node, a general processor as an application node and a memory as a storage node, and the application node and the transmission node adopt a shared memory mode for data transmission; The application node sends a data read-write address to the transmission node in advance; the method comprises: When receiving a data write-transmission node request, the application node sends the data to be written encapsulated into a standard interface format to the storage node, and sends a data read signal to the transmission node, so that the transmission node reads the data to be written from the storage node based on a read address; When receiving a data write-application node request, the transmission node sends target data encapsulated into the standard interface format to the storage node based on a write address, and sends a data read signal to the application node, so that the application node reads the target data from the storage node; Read configuration information from the storage node, obtain read configuration information by analyzing the configuration information, and send the read configuration information to a read module, so that the read module performs a data read operation based on a read start address in the read configuration information: Read target actual data from the storage node based on the read start address, perform packet detection on the target actual data based on a data format of the target actual data, obtain a start packet and / or an end packet and / or an address information packet, generate a start flag based on the start packet, the start flag is used to trigger an address resolution operation on the address information packet and serves as an enable flag bit of the read module or a write module, and generate an end flag based on the end packet, the end flag is used to trigger an end packet resolution operation and serves as an enable flag bit of the read module or the write module.

2. The software defined radio communication method for SoC heterogeneous platform of claim 1, wherein, Further comprising: Obtain write configuration information and / or control information by analyzing the configuration information; Send the write configuration information to a write module, so that the write module performs a data write operation based on a write start address in the write configuration information; Generate a control instruction based on the control information, and send the control instruction to a target module to complete a reset operation.

3. The software defined radio communication method for SoC heterogeneous platform according to claim 1 or 2, characterized in that, Further comprising: Preconfigure a hardware abstraction layer interface and a corresponding configuration package file for a waveform component processing waveform data of a software radio communication system, so that the waveform component receives or sends an extensible signal through the hardware abstraction layer interface and the configuration package file; Receive a read signal and / or a write signal from the waveform component; If there are multiple read signals and write signals in an enabled state at the same time, arbitrate the read signals and the write signals, so that the read operation and the write operation cannot be performed at the same time.

4. The software defined radio communication method for SoC heterogeneous platform of claim 3, wherein, The arbitration of the read signals and the write signals when there are multiple read signals and write signals in an enabled state at the same time, so that the read operation and the write operation cannot be performed at the same time, comprises: Determine whether there is a first enable signal; If there is the first enable signal, determine whether there is a second enable signal after a first enable operation transmission ends; if there is no first enable signal, directly determine whether there is a second enable signal; If the second enable signal does not exist, returning to the step of judging whether the first enable signal exists; If the second enable signal exists, judging whether a feedback signal is configured in the configuration package file; if the feedback signal is configured, transmitting the received data to a module performing an operation type different from that corresponding to the first enable signal, and generating the feedback signal; if the feedback signal is not configured, transmitting the received data to the module performing the operation type different from that corresponding to the first enable signal; The first enable signal and the second enable signal are read enable signals or write enable signals, and the operation types corresponding to the first enable signal and the second enable signal are read operation and write operation.

5. A software defined radio communication apparatus for a SoC heterogeneous platform, characterized in that, Applied to a software radio communication system including a special-purpose processor as a transmission node, a general-purpose processor as an application node, and a memory as a storage node, the system comprises: The application node comprises a general-purpose waveform component, a general-purpose hardware abstraction layer, and a general-purpose driver adaptation layer; the transmission node comprises a special-purpose waveform component, a special-purpose hardware abstraction layer, and a special-purpose driver adaptation layer; the application node and the transmission node transmit data in a shared memory mode, and the general-purpose hardware abstraction layer of the application node sends data read-write addresses to the special-purpose hardware abstraction layer of the transmission node in advance; The general-purpose hardware abstraction layer is configured to, when there is a data write-transmission-node request, encapsulate the data to be written into a standard interface format, send the data to the memory through the general-purpose driver adaptation layer, and send a data read signal to the special-purpose hardware abstraction layer, so that the special-purpose waveform component reads the data to be written from the storage node based on a read address through the special-purpose driver adaptation layer; The special-purpose hardware abstraction layer is configured to, when there is a data write-application-node request, send target data encapsulated into the standard interface format to the storage node based on a write address through the special-purpose driver adaptation layer, and send a data read signal to the general-purpose hardware abstraction layer, so that the target data is read from the storage node through the general-purpose hardware abstraction layer and the general-purpose driver adaptation layer; The special-purpose hardware abstraction layer comprises a read module and a configuration module; the configuration module reads configuration information from the storage node, obtains read configuration information by analyzing the configuration information, and sends the read configuration information to the read module; the read module performs a data read operation based on a read start address in the read configuration information: reads target actual data from the storage node based on the read start address; performs packet detection on the target actual data based on a data format of the target actual data, to obtain a start packet and / or an end packet and / or an address information packet; generates a start flag based on the start packet, the start flag being used to trigger an address resolution operation on the address information packet and serving as an enable flag bit of the read module or a write module; and generates an end flag based on the end packet, the end flag being used to trigger an end-packet analysis operation and serving as an enable flag bit of the read module or the write module.

6. The software defined radio communication apparatus for SoC heterogeneous platform of claim 5, wherein, The special-purpose hardware abstraction layer comprises a write module and an extension interface module; The expansion interface module is configured to provide a data interaction port and a configuration package file for the dedicated waveform component and the dedicated hardware abstraction layer; The writing module is configured to obtain to-be-written data from the dedicated waveform component and write the to-be-written data into the memory through the dedicated drive adaptation layer; The reading module is configured to read waveform data from the memory and transmit the waveform data to the dedicated waveform component; The configuration module is configured to read configuration information from the storage node; Write configuration information and / or control information are obtained by analyzing the configuration information; The write configuration information is sent to the writing module to perform a data writing operation based on a write start address in the write configuration information; Control instructions are generated based on the control information, and the control instructions are sent to a target module to complete a reset operation.

7. The software defined radio communication apparatus for SoC heterogeneous platform of claim 6, wherein, The expansion interface module includes a capacity sending module, a read arbitration module, a write arbitration module, and a target interface module; the read arbitration module and the write arbitration module are not in a working state at the same time; The capacity sending module is configured to send a spatial capacity value of the dedicated waveform component transmission data to the reading module or the writing module; The read arbitration module is configured to receive a read enable signal and a write enable signal from the dedicated waveform component, and when there are multiple read signals and write signals in an enabled state, arbitration is performed to determine whether the reading module or the writing module is currently in a working state; The write arbitration module is configured to receive a read enable signal and a write enable signal from the dedicated waveform component, and when there are multiple read signals and write signals in an enabled state, arbitration is performed to determine whether the reading module or the writing module is currently in a working state.

8. The software defined radio communication apparatus for SoC heterogeneous platform of claim 6, wherein, The writing module is instantiated as a plurality of sub-writing modules, each sub-writing module having the same logical architecture, and each sub-writing module including a sending module and a data packet module; the data packet module is configured to group data generated by the dedicated waveform component into data packets according to a preset packet format to generate write data packets, and the sending module is configured to send a write signal to a corresponding drive interface and write the received write data packets into the memory; The reading module is instantiated as a plurality of sub-reading modules, each sub-reading module having the same logical architecture, and each sub-reading module including a receiving module and an analysis module; the analysis module is configured to obtain read address information after determining that the received grouped data meets the requirements; and the receiving module is configured to read the grouped data from the read address information and send a data enable signal to the dedicated waveform component.

9. A software radio communication system, characterized by The electronic device includes a processor, a general-purpose processor, a memory, and an electronic device; The dedicated processor and the general-purpose processor perform data transmission through the memory in a shared memory mode; The electronic device includes a processor, a general-purpose processor, a memory, and an electronic device; The processor is configured to implement the steps of the software radio communication method for a SoC heterogeneous platform according to any one of claims 1 to 4 when executing a computer program stored in the memory.

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