Wireless communication circuitry, methods, devices, and storage media

Abstract

The application provides a wireless communication circuit, method, device and storage medium. In the circuit, when starting to send a first SRS, a processor sends a first value to a register, so that a controller can control a radio frequency switch to connect a second port with a first antenna port and disconnect a first port from the first antenna port according to the first value provided by the register; after the first SRS is sent, the processor immediately sends a second value to the register, so that the controller can timely control the radio frequency switch to disconnect the second port from the first antenna port and connect the first port with the first antenna port according to the second value provided by the register. Thus, after the first SRS is sent, the receiving channel in the frequency division duplex mode can be quickly recovered, and the data throughput of the receiving channel is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of radio frequency electronic technology, and in particular to a wireless communication circuit, method, device and storage medium. BACKGROUND

[0002] Non-Standalone (NSA) refers to coexistence of 4G base stations and 5G base stations on the wireless access network side, and a networking architecture of a core network adopting 4G core network or 5G core network, which requires 4G network and 5G network to work cooperatively.

[0003] Currently, a dual connectivity (DC) mode is adopted in NSA to realize cooperative work of 4G network and 5G network, which requires that, in a terminal device supporting simultaneous transmission and reception of 4G and 5G, a radio frequency front-end device supports simultaneous work of 4G and 5G radio frequency front-end paths. Especially when the 5G network is a TDD frequency band, it is required to ensure that, in a radio frequency transmission path switching scenario of 5G uplink signals, the 4G and 5G radio frequency reception paths can work simultaneously.

[0004] However, currently, in a terminal device supporting simultaneous transmission and reception of dual standards, when the 4G intermediate frequency band and the 5G n41 frequency band dual standard (such as a frequency band combination of DC_B3-n41) work simultaneously, the radio frequency transmission path of 5G uplink signals needs to be switched, such as multiple sounding reference signals (SRS) of n41 being roundly transmitted, which will cause the 4G radio frequency reception path (such as multiple-in multiple-out (MIMO) radio frequency reception path of B3) to be interrupted, thereby reducing the data throughput of the terminal device. SUMMARY

[0005] In order to solve the technical problem of the 4G radio frequency reception path of the terminal device supporting NSA standard being interrupted, the present application provides a wireless communication circuit, method, device and storage medium, which can quickly recover the radio frequency reception path of the 4G network when the SRS round transmission interrupts the 4G radio frequency reception path, thereby guaranteeing the data throughput of the terminal device.

[0006] In a first aspect, the embodiments of the present application provide a wireless communication circuit. The circuit comprises a processor, a register, a controller and a radio frequency switch; the processor is electrically connected with the register, and the controller is electrically connected with the register and the radio frequency switch respectively; the radio frequency switch comprises at least a first port, a second port and a first antenna port; when the first port is in communication with the first antenna port, a receiving channel of a radio frequency signal in a frequency division duplex mode is formed; when the second port is in communication with the first antenna port, a sounding reference signal (SRS) sending channel for sending SRS is formed; the processor is configured to generate a first SRS and send a first value to the register when the first SRS is generated; the processor is further configured to send a second value to the register after the first SRS is sent through the SRS sending channel (which can be understood as when the first SRS is completely sent); the register is configured to output the first value to the controller when the first value is received; the register is further configured to output the second value to the controller when the second value is received; and the controller is configured to control the radio frequency switch to connect the second port with the first antenna port and disconnect the first port from the first antenna port when the first value is received; the controller is further configured to control the radio frequency switch to disconnect the second port from the first antenna port and connect the first port with the first antenna port when the second value is received.

[0007] The above implementation can be understood as follows: when the processor generates the first SRS (which can be understood as when the processor starts to send the first SRS, or understood as before the first SRS is about to be sent through the SRS sending channel), the processor sends the first value to the register, so that the controller can control the radio frequency switch to connect the second port with the first antenna port and disconnect the first port from the first antenna port according to the first value provided by the register; after the first SRS is completely sent, the processor can immediately send the second value to the register, so that the controller can timely control the radio frequency switch to disconnect the second port from the first antenna port and connect the first port with the first antenna port according to the second value provided by the register. In this way, after the first SRS is completely sent, the receiving channel in the frequency division duplex mode can be quickly recovered, so as to ensure the data throughput of the receiving channel.

[0008] According to the first aspect, the radio frequency switch further comprises a second antenna port, the register comprises a first register and a second register; wherein the processor is electrically connected with the register, comprising: the processor is electrically connected with the first register and the second register respectively; wherein the controller is electrically connected with the register and the radio frequency switch respectively, comprising: the controller is electrically connected with the first register, the second register and the radio frequency switch respectively; wherein the processor is configured to generate a first SRS, and send a first value to the register when the first SRS is generated, comprising: the processor is configured to generate a first SRS, and send a first value to the first register when the first SRS is generated; wherein the processor is further configured to send a second value to the register after the first SRS is sent through the SRS sending channel, comprising: the processor is further configured to send a second value to the first register after the first SRS is sent through the SRS sending channel; wherein the register is configured to output the first value to the controller when the first value is received, comprising: the first register is configured to output the first value to the controller when the first value is received; wherein the register is further configured to output the second value to the controller when the second value is received, comprising: the first register is further configured to output the second value to the controller when the second value is received; wherein the processor is further configured to send a third value or a fourth value to the second register when the first SRS is generated, and after the first SRS is sent through the SRS sending channel; the second register is configured to output the third value to the controller when the third value is received; the second register is further configured to output the fourth value to the controller when the fourth value is received; wherein the controller is configured to control the radio frequency switch to connect the second port with the first antenna port, and disconnect the connection between the first port and the first antenna port when the first value is received, comprising: the controller is configured to control the radio frequency switch to connect the second port with the first antenna port, and disconnect the connection between the first port and the first antenna port when the first value and the third value are received; or, the controller is configured to control the radio frequency switch to connect the second port with the second antenna port, and disconnect the connection between the first port and the second antenna port when the first value and the fourth value are received; wherein the controller is further configured to control the radio frequency switch to disconnect the connection between the second port and the first antenna port, and connect the first port with the first antenna port when the second value is received, comprising: the controller is further configured to control the radio frequency switch to disconnect the connection between the second port and the first antenna port, and connect the first port with the first antenna port when the second value and the third value are received; or, the controller is further configured to control the radio frequency switch to disconnect the connection between the second port and the first antenna port, and connect the first port with the first antenna port when the second value and the fourth value are received.

[0009] Therefore, by setting the second register, the antenna port that can be preempted is determined, such as the first antenna port or the second antenna port, the first register determines the preemption of the first port and the second port to the antenna port determined by the second register, so that the SRS sending channel is connected when the first SRS needs to be sent, and after the first SRS is sent, the receiving channel can be quickly recovered from the interrupted state to the connected state, thereby guaranteeing the data throughput of the receiving channel.

[0010] In some embodiments, the radio frequency switch further comprises a second antenna port, and the registers comprise a first register, a second register, and a third register. The processor is electrically connected with the registers, including that the processor is electrically connected with the first register, the second register, and the third register, respectively. The controller is electrically connected with the registers and the radio frequency switch, including that the controller is electrically connected with the first register, the second register, the third register, and the radio frequency switch, respectively. The processor is configured to generate the first SRS and send a first value to the registers when the first SRS is generated, including that the processor is configured to generate the first SRS and send the first value to the first register when the first SRS is generated. The processor is further configured to send a second value to the registers after the first SRS is sent through the SRS sending channel, including that the processor is further configured to send the second value to the first register after the first SRS is sent through the SRS sending channel. The registers are configured to output the first value to the controller when the first value is received, including that the first register is configured to output the first value to the controller when the first value is received. The registers are further configured to output the second value to the controller when the second value is received, including that the first register is further configured to output the second value to the controller when the second value is received. When the second register is in an enabled state and the third register is not in the enabled state, the processor is further configured to send a third value to the second register when the first SRS is generated and after the first SRS is sent through the SRS sending channel. The second register in the enabled state is configured to output the third value to the controller when the third value is received. When the third register is in the enabled state and the second register is not in the enabled state, the processor is further configured to send a fourth value to the third register when the first SRS is generated and after the first SRS is sent through the SRS sending channel. The third register in the enabled state is configured to output the fourth value to the controller when the fourth value is received. The controller is configured to control the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port when the first value is received, including that the controller is configured to control the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port when the first value and the third value are received. Alternatively, the controller is configured to control the radio frequency switch to connect the second port with the second antenna port and disconnect the connection between the first port and the second antenna port when the first value and the fourth value are received. The controller is further configured to control the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port when the second value is received, including that the controller is further configured to control the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port when the second value and the third value are received.Alternatively, the controller is further configured to, when the second value and the fourth value are received, control the radio frequency switch to disconnect the second port from the first antenna port and connect the first port to the first antenna port.

[0011] Thus, when there are two antenna ports, one antenna port, such as the first antenna port, is controlled by setting the second register and another antenna port, such as the second antenna port, is controlled by setting the third register. In this way, the controller can control the second port or the first port to connect to the antenna port controlled by the second register or the third register which is currently in the enabled state according to the first value provided by the first register. Alternatively, the controller can control the second port or the first port to disconnect from the antenna port controlled by the second register or the third register which is currently in the enabled state according to the second value provided by the first register, so that it can be better adapted to the actual application scenario.

[0012] In some embodiments, the register further comprises a fourth register; the processor is electrically connected with the register, including that the processor is electrically connected with the first register, the second register, the third register and the fourth register respectively; the controller is electrically connected with the register and the radio frequency switch respectively, including that the controller is electrically connected with the first register, the second register, the third register, the fourth register and the radio frequency switch respectively; the processor is further configured to send a fifth value or a sixth value to the fourth register when the first SRS is generated and after the first SRS is sent through the SRS sending channel; the fourth register is configured to output the fifth value to the controller when the fifth value is received; the fourth register is further configured to output the sixth value to the controller when the sixth value is received; when the second register is in the enabled state and the third register is not in the enabled state: the controller is configured to control the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port when the first value and the third value are received, including that the controller is configured to control the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port when the first value, the third value and the fifth value are received; or the controller is configured to control the radio frequency switch to connect the second port with the second antenna port and disconnect the connection between the first port and the second antenna port when the first value, the third value and the sixth value are received; the controller is further configured to control the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port when the second value and the third value are received, including that the controller is further configured to control the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port when the second value, the third value and the fifth value are received; or the controller is further configured to control the radio frequency switch to disconnect the connection between the second port and the second antenna port and connect the first port with the second antenna port when the second value, the third value and the sixth value are received; when the third register is in the enabled state and the second register is not in the enabled state: the controller is configured to control the radio frequency switch to connect the second port with the second antenna port and disconnect the connection between the first port and the second antenna port when the first value and the fourth value are received, including that the controller is configured to control the radio frequency switch to connect the second port with the second antenna port and disconnect the connection between the first port and the second antenna port when the first value, the fourth value and the fifth value are received; or the controller is configured to control the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port when the first value, the fourth value and the sixth value are received.The controller is further configured to, when the second value and the fourth value are received, control the radio frequency switch to disconnect the second port from the first antenna port, and connect the first port to the first antenna port, including that the controller is further configured to, when the second value, the fourth value and the fifth value are received, control the radio frequency switch to disconnect the second port from the first antenna port, and connect the first port to the first antenna port, or the controller is further configured to, when the second value, the fourth value and the sixth value are received, control the radio frequency switch to disconnect the second port from the second antenna port, and connect the first port to the second antenna port.

[0013] Thus, by setting four registers to cooperate with each other, the communication and interruption of each input port and each antenna port in the radio frequency switch are realized, so that the actual application scenarios can be better adapted.

[0014] According to the first aspect, or any one of the implementations of the first aspect, the registers, the controller and the radio frequency switch are arranged in a radio frequency front-end module of the terminal device. Thus, the wireless communication circuit can solve the problem that the SRS rotation easily interrupts the receiving channel of the FDD mode radio frequency signal in the radio frequency front-end module.

[0015] According to the first aspect, or any one of the implementations of the first aspect, the terminal device supports EN-DC (which can be understood as that the terminal device works in an EN-DC communication system), and supports DC_B3-n41 combination.

[0016] According to the first aspect, or any one of the implementations of the first aspect, the first antenna port and the second antenna port of the radio frequency switch are coupled with an antenna module of the terminal device respectively; wherein when the SRS sending channel is connected, the first SRS is sent through the antenna module; and when the receiving channel is connected, the B3 frequency band radio frequency signal and the n41 frequency band radio frequency signal are received through the antenna module.

[0017] According to the first aspect, or any one of the implementations of the first aspect, the antenna module includes 4 antennas; in the DC_B3-n41 combination, when the SRS generated by the processor includes the first SRS and the second SRS, the first SRS and the second SRS are rotated by 2 antennas; and in the DC_B3-n41 combination, when the SRS generated by the processor includes the first SRS, the second SRS, the third SRS and the fourth SRS, the first SRS, the second SRS, the third SRS and the fourth SRS are rotated by 4 antennas.

[0018] In a DC_B3-n41 combination, when the SRS generated by the processor includes a first SRS, and a second SRS, a third SRS, and a fourth SRS, the first SRS, the second SRS, the third SRS, and the fourth SRS are transmitted through 4 antennas, including: in the DC_B3-n41 combination, when the SRS generated by the processor includes the first SRS, and the second SRS, the third SRS, and the fourth SRS, the processor sends the first SRS, the second SRS, the third SRS, and the fourth SRS to the first transceiver module; the first transceiver module sends the first SRS to the first receiving module, and the first receiving module sends the first SRS through the corresponding antenna; the first transceiver module sends the second SRS through the corresponding antenna; the first transceiver module sends the third SRS to the second transceiver module, and the second transceiver module sends the third SRS through the corresponding antenna; the first transceiver module sends the fourth SRS to the second receiving module, and the second receiving module sends the fourth SRS through the corresponding antenna.

[0019] According to the first aspect, or any one of the implementations of the first aspect, the register, the controller, and the radio switch are arranged in a radio front-end module of the terminal device, including: the register, the controller, and the radio switch are specifically arranged in the first receiving module; wherein in the first receiving module: the first port includes a first radio receiving port and a second radio receiving port, the first radio port is used to receive a radio signal of the n41 frequency band, and the second radio port is used to receive a radio signal of the B3 frequency band; the controller is used to, when the first value is received, control the radio switch to communicate the second port with the first antenna port and disconnect the connection between the first port and the first antenna port, including: the controller is used to, when the first value is received, control the radio switch to communicate the second port with the first antenna port, disconnect the connection between the first radio receiving port and the first antenna port, and disconnect the connection between the second radio receiving port and the first antenna port; the controller is further used to, when the second value is received, control the radio switch to disconnect the connection between the second port and the first antenna port and communicate the first port with the first antenna port, including: the controller is further used to, when the second value is received, control the radio switch to disconnect the connection between the second port and the first antenna port, communicate the first radio receiving port with the first antenna port, and communicate the second radio receiving port with the first antenna port.

[0020] According to the first aspect, or any one of the implementations of the first aspect, the register, the controller and the radio frequency switch are integrated into one functional device, and integrated into a radio frequency front-end module of the terminal device. In this way, the functional device can occupy less space on a circuit board in the terminal device, and installation is facilitated.

[0021] According to the first aspect, or any one of the implementations of the first aspect, the register, the controller and the radio frequency switch are independent functional devices, and are respectively integrated into a radio frequency front-end module of the terminal device. In this way, maintenance is facilitated, and any one or more of the devices can be replaced individually.

[0022] In a second aspect, an embodiment of the present application provides a terminal device. The terminal device comprises a radio frequency front-end module, an antenna module and the wireless communication circuit of the first aspect and any one of the implementations of the first aspect.

[0023] The second aspect and any one of the implementations of the second aspect correspond to the first aspect and any one of the implementations of the first aspect, respectively. The technical effects corresponding to the second aspect and any one of the implementations of the second aspect can be referred to the technical effects corresponding to the first aspect and any one of the implementations of the first aspect, which will not be described herein again.

[0024] In a third aspect, an embodiment of the present application provides a wireless communication method. The method is applied to a wireless communication circuit. The wireless communication circuit comprises a processor, a register, a controller and a radio frequency switch. The processor is electrically connected with the register, and the controller is electrically connected with the register and the radio frequency switch, respectively. The radio frequency switch comprises at least a first port, a second port and a first antenna port. When the first port is in communication with the first antenna port, a receiving channel of a radio frequency signal in a receive frequency division duplex mode is formed. When the second port is in communication with the first antenna port, a sounding reference signal (SRS) transmission channel for transmitting an SRS is formed. The method comprises the following steps: the processor generates a first SRS, and sends a first value to the register when the first SRS is generated; the register outputs the first value to the controller when the first value is received; the controller controls the radio frequency switch to connect the second port with the first antenna port and disconnect the first port from the first antenna port when the first value is received; the processor sends a second value to the register after the first SRS is transmitted through the SRS transmission channel; the register outputs the second value to the controller when the second value is received; and the controller controls the radio frequency switch to disconnect the second port from the first antenna port and connect the first port with the first antenna port when the second value is received.

[0025] The wireless communication circuit is, for example, the wireless communication circuit of the first aspect and any one of the implementations of the first aspect.

[0026] According to a third aspect, the radio frequency switch further comprises a second antenna port, the register comprises a first register and a second register; the processor is electrically connected with the first register and the second register respectively; the controller is electrically connected with the first register, the second register and the radio frequency switch respectively; the processor generates the first SRS and sends a first value to the register when the first SRS is generated, comprising: the processor generates the first SRS and sends the first value to the first register when the first SRS is generated; wherein the register outputs the first value to the controller when the first value is received, comprising: the first register outputs the first value to the controller when the first value is received; wherein the processor sends a second value to the register after the first SRS is sent through the SRS sending channel, comprising: the processor sends the second value to the first register after the first SRS is sent through the SRS sending channel; wherein the register outputs the second value to the controller when the second value is received, comprising: the first register outputs the second value to the controller when the second value is received; the method further comprises: the processor sends a third value or a fourth value to the second register when the first SRS is generated, and after the first SRS is sent through the SRS sending channel; the second register outputs the third value to the controller when the third value is received; the second register outputs the fourth value to the controller when the fourth value is received; wherein the controller controls the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port when the first value is received, comprising: the controller controls the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port when the first value and the third value are received; or the controller controls the radio frequency switch to connect the second port with the second antenna port and disconnect the connection between the first port and the second antenna port when the first value and the fourth value are received; wherein the controller controls the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port when the second value is received, comprising: the controller controls the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port when the second value and the third value are received; or the controller controls the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port when the second value and the fourth value are received.

[0027] In a third aspect, or any implementation thereof, the radio frequency switch further includes a second antenna port, the registers include a first register, a second register, and a third register; the processor is electrically connected with the first register, the second register, and the third register respectively; the controller is electrically connected with the first register, the second register, the third register, and the radio frequency switch respectively; wherein the register, when receiving the first value, outputs the first value to the controller, including: the first register, when receiving the first value, outputs the first value to the controller; wherein the processor, after the first SRS is sent through the SRS sending channel, sends a second value to the register, including: the processor, after the first SRS is sent through the SRS sending channel, sends the second value to the first register; wherein the register, when receiving the second value, outputs the second value to the controller, including: the first register, when receiving the second value, outputs the second value to the controller; the method further includes: when the second register is in an enabled state and the third register is not in the enabled state, the processor sends a third value to the second register when generating the first SRS and after the first SRS is sent through the SRS sending channel; the second register in the enabled state, when receiving the third value, outputs the third value to the controller; when the third register is in the enabled state and the second register is not in the enabled state, the processor sends a fourth value to the third register when generating the first SRS and after the first SRS is sent through the SRS sending channel; the third register in the enabled state, when receiving the fourth value, outputs the fourth value to the controller; wherein the controller, when receiving the first value, controls the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port, including: the controller, when receiving the first value and the third value, controls the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port; or the controller, when receiving the first value and the fourth value, controls the radio frequency switch to connect the second port with the second antenna port and disconnect the connection between the first port and the second antenna port; wherein the controller, when receiving the second value, controls the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port, including: the controller, when receiving the second value and the third value, controls the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port; or the controller, when receiving the second value and the fourth value, controls the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port.

[0028] According to a third aspect, or any possible implementation mode of the third aspect, the register further comprises a fourth register; the processor is electrically connected with the first register, the second register, the third register and the fourth register respectively; the controller is electrically connected with the first register, the second register, the third register, the fourth register and the radio frequency switch respectively; the method further comprises: the processor sends the fifth value or the sixth value to the fourth register when the first SRS is generated and after the first SRS is sent through the SRS sending channel; the fourth register outputs the fifth value to the controller when the fifth value is received; the fourth register outputs the sixth value to the controller when the sixth value is received; wherein, when the second register is in the enabled state and the third register is not in the enabled state: wherein, the controller controls the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port when the first value and the third value are received, comprising: the controller controls the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port when the first value, the third value and the fifth value are received; or, the controller controls the radio frequency switch to connect the second port with the second antenna port and disconnect the connection between the first port and the second antenna port when the first value, the third value and the sixth value are received; wherein, the controller controls the radio frequency switch to connect the second port with the second antenna port and disconnect the connection between the first port and the second antenna port when the first value and the fourth value are received, comprising: the controller controls the radio frequency switch to connect the second port with the second antenna port and disconnect the connection between the first port and the second antenna port when the first value, the fourth value and the fifth value are received; or, the controller controls the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port when the first value, the fourth value and the sixth value are received; wherein, the controller controls the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port when the second value and the third value are received, comprising: the controller controls the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port when the second value, the third value and the fifth value are received; or, the controller controls the radio frequency switch to disconnect the connection between the second port and the second antenna port and connect the first port with the second antenna port when the second value, the third value and the sixth value are received; wherein, the controller controls the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port when the second value and the fourth value are received, comprising: the controller controls the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port when the second value, the fourth value and the fifth value are received; or, the controller controls the radio frequency switch to disconnect the connection between the second port and the second antenna port and connect the first port with the second antenna port when the second value, the fourth value and the sixth value are received.

[0029] According to a third aspect, or any possible implementation mode of the third aspect, the register, the controller and the radio frequency switch are arranged in a radio frequency front-end module of the terminal device; the terminal device works in an EN-DC communication system and supports a DC_B3-n41 combination; the first antenna port and the second antenna port of the radio frequency switch are coupled with antenna modules of the terminal device respectively; the method further comprises: when the SRS sending channel is connected, sending the first SRS through the antenna modules; when the receiving channel is connected, receiving the radio frequency signals of the B3 frequency band and the n41 frequency band through the antenna modules.

[0030] According to the third aspect, or any possible implementation mode of the third aspect, the antenna modules comprise four antennas; the method further comprises: in the DC_B3-n41 combination, when the SRS generated by the processor comprises the first SRS and the second SRS, the first SRS and the second SRS are transmitted through two antennas alternately; in the DC_B3-n41 combination, when the SRS generated by the processor comprises the first SRS and the second SRS, the third SRS and the fourth SRS, the first SRS, the second SRS, the third SRS and the fourth SRS are transmitted through four antennas alternately.

[0031] According to the third aspect, or any possible implementation mode of the third aspect, the radio frequency front-end module comprises a first transceiver module, a second transceiver module, a first receiving module and a second receiving module, and the first transceiver module, the second transceiver module, the first receiving module and the second receiving module correspond to one antenna respectively; in the DC_B3-n41 combination, when the SRS generated by the processor comprises the first SRS and the second SRS, the third SRS and the fourth SRS, the first SRS, the second SRS, the third SRS and the fourth SRS are transmitted through four antennas alternately, comprising: in the DC_B3-n41 combination, when the SRS generated by the processor comprises the first SRS and the second SRS, the third SRS and the fourth SRS, the processor sends the first SRS, the second SRS, the third SRS and the fourth SRS to the first transceiver module; the first transceiver module sends the first SRS to the first receiving module, and the first receiving module sends the first SRS through the corresponding antenna; the first transceiver module sends the second SRS through the corresponding antenna; the first transceiver module sends the third SRS to the second transceiver module, and the second transceiver module sends the third SRS through the corresponding antenna; the first transceiver module sends the fourth SRS to the second receiving module, and the second receiving module sends the fourth SRS through the corresponding antenna.

[0032] In a third aspect, or any possible implementation of the third aspect, the method according to claim 18, wherein the register, the controller and the radio frequency switch are arranged in the first receiving module; the first port comprises a first radio frequency receiving port and a second radio frequency receiving port, the first radio frequency port receives a radio frequency signal of the n41 frequency band, and the second radio frequency port receives a radio frequency signal of the B3 frequency band; when the first value is received, the controller controls the radio frequency switch to connect the second port with the first antenna port and disconnect the first port from the first antenna port, including: when the first value is received, the controller controls the radio frequency switch to connect the second port with the first antenna port, disconnect the first radio frequency receiving port from the first antenna port, and disconnect the second radio frequency receiving port from the first antenna port; when the second value is received, the controller controls the radio frequency switch to disconnect the second port from the first antenna port and connect the first port with the first antenna port, including: when the second value is received, the controller controls the radio frequency switch to disconnect the second port from the first antenna port, connect the first radio frequency receiving port with the first antenna port, and connect the second radio frequency receiving port with the first antenna port.

[0033] The third aspect and any possible implementation of the third aspect correspond to the first aspect and any possible implementation of the first aspect respectively. The technical effects of the third aspect and any possible implementation of the third aspect correspond to the technical effects of the first aspect and any possible implementation of the first aspect respectively, which will not be described here.

[0034] In a fourth aspect, the embodiments of the present application provide a computer readable medium for storing a computer program, the computer program comprising instructions for executing the method in the third aspect or any possible implementation of the third aspect.

[0035] The fourth aspect and any possible implementation of the fourth aspect correspond to the third aspect and any possible implementation of the third aspect respectively. The technical effects of the fourth aspect and any possible implementation of the fourth aspect correspond to the technical effects of the third aspect and any possible implementation of the third aspect respectively, which will not be described here.

[0036] In a fifth aspect, the embodiments of the present application provide a computer program, the computer program comprising instructions for executing the method in the third aspect or any possible implementation of the third aspect.

[0037] The fifth aspect and any possible implementation of the fifth aspect correspond to the third aspect and any possible implementation of the third aspect respectively. The technical effects of the fifth aspect and any possible implementation of the fifth aspect correspond to the technical effects of the third aspect and any possible implementation of the third aspect respectively, which will not be described here.

[0038] In a sixth aspect, an embodiment of the present application provides a chip system applied to a terminal device, the chip system comprising a processor and a radio frequency front-end module, the radio frequency front-end module comprising a register, a controller and a radio frequency switch; the processor is configured to invoke and run a computer program from a memory of the terminal device, so that the terminal device installed with the chip system performs the wireless communication method of the third aspect and any one of the implementation manners of the third aspect.

[0039] The sixth aspect and any one of the implementation manners of the sixth aspect correspond to the third aspect and any one of the implementation manners of the third aspect respectively. The technical effects corresponding to the sixth aspect and any one of the implementation manners of the sixth aspect can refer to the technical effects corresponding to the third aspect and any one of the implementation manners of the third aspect, which will not be described herein again. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 A schematic diagram of a wireless communication system is exemplarily shown;

[0041] Figure 2 A schematic diagram of a terminal device is exemplarily shown;

[0042] Figure 3 A schematic diagram of another terminal device is exemplarily shown;

[0043] Figure 4 A schematic diagram of another terminal device is exemplarily shown;

[0044] Figure 5 A schematic diagram of a partial structure of a radio frequency front-end module is exemplarily shown;

[0045] Figure 6 A configuration schematic diagram of a TDD mode is exemplarily shown;

[0046] Figure 7 A schematic diagram of slots available for SRS in each slot of a TDD mode is exemplarily shown;

[0047] Figure 8 A schematic diagram of a TDD mode and an FDD mode affected by SRS rotation is exemplarily shown;

[0048] Figure 9 A schematic diagram of a time delay existing in a radio frequency receiving channel of a B3 frequency band recovered by SOC self-scheduling is exemplarily shown;

[0049] Figure 10 A time comparison schematic diagram of a radio frequency receiving channel of a B3 frequency band recovered by device self-scheduling and a radio frequency receiving channel of a B3 frequency band recovered by SOC self-scheduling is exemplarily shown;

[0050] Figure 11 A structure diagram of a wireless communication circuit provided by the embodiment of the application is shown as an example;

[0051] Figure 12 A structure diagram of a radio frequency front end module of a radio frequency receiving channel corresponding to a radio frequency signal of a frequency band in a frequency division duplex mode provided by the embodiment of the application is shown as an example;

[0052] Figure 13 A diagram of communication and disconnection of the radio frequency receiving channel and the radio frequency transmitting channel is shown as an example;

[0053] Figure 14 Another diagram of communication and disconnection of the radio frequency receiving channel and the radio frequency transmitting channel is shown as an example;

[0054] Figure 15 An interaction diagram of devices when a first SRS is transmitted and the first SRS is stopped from being transmitted under a DC_B3-n41 combination is shown as an example;

[0055] Figure 16 A scene diagram of a radio frequency receiving channel corresponding to a radio frequency signal of a frequency band in a frequency division duplex mode provided by the embodiment of the application is shown as an example;

[0056] Figure 17 Another scene diagram of a radio frequency receiving channel corresponding to a radio frequency signal of a frequency band in a frequency division duplex mode provided by the embodiment of the application is shown as an example;

[0057] Figure 18 Another structure diagram of a radio frequency front end module of a radio frequency receiving channel corresponding to a radio frequency signal of a frequency band in a frequency division duplex mode provided by the embodiment of the application is shown as an example;

[0058] Figure 19 Another scene diagram of a radio frequency receiving channel corresponding to a radio frequency signal of a frequency band in a frequency division duplex mode provided by the embodiment of the application is shown as an example;

[0059] Figure 20 Another scene diagram of a radio frequency receiving channel corresponding to a radio frequency signal of a frequency band in a frequency division duplex mode provided by the embodiment of the application is shown as an example;

[0060] Figure 21 Another scene diagram of a radio frequency receiving channel corresponding to a radio frequency signal of a frequency band in a frequency division duplex mode provided by the embodiment of the application is shown as an example;

[0061] Figure 22Fig. 6 is another schematic diagram of a scenario of implementing the radio frequency receiving channel corresponding to the radio frequency signal of the frequency band using the frequency division duplex mode according to the embodiment of the present application;

[0062] Figure 23 Fig. 6 is another schematic diagram of a scenario of implementing the radio frequency receiving channel corresponding to the radio frequency signal of the frequency band using the frequency division duplex mode according to the embodiment of the present application;

[0063] Figure 24 Fig. 6 is another schematic diagram of a scenario of implementing the radio frequency receiving channel corresponding to the radio frequency signal of the frequency band using the frequency division duplex mode according to the embodiment of the present application;

[0064] Figure 25 Fig. 6 is another schematic diagram of a scenario of implementing the radio frequency receiving channel corresponding to the radio frequency signal of the frequency band using the frequency division duplex mode according to the embodiment of the present application;

[0065] Figure 26 Fig. 6 is another schematic diagram of a scenario of implementing the radio frequency receiving channel corresponding to the radio frequency signal of the frequency band using the frequency division duplex mode according to the embodiment of the present application;

[0066] Figure 27 Fig. 6 is another schematic diagram of a scenario of implementing the radio frequency receiving channel corresponding to the radio frequency signal of the frequency band using the frequency division duplex mode according to the embodiment of the present application;

[0067] Figure 28 Fig. 6 is another schematic diagram of a scenario of implementing the radio frequency receiving channel corresponding to the radio frequency signal of the frequency band using the frequency division duplex mode according to the embodiment of the present application;

[0068] Figure 29 Fig. 6 is another schematic diagram of a scenario of implementing the radio frequency receiving channel corresponding to the radio frequency signal of the frequency band using the frequency division duplex mode according to the embodiment of the present application;

[0069] Figure 30 Fig. 6 is another schematic diagram of a scenario of implementing the radio frequency receiving channel corresponding to the radio frequency signal of the frequency band using the frequency division duplex mode according to the embodiment of the present application; DETAILED DESCRIPTION

[0070] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0071] The term "and / or", merely describes an associated relationship, which means that there can be three relationships, for example, A and / or B, which can represent: A exists alone, A and B exist together, and B exists alone.

[0072] The terms "first" and "second" and the like in the description and claims of the present application are used for the purpose of differentiating a different object, rather than for describing a specific order of the object. For example, a first target object and a second target object are used to distinguish different target objects, rather than to describe a specific order of the target objects.

[0073] In the embodiments of the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design presented as "exemplary" or "for example" in the embodiments of the present application should not be construed as being more preferred or advantageous than other embodiments or designs. Rather, the use of "exemplary" or "for example" is intended to present concepts in a concrete manner.

[0074] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more. For example, a plurality of processing units means two or more processing units; a plurality of systems means two or more systems.

[0075] Before the technical solutions provided by the embodiments of the present application are described, the content involved in the work of the terminal device supporting 4G and 5G dual-mode simultaneous transceiving in NSA is first described.

[0076] Specifically, for a terminal device supporting 4G and 5G dual-mode simultaneous transceiving, in order to ensure that the radio frequency devices on the 4G and 5G paths can work simultaneously, in some implementation manners, the terminal device can be provided with independent 4G radio frequency front-end paths and 5G radio frequency front-end paths. Among them, the 4G radio frequency front-end path can include various radio frequency front-end devices, such as radio frequency switch devices, filter frequency selection devices, etc. Similarly, the 5G radio frequency front-end path can also include various radio frequency front-end devices, such as radio frequency switch devices, filter frequency selection devices, and low-noise amplifiers, etc. In this way, by setting independent 4G radio frequency front-end paths and 5G radio frequency front-end paths, the transceiving of 4G radio frequency signals of different frequency bands and 5G radio frequency signals of different frequency bands can be supported.

[0077] Exemplarily, in other implementations, the 4G radio frequency front-end path and the 5G radio frequency front-end path can also share the radio frequency front-end device. For this mode, the first radio frequency signal filtering and frequency selecting device, the low noise amplifier, and the second radio frequency signal filtering and frequency selecting device, the low noise amplifier can be configured to the same radio frequency switch device, and then the same antenna channel is selected through the same radio frequency switch device, so as to realize the radio frequency front-end path sharing the antenna channel and the radio frequency switch device of the first radio frequency signal and the second radio frequency signal, and finally reduce the antenna scheme complexity and the space occupied by the radio frequency front-end device.

[0078] It should be noted that in some implementations, the first radio frequency signal and the second radio frequency signal described above can be radio frequency signals of different systems, for example, the first radio frequency signal is a 4G radio frequency signal, and the second radio frequency signal is a 5G radio frequency signal. In other implementations, the first radio frequency signal and the second radio frequency signal can also be radio frequency signals of the same system but different frequency bands.

[0079] In addition, it should also be noted that the frequency band of the 5G radio frequency signal described above can be Sub6G, i.e. the frequency band below 7.125GHz; and the frequency band of the 4G radio frequency signal can be Sub3G, i.e. the frequency band below 3GHz.

[0080] It can be found that the frequency band of the 5G radio frequency signal and the frequency band of the 4G radio frequency signal described above overlap, specifically the frequency band below 3GHz overlaps. The frequency band below 3GHz can include a low frequency band (LB), a middle frequency band (MB), and a high frequency band (HB).

[0081] It can be understood that the LB is specifically a frequency band below 1000Mhz, the MB is specifically a frequency band of 1.7-2.3GHz, and the HB is specifically a frequency band of 2.3-2.7GHz.

[0082] In addition, it should also be understood that the LB and the MB can constitute an LMB, and the MB and the HB can constitute an MHB.

[0083] For the convenience of description, the 2.7GHz-7.2GHz is referred to as a 5G high frequency band in the embodiments of the present application.

[0084] In addition, it should be noted that in order to better realize communication, the 4G frequency range and the 5G frequency range are currently divided into different frequency bands, and in order to distinguish the divided frequency bands, different frequency bands are also assigned corresponding frequency band numbers.

[0085] Exemplarily, for the frequency bands divided by the 5G frequency range, the frequency band number starts with "n", for example, n41, n7, and the like. For the frequencies divided by the 4G frequency range, the frequency band number starts with "B", for example, B41, B7, and the like. For the allocation of the frequency band number, the above LB can include n28A, B28A, n28B, B28B, n20, B20, n8, B8, and the like; the above MB can include B1, n3, B3, and the like; and the above HB can include n41, B41, n40, B40, n7, B7, and the like.

[0086] It should be understood that the above description is only an example for better understanding the technical solutions of the embodiments and is not the only limitation of the embodiments.

[0087] In addition, it should be noted that, in order to enable the terminal device to support dual-mode simultaneous transmission and reception, thereby being applicable to the dual-connection wireless communication system deployed in the NSA mode, the terminal device needs to integrate a radio frequency front-end module capable of receiving and transmitting the above frequency bands in the DC form.

[0088] Exemplarily, the dual-connection wireless communication system deployed in the NSA mode is, for example, a wireless communication system in the form of LTE-NR dual connectivity. The LTE-NR dual connectivity can include EN-DC (E-UTRA-NR Dual Connectivity), NGEN-DC (NG RAN E-UTRA-NR Dual Connectivity), or NE-DC (NR-E-UTRA Dual Connectivity), and the like.

[0089] Specifically, EN-DC refers to accessing a 4G core network (EPC) as a core network, a 4G base station as a master base station (MeNB), and a 5G base station as a secondary base station (SeNB). NGEN-DC refers to accessing a 5G core network (5GC) as a core network, a 4G base station as a MeNB, and a 5G base station as a SeNB. NE-DC refers to accessing a 5GC as a core network, a 5G base station as a MeNB, and a 4G base station as a SeNB.

[0090] It should be understood that the above description is only an example for better understanding the technical solutions of the embodiments and is not the only limitation of the embodiments. With the development of communication technology, the above NSA mode deployed dual-connection can also be other dual-connection forms, for example, dual-connection of 5G new radio (NR) and future next-generation communication technology (for example, 6G), or dual-connection of 4G and future next-generation communication technology (for example, 6G), and the like, which is not limited herein.

[0091] For the wireless communication system with dual connectivity deployed in NSA mode as mentioned above, the wireless communication system can be as shown in Figure 1 . Referring to Figure 1 , the wireless communication system can include a terminal device supporting dual-mode simultaneous transceiving capability, and an access network device 1 and an access network device 2, for example.

[0092] For example, in some implementations, for example, in the first phase of the deployment of the 5th generation (5G) system, a non-standalone network mode of 5G NR is often selected, for example, an EN-DC communication system based on option3x (user plane data is separated in EPC (S-GW)) or option3 (user plane data is separated in eNodeB) architecture. For the scenario where the wireless communication system is an EN-DC communication system, the access network device 1 can be an evolved Node B (eNodeB or eNB) in the long term evolution (LTE) system, i.e., a 4G base station, the access network device 2 can be a gNode B (gNB) in the NR system, i.e., a 5G base station, and the terminal device can communicate with the eNB and the gNB simultaneously.

[0093] For example, in some implementations, for example, in the first phase of the deployment of the 5th generation (5G) system, a non-standalone network mode of 5G NR is often selected, for example, an EN-DC communication system based on option3x (user plane data is separated in EPC (S-GW)) or option3 (user plane data is separated in eNodeB) architecture. For the scenario where the wireless communication system is an EN-DC communication system, the access network device 1 can be an evolved Node B (eNodeB or eNB) in the long term evolution (LTE) system, i.e., a 4G base station, the access network device 2 can be a gNode B (gNB) in the NR system, i.e., a 5G base station, and the terminal device can communicate with the eNB and the gNB simultaneously.

[0094] In addition, the terminal device supporting the dual-mode simultaneous transceiving function can be referred to as a user equipment (UE), an access terminal, a user unit, a user station, a mobile station, a mobile station, a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent, or a user device, and the like in actual application, which will not be listed one by one here, and the present application does not make any limitation.

[0095] Specifically, in the embodiments of the present application, the terminal device supporting the dual-mode simultaneous transceiving function can be a mobile phone, a tablet computer (Pad), a computer with wireless transceiving function, a virtual reality (VR) terminal, an augmented reality (AR) terminal, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, a smart watch, a smart bracelet, smart glasses, and other sports accessories or wearable devices, and the like, which will not be listed one by one here, and the present application does not make any limitation.

[0096] It should be understood that Figure 1 The wireless communication system shown is only an example for better understanding of the technical solutions of the embodiments, and is not the only limitation of the embodiments. In actual application, in addition to the function units shown Figure 1 in the wireless communication system, other function units can also be included, and the present application does not make any limitation.

[0097] In addition, it should be noted that the terminal device in the embodiments, and the communication system in which the terminal device works, are all taken as an example of EN-DC communication system, i.e., a communication system using NSA network architecture. For the terminal device working in the EN-DC communication system, as a feasible way, it can support receiving radio frequency signals of B3 frequency band and n41 frequency band at the same time, i.e., supporting DC_B3-n41 combination.

[0098] It should be understood that the above description is only an example for better understanding of the technical solutions of the embodiments, and is not the only limitation of the embodiments.

[0099] For the structure of the terminal device supporting the dual-mode simultaneous transceiving function, it can be as shown in Figure 2 . Referring toFigure 2 The terminal device can include a processor, a radio frequency front end module (RFFEM), a radio frequency front end power supply module, and an antenna module.

[0100] For the processor, in some implementations, one or more processing units can be included, for example: the processor can include an application processor (AP), a modem, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband, a radio frequency transceiver, a neural-network processing unit (NPU), etc.

[0101] The controller can generate operation control signals according to the instruction operation code and the timing signal to complete the control of fetching and executing instructions.

[0102] The baseband refers to a baseband signal to be synthesized for transmission, and / or a baseband signal received for decoding. Specifically, when transmitting, the baseband encodes voice or other digital signals into a baseband signal (baseband code) for transmission; when receiving, the baseband signal (baseband code) received is decoded into voice or other digital signals. Understandably, the baseband can include an encoder, a decoder, and a baseband processor, etc. The encoder is used to synthesize the baseband signal to be transmitted; the decoder is used to decode the received baseband signal; and the baseband processor can be a microprocessor (MCU) that can be used to control the encoder and the decoder, for example, the baseband processor can be used to complete the scheduling of encoding and decoding, the communication between the encoder and the decoder, and the peripheral device driving (the components outside the baseband can be enabled by sending an enable signal to the components outside the baseband to enable the components outside the baseband), etc.

[0103] The modem can include a modulator and a demodulator. Specifically, the modulator is used to modulate the baseband signal to be sent into a baseband modulation signal; the demodulator is used to demodulate the received baseband modulation signal into a baseband signal, and then the demodulator transmits the demodulated baseband signal to the baseband processing. After the baseband processing, the baseband signal is transmitted to the application processor. The application processor outputs the sound signal through the audio device (not limited to the loudspeaker, the receiver, etc.), or displays the image or video through the display screen.

[0104] The radio frequency transceiver is configured to up-convert the baseband modulated signal outputted by the modem processor into a radio frequency (RF) signal, and output the RF signal to the radio frequency front-end module, so as to be transmitted by one or more antennas in the antenna module later. The radio frequency transceiver is also configured to down-convert the RF signal received through the antenna module and the radio frequency front-end module into a baseband modulated signal, so as to be processed by the modem processor and the baseband later.

[0105] In some implementations, the modem can have the function of the baseband.

[0106] In some implementations, the processor can further be provided with a memory for storing instructions and data. The memory in the processor can be a cache memory. The memory can store instructions or data that have just been used or are used repeatedly by the processor. In this way, if the processor needs to use the instructions or data again, the instructions or data can be directly called from the memory, without the need to be re-read from an external memory or other storage device, thereby avoiding repeated access and reducing the waiting time of the processor, and thus improving the efficiency of the system.

[0107] As described above with respect to various types of processors, the processor can modulate a signal according to a mobile communication technology or a wireless communication technology.

[0108] The mobile communication technology can include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), emerging wireless communication technology (also referred to as the fifth generation mobile communication technology, English: 5th generation mobile networks or 5th generation wireless systems, 5th-Generation, 5th-Generation New Radio, 5G, 5G technology or 5G NR), etc., which are not listed one by one here, and the present application does not limit this.

[0109] The wireless communication technology can include a wireless local area network (WLAN) (such as a wireless fidelity (Wi-Fi) network), Bluetooth (BT), a global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR) technology, and the like, which are not listed one by one here, and the present application does not make any limitation.

[0110] It should be understood that the above description is only an example for better understanding the technical solutions of the embodiments and is not the only limitation of the embodiments.

[0111] In addition, it can be understood that in the processor, the different processing units listed above can be independent devices or can be integrated in one or more integrated circuits, and the present application does not make any limitation.

[0112] Referring back to Figure 2 , for example, the radio frequency front-end module is configured to receive and transmit RF signals through the antenna module, for example, to transmit RF signals through a radio frequency transmission channel in the radio frequency front-end module and the antenna module, and to receive RF signals through a radio frequency receiving channel in the radio frequency front-end module and the antenna module.

[0113] In addition, as described above for the radio frequency transmission channel and the radio frequency receiving channel, the radio frequency front-end module can amplify and filter RF signals through filtering frequency devices, low-noise amplifiers, radio frequency power amplifiers, and the like when transmitting and receiving RF signals.

[0114] Referring back to Figure 2 , for example, the antenna module is configured to transmit and receive RF signals in the form of electromagnetic waves. It can be understood that in some implementations, the antenna module can include multiple antennas or multiple groups of antennas (a group of antennas includes more than two antennas), and each antenna or group of antennas can be used to cover a single or multiple communication frequency bands. The multiple antennas can be one or more of multi-frequency antennas, array antennas, or on-chip antennas.

[0115] Referring back to Figure 2For example, the processor and the antenna module can be disposed on the same circuit board and coupled to each other, so as to realize various functions associated with transmitting and receiving radio frequency signals. For example, when the terminal device transmits a signal, the baseband synthesizes the data (digital signal) to be transmitted into a baseband signal to be transmitted, the baseband signal is modulated into a baseband modulated signal by the modem, the baseband modulated signal is converted into a transmission signal (radio frequency signal) by the radio frequency transceiver, the transmission signal is processed by the radio frequency front-end module, and then transmitted to the antenna module and transmitted out by the antenna module. For the path of the transmission signal transmitted from the processor to the antenna module, it can be referred to as a transmission link (or referred to as: a transmission path).

[0116] Correspondingly, when the terminal device needs to receive a signal, the antenna module transmits the received signal (radio frequency signal) to the radio frequency front-end module, the radio frequency front-end module processes the radio frequency signal and transmits the radio frequency signal to the radio frequency transceiver, the radio frequency transceiver processes the radio frequency signal into a baseband modulated signal and transmits the baseband modulated signal to the modem, the modem converts the baseband modulated signal into a baseband signal and transmits the baseband signal to the baseband, and the baseband converts the baseband signal into data and transmits the data to the corresponding application processor. For the path of the radio frequency signal transmitted from the antenna module to the processor, it can be referred to as a receiving link (or referred to as: a receiving path).

[0117] Continuing to refer to Figure 2 For example, the radio frequency front-end power supply module is configured to receive an input from the battery and / or the charging management module and supply power to the radio frequency front-end module. For example, the radio frequency front-end power supply module is configured to supply power to the power amplifier in the radio frequency front-end module.

[0118] In addition, it should be noted that in some implementations, the radio frequency front-end power supply module can also be disposed in the processor.

[0119] Continuing to refer to Figure 2 For example, the processor can further provide a control signal CON to the radio frequency front-end power supply module, provide a first radio frequency signal TX1 and a second radio frequency signal TX2 to the radio frequency front-end power supply module, and provide an enable signal PA11_EN, PA12_EN, PA13_EN, etc. for the power amplifier included in the radio frequency front-end module to the radio frequency front-end power supply module.

[0120] Continuing to refer to Figure 2 For example, the processor can further receive a radio frequency signal RX1 and a radio frequency signal RX2 transmitted through a radio frequency receiving channel in the radio frequency front-end module.

[0121] Continuing to refer to Figure 2For example, the RF front-end module can further include a first power supply end Vpa11 and a second power supply end Vpa12. The first power supply end Vpa11 of the RF front-end module is coupled with the first power supply end Vpa11 of the RF front-end module, and the second power supply end Vpa12 of the RF front-end module is coupled with the second power supply end Vpa12 of the RF front-end module.

[0122] Optionally, in some implementations, the RF front-end power supply module can further include a third power supply end Vpa13. The third power supply end Vpa13 of the RF front-end power supply module is coupled with the third power supply end Vpa13 of the RF front-end module.

[0123] It should be noted that the number of power supply ends included in the RF front-end power supply module is related to the number of power amplifiers included in the RF front-end module, which can be reasonably set according to the needs.

[0124] For example, the supply voltages of the two power amplifiers included in the RF front-end module are different, and the RF front-end power supply module can include two power supply ends to supply power to the two power amplifiers respectively.

[0125] It should be understood that the above description is only an example for better understanding the technical solutions of the embodiments and is not the only limitation of the embodiments.

[0126] Continuing to refer to Figure 2 For example, the RF front-end module can further include a first RF signal end RF_1, a second RF signal end RF_2, a third RF signal end RF_3,..., and an Nth RF signal end RF_N. Wherein N is any positive integer.

[0127] Continuing to refer to Figure 2 For example, the first RF signal end RF_I of the RF front-end module is coupled with the first RF signal end RF_1 of the antenna module, the second RF signal end RF_2 of the RF front-end module is coupled with the second RF signal end RF_2 of the antenna module, the third RF signal end RF_3 of the RF front-end module is coupled with the third RF signal end RF_3 of the antenna module,..., and the Nth RF signal end RF_N of the RF front-end module is coupled with the Nth RF signal end RF_N of the antenna module.

[0128] It should be noted that the value of N can be related to the number of antennas included in the antenna module, for example, N = 4, 6, etc. positive integer.

[0129] Therefore, by Figure 2The terminal device shown can know that the processor can provide a power supply control signal to the radio frequency front-end power supply module, which acts on the radio frequency front-end power supply module to make the radio frequency front-end power supply module supply power to the radio frequency front-end module. The processor outputs a first radio frequency signal TX1 to the radio frequency front-end module, and the processor outputs a second radio frequency signal TX2 to the radio frequency front-end module. The radio frequency front-end module is used to amplify, filter and / or transmit the first radio frequency signal and the second radio frequency signal, and output to the antenna module through any one or more of the first radio frequency signal end RF_1, the second radio frequency signal end RF_2, the second radio frequency signal end RF_3,..., and the Nth radio frequency signal end RF_N. The antenna module is used to emit the first radio frequency signal and the second radio frequency signal in the form of electromagnetic waves.

[0130] For Figure 2 The terminal device shown, in the embodiments of the present application, the first radio frequency signal and the second radio frequency signal mentioned above can be radio frequency signals for the terminal device to communicate with access network devices of different systems at the same time. For example, the first radio frequency signal can be a radio frequency signal for the terminal device to communicate with a 4G base station, and the second radio frequency signal can be a radio frequency signal for the terminal device to communicate with a 5G base station. For the specific structure of the radio frequency front-end module and its radio frequency signal processing mode, please refer to the explanation and description of the following embodiments, which will not be repeated here.

[0131] It should be understood that Figure 2 The structure of the terminal device shown is only an example for better understanding of the technical solutions of the embodiments, and does not constitute a specific limitation on the terminal device. In actual application, the terminal device can include more or fewer components than Figure 2 the one shown, or combine certain components, or split certain components, or different component arrangement.

[0132] In addition, it can be understood that Figure 2 The components shown can be realized in hardware, software, or a combination of software and hardware.

[0133] For the terminal device supporting dual-system simultaneous transmission and reception mentioned in the above embodiments, when it performs wireless communication, it will use the antennas in the antenna module to transmit sounding reference signals (SRS) to the network side (eNB / gNB) in turn, so that the network side can evaluate the uplink and downlink channel quality according to the SRS, and make frequency selective scheduling according to the uplink channel quality evaluation information, and make downlink beamforming according to the downlink channel quality evaluation information.

[0134] In order to better understand the way of the terminal device supporting dual-system simultaneous transmission and reception to transmit SRS in turn, the present embodiment takes the working scenario of NSA combination DC_B3-n41 as an example.

[0135] It should be noted that according to the current protocol, the SRS of the n41 frequency band is required to have at least 4 antennas (or at least support 4 antennas for operation) in the terminal device. In specific operation, the 4 antennas can be used for SRS transmission. For example, when there are 4 SRSs to be transmitted, each SRS needs to be transmitted through an antenna. For the transmission of only 2 SRSs, the corresponding antennas of the two SRSs can be selected for transmission. For ease of description, the following examples are based on the transmission of 4 SRSs.

[0136] Exemplarily, in an implementation mode, Figure 2 The processor in the terminal device can be as Figure 3 The SOC can be understood as a system on chip (System on Chip), which can also be called a system on chip. It is an integrated circuit with a dedicated target, which contains a complete system and all embedded software. RFIC can be understood as a radio frequency integrated circuit / radio frequency chip, or the radio frequency transceiver mentioned in the above embodiment.

[0137] Exemplarily, in this embodiment, the SOC can have the functions of the AP and the Modem mentioned above. That is, when SRS needs to be transmitted, the SRS of the digital signal is generated, such as Figure 3 SRS1, SRS2, SRS3 and SSR4 (respectively represented as: n41_NSA_SRS_Signal1, n41_NSA_SRS_Signal2, n41_NSA_SRS_Signal3 and n41_NSA_SRS_Signal4) shown in

[0138] It can be understood that in some implementation modes, Figure 3 The 4 SRSs shown in

[0139] In addition, when generating SRS, it is determined by the Modem whether to generate SRS1, SRS2, SRS3 or SRS4.

[0140] In addition, it can be understood that the RFIC is also used to down-convert the radio frequency signals received through the radio frequency receiving channels in the antenna module and the radio frequency front-end module, such as the radio frequency signals of the B3 frequency band and the n41 frequency band as mentioned below, into baseband modulation signals to feed back to the SOC for subsequent processing by the SOC.

[0141] With reference to the foregoing Figure 3 , for example, the radio frequency front-end module can include a receiving module and a transceiving module. The receiving module can include a first receiving module (corresponding to the receiving module 1 below) and a second receiving module (corresponding to the receiving module 2 below), and the transceiving module can include a first transceiving module (corresponding to the transceiving module 1 below) and a second transceiving module (corresponding to the transceiving module 2 below).

[0142] With reference to the foregoing Figure 3 , for example, the antenna module can include an antenna 1, an antenna 2, an antenna 3, and an antenna 4.

[0143] It can be understood that in actual operation, the first receiving module, the second receiving module, the first transceiving module, and the second transceiving module in the radio frequency front-end module can correspond to different antennas for different operation scenarios. This embodiment takes the case where the first transceiving module corresponds to the antenna 1, the first receiving module corresponds to the antenna 2, the second transceiving module corresponds to the antenna 3, and the second receiving module corresponds to the antenna 4 in the DC_B3-n41 scenario of the NSA network networking structure as an example.

[0144] With reference to the foregoing Figure 3 , for example, in the DC_B3-n41 scenario of the NSA network networking structure, the n41 1T4R SRS rotation, that is, the rotation of SRS using 4 antennas in the mobile frequency band of n41, the paths of the 4 SRS are as follows: for the n41_NSA_SRS_Signal1 SRS rotation signal, the SRS rotation signal is sent to the network side through the first transceiving module and the antenna 1; for the n41_NSA_SRS_Signal2 SRS rotation signal, the SRS rotation signal is sent to the network side through the first receiving module and the antenna 2; for the n41_NSA_SRS_Signal3 SRS rotation signal, the SRS rotation signal is sent to the network side through the second transceiving module and the antenna 3; and for the n41_NSA_SRS_Signal4 SRS rotation signal, the SRS rotation signal is sent to the network side through the second receiving module and the antenna 4.

[0145] In order to better understand the above n41 1T4R SRS rotation, taking the B3 frequency band that realizes dual connectivity with the n41 frequency band as an example, that is, DC_B3-n41, the n41 1T4R SRS rotation in the DC_B3-n41 combination is described.

[0146] First of all, it needs to be pointed out that in the DC_B3-n41 combination, the first receiving module is used to support Time Division Duplexing (TDD) NR band (specifically n41 band, and subsequent NR band is also n41 band) diversity reception, and LTE band (specifically B3 band, and subsequent LTE band is also B3 band) MIMO diversity reception. The second receiving module is used to support TDD NR band MIMO diversity reception, and LTE band diversity reception.

[0147] The first transceiving module is used to support TDD NR band transmission and main set reception, and LTE band MIMO main set reception.

[0148] The second transceiving module is used to support TDD NR band MIMO main set reception, and LTE band transmission and main set reception.

[0149] It can be understood that TDD refers to a frequency band with the same uplink and downlink working frequency, for example, the transmission and reception of n41 band radio frequency signals both use the frequency band of 2496-2690 Hz as defined by the protocol, but the time occupied by the uplink and downlink frequency resources can be adjusted as needed. In specific implementation, the time occupied by the uplink and downlink is generally divided into several time periods (these time periods can be referred to as time slots) according to a fixed interval, and then the transmission and reception of n41 band radio frequency signals are performed in the corresponding time slots.

[0150] In addition, it should also be understood that the transmission and reception of B3 band radio frequency signals is Frequency Division Duplexing (FDD). For FDD, different frequency bands are used for uplink and downlink, for example, 1920-1980 Hz for uplink and 2110-2170 Hz for downlink. In the process of communication with the network side, the transmission and reception of B3 band radio frequency signals in the time dimension is continuous.

[0151] Therefore, in the DC_B3-n41 scenario (or other NSA combination working scenarios involving LTE band and NR TDD band), when the terminal device performs SRS rotation (this embodiment takes n41 1T4R SRS as an example), the TDD n41 band radio frequency transmission signal will occupy the port of the LTE B3 band radio frequency signal, causing the reception of the B3 band radio frequency signal to be interrupted, resulting in deterioration of the data throughput of the B3 band radio frequency signal. It should be noted that when LTE band and TDD NR band work in NSA scenario, due to the asynchronous working of the network, the LTE band radio frequency signal is interrupted.

[0152] Still taking the DC_B3-n41 combination as an example, in the DC_B3-n41 scenario, the specific structure of the terminal device for transmitting SRS of the n41 frequency band can be as shown in Figure 4

[0153] Among them, the receiving module 1 is mainly used to support TDD NR frequency band diversity reception and LTE frequency band MIMO diversity reception. In the DC_B3-n41 scenario, the TDD NR frequency band diversity reception is the diversity reception of the radio frequency signal of the n41 frequency band; the LTE frequency band MIMO diversity reception is the MIMO diversity of the radio frequency signal of the B3 frequency band. The subsequent TDD NR frequency band refers to the n41 frequency band, and the LTE frequency band refers to the B3 frequency band.

[0154] Among them, the transceiving module 1 is mainly used to support TDD NR frequency band transmission main set reception and LTE frequency band MIMO main set reception.

[0155] Among them, the transceiving module 2 is mainly used to support TDD NR frequency band MIMO main set reception and LTE frequency band transmission main set reception.

[0156] Among them, the receiving module 2 is mainly used to support TDD NR frequency band MIMO diversity reception and LTE frequency band diversity reception.

[0157] Continuing to refer to Figure 4 , for example, when the transceiving module 1 receives SRS1 provided by the RFIC, it can be known from the above description that SRS1 is transmitted by the antenna 1 corresponding to the transceiving module 1, so SRS1 will be processed by the radio frequency power amplifier PA1 and the filter LB1 in the transceiving module 1, and then transmitted to the P3 port in the radio frequency switch 2. The P3 port of the radio frequency switch 2 will be in communication with the antenna port ANT1 port shown in the transceiving module 1, and then SRS1 is transmitted through the antenna 1.

[0158] Continuing to refer to Figure 4 , for example, when the transceiving module 1 receives SRS2 provided by the RFIC, it can be known from the above description that SRS2 is transmitted by the antenna 2 corresponding to the receiving module 1, so SRS2 will be processed by the radio frequency power amplifier PA1 and the filter LB1 in the transceiving module 1, and then transmitted to the P3 port in the radio frequency switch 2. The P3 port of the radio frequency switch 2 will be in communication with the SRS_OUT port shown in the transceiving module 1, and then SRS2 is transmitted to the MHB_TRX port shown in the receiving module 1. Since the MHB_TRX port shown in the receiving module 1 is in communication with the P8 port in the radio frequency switch 1, SRS2 will be input to the P8 port, and then output from the P8 port and the MHB_ANT1 port shown in the receiving module 1, and then SRS2 is transmitted through the antenna 2.

[0159] Continuing to refer to​Figure 4 For example, when transceiver module 1 receives SRS3 provided by the RFIC, as described above, SRS3 is transmitted by antenna 3 corresponding to transceiver module 2. Therefore, SRS3 will be processed by RF power amplifier PA1 and filter LB1 in transceiver module 1 and then sent to port P3 in RF switch 2. Port P3 of RF switch 2 will be connected to port ANT2 shown in transceiver module 1. Then, by closing contact point a of switch S to contact point b, SRS3 is transmitted to the port corresponding to RF switch 3 in transceiver module 2. Finally, RF switch 3 turns on the SRS transmission channel to transmit SRS3, and SRS3 is transmitted through antenna 3.

[0160] See also Figure 4 For example, when transceiver module 1 receives SRS4 provided by the RFIC, as described above, SRS4 is transmitted by antenna 4 corresponding to receiver module 2. Therefore, SRS4 will be processed by RF power amplifier PA1 and filter LB1 in transceiver module 1 and then sent to port P3 in RF switch 2. Port P3 of RF switch 2 will be connected to port ANT2 shown in transceiver module 1. Then, by closing contact point a of switch S to contact point c, SRS4 is transmitted to the port corresponding to RF switch 4 in receiver module 2. Finally, RF switch 4 turns on the SRS transmission channel to transmit SRS4, and SRS4 is transmitted through antenna 4.

[0161] To better understand the causes of the above problems, let's take the first receiving module as an example. Figure 5 The structure of the receiving module 1 shown is as follows: the first transceiver module is... Figure 5 Taking the structure of transceiver module 1 as an example, the first transceiver module transmits the SRS round-robin signal n41_NSA_SRS_Signal2 output by the RFIC through the first receiving module and antenna 2. Figure 5 The reasons for the above problems will be explained in detail when the channel between antennas 2 and the network side is transmitted by antenna 2.

[0162] See Figure 5 For example, in some implementations, the receiving module 1 may include low noise amplifiers LNA1, LNA2, LNA3, LNA4, signal selectors SW1, SW2, SW3, SW4, filters LB1, LB2, LB3, LB4, LB5, LB6, RF switch 1, and other functional devices.

[0163] Furthermore, it should be noted that the receiving module 1 may also include a mobile industry processor interface (MIPI) and a logic controller. Figure 5 (not shown in the image), etc.

[0164] Continuing to refer to Figure 5 , exemplary, the radio frequency switch 1 can include 8 ports P1 to P8, and the 8 ports can be connected to the antenna 2 through the MHB ANT1 port or the MHB ANT2 port to realize the communication between the antenna 2 and the 8 ports (for example, MHB ANT1), so as to receive the radio frequency signals of the MHB frequency range through the antenna 2, such as the radio frequency signals of the B40, n41, B1 / 66, B3, B39, B7 and the like, and transmit the received radio frequency signals to the corresponding filters through the P1 to P8 ports, so as to filter out the radio frequency signals of the required frequency band through the corresponding filters and transmit the radio frequency signals to the corresponding radio frequency signal gating network, such as SW1 to SW4 in Figure 5 , and then the selected radio frequency signals are fed back to the RFIC through the corresponding antenna port after being amplified by the low noise amplifier in the radio frequency signal gating network. Figure 5

[0165] Continuing to refer to Figure 5 , exemplary, the LB1 is used to filter out the radio frequency signals of the n40 frequency band, and transmit the filtered radio frequency signals of the B40 frequency band to the B40 input end of the SW2. The other input end of the SW2 is connected with the audio input interface AUX1 provided by the receiving module 1. In the specific operation, the SW2 selects one of the radio frequency signals input from the B40 input end or the input end connected with the AUX1 interface according to the business demand, and finally transmits the selected radio frequency signal to the LNA2, and then the radio frequency signal amplified by the LNA2 is fed back to the RFIC through the MUX selecting any antenna port, such as OUT3.

[0166] Continuing to refer to Figure 5 , exemplary, the LB2 is used to filter out the radio frequency signals of the n41 frequency band, and transmit the filtered radio frequency signals of the n41 frequency band to the n41 input end of the SW4. The LB6 is used to filter out the radio frequency signals of the B7 frequency band, and transmit the filtered radio frequency signals of the B7 frequency band to the B7 input end of the SW4. In the specific operation, the SW4 selects one of the radio frequency signals input from the n41 input end or the B7 input end according to the business demand, and finally transmits the selected radio frequency signal to the LNA4, and then the radio frequency signal amplified by the LNA4 is fed back to the RFIC through the MUX selecting any antenna port, such as OUT4.

[0167] Continuing to refer to Figure 5 ​, exemplary, LB3 is used to filter out the B1 / 66 frequency band of the radio frequency signal, and the filtered B1 / 66 frequency band of the radio frequency signal is delivered to the B1 / 66 input end of SW1. Another input end of SW2 is connected with the audio input interface AUX2 provided by the receiving module 1. In specific operation, SW1 will select one of the radio frequency signals input by the B1 / 66 input end or the input end connected with the AUX2 interface according to business needs, and finally deliver the selected radio frequency signal to LNA1. After low-noise amplification processing by LNA1, the low-noise amplified radio frequency signal is fed back to RFIC through the MUX selecting an arbitrary antenna port, such as OUT2.

[0168] Continuing to refer to Figure 5 , exemplary, LB4 is used to filter out the B3 frequency band of the radio frequency signal, and the filtered B3 frequency band of the radio frequency signal is delivered to the B3 input end of SW3. LB5 is used to filter out the B39 frequency band of the radio frequency signal, and the filtered B39 frequency band of the radio frequency signal is delivered to the B39 input end of SW3. In specific operation, SW3 will select one of the radio frequency signals input by the B3 input end or the B39 input end according to business needs, and finally deliver the selected radio frequency signal to LNA3. After low-noise amplification processing by LNA3, the low-noise amplified radio frequency signal is fed back to RFIC through the MUX selecting an arbitrary antenna port, such as OUT3.

[0169] Based on Figure 5 The receiving module 1 shown in the combination scenario of DC_B3-n41, the filter LB4 for filtering out the B3 frequency band of the radio frequency signal and the filter LB2 for filtering out the n41 frequency band of the radio frequency signal in the receiving module 1 are double-opened, that is, the P2 port and the P3 port in the radio frequency switch 1 are double-opened and connected to the MHB_ANT1 port or the MHB_ANT2 port, Figure 5 Taking the connection to the MHB_ANT1 port as an example, the radio frequency signals of the B3 frequency band and the n41 frequency band are simultaneously received.

[0170] Continuing to refer to Figure 5 , exemplary, in some implementations, the transceiver module 1 can include functional devices such as MUX, radio frequency power amplifier PA1, low-noise amplifiers LNA2 and LNA3, filters LB1, LB2 and LB3, and radio frequency switch 2.

[0171] Continuing to refer to Figure 5, exemplary, the radio frequency switch 2 can include four ports P1 to P4. Among them, the P1 port and the P2 port can be respectively communicated with the antenna 1 through the ANT1 port or the ANT2 port in the transceiver module 1, thereby realizing receiving the radio frequency signals in the MHB frequency range through the antenna 1, such as the radio frequency signals of the B3 and n41 frequency bands, and conveying the received radio frequency signals to the corresponding filter through the P1 port and the P2 port. For example, the radio frequency signals output by the P1 port are conveyed to the filter LB2, and the B3 frequency band radio frequency signals (B3_RX shown in Figure 5 ) are filtered out by the LB2, and then the filtered B3 frequency band radio frequency signals are conveyed to the low noise amplifier LNA2 in the transceiver module 1, and after the low noise amplification processing of the LNA2, the low noise amplification processed radio frequency signals are fed back to the RFIC through the MUX in the transceiver module 1 and an arbitrary antenna port, such as the OUT1 antenna port.

[0172] For another example, the radio frequency signals output by the P2 port are conveyed to the filter LB3, and the n41 frequency band radio frequency signals (n41_RX shown in Figure 5 ) are filtered out by the LB3, and then the filtered n41 frequency band radio frequency signals are conveyed to the low noise amplifier LNA3 in the transceiver module 1, and after the low noise amplification processing of the LNA3, the low noise amplification processed radio frequency signals are fed back to the RFIC through the MUX in the transceiver module 1 and an arbitrary antenna port, such as the OUT2 antenna port.

[0173] Continuing to refer to Figure 5 , exemplary, the P4 port in the radio frequency switch 2 is connected with the ANT1 port, the ANT2 port, the TRX port and the SRS_OUT port (used for transmitting radio frequency transmission and reception signals, such as SRS round-robin signals that need to be round-robin) in the transceiver module 1.

[0174] Continuing to refer to Figure 5 , exemplary, the P3 port in the radio frequency switch 2 is connected with the ANT1 port, the ANT2 port and the SRS_OUT port in the transceiver module 1. Among them, the SRS_OUT port is used to communicate with the MHB_TRX port in the receiving module 1, and the MHB_TRX port is connected with the P8 port of the radio frequency switch 1 in the receiving module. In this way, when the n41_NSA_SRS_Signal2 SRS round-robin signal is subsequently round-robin, the transceiver module 1 can transmit the n41_NSA_SRS_Signal2 SRS round-robin signal to the receiving module 1 through the SRS_OUT port and the MHB_TRX port, so that the P8 port in the radio frequency switch 1 occupies the MHB_ANT1 port, and then the n41_NSA_SRS_Signal2 SRS round-robin signal is sent to the network side through the antenna 2.

[0175] With reference to Figure 5 , exemplary, when the SRS is transmitted by the n41, no matter is the n41_NSA_SRS_Signal1, the n41_NSA_SRS_Signal2, the n41_NSA_SRS_Signal3, or the n41_NSA_SRS_Signal4, the SRS is received by the transceiver module 1 from the RFIC. Specifically, when the transceiver module 1 receives the above-mentioned four SRSs from the RFIC, the SRSs are amplified by the PA1 first, and then the amplified SRSs are transmitted to the filter LB1, and after the spurious signals are filtered by the LB1, the SRSs are finally transmitted to the network side through the P3 port of the RF switch 2, and then transmitted to the network side through the antenna connected to the corresponding port. Figure 6

[0176] With reference to Figure 6 , exemplary, for the n41_NSA_SRS_Signal1 transmitted through the PA1 and the LB1 in the transceiver module 1, the P3 port of the RF switch 2 will finally occupy the ANT1 port, and then the n41_NSA_SRS_Signal1 will be transmitted to the network side through the antenna 1 connected to the ANT1.

[0177] With reference to Figure 6 , exemplary, for the n41_NSA_SRS_Signal2 transmitted through the PA1 and the LB1 in the transceiver module 1, the P3 port of the RF switch 2 will finally occupy the SRS_OUT port, so that the n41_NSA_SRS_Signal2 can be transmitted to the receiving module 1 through the SRS_OUT port of the transceiver module 1 and the MHB_TRX port of the receiving module 1, so that the P8 port of the RF switch 1 occupies the MHB_ANT1 port, and then the n41_NSA_SRS_Signal2 is transmitted to the network side through the antenna 2.

[0178] ​Thus, the SRS round-robin signal can be transmitted by means of the antenna 2 for receiving the radio frequency signal, i.e. the n41_NSA_SRS_Signal2 SRS round-robin signal. Similarly, in the case that the transceiver module 2 and the receiving module 2 have a similar structure to the receiving module 1, the transceiver module 1 can also transmit the SRS round-robin signal by means of the antenna 3 and the antenna 4 through the transceiver module 2 and the receiving module 2 in the above-mentioned manner. Further, the network side can learn the corresponding resources of each antenna in the frequency domain and the time domain, so as to reasonably allocate the resources of each antenna when communicating with the network side.

[0179] However, as can be seen from the above description, when transmitting the SRS round-robin signal by means of other antennas, such as transmitting the n41_NSA_SRS_Signal2 SRS round-robin signal by means of the antenna 2, the P8 port of the radio frequency switch 1 in the receiving module 1 will occupy the MHB_ANT1 port. In the combination of DC_B3-n41, the P2 port and the P3 port of the radio frequency switch 1 in the receiving module 1 are double-opened and connected to the MHB_ANT1 port or the MHB_ANT2 port, Figure 6 Taking the connection to the MHB_ANT1 port as an example. Therefore, when transmitting the n41_NSA_SRS_Signal2 SRS round-robin signal by means of the antenna 2, the channel between the P2 port and the MHB_ANT1 port of the radio frequency switch 1 in the receiving module 1 and the channel between the P3 port and the MHB_ANT1 port will be inevitably interrupted, i.e. the channel between the P2 port and the MHB_ANT1 port will change from a connected state to an interrupted state, and the channel between the P3 port and the MHB_ANT1 port will also change from a connected state to an interrupted state.

[0180] However, as can be seen from the above description, the radio frequency signal of the n41 frequency band is transmitted and received in a TDD mode, and the radio frequency signal of the B3 frequency band is transmitted and received in an FDD mode.

[0181] In order to facilitate understanding of the relationship between the frame, the subframe, the slot and the symbol in a scheduling period under the TDD mode, the time domain resource relationship of the 5G system is explained below in combination with Table 1.

[0182] Table 1 Relationship table of frame, subframe, slot and symbol

[0183]

[0184] As shown in Table 1, for a frame of data transmitted and received in a scheduling period, the frame can include a plurality of subframes, each of the subframes corresponds to a certain slot, and each of the slots can include a specific number of symbols. As shown in Table 1, in different frequency bands, the number of subframes included in a frame in a same scheduling period (time length) is usually fixed as 10, the number of slots included in a subframe is different, and the number of symbols included in a slot does not change with the parameters, but changes with the configuration type of the slot.

[0185] Specifically, when the configuration type of the slot is 0, the number of symbols included in a slot is fixed as 14; when the configuration type of the slot is 1, the number of symbols included in a slot is fixed as 12. In this embodiment, the configuration type of the slot is 0, and the number of symbols included in a slot is fixed as 14.

[0186] Continuing to refer to Table 1, for example, in the case of a frequency band of 15 KHz, a frame of data transmitted and received in a scheduling period of 10 ms includes 10 subframes, and each of the subframes includes 1 slot, i.e., a frame includes 10 slots, and in the case of a scheduling period of 10 ms, a slot occupies a time length of 1 ms.

[0187] Continuing to refer to Table 1, for example, in the case of a frequency band of 30 KHz, a frame of data transmitted and received in a scheduling period of 10 ms includes 10 subframes, and each of the subframes includes 2 slots, i.e., a frame includes 20 slots, and in the case of a scheduling period of 10 ms, a slot occupies a time length of 0.5 ms.

[0188] Continuing to refer to Table 1, for example, in the case of a frequency band of 60 KHz, a frame of data transmitted and received in a scheduling period of 10 ms includes 10 subframes, and each of the subframes includes 4 slots, i.e., a frame includes 40 slots, and in the case of a scheduling period of 10 ms, a slot occupies a time length of 0.25 ms.

[0189] Continuing to refer to Table 1, for example, in the case of a frequency band of 120 KHz, a frame of data transmitted and received in a scheduling period of 10 ms includes 10 subframes, and each of the subframes includes 8 slots, i.e., a frame includes 80 slots, and in the case of a scheduling period of 10 ms, a slot occupies a time length of 0.125 ms.

[0190] It should be understood that the above description is only an example for better understanding the technical solutions of the embodiments and is not the only limitation of the embodiments.

[0191] For ease of illustration, the embodiments take one scheduling period of 10 ms as an example, and the TDD configuration corresponding to the n41 frequency band in a frequency band of 15 KHz is described. It can be understood that the allocation relationship of the time domain resource is only exemplarily described in 15 KHz, and is not applied to the existing network.

[0192] In addition, it should be noted that in the scheduling period corresponding to the TDD mode, a part of the slots can be configured as uplink time slots (U), a part of the slots can be configured as downlink time slots (D), and a part of the slots can be configured as special time slots (S) according to needs.

[0193] Referring to Figure 6 , for example, the ratio between the downlink time slots, the special time slots and the uplink time slots is 7:1:2, that is, in 10 slots, the slots numbered 0-6 are configured as downlink time slots, the slot numbered 7 is configured as a special time slot, and the slots numbered 8 and 9 are configured as uplink time slots.

[0194] Continuing to refer to Figure 6 , for example, for each slot configured as a downlink time slot, the 14 symbols included therein are all downlink time slots, such as the 14 symbols numbered 0-13 corresponding to the slot numbered 0 in Figure 6 . In this way, the terminal device can perform the operation of receiving the radio frequency signal from the network side in each symbol of each slot configured as a downlink time slot.

[0195] Continuing to refer to Figure 6 , for example, for each slot configured as an uplink time slot, the 14 symbols included therein are all uplink time slots, such as the 14 symbols numbered 0-13 corresponding to the slot numbered 0 in Figure 6 . In this way, the terminal device can perform the operation of sending the radio frequency signal to the network side in each symbol of each slot configured as an uplink time slot.

[0196] Continuing to refer to Figure 6 , for example, for each slot configured as a special time slot, the 14 symbols included therein can be configured as DwPTS (still represented by D in Figure 6 ) and UpPTS (still represented by U in Figure 5A part of the symbols is configured as GP (denoted as U in the figure) Figure 7 In the figure, UpPTS is mainly used for uplink synchronization and random access, DwPTS is mainly used for downlink synchronization and distinguishing adjacent cells, and GP is used for protecting bandwidth and determining coverage.

[0197] Referring to Figure 7 For example, for No. 7, the slot configured as a special slot includes 14 symbols in a ratio of 6:4:4 between DwPTS, GP and UpPTS, i.e., among the 14 symbols, Nos. 0-5 are configured as DwPTS, Nos. 6-9 are configured as GP, and Nos. 10-13 are configured as UpPTS.

[0198] As can be understood, in each scheduling period, the terminal device needs to obtain uplink resources before transmitting a radio frequency signal to the network side. Therefore, for the TDD configuration shown in Figure 7 The SRS transmission can occur in the UpPTS of the special slot or in any uplink slot. In the UpPTS or uplink slot where SRS can be transmitted, the terminal device does not need to obtain a radio frequency signal from the network side in the downlink slot or DwPTS. When entering the slot corresponding to the downlink slot or DwPTS, the terminal device will occupy the MHB_ANT1 port to receive the radio frequency signal from the network side through the antenna 2, i.e., the Figure 7 In the UpPTS or uplink slot, the P8 port in the radio frequency switch 1 in the receiving module 1 occupies the MHB_ANT1 port, transmits the n41_NSA_SRS_Signal2, and then in the next scheduling period, when entering the downlink slot or DwPTS, the P2 port in the radio frequency switch 1 in the receiving module 1 will automatically occupy the MHB_ANT1 port to receive the n41 frequency band radio frequency signal. Therefore, the SRS transmission will not affect the reception of the n41 frequency band radio frequency signal in the TDD mode.

[0199] In addition, it should be noted that for 1T4R SRS transmission, 4 SRS transmission signals need to be transmitted in one scheduling period, so in one scheduling period, SRS transmission occupies at most 4 symbols. According to the protocol, the last 6 (if less than 6, all) uplink slots in the slot can be configured for SRS transmission.

[0200] As Figure 8As shown, exemplary, for the case that the ratio between DwPTS, GP and UpPTS in the special slot is 6:4:4, SRS can be transmitted in the symbols numbered 10~13 in the special slot.

[0201] Exemplary, in some implementations, SRS can be transmitted in the last 4 symbols of the UpPTS of the S slot, as shown in the following table. Figure 8 In one scheduling period, SRS1 can be transmitted by antenna 1 at the time corresponding to the symbol numbered 11 in the special slot; SRS4 can be transmitted by antenna 4 at the time corresponding to the symbol numbered 13 in the special slot. In another scheduling period, SRS2 can be transmitted by antenna 2 at the time corresponding to the symbol numbered 12 in the special slot. In another scheduling period, SRS3 can be transmitted by antenna 3 at the time corresponding to the symbol numbered 12 in the special slot.

[0202] It should be understood that the above description is only an example for better understanding the technical scheme of the embodiment, and is not the only limitation of the embodiment.

[0203] Continuing to refer to Figure 8 As shown, exemplary, for each slot configured as an uplink slot, since all the 14 symbols included in the slot are uplink symbols, the 6 symbols numbered 8~13 can be configured for SRS transmission.

[0204] Exemplary, in some other implementations, SRS can also be transmitted in the last 6 symbols of the U slot. As shown in the following table. Figure 8 In one scheduling period, SRS1 can be transmitted by antenna 1 at the time corresponding to the symbol numbered 9 in the uplink slot; SRS2 can be transmitted by antenna 2 at the time corresponding to the symbol numbered 11 in the uplink slot; SRS3 can be transmitted by antenna 3 at the time corresponding to the symbol numbered 13 in the uplink slot. In another scheduling period, SRS4 can be transmitted by antenna 4 at the time corresponding to the symbol numbered 13 in the uplink slot.

[0205] It should be understood that the above description is only an example for better understanding the technical scheme of the embodiment, and is not the only limitation of the embodiment.

[0206] In addition, it should be noted that, regarding SRS transmission, in some implementations, one SRS can be transmitted at a time, such as transmitting SRS1 first, then transmitting SRS2, then transmitting SRS3, and then transmitting SRS4.

[0207] For example, in other implementations, the RFIC can also send the four SRSs together to the transceiver 1, and the transceiver 1 can send the corresponding SRSs to the corresponding modules, and then send them out through the corresponding antennas.

[0208] However, for the FDD mode, the channel between the P3 port and the MHB ANT1 port in the radio frequency switch 1 needs to be in a connected state at all times within the scheduling period, so that the terminal device can receive the B3 frequency band radio frequency signal issued by the network side. However, when the SRS is rotated, the P8 port in the radio frequency switch 1 will occupy the MHB ANT1 port, thereby breaking the channel between the P3 port and the MHB ANT1 port.

[0209] That is, for the transceiving of the n41 frequency band radio frequency signal of the TDD mode, the uplink and the downlink are both working in the same frequency band, such as 2496-2690 Hz shown in Figure 6 . For the transceiving of the B3 frequency band radio frequency signal of the FDD mode, the uplink and the downlink work in different frequency bands, Figure 7 only the frequency band corresponding to the downlink is shown, such as 2110-2170 Hz.

[0210] In addition, it should be understood that the above description of the uplink, downlink and SRS timing resource allocation is not actually applied in the network, but is only used to illustrate the difference between the TDD / FDD time domain resource calling.

[0211] Continuing to refer to Figure 8 , for example, in each scheduling period, for the TDD mode, when in the downlink channel working time, the channel between the P2 port and the MHB ANT1 port in the radio frequency switch 1 is in a connected state, and the terminal device can receive the n41 frequency band radio frequency signal issued by the network side through the downlink channel between the P2 port and the MHB ANT1 port in the radio frequency switch 1; when in the uplink channel working time, or in the symbol of the UpPTS in the special time slot described above, for the receiving module 1 described above, since it is essentially only used to receive the n41 frequency band and the supported frequency band radio frequency signal, therefore in this time period, the terminal device does not originally need to receive the n41 frequency band radio frequency signal issued by the network side, therefore in this time period, when there is an SRS2 to be sent through the antenna 2, the P8 port of the radio frequency switch 1 in the receiving module 1 occupies the MHB ANT1 port, and sending the SRS2 through the antenna 2 to the network side will not affect the reception of the n41 frequency band radio frequency signal. That is, for the TDD n41 frequency band radio frequency signal transceiving shown in Figure 9 , since the time period from the start of the SRS2 T1 to the stop of the SRS2 T2 corresponds to the last 4 symbols of the S slot. Through Figure 9 andFigure 9 It can be seen that the last 4 symbols of the S time slot are UpPTS. Therefore, sending SRS2 in this time period will not affect the reception of the TDD n41 frequency band radio frequency signal.

[0212] Continuing to refer to Figure 9 , it is exemplary that, in each scheduling period, for the FDD mode, the terminal device needs to receive the B3 frequency band radio frequency signal issued by the network side through the channel between the P3 port and the MHB ANT1 port of the radio frequency switch 1 at all times. Therefore, if at the same time, such as the uplink channel working time corresponding to the TDD mode, or the symbol time of the UpPTS in the special time slot mentioned above, when there is an SRS round signal to be sent through the antenna 2, the P8 port of the radio frequency switch 1 in the receiving module 1 occupies the MHB ANT1 port, and the channel between the P3 port and the MHB ANT1 port is interrupted when sending the SRS round signal to the network side through the antenna 2, thereby causing the reception of the B3 frequency band radio frequency signal to be interrupted, i.e. in the T1 to T2 time period, the B3 frequency band radio frequency signal cannot be received.

[0213] In addition, it should be noted that after the FDD B3 frequency band radio frequency signal reception is interrupted, even if the platform side software algorithm recovers the LTE B3 frequency band radio frequency receiving channel as soon as possible through self-scheduling and resource arbitration (hereinafter referred to as: SOC self-scheduling recovery B3 reception), because the SOC self-scheduling recovery B3 reception process involves complex processing logic, it takes a long time, for example, it may take T3 time to recover the B3 frequency band radio frequency signal, so the B3 frequency band radio frequency signal data throughput is still deteriorated. That is, the time when the sending of SRS2 interrupts the reception of the B3 frequency band radio frequency signal includes not only the sending time of SRS2, but also the time required for self-scheduling recovery from T2 to T3.

[0214] As Figure 10 shown, after sending SRS, such as SRS2, in the special time slot S in the time corresponding to the 4 symbols numbered 10 to 13 with the attribute UpPTS, the terminal device starts SOC self-scheduling recovery B3 reception, but because the SOC self-scheduling recovery B3 reception process involves complex processing logic, it takes a long time, so from the time domain, it is often not possible to recover the B3 frequency band corresponding radio frequency receiving channel at the beginning of the slot numbered 8, but it will lag for a period of time, such as Figure 10 shown in the figure.

[0215] It should be understood that the above description is only an example for better understanding the technical scheme of the embodiment and is not the only limitation of the embodiment.

[0216] In addition, it should be understood that, for the B3 frequency band corresponding to the radio frequency receiving channel, the FDD is used, and there is no time domain for the frequency band used to receive the radio frequency signal Figure 11 The uplink time slot, the special time slot, and the downlink time slot are shown. Figure 11 Only the time domain corresponding to each gap in FDD is described, and the use of SOC self-scheduling to recover B3 reception has a delay problem.

[0217] In addition, it should be noted that, only DC_B3-n41 is used as an example to illustrate the impact of SRS round-robin interruption on LTE B3 radio frequency receiving channel for receiving signals, and for FDD mode working LTE frequency band and TDD mode 5G frequency band forming NSA dual-mode working mode, the above problems exist.

[0218] Therefore, the embodiments of the present application provide a wireless communication scheme, which aims to quickly recover the radio frequency receiving channel corresponding to the interrupted frequency band without relying on complex software algorithms, and to ensure data throughput.

[0219] Referring to Figure 11 , for example, after sending SRS2 in the time corresponding to the 10th to 13th properties of UpPTS symbol in the special time slot S, based on the scheme provided by the present embodiment (hereinafter referred to as: device self-scheduling to recover B3 reception), the processor sends a first value to the register in the receiving module 1 when sending SRS2, and sends a second value to the register when stopping sending SRS. And set the controller to directly control the radio frequency switch 1 to turn on the SRS sending channel for sending SRS2 when the register provides the first value, and directly control the radio frequency switch 1 to turn on the receiving channel for receiving B3+n41 frequency band when the register provides the second value. Thus, the receiving channel corresponding to the B3 frequency band can be quickly recovered, for example Figure 11 As shown in the figure, the receiving channel corresponding to the B3 frequency band is recovered at the start time of the slot numbered 8, that is, at the start time of the symbol numbered 0 in the slot numbered 8. Compared with the SOC self-scheduling to recover B3 reception, which may be recovered at the start time of the symbol numbered 2 in the slot numbered 8, the radio frequency receiving channel corresponding to the B3 frequency band can be recovered in time, thereby ensuring data throughput.

[0220] It should be understood that the above description is only an example for better understanding the technical scheme of the present embodiment, and is not the only limitation of the present embodiment.

[0221] Referring to Figure 11 , for example, in the present embodiment, the wireless communication circuit can include a processor, a register, a controller, and a radio frequency switch. The processor is electrically connected to the register, and the controller is electrically connected to the register and the radio frequency switch.

[0222] In addition, it can be known from the above description that the embodiment is to quickly recover the receiving channel of the radio frequency signal of the frequency band in the FDD mode during the SRS round transmission and the radio frequency signal reception process of the frequency band in the FDD mode of the terminal device supporting dual-mode simultaneous transmission and reception. In order to realize the reception of the SRS round transmission and the radio frequency signal of the frequency band in the FDD mode, the radio frequency switch at least needs to include a first port and a second port, and an antenna port (hereinafter referred to as a first antenna port). When the first port is in communication with the first antenna port, a receiving channel of the radio frequency signal in the frequency division duplex mode is formed, such as a receiving channel of the radio frequency signal in the B3 frequency band. When the second port is in communication with the first antenna port, an SRS sending channel for sending a sounding reference signal SRS is formed.

[0223] Referring back to Figure 11 In the embodiment (1), for example, the processor in the wireless communication circuit is configured to generate a first SRS and send a first value to the register when the first SRS is generated.

[0224] It should be noted that the first SRS, for example, can be any one of SRS2, SRS3 and SRS4 in the above embodiment, that is, the SRS needs to be sent by the receiving module 1, the transceiving module 2 or the receiving module 2. In the embodiment and the following embodiments, the first SRS is SRS2 as described above. The second SRS appearing later is SRS1 as described above, the third SRS is SRS3 as described above, and the fourth SRS is SRS4 as described above.

[0225] Referring back to Figure 11 In the embodiment (1), for example, the register is configured to output the first value to the controller when the first value is received.

[0226] Referring back to Figure 5 In the embodiment (1), for example, the controller is configured to send a first control instruction to the radio frequency switch when the first value is received.

[0227] Specifically, in the embodiment, the first control instruction is used to instruct the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port.

[0228] In this way, when the first SRS needs to be sent, the processor directly sends the first value to the register, and the controller can control the radio frequency switch to turn on the SRS sending channel according to the first value sent by the register, and then send SRS2 through the antenna corresponding to the SRS sending channel, such as the antenna 2 corresponding to SRS2 as described above.

[0229] Referring back to Figure 12In the middle (2), exemplary, the processor is further configured to send the second value to the register after the first SRS is sent through the SRS sending channel.

[0230] Continuing to refer to Figure 13 In the middle (2), exemplary, the register is further configured to output the second value to the controller when the second value is received.

[0231] Continuing to refer to Figure 14 In the middle (2), exemplary, the controller is further configured to send a second control instruction to the radio frequency switch when the second value is received.

[0232] Specifically, in the present embodiment, the second control instruction is used to instruct the radio frequency switch to disconnect the connection between the second port and the first antenna port, and to connect the first port with the first antenna port.

[0233] In this way, when it is necessary to stop sending the first SRS, the processor directly sends the second value to the register, and the controller can immediately control the radio frequency switch to turn on the receiving channel according to the second value sent by the register, thereby quickly recovering the reception of the radio frequency signal of the B3 frequency band.

[0234] In addition, it should be noted that, in order to reduce the implementation cost and without adding additional functional devices in the terminal device, the radio frequency switch in the wireless communication circuit can be the same as the radio frequency switch in the above-mentioned receiving module 1 or the transceiving module 2 or the receiving module 2 of the radio frequency front-end module that has the above-mentioned problem, such as when the wireless communication circuit is integrated in the receiving module 1 of the radio frequency front-end module, the radio frequency switch can be the same as the radio frequency switch in the receiving module 1.

[0235] In addition, it should be noted that, in order to facilitate the integration of the wireless communication circuit, the above-mentioned register, controller and radio frequency switch can be integrated into a functional device and integrated into the radio frequency front-end module of the terminal device that has the function of interrupting the receiving channel of the radio frequency signal of the FDD mode after the SRS round-robin and failing to recover, such as in the above-mentioned receiving module 1 or the transceiving module 2 or the receiving module 2 that has the above-mentioned problem.

[0236] In addition, it should be noted that the register and the controller used in the present embodiment are originally existing devices in the above-mentioned receiving module 1 or the transceiving module 2 or the receiving module 2 that has the above-mentioned problem, that is, the technical solution provided in the present embodiment does not need to change the hardware structure of the terminal device.

[0237] It should be understood that the above description is only an example for better understanding the technical solution of the present embodiment, and is not the only limitation of the present embodiment.

[0238] In addition, it should be noted that in some implementations, the register can include a first register and a second register. For such implementations, the processor is electrically connected to the first register and the second register, respectively, and the controller is electrically connected to the first register, the second register, and the radio frequency switch, respectively.

[0239] For such implementations, the processor is configured to generate the first SRS and send a first value when the first SRS is generated, specifically to the first register.

[0240] Correspondingly, the processor sends a second value after the first SRS is sent through the SRS sending channel, also to the first register.

[0241] Correspondingly, the first value or the second value sent by the register to the controller as mentioned above is implemented by the first register.

[0242] In addition, for such implementations, the processor is further configured to send a third value or a fourth value to the second register when the first SRS is generated and after the first SRS is sent through the SRS sending channel.

[0243] Correspondingly, the second register is configured to output the third value to the controller when the third value is received, and output the fourth value to the controller when the fourth value is received.

[0244] Under such a structure, the interaction of the controller with the register and the radio frequency switch can include that the controller is configured to control the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port when the first value and the third value are received. Alternatively, the controller is configured to control the radio frequency switch to connect the second port with the second antenna port and disconnect the connection between the first port and the second antenna port when the first value and the fourth value are received.

[0245] Under such a structure, the interaction of the controller with the register and the radio frequency switch further includes that the controller is further configured to control the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port when the second value and the third value are received. Alternatively, the controller is further configured to control the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port when the second value and the fourth value are received.

[0246] In addition, it should be noted that in other implementations, the radio frequency switch can include not only the first antenna port but also a second antenna port.

[0247] Correspondingly, the register can include not only the first register and the second register but also a third register.

[0248] For this implementation, the processor is electrically connected with the first register, the second register and the third register respectively, and the controller is electrically connected with the first register, the second register, the third register and the radio frequency switch respectively.

[0249] As for the exchange between the processor and the first register, and the exchange between the first register and the controller, it is the same as the above-mentioned mode including the first register and the second register, which will not be described again.

[0250] As for the second register and the third register, they are both used to determine the antenna port to which the first port and the second port are connected. At the same time, only one of them can be in an enabled state, i.e., can exchange with the processor and the controller.

[0251] For the convenience of description, the embodiment configures that when the processor sends the third value to the second register, it indicates that the antenna port to which the first port or the second port is connectable is the first antenna port. The embodiment configures that when the processor sends the fourth value to the third register, it indicates that the antenna port to which the first port or the second port is connectable is the second antenna port.

[0252] Based on this, when the second register is in the enabled state and the third register is not in the enabled state, the processor is further used to send the third value to the second register when the first SRS is generated and after the first SRS is sent through the SRS sending channel.

[0253] Correspondingly, the second register in the enabled state is used to output the third value to the controller when the third value is received.

[0254] Correspondingly, the controller is used to control the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port when the first value and the third value are received, and control the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port when the second value and the third value are received.

[0255] In addition, it can be understood that according to the above configuration, when the controller receives the first value and the third value, or the second value and the third value, it indicates that the third register is in the enabled state, and therefore the currently connectable antenna port is the first antenna port.

[0256] In addition, based on the above configuration, when the third register is in the enabled state and the second register is not in the enabled state, the processor is further used to send the fourth value to the third register when the first SRS is generated and after the first SRS is sent through the SRS sending channel.

[0257] Correspondingly, the third register in the enabled state is used to output the fourth value to the controller when the fourth value is received.

[0258] Correspondingly, the controller is configured to control the radio frequency switch to connect the second port with the second antenna port and disconnect the connection between the first port and the second antenna port when the first value and the fourth value are received; and the controller is further configured to control the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port when the second value and the fourth value are received.

[0259] In addition, it can be understood that, according to the above configuration, when the controller receives the first value and the fourth value, or the second value and the fourth value, it indicates that the fourth register is in an enabled state, and therefore the currently connectable antenna port is the second antenna port.

[0260] In addition, it should be noted that, in other implementations, in the case where the radio frequency switch includes the first antenna port and the second antenna port, the registers can include not only the first register, the second register and the third register, but also a fourth register.

[0261] For this implementation, the processor is electrically connected with the first register, the second register, the third register and the fourth register respectively, and the controller is electrically connected with the first register, the second register, the third register, the fourth register and the radio frequency switch respectively.

[0262] As for the exchange between the processor and the first register, and the first register and the controller, it is the same as the above-mentioned implementation including the first register and the second register, which will not be described again.

[0263] As for the second register and the third register, they are both used to determine the antenna port to which the first port and the second port are to be connected. At the same time, only one of them can be in an enabled state, i.e., can exchange with the processor and the controller. The specific configuration is the same as the above-mentioned second register and third register, which will not be described again.

[0264] As for the fourth register, it is used to control the interaction of the antenna ports when the second register and the third register are in an enabled state. In this embodiment, when the value sent by the processor to the fourth register is the fifth value, it indicates that the value configured by the processor to the second register is the third value, and the connectable antenna port of the first port or the second port is the first antenna port. It indicates that the value of the third register is the fourth value, which indicates that the connectable antenna port of the first port or the second port is the second antenna port.

[0265] When the value sent by the processor to the fourth register is the sixth value, it indicates that the value configured by the processor to the second register is the third value, and the connectable antenna port of the first port or the second port is the second antenna port. It indicates that the value of the third register is the fourth value, which indicates that the connectable antenna port of the first port or the second port is the first antenna port.

[0266] Based on this, when the second register is in the enabled state and the third register is not in the enabled state, the controller is configured to, when receiving the first value, the third value and the fifth value, control the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port. Alternatively, when receiving the first value, the third value and the sixth value, the controller controls the radio frequency switch to connect the second port with the second antenna port and disconnect the connection between the first port and the second antenna port.

[0267] Based on this, when the second register is in the enabled state and the third register is not in the enabled state, the controller is further configured to, when receiving the second value, the third value and the fifth value, control the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port. Alternatively, when receiving the second value, the third value and the sixth value, the controller controls the radio frequency switch to disconnect the connection between the second port and the second antenna port and connect the first port with the second antenna port.

[0268] In addition, when the third register is in the enabled state and the second register is not in the enabled state, the controller is further configured to, when receiving the first value, the fourth value and the fifth value, control the radio frequency switch to connect the second port with the second antenna port and disconnect the connection between the first port and the second antenna port. Alternatively, the controller is configured to, when receiving the first value, the fourth value and the sixth value, control the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port.

[0269] In addition, when the third register is in the enabled state and the second register is not in the enabled state, the controller is further configured to, when receiving the second value, the fourth value and the fifth value, control the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port. Alternatively, when receiving the second value, the fourth value and the sixth value, the controller controls the radio frequency switch to disconnect the connection between the second port and the second antenna port and connect the first port with the second antenna port.

[0270] It should be understood that the above description is only an example for better understanding the technical scheme of the embodiment and is not the only limitation of the embodiment.

[0271] In order to better understand the wireless communication circuit provided by the embodiment, the registers, the controller and the radio frequency switch in the wireless communication circuit are taken as three independent functional devices and are integrated into the radio frequency front-end module of the terminal device, specifically in the receiving module 1 in the radio frequency front-end module.

[0272] Specifically, in the description of this specific example, RegC mentioned below will be regarded as the first register, RegA as the second register, RegB as the third register, RegD as the fourth register, and RF switch 1 as the RF switch.

[0273] In addition, the device used to generate the values ​​to be sent to each register is the Modem in the processor. The values ​​sent by the Modem to each register are received through the MIPI interface in the corresponding module and then transmitted to the corresponding register.

[0274] Furthermore, in the case where both the P3 port corresponding to B3 and the P2 port corresponding to n41 are open, i.e. in the DC_B3-n41 combination, the P2 port in RF switch 1 is regarded as the first RF port in the first port, the P3 port is regarded as the second RF port in the first port, the P8 port is regarded as the second port, the HMB_ANT1 port is regarded as the first antenna port, and the HMB_ANT2 port is regarded as the second antenna port.

[0275] Furthermore, for the first value mentioned above, such as RegC[0X01] or RegC[0X10] as mentioned below, the second value can be RegC[0X00] as mentioned below.

[0276] Furthermore, the fifth value mentioned above is, for example, RegD[0X00] as described below, and the sixth value is, for example, RegD[0X01] as described below.

[0277] For example, still using Figure 13 Taking the structure of the receiving module 1 shown as an example, in the wireless communication scheme provided in this embodiment, all ports in the RF switch 1, such as ports P1 to P8, are connected to the MHB_ANT1 port (hereinafter referred to as the ANT1 port) or the MHB_ANT2 port (hereinafter referred to as the ANT2 port) respectively. The connection and interruption values ​​between the eight ports P1 to P8 and the ANT1 port or the ANT2 port are configured in the register corresponding to the RF switch 1. Then, the controller (which can be called the switch controller in actual applications, and is referred to as the controller here) controls the connection and interruption of the channel between the corresponding port in the RF switch 1 and the ANT1 port or the ANT2 port according to the values ​​provided from the register. Figure 14 Taking the case of a single register as an example, the default setting connects to the ANT1 port.

[0278] See Figure 15 For example, in this embodiment, when it is necessary to receive SRS2 transmitted by the antenna 2 corresponding to the receiving module 1, the Modem will send a first value to the register in the receiving module 1, specifically by transmitting the first value to the register through the MIPI interface in the receiving module 1.

[0279] Correspondingly, after the register receives the first value, the register sends the first value to the controller, the controller generates a first control instruction, controls the switch S3 to be closed, and turns on the SRS sending channel between the P8 port and the ANT1 port. At the same time, the switch S1 and the switch S2 are controlled to be opened, so that the receiving channel between the P2 port and the ANT1 port and the receiving channel between the P3 port and the ANT1 port are disconnected, so that the SRS2 can be sent out through the SRS sending channel between the P8 port and the ANT1 port and the corresponding antenna 2, and the reception of the radio frequency signals of the B3 frequency band and the n41 frequency band is interrupted.

[0280] It should be understood that the above description is only an example for better understanding the technical scheme of the embodiment and is not the only limitation of the embodiment. In actual application, one single-pole multi-throw switch can be used to control the P2 port, the P3 port and the P8 port, that is, one action can realize that the P2 port and the P3 port are connected with the corresponding antenna port, and the P8 port is disconnected with the antenna port. In addition, one action can realize that the P2 port and the P3 port are connected with the corresponding antenna port, and the P8 port is connected with the antenna port.

[0281] Referring to Figure 15 For example, when the receiving module 1 does not need to receive the SRS2 sent by the corresponding antenna 2 of the receiving module 1, the Modem sends a second value to the register in the receiving module 1, specifically, the second value is transmitted to the register through the MIPI interface in the receiving module 1.

[0282] Correspondingly, after the register receives the second value, the register sends the second value to the controller, the controller generates a second control instruction, controls the switch S3 to be opened, and disconnects the SRS sending channel. At the same time, the switch S1 and the switch S2 are controlled to be closed, so that the radio frequency receiving channel between the P2 port and the ANT1 port and the radio frequency receiving channel between the P3 port and the ANT1 port are connected, so that the radio frequency signals of the n41 frequency band and the B3 frequency band sent by the network side can be received.

[0283] It should be understood that the above description is only an example for better understanding the technical scheme of the embodiment and is not the only limitation of the embodiment.

[0284] In addition, it should be noted that the values corresponding to the connection and interruption between the P1 to P8 ports and the ANT1 port or the ANT2 port stored in the register can be determined by the Modem in the processor according to the configuration strategy agreed with the register manufacturer, which will not be described here.

[0285] Thus, the controller can control the P8 port in the radio frequency switch 1 to stop preoccupying the ANT1 port or the ANT2 port and restore the radio frequency receiving channels originally used to receive the radio frequency signals sent by the network side in the seven P1-P7 ports when receiving the second value sent by the register, such as the channels between the P2 port and the P3 port and the ANT1 port or the ANT2 port mentioned above, so that the terminal device can receive the radio frequency signals of the n41 frequency band and the B3 frequency band through the two radio frequency receiving channels. That is, the states of the switch S1, the switch S2 and the switch S3 in the radio frequency switch 1 are switched from Figure 15 as shown in Figure 15 as shown in the figure. Specifically, the switch S1 is switched from the open state to the closed state, the switch S2 is switched from the open state to the closed state, and the switch S3 is switched from the closed state to the open state. Thus, the radio frequency receiving channel corresponding to the B3 frequency band in the FDD mode is restored, thereby ensuring the data throughput of the radio frequency signals of the B3 frequency band.

[0286] Based on the logical connection in the radio frequency switch 1 and the logical configuration process of the registers in the radio frequency switch 1, when the SRS round-robin is performed in the combination of DC_B3-n41, the interaction between the Modem, the RFIC, the first transceiver module, the registers in the first receiving module, the controller and the radio frequency switch can be as shown in Figure 15 .

[0287] Referring to Figure 13 , for example, when the first SRS, i.e., the SRS2 mentioned above, needs to be sent, the Modem will generate a digital signal of the first SRS (hereinafter referred to as: first SRS (digital signal)) and send the generated first SRS (digital signal) to the RFIC, i.e., step S101 is performed.

[0288] Continuing to refer to Figure 15 , for example, the Modem will also send a first value to the register in the first receiving module (receiving module 1) while performing step S101, i.e., step S201 is performed.

[0289] Continuing to refer to Figure 15 , for example, after receiving the first SRS (digital signal) sent by the Modem, the RFIC will perform analog-to-digital conversion on the first SRS (digital signal), convert the first SRS (digital signal) into a physical signal (hereinafter referred to as: first SRS (radio frequency signal)), and send the first SRS (radio frequency signal) to the first transceiver module.

[0290] Continuing to refer to Figure 15, exemplary, the first transceiver module receives the first SRS (radio frequency signal), the first SRS (radio frequency signal) is sent to the second port of the radio frequency switch in the first receiving module. The specific flow of the first SRS (radio frequency signal) can be seen in Figure 15 SRS2 flow in the middle.

[0291] Continue to participate Figure 16 , exemplary, in the process of executing steps S102 and S103, steps S202 and S203 are also in synchronization. Specifically, the register in the first receiving module receives the first value sent by the Modem, and immediately sends the first value to the controller in the first receiving module, that is, step S202 is executed. After the controller receives the first value, according to the good configuration strategy agreed with the register manufacturer, it can be determined that the SRS sending channel needs to be turned on and the receiving channel of B3+n41 needs to be turned off. Therefore, after the controller receives the first value, it will immediately send the first control instruction to the radio frequency switch, that is, step S203 is executed.

[0292] From the description of the above embodiment, it can be known that the first control instruction is used to instruct the radio frequency switch to open the switches S1 and S2 and close the switch S3. Therefore, after the radio frequency switch receives the first control instruction, it will immediately execute step S301, open S1 and S2 and close S3 according to the first control instruction, and send the first SRS through the SRS sending channel. In this way, the first SRS can be sent out through the antenna 2 through the SRS sending channel.

[0293] See Figure 17 , exemplary, when the first SRS does not need to be sent, that is, when the first SRS is sent, the Modem will immediately send the second value to the register in the first receiving module (receiving module 1), that is, step S204 is executed.

[0294] Continue to participate Figure 16 , exemplary, the register in the first receiving module receives the second value sent by the Modem, and immediately sends the second value to the controller in the first receiving module, that is, step S205 is executed. After the controller receives the second value, according to the good configuration strategy agreed with the register manufacturer, it can be determined that the first SRS does not need to be sent at present, so the SRS sending channel can be ported, and the receiving channel of B3+n41 needs to be restored immediately. Therefore, after the controller receives the second value, it will immediately send the second control instruction to the radio frequency switch, that is, step S206 is executed.

[0295] As can be known from the description of the above embodiment, the second control instruction is used to instruct the radio frequency switch to close the switch S1 and the switch S2 and open the switch S3. Therefore, after receiving the second control instruction, the radio frequency switch will immediately execute step S302, that is, according to the second control instruction, S1 and S2 are closed, S3 is opened, and the radio frequency signal of the B3+n41 frequency band is received through the receiving channel. In this way, the radio frequency signal of the B3 frequency band can be continuously received.

[0296] Based on Figure 16 The interaction logic shown is that when there is only one register, that is, only one RegC, in actual application, it can be divided into Figure 16 and Figure 16 Two processing scenarios are shown.

[0297] Referring to Figure 16 , for example, the P2 port and the P3 port in the radio frequency switch 1 (LFEM) are communicated with the ANT1 port, thereby realizing the conduction of the B3 radio frequency receiving channel and the n41 radio frequency receiving channel (the receiving channel (B3+N41) in Figure 17 ). The P8 port is communicated with the ANT1 port, thereby realizing the conduction of the SRS sending channel. When SRS2 needs to be sent, as can be known from the above description, the controller reads the first value from the register, and as can be known from the judgment, in this case, the P8 port will preempt the ANT1 port (ANT1 in Figure 18 ), that is, the P8 port is communicated with the ANT1, so that the SRS sending channel (the channel marked with ① in Figure 24 ) is in a communication state. Since the P8 port preempts the ANT1, the P2 port and the P3 port cannot be communicated with the ANT1, and the receiving channel (B3+N41) will be interrupted (the channel marked with ② in Figure 27 ), and in the process of the conduction of the SRS sending channel, the radio frequency signal of the B3 frequency band cannot be received.

[0298] Referring to Figure 19 , for example, when SRS2 is sent or there is no SRS2 to be sent, as can be known from the above description, the controller reads the second value from the register, and as can be known from the judgment, in this case, the P8 port will release the ANT1, and the SRS sending channel is in an interrupted state. Since the P8 port releases the ANT1, the P2 port and the P3 port can re-preempt the ANT1, thereby making the receiving channel (B3+N41) in the interrupted state recover to the communication state.

[0299] In addition, it should be noted that in some implementations, the above register can be one, that is, the identification of the preemption of the P1-P8 ports in the above radio frequency switch 1 to the ANT1 port / ANT2 port is managed by one register.

[0300] In addition, it should be noted that in other implementations, the above-mentioned register can also be multiple, that is, the identification of the P1-P8 ports in the above-mentioned radio frequency switch 1 occupying the ANT1 port / ANT2 port is managed by different registers.

[0301] In addition, it should be noted that in the case of multiple registers, the controller for reading the identification from the register and controlling the connection or interruption of the channel between the P1-P8 ports and the ANT1 port / ANT2 port in the radio frequency switch 1 can be one, that is, multiple registers are managed by one controller, or multiple, such as one register corresponding to one controller.

[0302] It should be understood that the above description is only an example for better understanding the technical solution of the embodiment and is not the only limitation of the embodiment. In order to facilitate the description of the specific logic of the P1-P8 ports in the radio frequency switch 1 occupying the ANT1 port / ANT2 port when the register is multiple, the following will be described in detail with reference to the accompanying drawings, taking the register as four (such as Figures 19 to 23 , three (such as Figure 19 , and two (such as Figure 20 ) for example, and these registers are all managed by one controller.

[0303] Referring to Figure 20 , for example, after the Modem generates values for different registers according to the configuration strategy, the values are received by the MIPI interface in the receiving module 1 and are stored in the corresponding registers, such as RegA, RegB, RegC, and RegD.

[0304] Correspondingly, after receiving the values from the Modem, RegA, RegB, RegC, and RegD will send the corresponding values to the controller.

[0305] Correspondingly, the controller will make a decision according to the received values, and then decide whether the P8 port occupies the ANT1 port or the ANT2 port, or whether the P2 port and the P3 port occupy the ANT1 port or the ANT2 port.

[0306] As to the role of the identification stored in the registers RegA, RegB, RegC, and RegD, it can be as shown in Tables 2-3.

[0307] Table 2: Register D Function Configuration Table

[0308]

[0309] For example, according to the content recorded in Table 2, RegD is used to control the switching between the ANT1 port and the ANT2 port (ANT_SWAP_CTR). Specifically, when the identification recorded in RegD (value) is "0X00", i.e. RegD[0X00], it indicates that the ANT1 port is controlled by RegA and the ANT2 port is controlled by RegB. That is, when RegA is enabled, the channels corresponding to the eight ports P1-P8 in the radio frequency switch 1 are connected through the ANT1 port. Correspondingly, when RegB is enabled, the channels corresponding to the eight ports P1-P8 in the radio frequency switch 1 are connected through the ANT2 port.

[0310] In addition, it should be noted that if RegA and RegB are both in the enabled state, according to the service requirement, part of the channels corresponding to the ports P1-P8 in the radio frequency switch 1 can be configured to be connected through the ANT1 port controlled by RegA, and the other part of the channels can be configured to be connected through the ANT2 port controlled by RegB.

[0311] Continuing to refer to Table 2, for example, when the identification recorded in RegD (value) is "0X01", i.e. RegD[0X01], it indicates that the ANT1 port is controlled by RegB and the ANT2 port is controlled by RegA. That is, when RegA is enabled, the channels corresponding to the eight ports P1-P8 in the radio frequency switch 1 are connected through the ANT2 port. Correspondingly, when RegB is enabled, the channels corresponding to the eight ports P1-P8 in the radio frequency switch 1 are connected through the ANT1 port.

[0312] In addition, it should be noted that if RegA and RegB are both in the enabled state, according to the service requirement, part of the channels corresponding to the ports P1-P8 in the radio frequency switch 1 can be configured to be connected through the ANT1 port controlled by RegB, and the other part of the channels can be configured to be connected through the ANT2 port controlled by RegA.

[0313] Continuing to refer to Table 2, for example, in some implementations, the function indicated by RegD[0X00] can be set as the default mode, and the function indicated by RegD[0X01] can be set as the interactive mode.

[0314] It should be understood that the above description is only an example for better understanding the technical scheme of the embodiment and is not the only limitation of the embodiment. Regarding the above two identifications configured for RegD, they can be agreed according to the service requirement, and the application does not limit this.

[0315] Table 3 Function configuration table of registers A, B and C when register D indicates the default mode

[0316]

[0317] For example, according to the content recorded in Table 3, when the identification (value) recorded in RegD indicates that RegA and RegB control the ANT1 port and the ANT2 port in the default mode described in Table 2, the function of RegA is to control the ANT1 port, and the function of RegB is to control the ANT2 port. That is, the connection and interruption of the channel between the eight ports P1-P8 in the radio frequency switch 1 and the ANT1 port are controlled by RegA (ANT1_CTRL). Correspondingly, the connection and interruption of the channel between the eight ports P1-P8 in the radio frequency switch 1 and the ANT2 port are controlled by RegB (ANT2_CTRL).

[0318] Continuing to refer to Table 3, for example, RegC is used to control the preemption of the P8 port in the radio frequency switch 1 to the ANT1 port or the ANT2 port (XSW_CTRL). Among them, RegC can manage three kinds of identification, and only one exists at the same time. Specifically, when the identification (value) recorded in RegC is "0X00", that is, RegC[0X00], it indicates that the port that needs to send SRS is closed, and the settings of RegA and RegB are reserved, that is, the P8 port does not preempt the ANT1 port or the ANT2 port, the ANT1 port is controlled by RegA, and the ANT2 port is controlled by RegB.

[0319] Continuing to refer to Table 3, for example, when the identification (value) recorded in RegC is "0X01", that is, RegC[0X01], it indicates that the port that needs to send SRS preempts the ANT1 port controlled by RegA, or indicates that the P8 port preempts the ANT2 port controlled by RegB.

[0320] Continuing to refer to Table 3, for example, when the identification (value) recorded in RegC is "0X10", that is, RegC[0X10], it indicates that the port that needs to send SRS preempts the ANT1 port controlled by RegA, or indicates that the P8 port preempts the ANT2 port controlled by RegB.

[0321] It should be understood that the above description is only an example for better understanding the technical scheme of the embodiment and is not the only limitation of the embodiment. Regarding the above three kinds of identification configured for RegC, it can be agreed according to the business needs, and the application does not limit this.

[0322] Table 4 Function configuration table of registers A, B and C when register D indicates the switching mode

[0323] Table 4 Function configuration table of registers A, B and C when register D indicates the switching mode

[0324]

[0325] For example, according to the content recorded in Table 4, when the identification (value) recorded in RegD indicates that RegA and RegB control the ANT1 port and the ANT2 port in the switching mode described in Table 2, the function of RegA is to control the ANT2 port, and the function of RegB is to control the ANT1 port. That is, the connection and interruption of the channel between the eight ports P1-P8 in the radio frequency switch 1 and the ANT1 port is controlled by RegB (ANT1_CTRL). Correspondingly, the connection and interruption of the channel between the eight ports P1-P8 in the radio frequency switch 1 and the ANT2 port is controlled by RegA (ANT2_CTRL).

[0326] Continuing to refer to Table 4, for example, RegC is used to control the preemption of the P8 port in the radio frequency switch 1 to the ANT1 port or the ANT2 port (XSW_CTRL). Among them, RegC can manage three kinds of identification, and only one exists at the same time. Specifically, when the identification (value) recorded in RegC is "0X00", that is, RegC[0X00], it indicates that the port that needs to send SRS is closed, and the settings of RegA and RegB are reserved, that is, the P8 port does not preempt the ANT1 port or the ANT2 port, the ANT1 port is controlled by RegB, and the ANT2 port is controlled by RegA.

[0327] Continuing to refer to Table 4, for example, when the identification (value) recorded in RegC is "0X01", that is, RegC[0X01], it indicates that the port that needs to send SRS preempts the ANT2 port controlled by RegA, or indicates that the P8 port preempts the ANT1 port controlled by RegB.

[0328] Continuing to refer to Table 4, for example, when the identification (value) recorded in RegC is "0X10", that is, RegC[0X10], it indicates that the port that needs to send SRS preempts the ANT2 port controlled by RegA, or indicates that the P8 port preempts the ANT1 port controlled by RegB.

[0329] It should be understood that the above description is only an example for better understanding the technical scheme of the embodiment and is not the only limitation of the embodiment. Regarding the above three kinds of identification configured for RegC, it can be agreed according to the business needs, and the application does not limit this.

[0330] For better understanding of the wireless communication scheme provided by the embodiments of the present application, in the case that the registers include the above-mentioned RegA, RegB, RegC, RegD, and the configuration strategy corresponding to each register is as shown in Tables 2 to 4, the controller controls the connection / disconnection of the SRS transmission channel of the n41 frequency band corresponding to the P8 port, the connection / disconnection of the reception channel of the n41 frequency band corresponding to the P2 port, and the connection / disconnection of the reception channel of the B3 frequency band corresponding to the P3 port in the radio frequency switch 1 under different configurations (recorded identification / value) of each register after making a decision, in combination with Figure 21 The specific description is as follows.

[0331] As can be seen from the above description, RegA is in the enabled state, and RegB is in the disabled state. At this time, only RegC, RegA, and RegD can receive the values sent by the processor. Referring to Figure 21 , for example, in the case that RegA receives the third value, RegC receives the first value, and RegD receives the fifth value, the values that the controller can obtain are the first value, the third value, and the fifth value. According to the description of the above embodiment, when the controller receives the first value, the third value, and the fifth value, the SRS transmission channel marked with ② is turned on, and SRS2 is sent through the SRS transmission channel marked with ②.

[0332] Referring to Figure 22 , for example, still taking the case that RegA is in the enabled state as an example, in the case that RegA receives the third value, RegC receives the first value, and RegD receives the sixth value, the values that the controller can obtain are the first value, the third value, and the sixth value. According to the description of the above embodiment, when the controller receives the first value, the third value, and the sixth value, the switching of the antenna port is performed, that is, the P8 port is connected to ANT2. At this time, Figure 22 the SRS transmission channel marked with ④ in

[0333] Referring to Figure 23 , for example, still taking the case that RegA is in the enabled state as an example, in the case that RegA receives the third value, RegC receives the second value, and RegD receives the fifth value, the values that the controller can obtain are the second value, the third value, and the fifth value. According to the description of the above embodiment, when the controller receives the second value, the third value, and the fifth value, the reception channel marked with ① in Figure 23 (B3+N41) is turned on, so that the reception of the radio frequency signals of the B3 frequency band and the n41 frequency band is restored.

[0334] Referring to Figure 23For example, still taking the case that RegA is in the enabled state, in the case that RegA receives the third value, RegC receives the second value, and RegD receives the sixth value, the values that the controller can obtain are the second value, the third value, and the sixth value. Through the description of the above embodiment, when the controller receives the second value, the third value, and the sixth value, the controller will switch the antenna ports, that is, the controller connects P2 and P3 to ANT2. At this time, Figure 23 The receiving channel (B3+N41) with reference numeral ③ is turned on, so that the receiving of the radio frequency signals of the B3 frequency band and the n41 frequency band is resumed.

[0335] It should be understood that the above description is only an example for better understanding the technical solutions of the embodiments and is not the only limitation of the embodiments.

[0336] In addition, as can be known from the above description, when RegB is in the enabled state, RegA is in the disabled state, and at this time, only RegC, RegB, and RegD can receive the values sent by the processor. Referring to Figure 23 For example, in the case that RegB receives the fourth value, RegC receives the first value, and RegD receives the fifth value, the values that the controller can obtain are the first value, the fourth value, and the fifth value. Through the description of the above embodiment, when the controller receives the first value, the fourth value, and the fifth value, the controller will turn on Figure 24 The SRS sending channel with reference numeral ④ is turned on, and SRS2 will be sent out through the SRS sending channel with reference numeral ④.

[0337] Similarly, when RegB is in the enabled state, in the case that RegB receives the fourth value, RegC receives the first value, and RegD receives the sixth value, the values that the controller can obtain are the first value, the fourth value, and the sixth value. Through the description of the above embodiment, when the controller receives the first value, the fourth value, and the sixth value, the controller can turn on Figure 24 The SRS sending channel with reference numeral ② is turned on, and SRS2 will be sent out through the SRS sending channel with reference numeral ②.

[0338] Similarly, when RegB is in the enabled state, in the case that RegB receives the fourth value, RegC receives the second value, and RegD receives the fifth value, the values that the controller can obtain are the second value, the fourth value, and the fifth value. Through the description of the above embodiment, when the controller receives the second value, the fourth value, and the fifth value, the controller can turn on Figure 25 The receiving channel (B3+N41) with reference numeral ③ is turned on, so that the receiving of the radio frequency signals of the B3 frequency band and the n41 frequency band is resumed.

[0339] Similarly, when RegB is in the enabled state, if RegB receives the fourth value, RegC receives the second value, and RegD receives the sixth value, the values that the controller can obtain are the second value, the fourth value, and the sixth value. Through the description of the above embodiment, when the controller receives the second value, the fourth value, and the sixth value, the switching of the antenna port is performed, that is, the P2 port and the P3 port are connected to the ANT2. At this time, the Figure 25 The receiving channel (B3+N41) with the reference sign ① is turned on, so that the reception of the radio frequency signals of the B3 frequency band and the n41 frequency band is restored.

[0340] It should be understood that the above description is only an example for better understanding the technical solutions of the embodiments and is not the only limitation of the embodiments.

[0341] Referring to Figure 25 , the structure of the receiving module 1 of the three registers RegA, RegB, and RegC is exemplarily shown. For the structure shown, Figure 26 In actual operation, after the Modem generates the values for different registers according to the configuration strategy, the values are received by the MIPI interface in the receiving module 1 and are respectively stored in the corresponding registers, such as RegA, RegB, and RegC.

[0342] Correspondingly, after RegA, RegB, and RegC receive the values from the Modem, the corresponding values are sent to the controller.

[0343] Correspondingly, the controller will make a decision according to the received values, and then decide whether the P8 port preoccupies the ANT1 port or the ANT2 port, or whether the P2 port and the P3 port preoccupy the ANT1 port or the ANT2 port.

[0344] Referring to Figure 26 , exemplarily, when RegA is in the enabled state, if RegA receives the third value and RegC receives the first value, the values that the controller can obtain are the first value and the third value. Through the description of the above embodiment, when the controller receives the first value and the third value, the Figure 26 The SRS2 will be sent out through the SRS sending channel with the reference sign ②.

[0345] Similarly, when RegA is in the enabled state, if RegA receives the third value and RegC receives the second value, the values that the controller can obtain are the second value and the third value. Through the description of the above embodiment, when the controller receives the second value and the third value, the Figure 27The receiving channel numbered as ① (B3+N41) is enabled, so that the receiving of the radio frequency signals of the B3 frequency band and the n41 frequency band is resumed.

[0346] Referring to Figure 27 , exemplary, when RegB receives the fourth value and RegC receives the first value, the controller can obtain the first value and the fourth value. Through the description of the above embodiment, when the controller receives the first value and the fourth value, it will turn on Figure 28 The SRS sending channel numbered as ④, SRS2 will be sent out through the SRS sending channel numbered as ④.

[0347] Similarly, when RegB receives the fourth value and RegC receives the second value, the controller can obtain the second value and the fourth value. Through the description of the above embodiment, when the controller receives the second value and the fourth value, it can turn on Figure 28 The receiving channel numbered as ① (B3+N41) is enabled, so that the receiving of the radio frequency signals of the B3 frequency band and the n41 frequency band is resumed.

[0348] It should be understood that the above description is only an example for better understanding the technical scheme of the embodiment and is not the only limitation of the embodiment.

[0349] In addition, it can be understood that in the scenario where the registers include RegA, RegB and RegC, RegA, RegB and RegC can follow the default mode or the exchange mode indicated by RegD by default, and the remaining processing logic is similar to the above embodiment. For specific implementation details, please refer to the above embodiment, which will not be described here.

[0350] Referring to Figure 28 , exemplary, the structure of the receiving module 1 of the registers including RegA (or RegB, the embodiment takes RegA as an example) and RegC is shown. For Figure 29 The structure shown, after the Modem generates values for different registers according to the configuration strategy, the MIPI interface in the receiving module 1 receives the values and stores them in the corresponding registers, such as RegA and RegC.

[0351] Correspondingly, after RegA and RegC receive the values from the Modem, they will send the corresponding values to the controller.

[0352] Correspondingly, the controller will make a decision according to the received values, and then decide whether the P8 port preoccupies the ANT1 port or the ANT2 port, or whether the P2 port and the P3 port preoccupy the ANT1 port or the ANT2 port.

[0353] In the embodiment, when the RegA corresponds to the third value, it indicates that the ANT1 port is available; when the RegA corresponds to the fourth value, it indicates that the ANT2 port is available.

[0354] Based on this, the controller can obtain the value of the first value and the third value when the RegA receives the third value and the RegC receives the first value. Figure 29 For example, when the RegA receives the third value and the RegC receives the second value, the controller can obtain the value of the second value and the third value. Figure 29 The SRS2 will be sent out through the SRS sending channel marked as ②.

[0355] For example, when the RegA receives the third value and the RegC receives the second value, the controller can obtain the value of the second value and the third value. Figure 30 The receiving channel marked as ① (B3+N41) is turned on, so as to restore the reception of the radio frequency signals of the B3 frequency band and the n41 frequency band.

[0356] For example, when the RegA receives the fourth value and the RegC receives the first value, the controller can obtain the value of the first value and the fourth value. Figure 30 The SRS2 will be sent out through the SRS sending channel marked as ④. Figure 30 For example, when the RegA receives the fourth value and the RegC receives the second value, the controller can obtain the value of the second value and the fourth value.

[0357] The receiving channel marked as ③ (B3+N41) is turned on, so as to restore the reception of the radio frequency signals of the B3 frequency band and the n41 frequency band. Figure 30 It should be understood that the above description is only an example for better understanding the technical scheme of the embodiment and is not the only limitation of the embodiment.

[0358]

[0359] ​Moreover, it can be understood that the terminal device comprises hardware and / or software modules corresponding to the functions described above in order to realize the functions. The algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented in hardware or a combination of hardware and computer software. Whether a certain function is implemented in hardware or computer software driven hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in conjunction with the embodiments, but such implementation should not be considered beyond the scope of the present application.

[0360] For example, the terminal device is a mobile phone, and the above-mentioned functions are realized by the mobile phone. Figure 30 For the DC_B3-n41 combination, the terminal device 100 can be used to transmit SRS and resume the receiving channel corresponding to B3+n41 in time after stopping transmitting SRS.

[0361] Referring to Figure 30 The terminal device 100 can include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, an antenna 3, an antenna 4, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headset interface 170D, a sensor module 180, a key 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc.

[0362] The antenna 1, the antenna 2, the antenna 3, and the antenna 4 are the antennas in the antenna module described in the above-mentioned embodiments.

[0363] It can be understood that in actual operation, the mobile communication module 150 can exchange data with the four antennas in the antenna module when operating, such as transmitting SRS through the antenna or receiving radio frequency signals through the antenna.

[0364] For example, when the wireless communication module 160 is operating, it can also exchange data with the four antennas in the antenna module, such as accessing the base station in the cell through the WLAN network.

[0365] Continuing to refer to Figure 2, exemplary, the processor 110 can include the AP 110A and the Modem 110B. In the technical solutions provided by the embodiments of the present application, the Modem can generate a SRS (digital signal) when sending a SRS, such as the first SRS, the second SRS, the third SRS and the fourth SRS described in the above embodiments, and then send the SRS (digital signal) to the RFIC 150A located in the mobile communication module.

[0366] Continuing to refer to Figure 30 , exemplary, the RFIC 150A performs analog-to-digital conversion on the SRS (digital signal) provided by the Modem and converts it into a physical signal (hereinafter referred to as: SRS (radio frequency signal)).

[0367] Continuing to refer to Figure 30 , exemplary, the SRS (radio frequency signal) converted by the RFIC 150A is sent to the radio frequency front end module 150B. Through the above description, specifically, to the first transceiver module in the radio frequency front end module.

[0368] It can be understood that when the SRS (radio frequency signal) sent to the first receiving module needs to be sent through other modules, such as the antenna corresponding to the first receiving module, or the second transceiver module, or the second receiving module, then the above-mentioned implementation logic can be used, that is, by sending different values to different registers, the B3+n41 corresponding receiving call on or off is realized, and the SRS corresponding SRS sending channel is interrupted or turned on.

[0369] For specific implementation logic, please refer to the above embodiments, which will not be repeated here.

[0370] In addition, it should be noted that in some implementations, the processor 110 can also include one or more interfaces. The interfaces can include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0371] It should be understood that the interface connection relationship between the modules shown in the embodiments of the present application is only illustrative and does not constitute a limitation on the structure of the terminal device 100.

[0372] Continuing to refer to Figure 30 For example, the power management module 141 is used to connect the battery 142 and the charging management module 140 is connected to the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140 to power the processor 110, the internal memory 121, the external memory, the display screen 194, the camera 193, and the wireless communication module 160, etc. The power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle count, battery health status (leakage, impedance), etc. In other implementations, the power management module 141 can also be disposed in the processor 110. In other implementations, the power management module 141 and the charging management module 140 can also be disposed in the same device.

[0373] It should be noted that Figure 30 The radio frequency front-end power supply module in the terminal device shown can be a functional sub-module in the power management module 141 for supplying power to the radio frequency front-end module.

[0374] Among them, the antenna 1, the antenna 2, the antenna 3 and the antenna 4 can be used for transmitting and receiving radio frequency signals.

[0375] It can be understood that each antenna in the terminal device 100 can be used to cover a single or multiple communication frequency bands. Different antennas can also be multiplexed to improve the utilization of the antennas. For example, in the wireless communication method for antenna rotation detection reference signal provided in the embodiments of the present application, the same antenna can be used to rotate the radio frequency signal of the n41 frequency band, and can also be multiplexed to receive the MIMO diversity of the B3 frequency band.

[0376] The mobile communication module 150 can provide a solution including 2G / 3G / 4G / 5G wireless communication applied to the terminal device 100. The mobile communication module 150 can include at least one filter, switch, power amplifier, low noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves from the antennas in the antenna module, and perform filtering, amplification, etc. on the received electromagnetic waves, and transmit them to the modem processor for demodulation. The mobile communication module 150 can also amplify the signals modulated by the modem processor and convert them into electromagnetic waves radiated by the antennas in the antenna module. In some implementations, at least part of the functional modules of the mobile communication module 150 can be arranged in the processor 110. In some implementations, at least part of the functional modules of the mobile communication module 150 and at least part of the modules of the processor 110 can be arranged in the same device.

[0377] The wireless communication module 160 can provide a solution including WLAN, Bluetooth, GNSS, FM, NFC, IR, etc. wireless communication applied to the terminal device 100. The wireless communication module 160 can be one or more devices integrated with at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antennas in the antenna module, performs frequency modulation and filtering processing on the electromagnetic wave signals, and sends the processed signals to the processor 110. The wireless communication module 160 can also receive signals to be sent from the processor 110, perform frequency modulation, amplification, and convert them into electromagnetic waves radiated by the antennas in the antenna module.

[0378] Continuing to refer to Figure 30 For example, the antennas in the antenna module are coupled with the mobile communication module 150 and the wireless communication module 160, so that the terminal device 100 can communicate with the network and other devices through mobile communication technology or wireless communication technology.

[0379] Specifically, in the present application, the technical solutions provided by the embodiments of the present application are implemented by the antenna module, the mobile communication module 150, the processor, etc. of the terminal device 100.

[0380] Continuing to refer to Figure 30 For example, the terminal device 100 implements the display function through the GPU, the display screen 194, and the application processor, etc.

[0381] See also Figure 30 For example, the external storage interface 120 can be used to connect an external storage card, such as a Micro SD card, to expand the storage capacity of the terminal device 100. The external storage card communicates with the processor 110 through the external storage interface 120 to perform data storage functions. For example, music, video, and other files can be saved on the external storage card.

[0382] See also Figure 30 For example, internal memory 121 can be used to store computer executable program code, which includes instructions. Processor 110 executes various functional applications and data processing of terminal device 100 by running the instructions stored in internal memory 121. Internal memory 121 may include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as sound playback, image playback, etc.), etc. The data storage area may store data created during the use of terminal device 100 (such as audio data, phonebook, etc.). Furthermore, internal memory 121 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc.

[0383] See also ​ For example, SIM card interface 195 is used to connect a SIM card.

[0384] This concludes the introduction to the hardware structure of terminal device 100. It should be understood that... ​ The terminal device 100 shown is merely an example; in a specific implementation, the terminal device 100 may have more than... ​ The more or fewer components shown can be combined into two or more components, or they can have different component configurations. ​ The various components shown can be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and / or application-specific integrated circuits.

[0385] Furthermore, it should be noted that in practical application scenarios, the wireless communication methods provided in the above embodiments implemented by the terminal device can also be executed by a chip system included in the terminal device. The chip system may include a processor and a radio frequency front-end module. The radio frequency front-end module includes registers, a controller, and a radio frequency switch. The processor is used to call and run a computer program from the memory, so that the terminal device with the chip system installed calls the computer program stored in the memory to implement the steps executed by the terminal device.

[0386] In addition, the embodiment of the present application further provides a computer readable storage medium, and the computer readable storage medium stores computer instructions. When the computer instructions run on a terminal device, the terminal device executes the related method steps to realize the wireless communication method in the above embodiment.

[0387] In addition, the embodiment of the present application further provides a computer program product, and when the computer program product runs on a terminal device, the terminal device executes the related steps to realize the wireless communication method in the above embodiment.

[0388] In addition, the embodiment of the present application further provides a chip (which can also be a component or a module), and the chip can include one or more processing circuits and one or more transceiver pins. The transceiver pins and the processing circuits communicate with each other through internal connection paths. The processing circuit executes the related method steps to realize the wireless communication method in the above embodiment, so as to control the receiving pin to receive a signal and control the sending pin to emit a signal.

[0389] In addition, it can be known from the above description that the terminal device, the computer readable storage medium, the computer program product or the chip provided by the embodiment of the present application are all used to execute the corresponding method provided above, so the beneficial effects that can be achieved by the terminal device, the computer readable storage medium, the computer program product or the chip can refer to the beneficial effects in the corresponding method provided above, and will not be described here.

[0390] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalent technical features. The modification or replacement does not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A wireless communication circuit, characterized by, The application relates to a radio frequency switch and a method for controlling the radio frequency switch. The radio frequency switch comprises a processor, a register, a controller and a radio frequency switch. The processor is electrically connected with the register, and the controller is electrically connected with the register and the radio frequency switch respectively. The radio frequency switch comprises at least a first port, a second port and a first antenna port. When the first port is in communication with the first antenna port, a receiving channel of a radio frequency signal in a receiving frequency division duplex mode is formed. When the second port is in communication with the first antenna port, a sounding reference signal (SRS) sending channel for sending SRS is formed. The processor is used for generating a first SRS and sending a first value to the register when the first SRS is generated. The processor is further used for sending a second value to the register after the first SRS is sent through the SRS sending channel. The register is used for outputting the first value to the controller when the first value is received. The register is further used for outputting the second value to the controller when the second value is received.

2. The circuit of claim 1, wherein, The controller is used for controlling the radio frequency switch to connect the second port with the first antenna port and disconnect the first port from the first antenna port when the first value is received. The controller is further used for controlling the radio frequency switch to disconnect the second port from the first antenna port and connect the first port with the first antenna port when the second value is received. The radio frequency switch further comprises a second antenna port, and the register comprises a first register and a second register. The processor is electrically connected with the register, and the controller is electrically connected with the register and the radio frequency switch respectively. The processor is electrically connected with the register, and the controller is electrically connected with the register and the radio frequency switch respectively. The processor is used for generating the first SRS and sending the first value to the register when the first SRS is generated. The processor is used for generating the first SRS and sending the first value to the first register when the first SRS is generated. The processor is further used for sending the second value to the register after the first SRS is sent through the SRS sending channel. The processor is further used for sending the second value to the first register after the first SRS is sent through the SRS sending channel. The first register is used for outputting the first value to the controller when the first value is received. The first register is further used for outputting the second value to the controller when the second value is received. ​ ​ The processor is further configured to send a third value or a fourth value to the second register when the first SRS is generated and after the first SRS is sent through the SRS sending channel. The second register is configured to output the third value to the controller when the third value is received. The second register is further configured to output the fourth value to the controller when the fourth value is received. The controller is configured to control the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port when the first value is received, including: The controller is configured to control the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port when the first value and the third value are received. Or, The controller is configured to control the radio frequency switch to connect the second port with the second antenna port and disconnect the connection between the first port and the second antenna port when the first value and the fourth value are received. The controller is further configured to control the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port when the second value is received, including: The controller is further configured to control the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port when the second value and the third value are received. Or, The controller is further configured to control the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port when the second value and the fourth value are received.

3. The circuit of claim 1, wherein, The radio frequency switch further comprises a second antenna port, and the register comprises a first register, a second register and a third register; The processor is electrically connected with the register, including: The processor is electrically connected with the first register, the second register and the third register respectively; The controller is electrically connected with the register and the radio frequency switch respectively, including: The controller is electrically connected with the first register, the second register, the third register and the radio frequency switch respectively; The processor is configured to generate the first SRS and send the first value to the register when the first SRS is generated, including: The processor is configured to generate the first SRS and send the first value to the first register when the first SRS is generated. The processor is further configured to send the second value to the register after the first SRS is sent through the SRS sending channel, including: The processor is further configured to send the second value to the first register after the first SRS is sent through the SRS sending channel. The register is configured to output the first value to the controller when the first value is received, including: The first register is configured to output the first value to the controller when the first value is received; The register is further configured to output the second value to the controller when the second value is received, including: The first register is further configured to output the second value to the controller when the second value is received; The processor is further configured to send a third value to the second register when the first SRS is generated and after the first SRS is sent through the SRS sending channel, when the second register is in the enabled state and the third register is not in the enabled state; The second register in the enabled state is configured to output the third value to the controller when the third value is received; The processor is further configured to send a fourth value to the third register when the first SRS is generated and after the first SRS is sent through the SRS sending channel, when the third register is in the enabled state and the second register is not in the enabled state; The third register in the enabled state is configured to output the fourth value to the controller when the fourth value is received; The controller is configured to control the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port when the first value is received, including: The controller is configured to control the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port when the first value and the third value are received; Or, The controller is configured to control the radio frequency switch to connect the second port with the second antenna port and disconnect the connection between the first port and the second antenna port when the first value and the fourth value are received; The controller is further configured to control the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port when the second value is received, including: The controller is further configured to control the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port when the second value and the third value are received; Or, The controller is further configured to control the radio frequency switch to disconnect the connection between the second port and the first antenna port and connect the first port with the first antenna port when the second value and the fourth value are received.

4. The circuit of claim 3, wherein, The register further includes a fourth register; The processor is electrically connected with the register, including: The processor is electrically connected with the first register, the second register, the third register and the fourth register respectively; The controller is electrically connected with the register and the radio frequency switch respectively, including: The controller is electrically connected with the first register, the second register, the third register, the fourth register and the radio frequency switch respectively; The processor is further configured to send a fifth value or a sixth value to the fourth register when the first SRS is generated and after the first SRS is sent through the SRS sending channel. The fourth register is configured to output the fifth value to the controller when the fifth value is received. The fourth register is further configured to output the sixth value to the controller when the sixth value is received. When the second register is in the enabled state and the third register is not in the enabled state: The controller is configured to control the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port when the first value and the third value are received, including: The controller is configured to control the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port when the first value, the third value and the fifth value are received. Or, The controller is configured to control the radio frequency switch to connect the second port with the second antenna port and disconnect the connection between the first port and the second antenna port when the first value, the third value and the sixth value are received. The controller is further configured to control the radio frequency switch to disconnect the second port with the first antenna port and connect the first port with the first antenna port when the second value and the third value are received, including: The controller is further configured to control the radio frequency switch to disconnect the second port with the first antenna port and connect the first port with the first antenna port when the second value, the third value and the fifth value are received. Or, The controller is further configured to control the radio frequency switch to disconnect the second port with the second antenna port and connect the first port with the second antenna port when the second value, the third value and the sixth value are received. When the third register is in the enabled state and the second register is not in the enabled state: The controller is configured to control the radio frequency switch to connect the second port with the second antenna port and disconnect the connection between the first port and the second antenna port when the first value and the fourth value are received, including: The controller is configured to control the radio frequency switch to connect the second port with the second antenna port and disconnect the connection between the first port and the second antenna port when the first value, the fourth value and the fifth value are received. Or, The controller is configured to control the radio frequency switch to connect the second port with the first antenna port and disconnect the connection between the first port and the first antenna port when the first value, the fourth value and the sixth value are received. The controller is further configured to, when the second value and the fourth value are received, control the radio frequency switch to disconnect the second port from the first antenna port and connect the first port to the first antenna port, including: The controller is further configured to, when the second value, the fourth value and the fifth value are received, control the radio frequency switch to disconnect the second port from the first antenna port and connect the first port to the first antenna port. Or, The controller is further configured to, when the second value, the fourth value and the sixth value are received, control the radio frequency switch to disconnect the second port from the second antenna port and connect the first port to the second antenna port.

5. The circuit according to any one of claims 1 to 4, characterized in that The register, the controller and the radio frequency switch are arranged in a radio frequency front-end module of a terminal device.

6. The circuit of claim 5, wherein, The terminal device supports EN-DC and supports DC_B3-n41 combination.

7. The circuit of claim 6, wherein, The first antenna port and the second antenna port of the radio frequency switch are coupled with antenna modules of the terminal device respectively. When the SRS sending channel is connected, the first SRS is sent through the antenna module; when the receiving channel is connected, the radio frequency signals of the B3 frequency band and the n41 frequency band are received through the antenna module.

8. The circuit of claim 7, wherein, The antenna module includes four antennas. In the DC_B3-n41 combination, when the SRS generated by the processor includes the first SRS and a second SRS, the first SRS and the second SRS are transmitted through two antennas alternately. In the DC_B3-n41 combination, when the SRS generated by the processor includes the first SRS, a second SRS, a third SRS and a fourth SRS, the first SRS, the second SRS, the third SRS and the fourth SRS are transmitted through four antennas alternately.

9. The circuit of claim 8, wherein, The radio frequency front-end module includes a first transceiver module, a second transceiver module, a first receiving module and a second receiving module, and the first transceiver module, the second transceiver module, the first receiving module and the second receiving module correspond to one antenna respectively. In the DC_B3-n41 combination, when the SRS generated by the processor includes the first SRS, the second SRS, the third SRS and the fourth SRS, the first SRS, the second SRS, the third SRS and the fourth SRS are transmitted through four antennas alternately, including: In the DC_B3-n41 combination, when the SRS generated by the processor includes the first SRS, the second SRS, the third SRS and the fourth SRS, the processor transmits the first SRS, the second SRS, the third SRS and the fourth SRS to the first transceiver module; The first transceiver module transmits the first SRS to the first receiving module, and the first receiving module transmits the first SRS through the corresponding antenna; The first transceiver module transmits the second SRS through the corresponding antenna; The first transceiver module sends the third SRS to the second transceiver module, and the second transceiver module sends the third SRS through a corresponding antenna; The first transceiver module sends the fourth SRS to the second receiving module, and the second receiving module sends the fourth SRS through a corresponding antenna.

10. The circuit of claim 9, wherein, The register, the controller and the radio frequency switch are arranged in the radio frequency front end module of the terminal device, comprising: The register, the controller and the radio frequency switch are arranged in the first receiving module; Among the first receiving module: The first port includes a first radio frequency receiving port and a second radio frequency receiving port, the first radio frequency port is used for receiving a radio frequency signal of the n41 frequency band, and the second radio frequency port is used for receiving a radio frequency signal of the B3 frequency band; The controller is used for controlling the radio frequency switch to communicate the second port with the first antenna port and disconnect the connection between the first port and the first antenna port when the first value is received, comprising: The controller is used for controlling the radio frequency switch to communicate the second port with the first antenna port and disconnect the connection between the first radio frequency receiving port and the first antenna port and disconnect the connection between the second radio frequency receiving port and the first antenna port when the first value is received; The controller is further used for controlling the radio frequency switch to disconnect the connection between the second port and the first antenna port and communicate the first port with the first antenna port when the second value is received, comprising: The controller is further used for controlling the radio frequency switch to disconnect the connection between the second port and the first antenna port and communicate the first radio frequency receiving port with the first antenna port and communicate the second radio frequency receiving port with the first antenna port when the second value is received.

11. A terminal device, comprising: The terminal device comprises a radio frequency front end module, an antenna module and a wireless communication circuit according to any one of claims 1 to 10.

12. A method of wireless communication, the method comprising: Applied to a wireless communication circuit; the wireless communication circuit comprises a processor, a register, a controller and a radio frequency switch; the processor is electrically connected with the register, and the controller is electrically connected with the register and the radio frequency switch respectively; the radio frequency switch comprises at least a first port, a second port and a first antenna port; when the first port communicates with the first antenna port, a receiving channel of a frequency division duplex mode radio frequency signal is formed; when the second port communicates with the first antenna port, an SRS sending channel of a sounding reference signal SRS is formed; The method comprises: The processor generates a first SRS and sends a first value to the register when the first SRS is generated; The register outputs the first value to the controller when the first value is received; The controller controls the radio frequency switch to communicate the second port with the first antenna port and disconnect the connection between the first port and the first antenna port when the first value is received; The processor sends a second value to the register after the first SRS is sent through the SRS sending channel; The register outputs the second value to the controller when the second value is received; The controller controls the radio frequency switch to disconnect the connection between the second port and the first antenna port and to connect the first port and the first antenna port when the second value is received.

13. The method of claim 12, wherein, The radio frequency switch further comprises a second antenna port, and the register comprises a first register and a second register; the processor is electrically connected to the first register and the second register respectively; the controller is electrically connected to the first register, the second register and the radio frequency switch respectively; The processor generates the first SRS and sends the first value to the register when the first SRS is generated, comprising: The processor generates the first SRS and sends the first value to the first register when the first SRS is generated; The register outputs the first value to the controller when the first value is received, comprising: The first register outputs the first value to the controller when the first value is received; The processor sends the second value to the register after the first SRS is sent through the SRS sending channel, comprising: The processor sends the second value to the first register after the first SRS is sent through the SRS sending channel; The register outputs the second value to the controller when the second value is received, comprising: The first register outputs the second value to the controller when the second value is received; The method further comprises: The processor sends a third value or a fourth value to the second register when the first SRS is generated and after the first SRS is sent through the SRS sending channel; The second register outputs the third value to the controller when the third value is received; The second register outputs the fourth value to the controller when the fourth value is received; The controller controls the radio frequency switch to connect the second port and the first antenna port and to disconnect the connection between the first port and the first antenna port when the first value is received, comprising: The controller controls the radio frequency switch to connect the second port and the first antenna port and to disconnect the connection between the first port and the first antenna port when the first value and the third value are received; Or, The controller controls the radio frequency switch to connect the second port and the second antenna port and to disconnect the connection between the first port and the second antenna port when the first value and the fourth value are received; The controller controls the radio frequency switch to disconnect the connection between the second port and the first antenna port and to connect the first port and the first antenna port when the second value is received, comprising: The controller controls the radio frequency switch to disconnect the connection between the second port and the first antenna port and to connect the first port with the first antenna port when the second value and the third value are received. Alternatively, The controller controls the radio frequency switch to disconnect the connection between the second port and the first antenna port and to connect the first port with the first antenna port when the second value and the fourth value are received.

14. The method of claim 12, wherein, The radio frequency switch further comprises a second antenna port, and the register comprises a first register, a second register and a third register; the processor is electrically connected with the first register, the second register and the third register respectively; the controller is electrically connected with the first register, the second register, the third register and the radio frequency switch respectively; The register outputs the first value to the controller when the first value is received, comprising: The first register outputs the first value to the controller when the first value is received. The processor sends the second value to the register after the first SRS is sent through the SRS sending channel, comprising: The processor sends the second value to the first register after the first SRS is sent through the SRS sending channel. The register outputs the second value to the controller when the second value is received, comprising: The first register outputs the second value to the controller when the second value is received. The method further comprises: When the second register is in the enabled state and the third register is not in the enabled state, the processor sends a third value to the second register when the first SRS is generated and after the first SRS is sent through the SRS sending channel; The second register in the enabled state outputs the third value to the controller when the third value is received. When the third register is in the enabled state and the second register is not in the enabled state, the processor sends a fourth value to the third register when the first SRS is generated and after the first SRS is sent through the SRS sending channel; The third register in the enabled state outputs the fourth value to the controller when the fourth value is received. The controller controls the radio frequency switch to connect the second port with the first antenna port and to disconnect the connection between the first port and the first antenna port when the first value is received, comprising: The controller controls the radio frequency switch to connect the second port with the first antenna port and to disconnect the connection between the first port and the first antenna port when the first value and the third value are received. Alternatively, The controller controls the radio frequency switch to connect the second port with the second antenna port and to disconnect the connection between the first port and the second antenna port when the first value and the fourth value are received. The controller controls the radio frequency switch to disconnect the second port from the first antenna port and to connect the first port to the first antenna port when the second value is received. The controller controls the radio frequency switch to disconnect the second port from the first antenna port and to connect the first port to the first antenna port when the second value and the third value are received. Alternatively, The controller controls the radio frequency switch to disconnect the second port from the first antenna port and to connect the first port to the first antenna port when the second value and the fourth value are received.

15. The method of claim 14, wherein, The register further comprises a fourth register; the processor is electrically connected with the first register, the second register, the third register and the fourth register respectively; the controller is electrically connected with the first register, the second register, the third register, the fourth register and the radio frequency switch respectively; The method further comprises: The processor sends a fifth value or a sixth value to the fourth register when the first SRS is generated and after the first SRS is sent through the SRS sending channel; The fourth register outputs the fifth value to the controller when the fifth value is received. The fourth register outputs the sixth value to the controller when the sixth value is received. When the second register is in the enabled state and the third register is not in the enabled state: The controller controls the radio frequency switch to connect the second port to the first antenna port and to disconnect the first port from the first antenna port when the first value and the third value are received. The controller controls the radio frequency switch to connect the second port to the first antenna port and to disconnect the first port from the first antenna port when the first value, the third value and the fifth value are received. Alternatively, The controller controls the radio frequency switch to connect the second port to the second antenna port and to disconnect the first port from the second antenna port when the first value, the third value and the sixth value are received. The controller controls the radio frequency switch to disconnect the second port from the first antenna port and to connect the first port to the first antenna port when the second value and the third value are received. The controller controls the radio frequency switch to disconnect the second port from the first antenna port and to connect the first port to the first antenna port when the second value, the third value and the fifth value are received. Alternatively, The controller controls the radio frequency switch to disconnect the second port from the first antenna port and to connect the first port to the first antenna port when the second value, the third value and the sixth value are received. When the third register is in the enabled state and the second register is not in the enabled state: When the controller receives the first value and the fourth value, the controller controls the radio frequency switch to connect the second port to the second antenna port and disconnect the first port from the second antenna port, including: When the controller receives the first value, the fourth value, and the fifth value, the controller controls the radio frequency switch to connect the second port to the second antenna port and disconnect the first port from the second antenna port; Alternatively, When the controller receives the first value, the fourth value, and the sixth value, the controller controls the radio frequency switch to connect the second port to the first antenna port and disconnect the first port from the first antenna port; When the controller receives the second value and the fourth value, the controller controls the radio frequency switch to disconnect the second port from the first antenna port and connect the first port to the first antenna port, including: When the controller receives the second value, the fourth value, and the fifth value, the controller controls the radio frequency switch to disconnect the second port from the first antenna port and connect the first port to the first antenna port; Alternatively, When the controller receives the second value, the fourth value, and the sixth value, the controller controls the radio frequency switch to disconnect the second port from the second antenna port and connect the first port to the second antenna port.

16. The method according to any one of claims 12 to 15, characterized in that, The registers, the controller, and the radio frequency switch are arranged in a radio frequency front-end module of a terminal device; the terminal device operates in an EN-DC communication system and supports a DC_B3-n41 combination; a first antenna port and a second antenna port of the radio frequency switch are coupled to an antenna module of the terminal device; The method further includes: When the SRS transmission channel is connected, the first SRS is transmitted through the antenna module; When the reception channel is connected, B3-band radio frequency signals and n41-band radio frequency signals are received through the antenna module.

17. The method of claim 16, wherein, The antenna module includes four antennas; The method further includes: When the processor generates SRSs including the first SRS and a second SRS in the DC_B3-n41 combination, the first SRS and the second SRS are transmitted through two antennas alternately; When the processor generates SRSs including the first SRS, a second SRS, a third SRS, and a fourth SRS in the DC_B3-n41 combination, the first SRS, the second SRS, the third SRS, and the fourth SRS are transmitted through four antennas alternately.

18. The method of claim 17, wherein, The radio frequency front-end module includes a first transceiver module, a second transceiver module, a first receiving module, and a second receiving module, and the first transceiver module, the second transceiver module, the first receiving module, and the second receiving module correspond to one antenna respectively. In the DC_B3-n41 combination, when the SRS generated by the processor includes the first SRS, and the second SRS, the third SRS and the fourth SRS, the first SRS, the second SRS, the third SRS and the fourth SRS are transmitted by 4 antennas in turn, including: In the DC_B3-n41 combination, when the SRS generated by the processor includes the first SRS, and the second SRS, the third SRS and the fourth SRS, the processor transmits the first SRS, the second SRS, the third SRS and the fourth SRS to the first transceiver module; The first transceiver module transmits the first SRS to the first receiving module, and the first receiving module transmits the first SRS through the corresponding antenna; The first transceiver module transmits the second SRS through the corresponding antenna; The first transceiver module transmits the third SRS to the second transceiver module, and the second transceiver module transmits the third SRS through the corresponding antenna; The first transceiver module transmits the fourth SRS to the second receiving module, and the second receiving module transmits the fourth SRS through the corresponding antenna.

19. The method of claim 18, wherein, The register, the controller and the radio frequency switch are specifically arranged in the first receiving module; the first port includes a first radio frequency receiving port and a second radio frequency receiving port, the first radio frequency port receives a radio frequency signal of the n41 frequency band, and the second radio frequency port receives a radio frequency signal of the B3 frequency band; When the first value is received, the controller controls the radio frequency switch to communicate the second port with the first antenna port and disconnect the connection between the first port and the first antenna port, including: When the first value is received, the controller controls the radio frequency switch to communicate the second port with the first antenna port and disconnect the connection between the first port and the first antenna port, including: When the second value is received, the controller controls the radio frequency switch to disconnect the connection between the second port and the first antenna port and communicate the first port with the first antenna port, including: When the second value is received, the controller controls the radio frequency switch to disconnect the connection between the second port and the first antenna port and communicate the first port with the first antenna port, including:

20. A computer-readable storage medium, characterized in that, The computer program, when running on a terminal device, causes the terminal device to execute the wireless communication method of any one of claims 12 to 19.

21. A chip system, characterized by The chip system applied to a terminal device includes a processor and a radio frequency front-end module, and the radio frequency front-end module includes a register, a controller and a radio frequency switch; The processor is configured to invoke and run a computer program from a memory of the terminal device, so that the terminal device performs the wireless communication method according to any one of claims 12 to 19.

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