A method and system for controlling a photon computing chip and a multi-photon computing unit DAC in an optoelectronic hybrid computing system

Abstract

The present invention relates to a photon computing chip and a multi-photon computing unit DAC sharing control method and system in an optoelectronic hybrid computing system. The photon computing chip includes a photon computing array composed of a plurality of photon computing units; a plurality of photon computing units in the photon computing array are respectively connected to the same DAC and share the DAC to form a subarray, and the plurality of subarrays can work in parallel; a signal buffer is connected in series between each photon computing unit and the DAC in the same subarray; the number of photon computing units contained in the plurality of subarrays is inconsistent, so that the subarrays containing different numbers of photon computing units have different computing powers. The photon computing array is divided into a plurality of subarrays with different computing powers, and the subarrays with corresponding computing powers can be matched according to computing power requirements or / and algorithm requirements. The photon computing units in each subarray share a DAC, and the computing power distribution is more flexible. Under the same computing power requirements, fewer DACs are involved, so that the use efficiency of the DAC is higher, and the power consumption and heat generation of the chip as a whole can be better controlled.

Description

Technical Field

[0001] The present invention relates to the field of photon computing technology, and in particular to a method and system for controlling a photon computing chip and a multi-photon computing unit DAC in an optoelectronic hybrid computing system. Background Art

[0002] In the process of AI calculation, electronic chips play an important role in data transmission and calculation. The whole process of artificial neural algorithm contains a large number of matrix multiplication operations, and the CPU based on traditional computer architecture is very laborious to process these operations, and the calculation efficiency is low. Therefore, academia and industry have turned their attention to new hardware structures specifically used for artificial neural networks and deep learning, such as GPU, ASIC and FPGA. However, no matter what kind of technical architecture, it is designed and manufactured using traditional microelectronics technology. The improvement of AI chip performance is inseparable from the improvement of microelectronics integration. However, at the beginning of the 21st century, it was difficult for microelectronics technology to develop according to the prediction of Moore's Law, and the difficulty of improving chip integration continued to increase.

[0003] Compared with electrons, photons have many unique properties: photons have no rest mass, no interaction force between photons, and almost no interference; different wavelengths of light can be used for multi-channel simultaneous communication, and at a modulation frequency of tens of hertz, photons can still obtain stable modulation and information transmission, while electrical signals face the problem of radiation loss at high frequencies; in addition, optical signals are not affected by electromagnetic fields and have strong confidentiality. What is even more unique is that by using some specific optical structures, photons can perform some mathematical operations with zero energy consumption. Therefore, the use of photons can achieve ultra-high-speed, low-energy or even zero-energy computing, thereby breaking through the performance and cost bottlenecks of traditional microelectronic chips.

[0004] As the semiconductor industry gradually enters the post-Moore era, the development of integrated circuits continues to evolve in different directions. On the one hand, the development of new semiconductor materials, especially carbon nanotubes and two-dimensional semiconductor materials, continues the essence of Moore's Law and continues to reduce the size of devices or chips, that is, "deep Moore" (More Moore); on the other hand, for specific application fields, the development of new architectures and heterogeneous integrated chips, such as neuromorphic chips, optoelectronic chips, quantum chips, etc., realizes "More than Moore" (More than Moore).

[0005] Among them, photonic chips based on silicon-based optoelectronic technology use materials and processes compatible with integrated circuits to integrate micron and nanoscale photonics, electronics and optoelectronic devices on the same silicon substrate to achieve functional integration and complementary advantages of microelectronic devices and optoelectronic devices, and obtain optoelectronic chips with superior performance, which is an effective way to solve the performance bottleneck and information congestion faced by traditional integrated circuits. Thanks to the mature application of optical fiber communication, photons, as information carriers, have more multiplexing dimensions than electrons, such as amplitude, phase, wavelength, mode, etc., and thus have larger bandwidth, faster speed and lower energy consumption. Early silicon-based optoelectronic chips were designed to replace copper interconnect technology and solve the bottleneck of interconnection communication between the processor core and memory of microelectronic chips. The microprocessor and storage unit are realized by microelectronic devices, while the photonic devices mainly complete signal transmission and information transmission. With the increasing maturity of silicon photonic technology and the huge advantages of optical communication, people's attention to silicon photonic computing chips has gradually shifted from information transmission to information processing, including analog computing, quantum computing, brain-like computing and other cutting-edge application fields.

[0006] In existing photonic computing chips, each photonic computing unit needs to be equipped with a DAC (Digital-to-Analog Converter). With the advancement of technology, the number of photonic computing units integrated in a single photonic computing chip is increasing, especially for photonic computing chips with large-scale computing arrays. Therefore, the number of DACs required is also increasing, making the size, power consumption and heat generation of photonic computing chips difficult to control. Summary of the invention

[0007] The purpose of the present invention is to provide a photonic computing chip and DAC sharing control method and system in an optoelectronic hybrid computing system, which partially solves or alleviates the above-mentioned deficiencies in the prior art and enables multiple photonic computing units in a photonic computing chip to share one DAC, thereby reducing the number of DACs used, and further reducing the size and power consumption of the photonic computing chip.

[0008] In order to solve the technical problems mentioned above, the present invention specifically adopts the following technical solutions: a photonic computing chip in an optoelectronic hybrid computing system, the photonic computing chip comprising a photonic computing array composed of a plurality of photonic computing units; a plurality of photonic computing units in the photonic computing array are respectively connected to the same DAC and share the DAC to form a subarray, and the plurality of subarrays can work in parallel; each photonic computing unit in the subarray can be connected and disconnected with the DAC shared by it, and the DAC only forms a path with one photonic computing unit at the same time; a signal buffer is connected in series between each photonic computing unit and the DAC in the same subarray; the number of photonic computing units contained in the plurality of subarrays is inconsistent, so that the subarrays containing different numbers of photonic computing units have different computing powers.

[0009] As an improvement, the photon computing units in the subarray are arranged in the form of N rows and N columns or N rows and M columns, where N and M are natural numbers.

[0010] The present invention also provides a control method for a photon computing chip shared by multiple photon computing units DAC in an optoelectronic hybrid computing system, which is applied to the photon computing chip shared by the multiple photon computing units DAC, and includes:

[0011] S101 sets a DAC duty cycle according to the number of photon computing units in the subarray, divides the duty cycle into a plurality of segments, and allocates at least one segment to each photon computing unit in the subarray;

[0012] S102 controls the DAC to form a path with the photon computing unit allocated to the time period in each time period;

[0013] S103, while the DAC sends a signal to the photon computing unit, the DAC temporarily stores the signal in a signal buffer corresponding to the photon computing unit until the DAC resends the signal to the photon computing unit in the next working cycle to refresh the signal in the signal buffer;

[0014] S104 matches subarrays with corresponding computing power according to computing power requirements and / or algorithm requirements of the computing task, and the number of matched subarrays is one or more.

[0015] As an improvement, the method of matching the subarrays with corresponding computing power according to the computing power requirements of the computing tasks includes:

[0016] S10411 obtains the computing power requirements of the computing task;

[0017] S10412 traverses all subarrays in the photon computing chip in ascending order according to the computing power at the highest operating frequency of the photon computing unit;

[0018] S10413 If the computing power of a certain subarray is greater than or equal to the computing power requirement of the computing task, the computing task is matched with the subarray and the traversal is stopped;

[0019] S10414 If the computing power of all individual subarrays is less than the computing power requirement of the computing task, the subarray with the largest computing power is matched to the computing task, and the computing power requirement of the computing task is subtracted from the computing power of the subarray;

[0020] S10415 repeats step S10412, step S10413 and step S10414 until the sum of the computing power of the matched sub-arrays is greater than or equal to the computing power requirement of the computing task;

[0021] Methods for matching subarrays with corresponding computing power according to the algorithm requirements of computing tasks include:

[0022] S10421 obtains the number of photon computing units required by the computing task algorithm;

[0023] S10422 traverses all subarrays in the photon computing chip in ascending order of the number of photon computing units included;

[0024] S10423 If the number of photon computing units in a certain subarray is greater than or equal to the number of photon computing units required for the computing task, the computing task is matched with the subarray, and the traversal is stopped;

[0025] S10424 If the number of photon computing units of all individual subarrays is less than the number of photon computing units required for the computing task, match the subarray with the largest number of photon computing units for the computing task, and subtract the number of photon computing units of the subarray from the number of photon computing units required for the computing task;

[0026] S10425 repeats step S10422, step S10423 and step S10424 until the sum of the numbers of photon computing units of the matching sub-arrays is greater than or equal to the number of photon computing units required for the computing task.

[0027] As an improvement, if the number of photon units required for a computing task is greater than the sum of the number of photon computing units in all sub-arrays, the computing task will be divided for multiple calculations by the photon computing chip.

[0028] As an improvement, the DAC operating frequency>the operating frequency of the photon computing unit*the number of photon computing units in the subarray.

[0029] As an improvement, the duty cycle of the DAC is greater than the operation cycle of the DAC.

[0030] As an improvement, the number of time periods in the DAC working cycle is consistent with the number of photon computing units sharing it.

[0031] As an improvement, the number of DAC operation cycles included in the DAC duty cycle is consistent with the number of photon calculation units shared by the DAC.

[0032] As an improvement, the method for obtaining the number of photon calculation units sharing the same DAC includes:

[0033] S201 obtains the operating frequency of the photon computing unit;

[0034] S202 obtains the operating frequency of DAC;

[0035] S203 obtains the number of photon computing units that share the same DAC according to the operating frequency of the photon computing unit and the operating frequency of the DAC.

[0036] The present invention also provides a photon computing chip control system shared by multiple photon computing units DAC in an optoelectronic hybrid computing system, comprising:

[0037] A duty cycle allocation module, used to set the DAC duty cycle according to the number of photon computing units in the subarray, divide the duty cycle into a plurality of segments, and allocate at least one segment to each photon computing unit in the subarray;

[0038] An on-off control module, used for controlling the DAC to form a path with the photon calculation unit allocated to the time period in each time period;

[0039] A signal buffer module, used for temporarily storing the signal in a signal buffer corresponding to the photon computing unit when the DAC sends the signal to the photon computing unit, until the signal in the signal buffer is refreshed when the DAC resends the signal to the photon computing unit in the next working cycle;

[0040] The subarray allocation module is used to match subarrays with corresponding computing power according to the computing power requirements of the computing tasks, and the number of matched subarrays is one or more.

[0041] The present invention is beneficial in that:

[0042] In the photon computing chip provided by the present invention, several photon computing units in the photon computing array are respectively connected to the same DAC and share the DAC to form a sub-array, and the several sub-arrays can work in parallel; and a signal buffer is connected in series between each photon computing unit and the DAC in the same sub-array; the number of photon computing units contained in the several sub-arrays is inconsistent, so that the sub-arrays containing different numbers of photon computing units have different computing powers.

[0043] By dividing the photon computing array into several sub-arrays with different computing powers, the sub-arrays with corresponding computing powers can be matched according to the computing power requirements and / or algorithm requirements. The photon computing units in each sub-array share a DAC, so compared with the above-mentioned existing technologies, its computing power allocation is more flexible. Under the same computing power requirements, fewer DACs are involved, making the use of DACs more efficient, and the overall volume, power consumption and heat generation of the chip can be better controlled.

[0044] Since photonic computing chips are mainly used in AI, the computing power requirements of computing tasks are generally relatively stable, so the photonic computing units contained in the subarray can be customized according to the needs. In actual use, most tasks can be completed by a matching subarray or a combination of multiple subarrays, thereby improving the efficiency of a single photonic computing unit and reducing the overall power consumption of the photonic computing chip.

[0045] In addition, in the present invention, a signal buffer is connected in series between each photon computing unit and the DAC in the same subarray, that is, the signal sent by the DAC to the photon computing unit will be cached in the signal buffer first. When it is necessary to resend, the signal in the signal buffer can be directly called without further calculation. When the DAC calculates and sends a signal to the photon computing unit again in the next working cycle, the previously cached signal can be automatically refreshed. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual scale. Obviously, the drawings described below are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without paying creative labor.

[0047] Figure 1 A schematic diagram of an embodiment of a plurality of sub-arrays in a photonic computing chip in an optoelectronic hybrid computing system of the present invention;

[0048] Figure 2 A schematic diagram of an embodiment of a signal buffer in a photonic computing chip in an optoelectronic hybrid computing system of the present invention;

[0049] Figure 3 A flowchart of an embodiment of a method for controlling a photon computing chip in an optoelectronic hybrid computing system of the present invention;

[0050] Figure 4 It is a schematic diagram of an embodiment of a photonic computing chip control system in the optoelectronic hybrid computing system of the present invention. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0052] Herein, suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present invention, and have no specific meanings by themselves. Therefore, "module", "component" or "unit" can be used mixedly.

[0053] In this document, the terms "upper", "lower", "inner", "outer", "front", "back", "one end", "the other end" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0054] In this document, unless otherwise clearly specified and limited, the terms "installed", "provided with", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0055] Herein "and / or" includes any and all combinations of one or more of the associated listed items.

[0056] Herein, "plurality" means two or more than two, ie, it includes two, three, four, five, etc.

[0057] In this specification, some embodiments may be disclosed in a format of being within a certain range. It should be understood that such description of "being within a certain range" is only for convenience and brevity, and should not be interpreted as a rigid limitation on the disclosed range. Therefore, the description of the range should be considered to have specifically disclosed all possible sub-ranges and independent numerical values ​​within this range. For example, the range The description of should be considered to have specifically disclosed sub-ranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within this range, for example, 1, 2, 3, 4, 5, and 6. The above rules apply regardless of the breadth of the range.

[0058] Definition of noun:

[0059] Optical AI chip: a chip specially designed for processing optical data and performing artificial intelligence (AI) inference, also known as a photonic computing chip, or photonic chip, or optical computing chip. It is based on the principle of optics, takes optical signals as input, and performs computing operations through a series of optical elements and devices. These optical elements can be components such as lasers, optical fibers, and optical modulators for processing and transmitting optical signals. For example, a photonic computing chip converts an optical signal into a weak photocurrent signal through a light-emitting diode, and then converts the photocurrent signal into a voltage signal U through a transimpedance amplifier TIA, and then the analog-to-digital converter ADC converts the voltage signal (i.e., analog signal) into a digital signal and outputs it to the FPGA for processing. At the same time, the FPGA outputs the processed digital signal to the digital-to-analog converter DAC to convert the digital signal output by the FPGA into an analog signal and input it into the photonic computing chip.

[0060] Computing unit: a single computing unit used to implement computing. For example, a single computing unit that implements photon computing using a Mach-Zehnder interferometer (MZI) or a micro-ring structure (MMR). Another example is a photon computing unit implemented using the carrier light absorption effect, or a photon computing unit based on the absorption effect of phase change materials. Specifically, computing units can be divided into photon computing units and hybrid computing units.

[0061] Computing array: Based on the above computing units, an N*N computing array is constructed, and there is a computing unit at each intersection of the input row waveguide and the output column waveguide in the computing array. If the computing unit adopts a photon computing unit, the computing array can also be called a photon computing array; if the computing unit adopts an optoelectronic hybrid computing unit, the computing array can also be called an optoelectronic hybrid computing array.

[0062] Digital to Analog Converter (DAC): A converter that converts a discrete signal in the form of binary digital quantity into an analog quantity based on a standard quantity (or reference quantity). This conversion is the inverse process of analog-to-digital conversion (A / D conversion), that is, converting a digital coded signal into a corresponding analog signal.

[0063] Prior art Chinese patent application CN112231631A discloses a pipeline control method for parallel operation of a storage-computing integrated chip, wherein the storage-computing integrated chip comprises a plurality of storage-computing integrated unit arrays arranged in an array, storage-computing integrated unit arrays in the same row share a DAC, storage-computing integrated unit arrays in the same column share an ADC, and storage-computing integrated unit arrays in different rows and columns can work in parallel at the same time, and each storage-computing integrated unit array working in parallel is used to implement matrix multiplication and addition operations of a layer of neural network; the pipeline control method for parallel operation of the storage-computing integrated chip comprises: obtaining the delay of each step of implementing a layer of neural network; and performing pipeline control on a plurality of storage-computing integrated unit arrays in different rows and columns working in parallel at the same time according to the delay of each step, so as to realize multi-task time division multiplexing.

[0064] In the above-mentioned prior art, the same row of storage and computing unit arrays share the same DAC. However, in actual use, in actual algorithm applications, some matrices for calculation are performed in the form of N*N. That is to say, even if only a 2*2 operation array is required, two rows of storage and computing units need to be called in the above-mentioned prior art, which will involve two DACs, making the distribution of the entire computing power not flexible enough. Similarly, when multiple DACs work at the same time, there are also problems of high power consumption and difficult to control heat generation.

[0065] Example 1: Figure 1 As shown, in order to solve the problem of inflexible computing power allocation in optoelectronic hybrid computing systems in the prior art, the present invention provides a photon computing chip in an optoelectronic hybrid computing system, wherein the photon computing chip includes a photon computing array composed of a plurality of photon computing units; the plurality of photon computing units in the photon computing array are respectively connected to the same DAC and share the DAC to form a sub-array, and the plurality of sub-arrays can work in parallel; each photon computing unit in the sub-array can be switched on and off with the DAC they share; and the DAC forms a path with only one photon computing unit at the same time; a signal buffer is connected in series between each photon computing unit and the DAC in the same sub-array; the number of photon computing units contained in the plurality of sub-arrays is inconsistent, so that the sub-arrays containing different numbers of photon computing units have different computing powers.

[0066] The principle of the present invention is that by dividing the photon computing array into several sub-arrays with different computing powers, the sub-arrays with corresponding computing powers can be matched according to the computing power requirements. The photon computing units in each sub-array share a DAC, so compared with the above-mentioned prior art, its computing power allocation is more flexible. Under the same computing power requirement, fewer DACs are involved, making the use of DACs more efficient, and the overall power consumption and heat generation of the chip can be better controlled.

[0067] In addition, since the main application field of photon computing chips is AI, the computing power requirements of computing tasks are generally relatively stable, so the photon computing units contained in the subarray can be customized according to the needs. In actual use, most tasks can be completed by a matching subarray or a combination of multiple subarrays, thereby improving the efficiency of a single photon computing unit and reducing the overall power consumption of the photon computing chip.

[0068] In the present invention, the photon computing units in the subarray are arranged in the form of N rows and M columns, where N and M are natural numbers, and N and M can be the same or different. For example, a 16*16 photon computing unit array (the numbers exemplified in the present invention are deliberately simplified for the convenience of description and understanding, and in fact the number of photon computing units in the photon computing chip is far more than the listed number), such as Figure 1 As shown, it can be divided into 8 4*4 sub-arrays and 2 8*8 sub-arrays. If the computing power of a 4*4 sub-array is 16 units and the computing power of an 8*8 sub-array is 64 units, then assuming that the computing power requirement of the computing task is 15 units, then a 4*4 unit sub-array can be matched, and the sub-array only requires one DAC. If it is the above-mentioned prior art, it is also a 16*16 array, and it is necessary to match 4 rows of integrated storage and computing units, a total of 4 DACs. Assuming that the computing power of the computing task requires 70 units, then a 4*4 unit sub-array and an 8*8 sub-array can be matched to work in parallel, and only 2 DACs are involved. If the above-mentioned prior art is adopted, 8 rows of integrated storage and computing units are required, involving 8 DACs.

[0069] In addition, since multiple photon computing units in the present invention share one DAC, and in fact the DAC can only perform one digital-to-analog conversion operation at the same time, in order not to slow down the operation speed of the photon computing unit, the DAC selected in this application has a higher operating frequency than the frequency of the photon computing unit. For example, the operating frequency of the photon computing unit is 100MHz, and ten photon computing units share one DAC, then the operating frequency of the DAC should be above 1GHz. Therefore, in fact, in the same subarray, the DAC does not serve each photon computing unit at the same time, but relies on a faster operating speed to serve each photon computing unit separately within a working time period.

[0070] However, the problem with the above solution is that the DAC cannot store the signals sent by multiple photon computing units, and the later signals will refresh the earlier signals. When the signal sent by a photon computing unit fails to be verified and needs to be resent, since the signal is not stored, it can only be reconverted and resent, which reduces the DAC working efficiency and causes delays.

[0071] In order to solve this problem, the present invention has a signal buffer connected in series between each photon computing unit and the DAC in the same subarray, that is, the signal sent by the DAC to the photon computing unit will be cached in the signal buffer first. When it needs to be resent, the signal in the signal buffer can be directly called without further calculation. When the DAC calculates and sends a signal to the photon computing unit again in the next working cycle, the previously cached signal can be automatically refreshed.

[0072] In this embodiment, the signal buffer may be a capacitor.

[0073] In addition, each photon computing unit in the subarray can be switched on and off with its shared DAC, and the DAC forms a path with only one photon computing unit at a time; therefore, a switching mechanism needs to be set between the photon computing units and their shared DACs. The switching mechanism can be a physical switch or a logic program integrated in the photon computing unit.

[0074] Example 2: Figure 2 As shown, the present invention also provides a photon computing chip control method shared by multiple photon computing units DAC in an optoelectronic hybrid computing system, which is applied to the photon computing chip shared by the multiple photon computing units DAC mentioned above, and includes the following steps:

[0075] S101 sets a DAC working cycle according to the number of photon computing units in the subarray, divides the working cycle into several segments, and allocates at least one segment to each photon computing unit in the subarray.

[0076] In some implementations, the DAC operating frequency>the operating frequency of the photon computing unit*the number of photon computing units in the subarray. For example, if the operating frequency of the photon computing unit is 100 MHz and ten photon computing units share one DAC, the operating frequency of the DAC should be above 1 GHz.

[0077] Ideally, the DAC has a duty cycle of 10 operating cycles (one operating cycle is the inverse of the frequency, i.e. 10 -9 seconds), it can be understood that the working cycle of the DAC is greater than the operating cycle of the DAC.

[0078] The DAC's working cycle can be divided into ten segments, each segment is one operating cycle, and each segment corresponds to one photon computing unit. Of course, considering issues such as latency, the working cycle can also be set to 20 operating cycles, and the working cycle can also be divided into ten segments, each segment corresponds to 2 operating cycles, and so on.

[0079] S102 controls the DAC to form a path with the photon computing unit allocated to the time period in each time period.

[0080] It is not possible for a DAC to send signals to multiple photonic computing units at the same time.

[0081] Therefore, it is necessary to set the connection and disconnection between each photon computing unit and the DAC according to the working cycle time period assigned to each photon computing unit, so that the time period in which the DAC sends the signal is exactly the time period in which the photon computing unit assigned to this time period is connected to it. -9 seconds to form a path with the DAC, and the time for each photon computing unit to form a path with the DAC is 10 -9 , then in the ten time periods of one working cycle of the DAC, the 10 generated signal segments will be sent to the ten photon computing units respectively, so that the DAC can serve the ten photon computing units in turn in one working cycle.

[0082] S103DAC temporarily stores the signal in the signal buffer corresponding to the photon computing unit while sending the signal to the photon computing unit, until the signal in the signal buffer is refreshed when the DAC resends the signal to the photon computing unit in the next working cycle.

[0083] The signals sent by DAC to the photon computing unit will be cached in the signal buffer first. When it needs to be resent, the signal in the signal buffer can be directly called without further calculation. When the DAC calculates and sends a signal to the photon computing unit again in the next working cycle, the previously cached signal can be automatically refreshed.

[0084] S104 matches subarrays with corresponding computing power according to computing power requirements and / or algorithm requirements of the computing task, and the number of matched subarrays is one or more.

[0085] The computing power of a subarray is proportional to the number of photon computing units in the subarray and the operating frequency of the photon computing units. The operating frequency of the photon computing unit is not fixed, but can float between the basic operating frequency and the maximum operating frequency. It is understandable that the computing power of the photon computing unit is the highest when it is at the highest operating frequency, and vice versa when it is running at the basic operating frequency.

[0086] In order to flexibly match the subarrays of appropriate computing power for the computing tasks and thus reduce the number of DAC calls, the specific matching steps include:

[0087] S10411 obtains the computing power requirements of the computing task.

[0088] Similarly, a 16*16 photon computing unit array is used, such as Figure 1As shown in the figure, it can be divided into 8 4*4 sub-arrays and 2 8*8 sub-arrays as an example. The computing power of a 4*4 sub-array is 16 units, and the computing power of an 8*8 sub-array is 64 units. The computing task requires 75 units of computing power.

[0089] S10412 traverses all sub-arrays in the photonic computing chip in ascending order of computing power according to the lowest operating frequency.

[0090] The operation frequency of the photon computing unit is different, and its computing power is also different. In order to improve the working efficiency of a single photon computing unit, in this implementation, the photon computing unit is operated at the highest operation frequency.

[0091] For ease of description and understanding, in this example, the computing power of the subarray with the lowest operating frequency is only 16 and 64, so the traversal is performed in the order of 16 to 64.

[0092] S10413 If the computing power of a certain subarray is greater than or equal to the computing power requirement of the computing task, the subarray is matched for the computing task and the traversal is stopped.

[0093] Obviously, the computing power of a single subarray cannot reach 75. If the computing power required for the computing task is 15, then the traversal can be terminated after matching the subarray with a computing power of 16.

[0094] S10414: If the computing power of all individual sub-arrays is less than the computing power requirement of the computing task, the sub-array with the largest computing power is matched to the computing task, and the computing power requirement of the computing task is subtracted from the computing power of the sub-array.

[0095] Since the computing power of a single subarray is less than the computing power of the computing task, the subarray with the largest computing power, that is, the subarray with a computing power of 64, is matched, and then the computing power requirement of the computing task is subtracted from the computing power of the subarray, that is, 75-64=11.

[0096] S10415 repeats step S1042, step S1043 and step S1044 until the sum of the computing power of the matched sub-arrays is greater than or equal to the computing power requirement of the computing task.

[0097] The computing power requirement of the computing task is still 11, and the traversal is performed again. At this time, the remaining sub-arrays are arranged from the smallest to the smallest, and the sub-array with a computing power of 16 is selected and the traversal is ended.

[0098] Finally, a 16-computing-power subarray and a 64-computing-power subarray were selected to handle the task, which involved the least DAC and helped control the power consumption of the chip.

[0099] The purpose of selecting a subarray based on the computing power of the photon computing unit at the best operating frequency is to improve the working efficiency of the subarray. According to the relationship between computing power, frequency and quantity, in some embodiments, under the premise of the same computing power requirement, the frequency of the photon computing unit can be appropriately reduced, and a larger number of photon computing units can be selected, thereby reducing the heat generated by the photon computing unit.

[0100] Another situation is to match sub-arrays according to algorithm requirements. The so-called algorithm requirements are that the algorithm of the computing task clearly requires the number of photon computing units. Specifically, the method of matching sub-arrays with corresponding computing power according to the algorithm requirements of the computing task includes:

[0101] S10421 obtains the number of photon computing units required by the computing task algorithm.

[0102] Similarly, a 16*16 photon computing unit array is used, such as Figure 1 As shown, it can be divided into 8 4*4 sub-arrays and 2 8*8 sub-arrays as an example. The algorithm requirement of the computing task requires 75 photon computing units.

[0103] S10422 traverses all sub-arrays in the photon computing chip in ascending order of the number of photon computing units contained.

[0104] S10423 If the number of photon computing units in a certain subarray is greater than or equal to the number of photon computing units required by the computing task, the computing task is matched with the subarray and the traversal is stopped.

[0105] Obviously, the number of photon computing units in a single subarray cannot reach 75. If the algorithm of the computing task requires 15 photon computing units, then the traversal can be ended after matching the 4*4 subarray.

[0106] S10424 If the number of photon computing units of all individual sub-arrays is less than the photon computing unit number requirement of the computing task, the sub-array with the largest number of photon computing units is matched to the computing task, and the photon computing unit number requirement of the computing task is subtracted from the number of photon computing units of the sub-array.

[0107] Since the number of photon computing units in a single subarray is less than the requirement of the computing task, the subarray with the largest number of photon computing units, i.e., the 8*8 subarray, is matched, and then the requirement of the computing task is subtracted from the number of photon computing units in the subarray, i.e., 75-64=11.

[0108] S10425 repeats step S10422, step S10423 and step S10424 until the sum of the numbers of photon computing units of the matching sub-arrays is greater than or equal to the number of photon computing units required for the computing task.

[0109] There are still 11 computing tasks left, so we traverse again. At this time, we select the subarray with 4*4 photon computing units from the remaining subarrays after arranging them from small to large, and then end the traversal.

[0110] There is another situation where the demand for the number of photon computing units in the task is higher than the sum of the number of photon computing units in all sub-arrays. In the above example, the number of photon computing units in all sub-arrays is 16*16=256. If the number of photon computing units required for a task is 1024, in the above case, the sub-arrays work in parallel and the step of allocating sub-arrays is no longer performed. It can be understood that when all sub-arrays work in parallel and the number of photon computing units required cannot be met, the computing task needs to be divided, and the entire photon computing chip needs multiple operations to complete the computing task.

[0111] In addition, the present invention also provides a method for obtaining the number of photon calculation units sharing the same DAC, that is, the number of photon calculation units in the subarray, including:

[0112] S201 obtains the operating frequency of the photon computing unit, for example, 100 MHz.

[0113] S202 obtains the operating frequency of the DAC, for example, 1 GHz.

[0114] S203 obtains the number of photon computing units that share the same DAC according to the operating frequency of the photon computing unit and the operating frequency of the DAC, 1G / 100M=10, that is, the DAC can be shared by a maximum of 10 photon computing units.

[0115] Implementation 3: If Figure 3 As shown, the present invention also provides a photon computing chip control system shared by multiple photon computing units DAC in an optoelectronic hybrid computing system, comprising:

[0116] A duty cycle allocation module, used to set the DAC duty cycle according to the number of photon computing units in the subarray, divide the duty cycle into a plurality of segments, and allocate at least one segment to each photon computing unit in the subarray;

[0117] An on-off control module, used for controlling the DAC to be connected to the photon calculation unit assigned to the time period in each time period;

[0118] A signal buffer module is used for temporarily storing the signal in a signal buffer corresponding to the photon computing segment when the DAC sends the signal to the photon computing unit, until the signal in the signal buffer is refreshed when the DAC resends the signal to the photon computing unit in the next working cycle;

[0119] The subarray allocation module is used to match subarrays with corresponding computing power according to the computing power requirements of the computing tasks, and the number of matched subarrays is one or more.

[0120] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0121] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a computer terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0122] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A photonic computing chip in an optoelectronic hybrid computing system, characterized in that: The photon computing chip comprises a photon computing array composed of a plurality of photon computing units; the plurality of photon computing units in the photon computing array are respectively connected to the same DAC and share the DAC to form a subarray, and the plurality of subarrays can work in parallel; each photon computing unit in the subarray can be switched on and off with the shared DAC, and the DAC forms a path with only one photon computing unit at the same time; a signal buffer is connected in series between each photon computing unit in the same subarray and the shared DAC; the DAC temporarily stores the signal in the signal buffer corresponding to the photon computing unit while sending a signal to the photon computing unit, until the DAC resends the signal to the photon computing unit in the next working cycle, and refreshes the signal in the signal buffer; the number of photon computing units contained in the plurality of subarrays is inconsistent, so that the subarrays containing different numbers of photon computing units have different computing powers; The working cycle of the DAC is set according to the number of photon computing units in the subarray, and the working cycle is divided into a plurality of segments, at least one segment is allocated to each photon computing unit in the subarray; the DAC is connected to the photon computing unit allocated to the time period in each time period; The method of matching a subarray with corresponding computing power according to the computing power requirement of a computing task includes: S10411 obtains the computing power requirements of the computing task; S10412 traverses all subarrays in the photon computing chip in ascending order according to the computing power at the highest operating frequency of the photon computing unit; S10413 If the computing power of a certain subarray is greater than or equal to the computing power requirement of the computing task, the computing task is matched with the subarray and the traversal is stopped; S10414 If the computing power of all individual subarrays is less than the computing power requirement of the computing task, the subarray with the largest computing power is matched to the computing task, and the computing power requirement of the computing task is subtracted from the computing power of the subarray; S10415 repeats step S10412, step S10413 and step S10414 until the sum of the computing power of the matched sub-arrays is greater than or equal to the computing power requirement of the computing task; Methods for matching subarrays with corresponding computing power according to the algorithm requirements of computing tasks include: S10421 obtains the number of photon computing units required by the computing task algorithm; S10422 traverses all subarrays in the photon computing chip in ascending order of the number of photon computing units included; S10423 If the number of photon computing units in a certain subarray is greater than or equal to the number of photon computing units required for the computing task, the computing task is matched with the subarray, and the traversal is stopped; S10424 If the number of photon computing units of all individual subarrays is less than the number of photon computing units required for the computing task, match the subarray with the largest number of photon computing units for the computing task, and subtract the number of photon computing units of the subarray from the number of photon computing units required for the computing task; S10425 repeats step S10422, step S10423 and step S10424 until the sum of the numbers of photon computing units of the matching sub-arrays is greater than or equal to the number of photon computing units required for the computing task.

2. The photon computing chip in the optoelectronic hybrid computing system according to claim 1, characterized in that: The photon computing units in the subarray are arranged in the form of N rows and M columns, where N and M are natural numbers.

3. A control method for a photon computing chip shared by multiple photon computing units DAC in an optoelectronic hybrid computing system, applied to the photon computing chip according to any one of claims 1 to 2, characterized in that include: S101 sets a common DAC duty cycle according to the number of photon computing units in each subarray, divides the duty cycle into a plurality of segments, and allocates at least one segment to each photon computing unit in the subarray; S102 controls the DAC to form a path with the photon computing unit allocated to the time period in each time period; S103, while the DAC sends a signal to the photon computing unit, the DAC temporarily stores the signal in a signal buffer corresponding to the photon computing unit until the DAC resends a signal to the photon computing unit in the next working cycle, and then refreshes the signal in the signal buffer; S104: matching a subarray with corresponding computing power according to the computing power requirement and / or algorithm requirement of the computing task, where the number of the matched subarrays is one or more; The method of matching a subarray with corresponding computing power according to the computing power requirement of a computing task includes: S10411 obtains the computing power requirements of the computing task; S10412 traverses all subarrays in the photon computing chip in ascending order according to the computing power at the highest operating frequency of the photon computing unit; S10413 If the computing power of a certain subarray is greater than or equal to the computing power requirement of the computing task, the computing task is matched with the subarray and the traversal is stopped; S10414 If the computing power of all individual subarrays is less than the computing power requirement of the computing task, the subarray with the largest computing power is matched to the computing task, and the computing power requirement of the computing task is subtracted from the computing power of the subarray; S10415 repeats step S10412, step S10413 and step S10414 until the sum of the computing power of the matched sub-arrays is greater than or equal to the computing power requirement of the computing task; Methods for matching subarrays with corresponding computing power according to the algorithm requirements of computing tasks include: S10421 obtains the number of photon computing units required by the computing task algorithm; S10422 traverses all subarrays in the photon computing chip in ascending order of the number of photon computing units included; S10423 If the number of photon computing units in a certain subarray is greater than or equal to the number of photon computing units required for the computing task, the computing task is matched with the subarray, and the traversal is stopped; S10424 If the number of photon computing units of all individual subarrays is less than the number of photon computing units required for the computing task, match the subarray with the largest number of photon computing units for the computing task, and subtract the number of photon computing units of the subarray from the number of photon computing units required for the computing task; S10425 repeats step S10422, step S10423 and step S10424 until the sum of the numbers of photon computing units of the matching sub-arrays is greater than or equal to the number of photon computing units required for the computing task.

4. The method for controlling a photon computing chip shared by multiple photon computing units DAC in an optoelectronic hybrid computing system according to claim 3, characterized in that: If the number of photon computing units required for a computing task is greater than the sum of the number of photon computing units in all sub-arrays, the computing task will be divided for multiple calculations by the photon computing chip.

5. The method for controlling a photon computing chip shared by multiple photon computing units DAC in an optoelectronic hybrid computing system according to claim 3, characterized in that: DAC operating frequency>operating frequency of photon computing unit*number of photon computing units in the subarray.

6. The method for controlling a photon computing chip shared by multiple photon computing units DAC in an optoelectronic hybrid computing system according to claim 3, characterized in that: The number of time periods in the DAC working cycle is consistent with the number of photon computing units sharing it.

7. The control method for a photon computing chip shared by multiple photon computing units DAC in an optoelectronic hybrid computing system according to claim 6, characterized in that: The number of DAC operation cycles included in the DAC working cycle is consistent with the number of photon computing units sharing the DAC.

8. The method for controlling a photon computing chip shared by multiple photon computing units DAC in an optoelectronic hybrid computing system according to claim 3, characterized in that: The steps to obtain the number of photon counting units sharing the same DAC include: S201 obtains the operating frequency of the photon computing unit; S202 obtains the operating frequency of DAC; S203 obtains the number of photon computing units that share the same DAC according to the operating frequency of the photon computing unit and the operating frequency of the DAC.

9. A photon computing chip control system shared by multiple photon computing units DAC in an optoelectronic hybrid computing system, applied to the photon computing chip described in any one of claims 1 to 2, characterized in that include: A duty cycle allocation module, used to set the DAC duty cycle according to the number of photon computing units in the subarray, divide the duty cycle into a plurality of segments, and allocate at least one segment to each photon computing unit in the subarray; An on-off control module, used for controlling the DAC to be connected to the photon calculation unit assigned to the time period in each time period; A signal buffer module, used for temporarily storing the signal in a signal buffer corresponding to the photon computing unit when the DAC sends the signal to the photon computing unit, until the signal in the signal buffer is refreshed when the DAC resends the signal to the photon computing unit in the next working cycle; A subarray allocation module, used to match a subarray with corresponding computing power according to the computing power requirement of the computing task, and the number of the matched subarrays is one or more; The method for the subarray allocation module to match the subarray with corresponding computing power according to the computing power requirement of the computing task includes: S10411 obtains the computing power requirements of the computing task; S10412 traverses all subarrays in the photon computing chip in ascending order according to the computing power at the highest operating frequency of the photon computing unit; S10413 If the computing power of a certain subarray is greater than or equal to the computing power requirement of the computing task, the computing task is matched with the subarray and the traversal is stopped; S10414 If the computing power of all individual subarrays is less than the computing power requirement of the computing task, the subarray with the largest computing power is matched to the computing task, and the computing power requirement of the computing task is subtracted from the computing power of the subarray; S10415 repeats step S10412, step S10413 and step S10414 until the sum of the computing power of the matched sub-arrays is greater than or equal to the computing power requirement of the computing task; Methods for matching subarrays with corresponding computing power according to the algorithm requirements of computing tasks include: S10421 obtains the number of photon computing units required by the computing task algorithm; S10422 traverses all subarrays in the photon computing chip in ascending order of the number of photon computing units included; S10423 If the number of photon computing units in a certain subarray is greater than or equal to the number of photon computing units required for the computing task, the computing task is matched with the subarray, and the traversal is stopped; S10424 If the number of photon computing units of all individual subarrays is less than the number of photon computing units required for the computing task, match the subarray with the largest number of photon computing units for the computing task, and subtract the number of photon computing units of the subarray from the number of photon computing units required for the computing task; S10425 repeats step S10422, step S10423 and step S10424 until the sum of the numbers of photon computing units of the matching sub-arrays is greater than or equal to the number of photon computing units required for the computing task.

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