Interrupt processing system, method, readable storage medium and program product

Abstract

The present invention discloses an interrupt processing system, method, readable storage medium and program product, which relate to the field of computer application technology, including: a peripheral component interconnection fast bus, which is used to convert the interrupt electrical signals received from each peripheral respectively into a message notification interrupt signal, and send each message notification interrupt signal to a platform-level interrupt controller; a platform-level interrupt controller, which is used to arbitrate each message notification interrupt signal; parse the currently selected message notification interrupt signal obtained by arbitration, and obtain the interrupt identification information of the target peripheral that sends the currently selected message notification interrupt signal; send an interrupt notification to a RISC‑V architecture processor; a RISC‑V architecture processor, which is used to call an available processor core to enter the interrupt service program corresponding to the target peripheral according to the obtained interrupt identification information to perform interrupt processing. The present invention improves the scalability of the platform-level interrupt controller and reduces the interrupt response delay.

Description

Technical Field

[0001] The present invention relates to the field of computer application technology, and in particular to an interrupt processing system, method, readable storage medium and program product. Background Art

[0002] The external interrupt of the central processing unit (CPU) is used to handle specific events or requests that occur outside the CPU. External interrupts can be initiated by hardware devices such as keyboards, printers, mice, etc., or by emergency situations such as power failures and hardware failures in the system.

[0003] The Platform Level Interrupt Controller (PLIC) is a system interrupt controller defined by the fifth-generation Reduced Instruction Set Computer V (RISC-V) architecture standard. It is mainly used for priority arbitration and dispatching of multiple external interrupt sources. In a relatively simple system with a single core or a small number of cores, ordinary platform-level interrupt controller processing can complete the corresponding external interrupt processing. However, with the increasing scale of the system, the current platform-level interrupt controller has poor scalability for hardware threads (Hart) of hundreds or even thousands of processor cores, and the wiring of the platform-level interrupt controller is complex. In addition, after receiving the interrupt signal, the processor core needs to query the peripherals one by one in the interrupt handler to determine the interrupt source, and the delay of the interrupt response is high.

[0004] In summary, how to effectively solve the problems of poor scalability of platform-level interrupt controllers and high delay in interrupt responses is an issue that those skilled in the art urgently need to solve. Summary of the invention

[0005] An object of the present invention is to provide an interrupt processing system, which improves the scalability of a platform-level interrupt controller and reduces interrupt response delay; another object of the present invention is to provide an interrupt processing device, a computer-readable storage medium and a computer program product.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0007] An interrupt processing system, comprising:

[0008] The peripheral component interconnection fast bus is used to receive the interrupt electrical signals sent by each peripheral respectively; convert each interrupt electrical signal into a message notification interrupt signal, and send each message notification interrupt signal to the platform-level interrupt controller;

[0009] The platform-level interrupt controller is used to arbitrate each message notification interrupt signal according to a preset interrupt arbitration mechanism to obtain a currently selected message notification interrupt signal; parse the currently selected message notification interrupt signal to obtain interrupt identification information of a target peripheral that sends the currently selected message notification interrupt signal; and send an interrupt notification to a RISC-V architecture processor;

[0010] The RISC-V architecture processor is used to obtain the interrupt identification information according to the interrupt notification; and call the available processor core to enter the interrupt service program corresponding to the target peripheral to perform interrupt processing according to the interrupt identification information.

[0011] In a specific embodiment of the present invention, the platform-level interrupt controller is also used to, before arbitrating each message notification interrupt signal according to a preset interrupt arbitration mechanism, when the first message notification interrupt signal is received, obtain the peripheral that sends the first message notification interrupt signal; set the target interrupt wait register corresponding to the peripheral that sends the first message notification interrupt signal to a non-enabled state; wherein the platform-level interrupt controller includes at least one interrupt wait register, and the interrupt wait register has a one-to-many relationship with each peripheral.

[0012] In a specific implementation of the present invention, the platform-level interrupt controller is specifically used to arbitrate the message notification interrupt signal sent by each peripheral corresponding to the target interrupt waiting register according to the preset interrupt arbitration mechanism.

[0013] In a specific implementation of the present invention, the platform-level interrupt controller is further configured to store the interrupt identification information in a read / complete register after obtaining the interrupt identification information of the target peripheral device that sends the currently selected message notification interrupt signal; wherein the read / complete register is deployed in the platform-level interrupt controller;

[0014] The RISC-V architecture processor is specifically used to read the interrupt identification information from the read / completion register.

[0015] In a specific implementation of the present invention, the platform-level interrupt controller is specifically used to determine the target peripheral type to which the target peripheral belongs according to the interrupt identification information; select a target read / complete register from a read / complete register set consisting of read / complete registers corresponding to each processor core of the target peripheral type; store the interrupt identification information in the target read / complete register;

[0016] The RISC-V architecture processor is specifically used to read the interrupt identification information from the target read / completion register; call the target processor core corresponding to the target read / completion register to enter the interrupt service program corresponding to the target peripheral to perform interrupt processing.

[0017] In a specific embodiment of the present invention, the platform-level interrupt controller is specifically used to select a target read / completion register from a read / completion register set consisting of read / completion registers corresponding to each processor core of the target peripheral type based on a load balancing principle.

[0018] In a specific embodiment of the present invention, the RISC-V architecture processor is also used to write the interrupt identification information back to the target read / completion register after the interrupt processing is completed.

[0019] In a specific embodiment of the present invention, the platform-level interrupt controller is also used to modify the state of the peripheral component interconnect fast bus when detecting the write-back action of the RISC-V architecture processor to the target read / completion register.

[0020] In a specific implementation of the present invention, the platform-level interrupt controller is specifically used to modify the state of the peripheral component interconnect fast bus by setting the target interrupt wait register to an enabled state.

[0021] In a specific implementation of the present invention, the platform-level interrupt controller is specifically used to arbitrate each message notification interrupt signal according to an interrupt priority arbitration mechanism set based on an urgency principle.

[0022] In a specific implementation of the present invention, the platform-level interrupt controller is specifically used to arbitrate each message notification interrupt signal according to an interrupt priority arbitration mechanism set based on a response time principle.

[0023] In a specific implementation of the present invention, the platform-level interrupt controller is specifically used to arbitrate each message notification interrupt signal according to an interrupt priority arbitration mechanism set based on a dependency principle.

[0024] An interrupt processing method, applied to a platform-level interrupt controller, comprises:

[0025] Receiving each message notification interrupt signal sent by the peripheral component interconnection fast bus; wherein each message notification interrupt signal is obtained by converting the interrupt electrical signal sent by each peripheral by the peripheral component interconnection fast bus;

[0026] Arbitrate each message notification interrupt signal according to a preset interrupt arbitration mechanism to obtain a currently selected message notification interrupt signal;

[0027] Parsing the currently selected message notification interrupt signal to obtain interrupt identification information of the target peripheral device that sends the currently selected message notification interrupt signal;

[0028] An interrupt notification is sent to a RISC-V architecture processor, so that the RISC-V architecture processor obtains the interrupt identification information according to the interrupt notification, and calls an available processor core to enter an interrupt service program corresponding to the target peripheral device to perform interrupt processing according to the interrupt identification information.

[0029] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the interrupt processing method described above are implemented.

[0030] A computer program product comprises a computer program, wherein the computer program implements the steps of the interrupt handling method as described above when executed by a processor.

[0031] The interrupt processing system provided by the present invention includes: a peripheral component interconnection fast bus, which is used to receive interrupt electrical signals respectively sent by each peripheral; convert each interrupt electrical signal into a message notification interrupt signal, and send each message notification interrupt signal to a platform-level interrupt controller; the platform-level interrupt controller is used to arbitrate each message notification interrupt signal according to a preset interrupt arbitration mechanism to obtain a currently selected message notification interrupt signal; parse the currently selected message notification interrupt signal to obtain interrupt identification information of a target peripheral that sends the currently selected message notification interrupt signal; send an interrupt notification to a RISC-V architecture processor; a RISC-V architecture processor is used to obtain interrupt identification information according to the interrupt notification; call an available processor core according to the interrupt identification information to enter an interrupt service program corresponding to the target peripheral to perform interrupt processing.

[0032] The beneficial effects of the present invention are: by setting a peripheral component interconnection fast bus between the peripheral and the platform-level interrupt controller, allocating exclusive channel bandwidth to each peripheral through the peripheral component interconnection fast bus, and converting each received interrupt electrical signal into a unified message notification interrupt signal, and sending each message notification interrupt signal to the platform-level interrupt controller, the complex connection settings between each peripheral and the platform-level interrupt controller are avoided, the connection complexity of the platform-level interrupt controller is greatly simplified, and the scalability of the platform-level interrupt controller is improved. In addition, the converted message notification interrupt signal carries the interrupt identification information of the target peripheral that sends the currently selected message notification interrupt signal, and the processor core does not need to query the interrupt source, which greatly reduces the interrupt response delay and improves the interrupt processing efficiency of the RISC-V architecture processor.

[0033] Correspondingly, the present invention also provides an interrupt processing method, a computer-readable storage medium and a computer program product corresponding to the above-mentioned interrupt processing system, which have the above-mentioned technical effects and are not described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 It is a structural block diagram of an interrupt processing system in the related art;

[0036] Figure 2 A structural block diagram of an interrupt processing system in an embodiment of the present invention;

[0037] Figure 3 A timing diagram of interrupt processing in an embodiment of the present invention;

[0038] Figure 4 is a flowchart of an implementation of an interrupt processing method in an embodiment of the present invention;

[0039] Figure 5 The figure is a structural block diagram of an interrupt processing device in an embodiment of the present invention.

[0040] Figure 1 The following are marked in the accompanying drawings:

[0041] 01- The interrupt source gate of the platform-level interrupt controller, 02- Platform-level interrupt controller, 03- RISC-V architecture processor;

[0042] Figure 2 and Figure 3 The following are marked in the accompanying drawings:

[0043] 1-Fast bus for interconnecting peripheral components, 2-Platform-level interrupt controller, 3-RISC-V architecture processor. DETAILED DESCRIPTION

[0044] The current platform-level interrupt controller has poor scalability for hardware threads of hundreds or even thousands of processor cores, and the wiring of the platform-level interrupt controller is complex. In addition, after receiving an interrupt signal, the processor core needs to query the peripherals one by one in the interrupt handler to determine the interrupt source, resulting in high delay in interrupt response.

[0045] See also Figure 1 , Figure 1 This is a structural block diagram of an interrupt processing system in the related art. In a traditional interrupt processing system, when there are many external interrupts, the external interrupt source is directly connected to the platform-level interrupt controller 02 through the gate 01 of the dedicated platform-level interrupt controller interrupt source, resulting in a more complicated connection of the platform-level interrupt controller 02. After receiving the interrupt signal, the RISC-V architecture processor 03 needs to query the peripherals one by one in the interrupt processing program to determine the interrupt source, resulting in a large delay in the interrupt response.

[0046] To this end, the interrupt processing system provided in the present invention converts the received interrupt electrical signals into a unified message notification interrupt signal through a peripheral component interconnection fast bus, and sends each message notification interrupt signal to a platform-level interrupt controller, which greatly simplifies the connection complexity of the platform-level interrupt controller, eliminates the need for the processor core to query the interrupt source, and reduces the interrupt response delay.

[0047] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0048] See also Figure 2 , Figure 2 This is a structural block diagram of an interrupt processing system in an embodiment of the present invention. The system may include:

[0049] The peripheral component interconnection fast bus 1 is used to receive the interrupt electrical signals sent by each peripheral respectively; convert each interrupt electrical signal into a message notification interrupt signal, and send each message notification interrupt signal to the platform-level interrupt controller 2;

[0050] The platform-level interrupt controller 2 is used to arbitrate each message notification interrupt signal according to a preset interrupt arbitration mechanism to obtain the currently selected message notification interrupt signal; parse the currently selected message notification interrupt signal to obtain the interrupt identification information of the target peripheral that sends the currently selected message notification interrupt signal; and send an interrupt notification to the RISC-V architecture processor 3;

[0051] The RISC-V architecture processor 3 is used to obtain interrupt identification information according to the interrupt notification; and call the available processor core to enter the interrupt service program corresponding to the target peripheral to perform interrupt processing according to the interrupt identification information.

[0052] The interrupt processing system provided by the embodiment of the present invention includes a peripheral component interconnect express bus 1 (Peripheral Component Interconnect Express, PCIE), a platform-level interrupt controller 2 and a RISC-V (Reduced Instruction Set Computer V, fifth-generation reduced instruction set) architecture processor. The peripheral component interconnect express bus 1 receives interrupt electrical signals sent by each peripheral (i.e., interrupt source), converts each interrupt electrical signal into a message signaled interrupt signal (Message Signaled Interrupt, MSI), and sends each message signaled interrupt signal to the platform-level interrupt controller 2.

[0053] The interrupts sent by peripherals can be device interrupts, instruction interrupts, fault interrupts, real-time clock interrupts, interrupts caused by certain errors in CPU internal operations, etc. Examples of various types of interrupts are as follows:

[0054] (1) Device interruption: such as data transmission requests from devices such as keyboards and printers;

[0055] (2) Instruction interrupt: An interrupt instruction set to facilitate users to use system resources or debug software. It is caused by an interrupt instruction pre-arranged by the program, such as the interrupt instruction called by the BIOS (Basic Input Output System) and DOS (Disk Operating System) system function.

[0056] (3) Fault interruption: The computer is equipped with an automatic fault detection device. If the power fails, the central processor is required to perform corresponding interrupt processing;

[0057] (4) Real-time clock interrupt: In automatic control systems, timing detection and time control are often encountered. In this case, an external clock circuit can be used for timing. The central processing unit can issue a command to start the clock circuit to start timing. When the timing time is up, the clock circuit will send an interrupt request to the central processing unit, which will be processed by the central processing unit;

[0058] (5) Interrupts caused by certain errors in the internal operations of the central processing unit: such as division errors, operation overflows, setting breakpoints during program debugging, etc.

[0059] An interrupt arbitration mechanism is preset. After receiving each message notification interrupt signal, the platform-level interrupt controller 2 arbitrates each message notification interrupt signal according to the preset interrupt arbitration mechanism to obtain the currently selected message notification interrupt signal. Each message notification interrupt signal contains the interrupt identification information of the target peripheral that sent the message notification interrupt signal. After the platform-level interrupt controller 2 obtains the currently selected message notification interrupt signal through arbitration, it parses the currently selected message notification interrupt signal to obtain the interrupt identification information of the target peripheral that sent the currently selected message notification interrupt signal, thereby knowing which peripheral sent the message notification interrupt signal that is currently arbitrated, and sending an interrupt notification to the RISC-V architecture processor 3.

[0060] Different peripherals may correspond to different interrupt service programs, such as corresponding interrupt service programs can be set for each type of peripheral. The RISC-V architecture processor 3 obtains interrupt identification information according to the interrupt notification, calls the available processor core according to the interrupt identification information to enter the interrupt service program corresponding to the target peripheral for interrupt processing, and can call the hardware thread corresponding to the available processor core according to the interrupt identification information to enter the interrupt service program corresponding to the target peripheral for interrupt processing. By setting a peripheral component interconnection fast bus 1 between the peripheral and the platform-level interrupt controller 2, the received interrupt electrical signals are converted into a unified message notification interrupt signal through the peripheral component interconnection fast bus 1, thereby improving the scalability of the platform-level interrupt controller 2. The converted message notification interrupt signal carries the interrupt identification information of the target peripheral that sends the currently selected message notification interrupt signal, and the processor core does not need to query the interrupt source, which greatly reduces the interrupt response delay.

[0061] It can be seen from the above technical solution that by setting a peripheral component interconnection fast bus between the peripheral and the platform-level interrupt controller, allocating exclusive channel bandwidth to each peripheral through the peripheral component interconnection fast bus, and converting each received interrupt electrical signal into a unified message notification interrupt signal, and sending each message notification interrupt signal to the platform-level interrupt controller, the complex connection settings between each peripheral and the platform-level interrupt controller are avoided, the connection complexity of the platform-level interrupt controller is greatly simplified, and the scalability of the platform-level interrupt controller is improved. In addition, the converted message notification interrupt signal carries the interrupt identification information of the target peripheral that sends the currently selected message notification interrupt signal, and the processor core does not need to query the interrupt source, which greatly reduces the interrupt response delay and improves the interrupt processing efficiency of the RISC-V architecture processor.

[0062] It should be noted that, based on the above embodiment, the embodiment of the present invention also provides corresponding improved solutions. In the subsequent embodiments, the same steps or corresponding steps as those in the above embodiment can be referenced to each other, and the corresponding beneficial effects can also be referenced to each other, which will not be repeated one by one in the following improved embodiments.

[0063] In a specific embodiment of the present invention, the platform-level interrupt controller 2 is also used to obtain the peripheral that sends the first message notification interrupt signal when the first message notification interrupt signal is received before arbitrating each message notification interrupt signal according to a preset interrupt arbitration mechanism; set the target interrupt waiting register corresponding to the peripheral that sends the first message notification interrupt signal to a non-enabled state; wherein the platform-level interrupt controller 2 includes at least one interrupt waiting register, and the interrupt waiting register and each peripheral have a one-to-many relationship.

[0064] At least one interrupt pending register is pre-deployed in the platform-level interrupt controller 2. The interrupt pending register and each peripheral have a one-to-many relationship. For example, the ratio of the interrupt pending register to the peripheral can be set to 1:32. Before the platform-level interrupt controller 2 arbitrates each message notification interrupt signal according to the preset interrupt arbitration mechanism, when the first message notification interrupt signal is received, the peripheral that sends the first message notification interrupt signal is obtained, and the target interrupt pending register corresponding to the peripheral that sends the first message notification interrupt signal is set to a non-enabled state. By setting the target interrupt pending register corresponding to the peripheral that sends the first message notification interrupt signal to a non-enabled state, it is ensured that the message notification interrupt signal received first participates in the interrupt signal arbitration processing first, and only the interrupt pending register corresponding to the peripheral that sends the first message notification interrupt signal is set to a non-enabled state. The other interrupt pending registers in the platform-level interrupt controller 2 are all enabled, so that the peripheral component interconnection fast bus 1 is shielded, thereby preventing subsequent interrupts of the peripherals corresponding to other interrupt pending registers.

[0065] After converting each interrupt electrical signal into a message notification interrupt signal, the peripheral component interconnection fast bus 1 sends each message notification interrupt signal in parallel to the platform-level interrupt controller 2. The platform-level interrupt controller 2 receives the message notification interrupt signal and obtains the first received message notification interrupt signal. The message notification interrupt signal uses a message passing method, and each peripheral can send an independent interrupt message, avoiding the interrupt conflict problem. The message notification interrupt signal supports more interrupt vectors, allowing more peripherals to send interrupt requests at the same time, improving the scalability and flexibility of the system.

[0066] In a specific implementation of the present invention, the platform-level interrupt controller 2 is specifically used to arbitrate the message notification interrupt signal sent by each peripheral corresponding to the target interrupt waiting register according to a preset interrupt arbitration mechanism.

[0067] After the target interrupt waiting register corresponding to the peripheral that sends the first message notification interrupt signal is set to a non-enabled state, each peripheral corresponding to the target interrupt waiting register can send a message notification interrupt signal. The platform-level interrupt controller 2 arbitrates the message notification interrupt signals sent by each peripheral corresponding to the target interrupt waiting register according to a preset interrupt arbitration mechanism, such as being set to arbitrate each message notification interrupt signal received within a preset time period starting from the moment the first message notification interrupt signal is received. By arbitrating only the message notification interrupt signals sent by each peripheral corresponding to the target interrupt waiting register, the arbitration amount of the message notification interrupt signals is greatly reduced, the arbitration efficiency of each message notification interrupt signal is improved, and thus the interrupt processing efficiency is improved.

[0068] In a specific embodiment of the present invention, the platform-level interrupt controller 2 is further used to store the interrupt identification information in the read / complete register after obtaining the interrupt identification information of the target peripheral device that sends the currently selected message notification interrupt signal; wherein the read / complete register is deployed in the platform-level interrupt controller 2;

[0069] The RISC-V architecture processor 3 is specifically used to read interrupt identification information from a read / completion register.

[0070] A read / complete register is pre-deployed in the platform-level interrupt controller 2, and the platform-level interrupt controller 2 is also used to store the interrupt identification information in the read / complete register after obtaining the interrupt identification information of the target peripheral device that sends the currently selected message notification interrupt signal. After receiving the interrupt notification, the RISC-V architecture processor 3 reads the interrupt identification information from the read / complete register. By storing the interrupt identification information in the read / complete register, it is convenient for the RISC-V architecture processor 3 to directly read the interrupt identification information of the target peripheral device that sends the currently selected message notification interrupt signal from the read / complete register after receiving the interrupt notification, thereby reducing the interrupt delay and improving the interrupt response efficiency.

[0071] In a specific embodiment of the present invention, the platform-level interrupt controller 2 is specifically used to determine the target peripheral type to which the target peripheral belongs according to the interrupt identification information; select a target read / complete register from a read / complete register set consisting of read / complete registers corresponding to each processor core of the target peripheral type; store the interrupt identification information in the target read / complete register;

[0072] The RISC-V architecture processor 3 is specifically used to read the interrupt identification information from the target read / completion register; call the target processor core corresponding to the target read / completion register to enter the interrupt service program corresponding to the target peripheral to perform interrupt processing.

[0073] Each processor core corresponds to a read / complete register. The platform-level interrupt controller 2 is specifically used to determine the target peripheral type to which the target peripheral belongs according to the interrupt identification information, and select the target read / complete register from the read / complete register set consisting of the read / complete registers corresponding to each processor core of the target peripheral type. For example, the target read / complete register can be randomly selected from the read / complete register set consisting of the read / complete registers corresponding to each processor core of the target peripheral type. The read / complete register with the smallest current load can also be selected as the target read / complete register according to the current load size of each read / complete register in the read / complete register set. By selecting the target read / complete register from the read / complete register set consisting of the read / complete registers corresponding to each processor core of the target peripheral type to which the target peripheral belongs, the selection process of the target read / complete register is simplified, and the accuracy of the selected target read / complete register is improved.

[0074] In a specific implementation of the present invention, the platform-level interrupt controller 2 is specifically used to select a target read / complete register from a read / complete register set consisting of read / complete registers corresponding to each processor core of the target peripheral type based on a load balancing principle.

[0075] The platform-level interrupt controller 2 is specifically used to select a target read / complete register from a read / complete register set consisting of read / complete registers corresponding to each processor core of the target peripheral type based on a load balancing principle. By selecting the target read / complete register based on the load balancing principle, the utilization rate of each processor core in the RISC-V architecture processor 3 is improved, and the system performance is improved.

[0076] In a specific embodiment of the present invention, the RISC-V architecture processor 3 is also used to write the interrupt identification information back to the target read / completion register after the interrupt processing is completed.

[0077] The RISC-V architecture processor 3 is also used to write the interrupt identification information back to the target read / complete register after the interrupt processing is completed. After the interrupt processing is completed, the RISC-V architecture processor 3 writes the interrupt identification information back to the target read / complete register, so that the platform-level interrupt controller 2 can promptly perceive the currently selected message to inform that the interrupt signal has been processed, so that the peripheral component interconnection fast bus 1 is unshielded, and then the preparation work for processing subsequent interrupt signals is carried out in time, thereby improving the efficiency of interrupt processing.

[0078] In a specific embodiment of the present invention, the platform-level interrupt controller 2 is also used to modify the state of the peripheral component interconnect fast bus 1 when a write-back action of the RISC-V architecture processor 3 to the target read / completion register is detected.

[0079] The write-back action mark of the read / complete register is pre-set to indicate that the currently selected message notification interrupt signal has been processed. The platform-level interrupt controller 2 is also used to, when detecting the write-back action of the RISC-V architecture processor 3 to the target read / complete register, indicate that the currently selected message notification interrupt signal has been processed, and modify the state of the peripheral component interconnection fast bus 1, so as to facilitate the reception and processing of subsequent interrupt signals. By setting the write-back action mark of the read / complete register to indicate that the currently selected message notification interrupt signal has been processed, the efficiency of identifying that the interrupt signal has been processed is improved, thereby improving the efficiency of interrupt processing.

[0080] In a specific implementation of the present invention, the platform-level interrupt controller 2 is specifically used to modify the state of the peripheral component interconnect fast bus 1 by setting the target interrupt wait register to an enabled state.

[0081] The platform-level interrupt controller 2 is specifically used to modify the state of the peripheral component interconnection fast bus 1 by setting the target interrupt waiting register to the enabled state when the RISC-V architecture processor 3 detects the write-back action to the target read / completion register. By setting the target interrupt waiting register to the enabled state, all interrupt waiting registers are enabled, so that when the platform-level interrupt controller 2 receives that all interrupt waiting registers are enabled, it can be said that the currently selected message notifies that the interrupt signal has been processed and other peripherals have been allowed to send interrupt signals, which simplifies the recognition process of the interrupt signal being processed and improves the recognition efficiency of the interrupt signal being processed.

[0082] In a specific implementation of the present invention, the platform-level interrupt controller 2 is specifically configured to arbitrate each message notification interrupt signal according to an interrupt priority arbitration mechanism set based on an urgency principle.

[0083] The platform-level interrupt controller 2 is specifically used to arbitrate each message notification interrupt signal according to an interrupt priority arbitration mechanism set based on the urgency principle. Suppose a computer system is processing a user's data input task, and suddenly two hardware interrupts occur: a hard disk failure and a network connection interruption. According to the interrupt priority principle, the system may determine that the hard disk failure is more urgent and important, so it gives priority to the hard disk failure interruption and temporarily puts the network connection interruption on hold. After the hard disk failure is handled, the system handles the network connection interruption. By arbitrating each message notification interrupt signal through an interrupt priority arbitration mechanism set based on the urgency principle, the system can ensure that the most critical problems are solved in the shortest time, thereby ensuring the security and integrity of user data.

[0084] In a specific implementation of the present invention, the platform-level interrupt controller 2 is specifically configured to arbitrate each message notification interrupt signal according to an interrupt priority arbitration mechanism set based on a response time principle.

[0085] The platform-level interrupt controller 2 is specifically used to arbitrate each message notification interrupt signal according to the interrupt priority arbitration mechanism set based on the response time principle. By arbitrating each message notification interrupt signal according to the interrupt priority arbitration mechanism set based on the response time principle, it is ensured that the message notification interrupt signal with high response time requirements is processed first, thereby improving the effectiveness of the interrupt response.

[0086] In a specific implementation of the present invention, the platform-level interrupt controller 2 is specifically configured to arbitrate each message notification interrupt signal according to an interrupt priority arbitration mechanism set based on a dependency principle.

[0087] The platform-level interrupt controller 2 is specifically used to arbitrate each message notification interrupt signal according to the interrupt priority arbitration mechanism set based on the dependency principle. By arbitrating each message notification interrupt signal according to the interrupt priority arbitration mechanism set based on the dependency principle, it is ensured that the dependent message notification interrupt signal is processed first, thereby improving the interrupt processing efficiency.

[0088] See also Figure 3 , Figure 3 It is a timing diagram of interrupt processing in an embodiment of the present invention. When an external interrupt occurs, if the peripheral component interconnection fast bus 1 is not shielded, the interrupt source initiates an interrupt request through the peripheral component interconnection fast bus 1. According to the interrupt arbitration mechanism, if the platform-level interrupt controller 2 selects the interrupt source after arbitration, the platform-level interrupt controller 2 initiates an interrupt notification to the RISC-V architecture processor 3. When the RISC-V architecture processor 3 receives the interrupt notification, it responds to the interrupt, and the platform-level interrupt controller 2 returns the interrupt identification information of the interrupt source, and clears the interrupt waiting register. After the RISC-V architecture processor 3 receives the interrupt identification information, it knows the specific external interrupt source to which it needs to respond through this interrupt identification information, and then enters the interrupt service program corresponding to the interrupt source for processing. After the interrupt processing is completely completed, the RISC-V architecture processor 3 initiates an interrupt completion write operation to the platform-level interrupt controller 2, and writes the interrupt identification information to be completed. At the same time, the platform-level interrupt controller 2 unshields the peripheral component interconnection fast bus 1, allowing other peripherals to send interrupt requests.

[0089] Corresponding to the above system embodiment, the present invention further provides an interrupt processing method. The interrupt processing method described below and the interrupt processing system described above can be referred to in correspondence with each other.

[0090] See also Figure 4 , Figure 4 The present invention is a flowchart of an interrupt processing method according to an embodiment of the present invention. The method may include the following steps:

[0091] S401: receiving each message notification interrupt signal sent by the peripheral component interconnect fast bus.

[0092] Among them, each message notification interrupt signal is obtained by converting the interrupt electrical signal sent by each peripheral device respectively through the peripheral component interconnection fast bus.

[0093] S402: Arbitrate each message notification interrupt signal according to a preset interrupt arbitration mechanism to obtain a currently selected message notification interrupt signal.

[0094] S403: Analyze the currently selected message notification interrupt signal to obtain interrupt identification information of the target peripheral device that sends the currently selected message notification interrupt signal.

[0095] S404: Send an interrupt notification to the RISC-V architecture processor, so that the RISC-V architecture processor obtains interrupt identification information according to the interrupt notification, and calls the available processor core to enter the interrupt service program corresponding to the target peripheral to perform interrupt processing according to the interrupt identification information.

[0096] It can be seen from the above technical solution that by setting a peripheral component interconnection fast bus between the peripheral and the platform-level interrupt controller, allocating exclusive channel bandwidth to each peripheral through the peripheral component interconnection fast bus, and converting each received interrupt electrical signal into a unified message notification interrupt signal, and sending each message notification interrupt signal to the platform-level interrupt controller, the complex connection settings between each peripheral and the platform-level interrupt controller are avoided, the connection complexity of the platform-level interrupt controller is greatly simplified, and the scalability of the platform-level interrupt controller is improved. In addition, the converted message notification interrupt signal carries the interrupt identification information of the target peripheral that sends the currently selected message notification interrupt signal, and the processor core does not need to query the interrupt source, which greatly reduces the interrupt response delay and improves the interrupt processing efficiency of the RISC-V architecture processor.

[0097] In a specific implementation of the present invention, before arbitrating each message notification interrupt signal according to a preset interrupt arbitration mechanism, the method may further include the following steps:

[0098] Step 1: when the first message notification interrupt signal is received, obtain the peripheral that sends the first message notification interrupt signal;

[0099] Step 2: Set the target interrupt waiting register corresponding to the peripheral that sends the first message to notify the interrupt signal to a non-enabled state;

[0100] The platform-level interrupt controller includes at least one interrupt waiting register, and the interrupt waiting register and each peripheral are in a one-to-many relationship.

[0101] In a specific implementation of the present invention, arbitrating each message notification interrupt signal according to a preset interrupt arbitration mechanism may include the following steps:

[0102] The message notification interrupt signal sent by each peripheral corresponding to the target interrupt waiting register is arbitrated according to the preset interrupt arbitration mechanism.

[0103] In a specific implementation of the present invention, after obtaining the interrupt identification information of the target peripheral device that sends the currently selected message notification interrupt signal, the method may further include the following steps:

[0104] Storing the interrupt identification information in the read / complete register so that the RISC-V architecture processor reads the interrupt identification information from the read / complete register;

[0105] Among them, the read / completion register is deployed in the platform-level interrupt controller.

[0106] In a specific implementation of the present invention, storing the interrupt identification information in the read / complete register may include the following steps:

[0107] Step 1: Determine the target peripheral type to which the target peripheral belongs according to the interrupt identification information;

[0108] Step 2: Select a target read / complete register from a read / complete register set consisting of read / complete registers corresponding to each processor core of the target peripheral type;

[0109] Step 3: Store the interrupt identification information in the target read / completion register so that the RISC-V architecture processor reads the interrupt identification information from the target read / completion register and calls the target processor core corresponding to the target read / completion register to enter the interrupt service program corresponding to the target peripheral for interrupt processing.

[0110] In a specific implementation of the present invention, selecting a target read / complete register from a read / complete register set consisting of read / complete registers corresponding to each processor core of the target peripheral type may include the following steps:

[0111] Based on the load balancing principle, a target read / complete register is selected from a read / complete register set consisting of read / complete registers corresponding to each processor core of the target peripheral type.

[0112] In a specific embodiment of the present invention, the method may further include the following steps:

[0113] When a write-back action of a RISC-V architecture processor to a target read / completion register is detected, the state of the peripheral component interconnect fast bus is modified.

[0114] In a specific implementation of the present invention, modifying the state of the peripheral component interconnect fast bus may include the following steps:

[0115] The state of the Peripheral Component Interconnect Express bus is modified by setting the target interrupt wait register to an enabled state.

[0116] In a specific implementation of the present invention, arbitrating each message notification interrupt signal according to a preset interrupt arbitration mechanism may include the following steps:

[0117] Each message notification interrupt signal is arbitrated according to an interrupt priority arbitration mechanism set based on the urgency principle.

[0118] In a specific implementation of the present invention, arbitrating each message notification interrupt signal according to a preset interrupt arbitration mechanism may include the following steps:

[0119] Each message notification interrupt signal is arbitrated according to an interrupt priority arbitration mechanism set based on a response time principle.

[0120] In a specific implementation of the present invention, arbitrating each message notification interrupt signal according to a preset interrupt arbitration mechanism may include the following steps:

[0121] Each message notification interrupt signal is arbitrated according to an interrupt priority arbitration mechanism set based on the dependency principle.

[0122] Corresponding to the above system embodiment, the present invention further provides an interrupt processing device. The interrupt processing device described below and the interrupt processing system described above can be referred to each other.

[0123] See also Figure 5 , Figure 5 This is a structural block diagram of an interrupt processing device in an embodiment of the present invention, and the device may include:

[0124] The interrupt signal receiving module 51 is used to receive each message notification interrupt signal sent by the peripheral component interconnection fast bus; wherein each message notification interrupt signal is obtained by converting the interrupt electrical signal sent by each peripheral by the peripheral component interconnection fast bus;

[0125] An interrupt arbitration module 52, used to arbitrate each message notification interrupt signal according to a preset interrupt arbitration mechanism to obtain a currently selected message notification interrupt signal;

[0126] An interrupt identification information obtaining module 53 is used to parse the currently selected message notification interrupt signal to obtain the interrupt identification information of the target peripheral device that sends the currently selected message notification interrupt signal;

[0127] The interrupt processing module 54 is used to send an interrupt notification to the RISC-V architecture processor so that the RISC-V architecture processor obtains interrupt identification information according to the interrupt notification, and calls the available processor core to enter the interrupt service program corresponding to the target peripheral to perform interrupt processing according to the interrupt identification information.

[0128] It can be seen from the above technical solution that by setting a peripheral component interconnection fast bus between the peripheral and the platform-level interrupt controller, allocating exclusive channel bandwidth to each peripheral through the peripheral component interconnection fast bus, and converting each received interrupt electrical signal into a unified message notification interrupt signal, and sending each message notification interrupt signal to the platform-level interrupt controller, the complex connection settings between each peripheral and the platform-level interrupt controller are avoided, the connection complexity of the platform-level interrupt controller is greatly simplified, and the scalability of the platform-level interrupt controller is improved. In addition, the converted message notification interrupt signal carries the interrupt identification information of the target peripheral that sends the currently selected message notification interrupt signal, and the processor core does not need to query the interrupt source, which greatly reduces the interrupt response delay and improves the interrupt processing efficiency of the RISC-V architecture processor.

[0129] In a specific embodiment of the present invention, the device may further include:

[0130] A peripheral acquisition module, used for acquiring the peripheral that sends the first message notification interrupt signal when the first message notification interrupt signal is received before arbitrating each message notification interrupt signal according to a preset interrupt arbitration mechanism;

[0131] An interrupt waiting register state setting module is used to set the target interrupt waiting register corresponding to the peripheral device that sends the first message to notify the interrupt signal to a non-enabled state;

[0132] The platform-level interrupt controller includes at least one interrupt waiting register, and the interrupt waiting register and each peripheral are in a one-to-many relationship.

[0133] In a specific implementation of the present invention, the interrupt arbitration module 52 is specifically a module that arbitrates the message notification interrupt signal sent by each peripheral corresponding to the target interrupt waiting register according to a preset interrupt arbitration mechanism.

[0134] In a specific embodiment of the present invention, the device may further include:

[0135] An interrupt identification storage module is used to store the interrupt identification information in a read / complete register after obtaining the interrupt identification information of the target peripheral device that sends the currently selected message notification interrupt signal, so that the RISC-V architecture processor reads the interrupt identification information from the read / complete register;

[0136] Among them, the read / completion register is deployed in the platform-level interrupt controller.

[0137] In a specific implementation of the present invention, the interruption identification storage module includes:

[0138] The peripheral type determination submodule is used to determine the target peripheral type to which the target peripheral belongs according to the interrupt identification information;

[0139] A register selection submodule, used to select a target read / complete register from a read / complete register set consisting of read / complete registers corresponding to each processor core of the target peripheral type;

[0140] The interrupt identification storage submodule is used to store the interrupt identification information in the target read / completion register so that the RISC-V architecture processor reads the interrupt identification information from the target read / completion register and calls the target processor core corresponding to the target read / completion register to enter the interrupt service program corresponding to the target peripheral for interrupt processing.

[0141] In a specific embodiment of the present invention, the register selection submodule is specifically a module that selects a target read / completion register from a read / completion register set consisting of read / completion registers corresponding to each processor core of the target peripheral type based on the load balancing principle.

[0142] In a specific embodiment of the present invention, the device may further include:

[0143] The state modification module is used to modify the state of the peripheral component interconnect fast bus when detecting the RISC-V architecture processor's write-back action to the target read / completion register.

[0144] In a specific implementation of the present invention, the state modification module is specifically a module that modifies the state of the peripheral component interconnect fast bus by setting the target interrupt wait register to an enabled state.

[0145] In a specific implementation of the present invention, the interrupt arbitration module 52 is specifically a module for arbitrating each message notification interrupt signal according to an interrupt priority arbitration mechanism set based on the urgency principle.

[0146] In a specific implementation of the present invention, the interrupt arbitration module 52 is specifically a module for arbitrating each message notification interrupt signal according to an interrupt priority arbitration mechanism set based on a response time principle.

[0147] In a specific implementation of the present invention, the interrupt arbitration module 52 is specifically a module for arbitrating each message notification interrupt signal according to an interrupt priority arbitration mechanism set based on the dependency principle.

[0148] Corresponding to the above method embodiment, the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the following steps can be implemented:

[0149] Receive each message notification interrupt signal sent by the peripheral component interconnection fast bus; wherein each message notification interrupt signal is obtained by converting the interrupt electrical signal sent by each peripheral by the peripheral component interconnection fast bus; arbitrate each message notification interrupt signal according to a preset interrupt arbitration mechanism to obtain the currently selected message notification interrupt signal; parse the currently selected message notification interrupt signal to obtain the interrupt identification information of the target peripheral that sent the currently selected message notification interrupt signal; send an interrupt notification to the RISC-V architecture processor, so that the RISC-V architecture processor obtains the interrupt identification information according to the interrupt notification, and calls the available processor core according to the interrupt identification information to enter the interrupt service program corresponding to the target peripheral to perform interrupt processing.

[0150] The computer-readable storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0151] For an introduction to the computer-readable storage medium provided by the present invention, please refer to the above method embodiment, and the present invention will not be elaborated here.

[0152] Corresponding to the above method embodiment, the present invention also provides a computer program product, including a computer program, which implements the steps of the above interrupt processing method when executed by a processor.

[0153] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the devices, equipment and computer-readable storage media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0154] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the technical solution and core ideas of the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. An interrupt processing system, characterized in that: include: A peripheral component interconnection fast bus for receiving interrupt electrical signals sent by each peripheral; Convert each interrupt electrical signal into a message notification interrupt signal, and send each message notification interrupt signal to a platform-level interrupt controller; The platform-level interrupt controller is used to arbitrate each message notification interrupt signal according to a preset interrupt arbitration mechanism to obtain a currently selected message notification interrupt signal; Parsing the currently selected message notification interrupt signal to obtain interrupt identification information of the target peripheral device that sends the currently selected message notification interrupt signal; sending an interrupt notification to the RISC-V architecture processor; The RISC-V architecture processor is used to obtain the interrupt identification information according to the interrupt notification; and call the available processor core to enter the interrupt service program corresponding to the target peripheral device to perform interrupt processing according to the interrupt identification information; The platform-level interrupt controller is further used to determine the target peripheral type to which the target peripheral belongs according to the interrupt identification information after obtaining the interrupt identification information of the target peripheral that sends the currently selected message notification interrupt signal; and select a target read / complete register from a read / complete register set consisting of read / complete registers corresponding to each processor core of the target peripheral type; Storing the interrupt identification information in the target read / complete register; wherein the read / complete register is deployed in the platform-level interrupt controller; The RISC-V architecture processor is specifically used to read the interrupt identification information from the target read / completion register; call the target processor core corresponding to the target read / completion register to enter the interrupt service program corresponding to the target peripheral to perform interrupt processing.

2. The interrupt processing system according to claim 1, characterized in that: The platform-level interrupt controller is further configured to, before arbitrating each message notification interrupt signal according to a preset interrupt arbitration mechanism, obtain the peripheral device that sends the first message notification interrupt signal when the first message notification interrupt signal is received; The target interrupt waiting register corresponding to the peripheral device that sends the first message notifying the interrupt signal is set to a non-enabled state; wherein the platform-level interrupt controller includes at least one interrupt waiting register, and the interrupt waiting register and each peripheral device have a one-to-many relationship.

3. The interrupt processing system according to claim 2, characterized in that: The platform-level interrupt controller is specifically used to arbitrate the message notification interrupt signal sent by each peripheral corresponding to the target interrupt waiting register according to the preset interrupt arbitration mechanism.

4. The interrupt processing system according to claim 1, characterized in that: The platform-level interrupt controller is specifically used to select a target read / complete register from a read / complete register set consisting of read / complete registers corresponding to each processor core of the target peripheral type based on a load balancing principle.

5. The interrupt processing system according to claim 2 or 3, characterized in that: The RISC-V architecture processor is also used to write the interrupt identification information back to the target read / completion register after the interrupt processing is completed.

6. The interrupt processing system according to claim 5, characterized in that: The platform-level interrupt controller is also used to modify the state of the peripheral component interconnect fast bus when detecting the RISC-V architecture processor's write-back action to the target read / completion register.

7. The interrupt processing system according to claim 6, characterized in that: The platform-level interrupt controller is specifically used to modify the state of the peripheral component interconnect fast bus by setting the target interrupt wait register to an enabled state.

8. The interrupt processing system according to claim 1, characterized in that: The platform-level interrupt controller is specifically used to arbitrate each message notification interrupt signal according to an interrupt priority arbitration mechanism set based on the urgency principle.

9. The interrupt processing system according to claim 1, characterized in that: The platform-level interrupt controller is specifically used to arbitrate each message notification interrupt signal according to an interrupt priority arbitration mechanism set based on a response time principle.

10. The interrupt processing system according to claim 1, characterized in that: The platform-level interrupt controller is specifically used to arbitrate each message notification interrupt signal according to an interrupt priority arbitration mechanism set based on a dependency principle.

11. An interrupt processing method, characterized in that: Applicable to platform-level interrupt controllers, including: Receiving each message notification interrupt signal sent by the peripheral component interconnection fast bus; wherein each message notification interrupt signal is obtained by converting the interrupt electrical signal sent by each peripheral by the peripheral component interconnection fast bus; Arbitrate each message notification interrupt signal according to a preset interrupt arbitration mechanism to obtain a currently selected message notification interrupt signal; Parsing the currently selected message notification interrupt signal to obtain interrupt identification information of the target peripheral device that sends the currently selected message notification interrupt signal; Determine the target peripheral device type to which the target peripheral device belongs according to the interrupt identification information; Selecting a target read / complete register from a read / complete register set consisting of read / complete registers corresponding to each processor core of the target peripheral type; wherein the read / complete register is deployed in the platform-level interrupt controller; Store the interrupt identification information into the target read / completion register; An interrupt notification is sent to a RISC-V architecture processor so that the RISC-V architecture processor reads interrupt identification information from a target read / completion register according to the interrupt notification, and calls a target processor core corresponding to the target read / completion register to enter an interrupt service program corresponding to a target peripheral for interrupt processing.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, the steps of the interrupt processing method according to claim 11 are implemented.

13. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the steps of the interrupt handling method according to claim 11 are implemented.

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