Multi-tag anti-collision mechanism NFC reader / writer

Abstract

The present invention provides a multi-tag anti-collision mechanism NFC reader / writer, comprising: an NFC reader / writer module, which is integrated with a tag anti-collision algorithm, and when the number of NFC tags is 1, a single NFC tag information is identified; when the number of NFC tags is greater than 1, the tag anti-collision identification algorithm is turned on and the identification order of the NFC tags is set, and then each NFC tag information is read one by one according to the identification order; an NFC antenna impedance matching module, which accepts the control of the NFC reader / writer module and automatically adapts the difference between the input impedance of the NFC antenna and the output impedance of the NFC reader / writer module. The multi-tag anti-collision mechanism NFC reader / writer provided by the present invention can orderly poll the information of multiple tags when reading multiple NFC tags through the tag anti-collision algorithm.

Description

Technical Field

[0001] The present invention relates to the technical field of NFC readers and writers, and in particular to an NFC reader and writer with a multi-tag anti-collision mechanism. Background Art

[0002] At present, Near Field Communication (NFC) is a technology that is increasingly widely used. Devices using NFC technology (such as mobile phones, home access control, and card devices) can communicate data when they are close to each other. It is a combination of contactless radio frequency identification (RFID) and interconnection technology. By integrating a card reader chip on a single chip and supplemented by an external controller, the functions of reader / writer (PICC), card emulation (Card Emulator), and AP2P data transmission (point-to-point transmission of music, video, photos and other file formats through a series of smart devices) can be realized. The above functions can realize applications such as mobile payment, electronic ticketing, access control, identity recognition, and anti-counterfeiting.

[0003] However, most NFC readers on the market can only read and write one NFC tag at a time. If you want to read and write multiple tags, the tags will conflict with each other and you will not be able to read or write any of the tags.

[0004] Therefore, it is necessary to provide a multi-tag anti-collision mechanism NFC reader / writer to solve the above technical problems. Summary of the invention

[0005] The main technical problem solved by the present invention is to provide an NFC reader / writer with a multi-tag anti-collision mechanism, which automatically sorts multiple tags through an anti-collision algorithm and polls NFC tag information.

[0006] In order to solve the above technical problems, a technical solution adopted by the present invention is to provide a multi-tag anti-collision mechanism NFC reader / writer, comprising:

[0007] The NFC reader / writer module integrates a tag anti-collision algorithm, which is used to first scan the number of NFC tags. When the number of NFC tags is 1, the single NFC tag information is identified. When the number of NFC tags is greater than 1, the tag anti-collision identification algorithm is turned on and the identification order of NFC tags is set, and then the information of each NFC tag is read one by one according to the identification order.

[0008] A power supply module, electrically connected to the NFC reader / writer module, for outputting 3.3V and 5V DC power to the NFC reader / writer module;

[0009] The microcontroller module is electrically connected to the NFC reader / writer module, and is used to encapsulate the tag identification and communication logic into a predetermined communication protocol, and communicate with the NFC reader / writer module and the host computer through a serial bus interface;

[0010] NFC antenna module, used to identify NFC tag information;

[0011] The NFC antenna impedance matching module is electrically connected to the NFC reader / writer module and the NFC antenna module, and is controlled by the NFC reader / writer module to automatically adapt to the difference between the input impedance of the NFC antenna and the output impedance of the NFC reader / writer module.

[0012] In one embodiment, the communication protocol comprises the ISO / IEC 15693 communication protocol.

[0013] In one embodiment, the multi-tag anti-collision mechanism NFC reader / writer is suitable for identifying NXP iCode series and / or STST25 series tags.

[0014] In one embodiment, the serial bus interface is an asynchronous serial communication interface.

[0015] In one embodiment, the microcontroller module includes a first chip with a model number of N32G031F8S7, and the NFC reader / writer module includes a second chip with a model number of ST25R3911B.

[0016] In one embodiment, the power supply module includes a 12V to 5V DC power unit and a 5V to 3.3V DC power unit.

[0017] In one embodiment, the 8th pin of the second chip is connected to the 5V DC output terminal of the power supply module through the first inductor and to the 3.3V DC output terminal of the power supply module through the second inductor, the 1st pin is connected to the 3.3V DC output terminal of the power supply module, the 4th pin and the 5th pin are connected to the second crystal oscillator unit, the 2nd pin and the 25th pin are respectively connected to resistors in series and then grounded through capacitors, the 28th pin is unloaded, the 32nd pin is connected to the 7th pin of the first chip, the 29th pin is connected to the 10th pin of the first chip through a resistor, the 30th pin is connected to the 13th pin of the first chip through a resistor, the 31st pin is connected to the 11th pin of the first chip, the 27th pin is connected to the 9th pin of the first chip, the 10th pin, the 11th pin, the 13th-20th pin, the 22nd pin and the 23rd pin are connected to the NFC antenna impedance matching module; the 3rd pin, the 7th pin, the 9th pin, the 24th pin and the ground wire are respectively connected with filter capacitors, and the 6th pin, the 12th pin, the 21st pin, the 26th pin and the 33rd pin are respectively grounded.

[0018] In one embodiment, pin 1 of the first chip is grounded through a resistor, pins 2 and 3 are connected to the first crystal oscillator unit, pins 4 and 17-20 are connected to the asynchronous serial communication interface, pins 5 and 16 are connected to the 3.3V DC output end of the power supply module, pins 6, 8 and 14 are connected to the LED display unit, and the LED display unit is connected to the 3.3V DC output end, pins 7, 9 and 11 are respectively connected to pins 32, 27 and 31 of the second chip, pin 10 is grounded through a capacitor and connected to pin 29 of the second chip through a resistor, pin 12 is unloaded, pin 13 is connected to pin 30 of the second chip through a resistor, pin 15 is grounded, and the asynchronous serial communication interface is connected to the 3.3V DC output end and the 5V DC output end of the power supply module.

[0019] In one embodiment, the 5V to 3.3V DC power unit includes a reset terminal for resetting the second chip.

[0020] The beneficial effects of the present invention are:

[0021] (1) Through the anti-collision algorithm, multiple tags are automatically sorted and NFC tag information is polled, solving the current problem of being unable to read due to conflicts between multiple tags;

[0022] (2) The technical solution of the present invention has high performance. With the software design, it can adapt to the impact of different numbers of tags on the antenna impedance and dynamically adjust the impedance of the matching circuit to obtain extremely high reading and writing performance of multiple NFC tags at a low cost.

[0023] (3) The microcontroller module is based on the first chip model N32G031F8S7. It encapsulates the processes with complex logical operations such as various electronic tag identification, authentication, and reading and writing storage areas in electronic tags into a simple communication protocol. It is connected to the user's host computer through a serial bus (UART), allowing the user to quickly add the NFC recognition function to the second chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a circuit structure block diagram of a first preferred embodiment of a multi-tag anti-collision mechanism NFC reader / writer of the present invention;

[0025] Figure 2 It is a schematic diagram of the circuit structure of a 12V to 5V DC power unit of the power supply module of the present invention;

[0026] Figure 3 It is a schematic diagram of the circuit structure of a 5V to 3.3V DC power unit of the power supply module of the present invention;

[0027] Figure 4-aIt is a schematic diagram of the circuit structure of the second chip U2 of the NFC reader / writer module and some of its peripheral electronic components;

[0028] Figure 4-b It is a schematic diagram of the circuit structure of the second crystal oscillator unit Y2 of the NFC reading and writing module;

[0029] Figure 4-c It is a schematic diagram of the circuit structure of the driving voltage switching unit of the NFC reader / writer module;

[0030] Figure 5 It is a schematic diagram of the circuit structure of the NFC antenna impedance matching module and the NFC antenna module;

[0031] Figure 6 It is a schematic diagram of a partial circuit structure of the first chip U1 of the microcontroller module and its peripheral electronic devices;

[0032] Figure 7-a It is a schematic diagram of the circuit structure of the LED display unit of the microcontroller module;

[0033] Figure 7-b It is a circuit structure diagram of the asynchronous serial communication interface of the microcontroller module. DETAILED DESCRIPTION

[0034] The technical solution of the present invention is described in detail below with reference to the accompanying drawings.

[0035] See also Figure 1 As shown, the multi-tag anti-collision mechanism NFC reader / writer of this embodiment includes:

[0036] The NFC reader / writer module integrates a tag anti-collision algorithm, which is used to first scan the number of NFC tags. When the number of NFC tags is 1, the single NFC tag information is identified. When the number of NFC tags is greater than 1, the tag anti-collision identification algorithm is turned on and the identification order of NFC tags is set, and then the information of each NFC tag is read one by one according to the identification order.

[0037] The power supply module is electrically connected to the NFC reader / writer module and is used to output 3.3V and 5V DC power to the NFC reader / writer module, and provide 5V and 3.3V DC power with low enough noise for use by various circuits;

[0038] A microcontroller module is electrically connected to the NFC reader / writer module, and is used to encapsulate the tag identification and communication logic into a predetermined communication protocol, and communicate with the NFC reader / writer module and a host computer through a serial bus interface, and the host computer is, for example, a computer host;

[0039] NFC antenna module, used to identify NFC tag information, is designed according to the actual product appearance and meets some prerequisites during the design, such as inductance;

[0040] The NFC antenna impedance matching module is electrically connected to the NFC reader / writer module and the NFC antenna module. It accepts the control of the NFC reader / writer module and automatically adapts the difference between the input impedance of the NFC antenna and the output impedance of the NFC reader / writer module to maximize the RF energy transmission. For example, by controlling Figure 5 The on / off of one or more circuits in which the capacitors C34-C41 are located changes the output impedance of the matching circuit, adapts to the impedance changes of the external antenna in real time, and maximizes the efficiency of RF energy transmission.

[0041] Therefore, the present invention has the ability to identify the number of NFC tags; when the number of identified NFC tags is greater than one, the NFC tag anti-collision identification function will be enabled, and the corresponding NFC tag will be found and read and written in a similar way to one-by-one identification; if the number of identified NFC tags is one, there is no need to enable the NFC tag anti-collision function, and the NFC reader / writer module can directly read and write the NFC tag.

[0042] The communication protocol used in the present invention includes the ISO / IEC 15693 communication protocol capable of reading devices operating in the 13.56 MHz frequency band. Further, the multi-tag anti-collision mechanism NFC reader is suitable for identifying NXP iCode series and / or ST ST25 series tags.

[0043] In one embodiment, the serial bus interface is an asynchronous serial communication interface, so that the technical product of the present invention has a simple structure, is cheap, has low cost, and can effectively communicate with the upper host.

[0044] In a preferred embodiment, the microcontroller module includes a first chip U1 of model N32G031F8S7, and the NFC reader / writer module includes a second chip U2 of model ST25R3911B. The core of the first chip U1 is 32bit ARM Cortex-M0, with a main frequency of 48MHz, and the clock frequency of interaction with the second chip U2 can reach 10MHz, which matches the reader / writer chip (second chip U2). The second chip U2 is a core component for communicating with NFC electronic tags, and complies with the communication specifications of IEC14443-A / B and IEC15693. The RF output power can reach 1.4W. For the working scenario of multiple NFC tags, it has automatic antenna tuning (AAT) to optimize the antenna impedance matching under different load conditions.

[0045] In the present invention, the power supply module includes a 12V to 5V DC unit, such as Figure 2 The power supply module further includes a 5V to 3.3V DC power unit, such as Figure 3 As shown. This meets the working requirements of the NFC reading and writing module and the microcontroller module.

[0046] The circuit structure diagram of the first preferred embodiment of the present invention is shown in FIG. Figure 4-a , Figure 4-b , Figure 4-c , Figure 5 , Figure 6 , Figure 7-a , Figure 7-b shown.

[0047] like Figure 4-a , Figure 4-b , Figure 4-c As shown, the 8th pin of the second chip U2 is connected to the 5V DC output terminal of the power supply module through the first inductor FB1, and is connected to the 3.3V DC output terminal of the power supply module through the second inductor FB2. The 1st pin is connected to the 3.3V DC output terminal of the power supply module, and the 4th and 5th pins are connected to the second crystal oscillator unit Y2 ( Figure 4-b As shown), pin 2 and pin 25 are connected in series with resistors and then grounded through capacitors, pin 28 is unloaded, pin 32 is connected to pin 7 of the first chip, pin 29 is connected to pin 10 of the first chip U1 through a resistor, pin 30 is connected to pin 13 of the first chip U1 through a resistor, pin 31 is connected to pin 11 of the first chip U1, pin 27 is connected to pin 9 of the first chip U1, pin 10, pin 11, pins 13-20, pin 22 and pin 23 are connected to the NFC antenna impedance matching module ( Figure 5 As shown); filter capacitors are connected between pins 3, 7, 9, 24 and the ground wire, and pins 6, 12, 21, 26 and 33 are grounded respectively.

[0048] In this embodiment, the second chip U2 is used as the core circuit of the NFC reader / writer module. The clock source of the second crystal oscillator unit Y2 required for its operation is preferably provided by a 27.12MHz crystal oscillator, and the internal logic circuit controls the transmission and reception of NFC signals. In specific applications, the NFC signal transmission circuit has the characteristics of a basic dynamic power control interval oscillator, and the receiving circuit has the characteristics of a basic adaptive impedance requirement, which can achieve excellent RF transceiver performance. Its transmission output and receiving input are both in differential mode and are connected to the matching circuit of the NFC antenna module.

[0049] like Figure 5 As shown, the NFC antenna impedance matching module and the NFC antenna module, inductors L1, L2, capacitors C24 and C25 form an EMC filter circuit, which is actually a first-order low-pass filter with a cut-off frequency of about 19MHz to prevent the second chip U2's RF output high-order harmonics from leaking to the outside. Capacitors C26-C31 form an antenna impedance matching circuit, and the actual parameters must be adjusted according to the antenna target impedance. Capacitors C22, C23, C32, and C33 form a capacitor voltage divider circuit to obtain the received signal and send it to the receiving circuit of the second chip U2 for receiving signal processing.

[0050] like Figure 6 As shown, the first pin of the first chip U1 is grounded through a resistor, the second and third pins are connected to the first crystal oscillator unit Y1, and the fourth and 17-20 pins are connected to the asynchronous serial communication interface ( Figure 7-b As shown in the figure), the 5th and 16th pins are connected to the 3.3V DC output terminal of the power supply module, and the 6th, 8th and 14th pins are connected to the LED display unit ( Figure 7-b As shown), and the LED display unit is connected to the 3.3V DC output terminal, the 7th, 9th and 11th pins are respectively connected to the 32nd, 27th and 31st pins of the second chip U2, the 10th pin is grounded through a capacitor and connected to the 29th pin of the second chip through a resistor, the 12th pin is unloaded, the 13th pin is connected to the 30th pin of the second chip through a resistor, the 15th pin is grounded, and the asynchronous serial communication interface ( Figure 7-b ) are connected to the 3.3V DC output terminal and 5V DC output terminal of the power supply module.

[0051] Further Figure 6 As shown, the second crystal oscillator unit Y2 provides an accurate clock source for the second chip U2, and the SPI bus is connected to the second chip U2.

[0052] In one embodiment, if Figure 3 As shown, the 5V to 3.3V DC power unit includes a reset terminal for resetting the second chip U2.

[0053] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure made using the contents of the present invention's specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A multi-tag anti-collision mechanism NFC reader / writer, characterized in that: include: The NFC reader / writer module integrates a tag anti-collision algorithm, which is used to first scan the number of NFC tags. When the number of NFC tags is 1, the single NFC tag information is identified. When the number of NFC tags is greater than 1, the tag anti-collision identification algorithm is turned on and the identification order of NFC tags is set, and then the information of each NFC tag is read one by one according to the identification order. A power supply module, electrically connected to the NFC reader / writer module, for outputting 3.3V and 5V DC power; The microcontroller module is electrically connected to the NFC reader / writer module, and is used to encapsulate the tag identification and communication logic into a predetermined communication protocol, and communicate with the NFC reader / writer module and the host computer through an asynchronous serial communication interface; NFC antenna module, used to identify NFC tag information; An NFC antenna impedance matching module is electrically connected to the NFC reader / writer module and the NFC antenna module, is controlled by the NFC reader / writer module, and adapts to the difference between the input impedance of the NFC antenna and the output impedance of the NFC reader / writer module; The microcontroller module includes a first chip with a model number of N32G031F8S7, and the NFC reader / writer module includes a second chip with a model number of ST25R3911B; the power supply module includes a 12V to 5V DC power unit and a 5V to 3.3V DC power unit; The 8th pin of the second chip is connected to the 5V DC output terminal of the power supply module through the first inductor and to the 3.3V DC output terminal of the power supply module through the second inductor, the 1st pin is connected to the 3.3V DC output terminal of the power supply module, the 4th pin and the 5th pin are connected to the second crystal oscillator unit, the 2nd pin and the 25th pin are respectively connected in series with resistors and then grounded through capacitors, the 28th pin is unloaded, the 32nd pin is connected to the 7th pin of the first chip, the 29th pin is connected to the 10th pin of the first chip through a resistor, the 30th pin is connected to the 13th pin of the first chip through a resistor, the 31st pin is connected to the 11th pin of the first chip, the 27th pin is connected to the 9th pin of the first chip, the 10th pin, the 11th pin, the 13th-20th pin, the 22nd pin and the 23rd pin are connected to the NFC antenna impedance matching module; the 3rd pin, the 7th pin, the 9th pin, the 24th pin and the ground wire are respectively connected with filter capacitors, the 6th pin, the 12th pin, Pin 21, pin 26 and pin 33 are grounded respectively; pin 1 of the first chip is grounded through a resistor, pin 2 and pin 3 are connected to the first crystal oscillator unit, pin 4 and pins 17-20 are connected to the asynchronous serial communication interface, pin 5 and pin 16 are connected to the 3.3V DC output end of the power supply module, pin 6, pin 8 and pin 14 are connected to the LED display unit, and the LED display unit is connected to the 3.3V DC output end, pin 7, pin 9 and pin 11 are respectively connected to pin 32, pin 27 and pin 31 of the second chip, pin 10 is grounded through a capacitor and connected to pin 29 of the second chip through a resistor, pin 12 is unloaded, pin 13 is connected to pin 30 of the second chip through a resistor, pin 15 is grounded, and the asynchronous serial communication interface is connected to the 3.3V DC output end and the 5V DC output end of the power supply module.

2. The multi-tag anti-collision mechanism NFC reader / writer according to claim 1, characterized in that: The communication protocol includes the ISO / IEC 15693 communication protocol.

3. The multi-tag anti-collision mechanism NFC reader / writer according to claim 1, characterized in that: The 5V to 3.3V DC power unit includes a reset terminal for resetting the second chip.

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