Pixel driving circuit, circuit driving method, driving substrate, and display device

Abstract

The present application provides a pixel driving circuit, a circuit driving method, a driving substrate, and a display device; the pixel driving circuit includes: a latching unit, which receives a write signal and is configured to latch the write signal within each sub-frame, generate an inverted signal having a phase opposite to that of the write signal and output the inverted signal to control pixels in the pixel driving circuit; a reset unit, which receives a scan signal and is grounded and is configured to, after being turned on by the scan signal, discharge the pixels through the turned-on reset unit to reset the voltages of the pixels.

Description

Technical Field

[0001] Embodiments of the present application relate to the technical field of circuit driving, and in particular, to a pixel driving circuit, a circuit driving method, a driving substrate, and a display device. Background Art

[0002] In a related pixel driving circuit, since the peak emission wavelength of an OLED (Organic Light Emitting Diode) is greatly affected by the current density (i.e., voltage), and in most OLEDs, there is a U-shaped variation relationship between the peak emission wavelength of the OLED and the current density. That is to say, at low current density, there is a negative correlation between the peak emission wavelength and the current density, and at high current density, there is a positive correlation between the peak emission wavelength and the current density, resulting in instability of the peak emission wavelength and thus color deviation in the displayed color.

[0003] Based on this, a solution that can avoid color deviation caused by voltage is needed. Summary of the Invention

[0004] In view of this, the purpose of the present application is to provide a pixel driving circuit, a circuit driving method, a driving substrate, and a display device.

[0005] Based on the above purpose, the present application provides a pixel driving circuit, including:

[0006] A latching unit, which accesses a write signal and is configured to latch the write signal within each sub-frame, generate an inverted signal with a phase opposite to that of the write signal, and output it to control pixels in the pixel driving circuit;

[0007] A reset unit, which accesses a scan signal and is grounded, and is configured to discharge the pixel through the activated reset unit after the scan signal activates, so as to reset the voltage of the pixel.

[0008] The pixel driving circuit further includes:

[0009] An input unit, which is connected to the latching unit, accesses bit data and the scan signal, and is configured to generate the write signal according to the bit data, and output the write signal to the latching unit after being activated by the scan signal;

[0010] A driving unit, which accesses an input signal, is connected to the latching unit and the reset unit, and is configured to access the inverted signal from the latching unit, light the pixels in the pixel driving circuit using the input signal after being activated by the inverted signal, and discharge through the reset unit in response to determining that the reset unit is activated.

[0011] Among them, the scanning signal includes a row scanning signal and a column scanning signal that are synchronized in time sequence;

[0012] Preferably, the input unit includes:

[0013] A serial-to-parallel conversion subunit, which accesses the bit data and is configured to generate corresponding write signals for each bit in sequence according to the bit positions of the bits in the bit data within a complete frame period, and serially output the corresponding write signals within the corresponding sub-frames in sequence;

[0014] A first transistor, whose source is connected to the serial-to-parallel conversion subunit, gate is connected to the row scanning signal, and drain is connected to the latch unit, and is configured to turn on when accessing a high-level row scanning signal within each sub-frame, access the write signal corresponding to this sub-frame from the serial-to-parallel conversion subunit, and output it to the latch unit;

[0015] A second transistor, whose source is connected to the serial-to-parallel conversion subunit, gate is connected to the column scanning signal, and drain is connected to the latch unit, and is configured to turn on when accessing a high-level column scanning signal within each sub-frame, access the write signal corresponding to this sub-frame from the serial-to-parallel conversion subunit, and output it to the latch unit.

[0016] Preferably, the serial-to-parallel conversion subunit is further configured to:

[0017] In response to receiving the bit data, determine the proportional relationship of the bit weight values of the bits in the bit data;

[0018] Divide the complete frame period according to the proportional relationship to obtain sub-frames corresponding to each bit, and the duration ratio between the sub-frames satisfies the proportional relationship;

[0019] In response to determining that the value of the bit is 1, generate and output a high-level write signal within the corresponding sub-frame;

[0020] In response to determining that the value of the bit is 0, generate and output a low-level write signal within the corresponding sub-frame.

[0021] Preferably, the latch unit includes:

[0022] A first inverter, whose input terminal is connected to the drain of the second transistor, and is configured to access the corresponding write signal from the second transistor within each sub-frame, generate an inverted signal with a potential opposite to that of the write signal, and write it to the driving unit;

[0023] A second inverter, with its input terminal connected to the output terminal of the first inverter, and its output terminal connected to the input terminal of the first inverter, and is configured to, within each sub-frame, access the inverted signal from the output terminal of the first inverter, generate the write signal with a potential opposite to that of the inverted signal, and output it to the input terminal of the first inverter to confirm and latch the write signal accessed by the first inverter;

[0024] A third inverter, with its input terminal connected to the drain of the first transistor, and its output terminal connected to the output terminal of the first inverter and the input terminal of the second inverter, and is configured to, within each sub-frame, access the corresponding write signal from the first transistor, generate the inverted signal with a potential opposite to that of the write signal, and write it into the driving unit;

[0025] The first inverter and the second inverter are further configured to, within the same sub-frame, in response to determining that one inverter generates the inverted signal and the other inverter does not generate the inverted signal, not write the inverted signal into the driving unit.

[0026] Preferably, the driving unit includes:

[0027] A third transistor, with its gate accessing the driving signal and its source connected to the input signal, and is configured to be turned on by the accessed driving signal and output the input signal after being turned on;

[0028] A fourth transistor, with its gate connected to the output terminal of the first inverter and the output terminal of the third inverter, and its source connected to the drain of the third transistor, and is configured to, within each sub-frame, access the inverted signal from the first inverter and the third inverter, and be controlled to be turned on or off by the inverted signal. When turned on, access the input signal from the drain of the third transistor and output it;

[0029] A light-emitting diode, with its anode connected to the drain of the fourth transistor, and is configured to, within each sub-frame, when the fourth transistor is turned on, access the input signal from the drain of the fourth transistor and be driven by the input signal.

[0030] Preferably, the reset unit includes:

[0031] A gate circuit component, accessing the row scanning signal and the column scanning signal, and is configured to, in response to determining that both the row scanning signal and the column scanning signal are at a high potential, output a high-potential logic signal;

[0032] The fifth transistor has its gate connected to the gate circuit component, its source connected to the anode of the light-emitting diode, and its drain grounded. It is configured to conduct in response to determining that a logic signal at a high potential is accessed from the gate circuit component, and the anode voltage of the light-emitting diode discharges through the conducting fifth transistor, so that the voltage of the anode is reset to a low potential.

[0033] Based on the same inventive concept, the present application further provides a circuit driving method for driving the pixel driving circuit as described in any one of the preceding items, including:

[0034] Making the latch unit access a write signal, latching the write signal within each sub-frame, generating and outputting an inverted signal with a phase opposite to that of the write signal to control the pixels in the pixel driving circuit;

[0035] Making the reset unit access a scan signal and be grounded. After being enabled by the scan signal, the pixel discharges through the enabled reset unit to reset the voltage of the pixel.

[0036] Wherein, the pixel driving circuit further includes an input unit and a driving unit;

[0037] The method further includes:

[0038] Making the input unit access bit data and the scan signal, generating the write signal according to the bit data, and after being enabled by the scan signal, outputting the write signal to the latch unit;

[0039] Making the driving unit access an input signal, accessing the inverted signal from the latch unit, and after being enabled by the inverted signal, using the input signal to light the pixels in the pixel driving circuit, and discharging through the reset unit in response to determining that the reset unit is enabled.

[0040] Wherein, the scan signal includes a row scan signal and a column scan signal;

[0041] Further, making the input unit generate the write signal according to the bit data, generating the write signal according to the bit data after being enabled by the scan signal, and after being enabled by the scan signal, outputting the write signal to the latch unit includes:

[0042] Within a complete frame period, making the parallel-to-serial conversion sub-unit in the input unit generate corresponding write signals for each bit in sequence according to the bit positions of the bits in the bit data, and sequentially serially output the corresponding write signals to the first transistor and the second transistor in the input unit within the corresponding sub-frames;

[0043] Within each sub-frame, the first transistor is turned on using the row scanning signal, and the second transistor is turned on using a column scanning signal synchronized with the row scanning signal, such that the first transistor and the second transistor synchronously receive corresponding write signals and output them to the latch unit.

[0044] Further, corresponding write signals are generated for each bit in sequence according to the bit positions of the bits in the bit data, including:

[0045] In response to receiving the bit data, determining the proportional relationship of the bit weight values of the bits in the bit data;

[0046] Dividing the complete frame period according to the proportional relationship to obtain sub-frames corresponding to each bit, and the duration ratio between the sub-frames satisfies the proportional relationship;

[0047] In response to determining that the value of a bit is 1, a high-level write signal is generated within the corresponding sub-frame;

[0048] In response to determining that the value of a bit is 0, a low-level write signal is generated within the corresponding sub-frame.

[0049] Wherein, the latch unit includes a first inverter, a second inverter, and a third inverter;

[0050] Further, within each sub-frame, the write signal is latched to generate and output an inverted signal with a phase opposite to that of the write signal, including:

[0051] Within each sub-frame, the first inverter is connected to the corresponding write signal to generate an inverted signal with a potential opposite to that of the write signal, and write it to the driving unit;

[0052] Within this sub-frame, the second inverter receives the inverted signal from the first inverter to generate the write signal with a potential opposite to that of the inverted signal, and output it to the first inverter to confirm and latch the write signal received by the first inverter;

[0053] Within this sub-frame, the third inverter receives the corresponding write signal from the first transistor to generate the inverted signal with a potential opposite to that of the write signal, and write it to the driving unit;

[0054] Within this sub-frame, in response to determining that either the first inverter or the second inverter generates the inverted signal and the other inverter does not generate the inverted signal, the inverted signal is not written to the driving unit.

[0055] Further, controlling the pixels in the pixel driving circuit includes:

[0056] Within each sub-frame of a complete frame period, control whether the pixel is lit within the sub-frame according to the corresponding write signal;

[0057] Control the grayscale display of the pixel within the complete frame period by the sum of the durations of the sub-frames in which the pixel is lit.

[0058] Based on the same inventive concept, the present application also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, it implements the circuit driving method described in any one of the above.

[0059] Based on the same inventive concept, the present application also provides a driving substrate, and the driving substrate includes the pixel driving circuit described in any one of the above.

[0060] Based on the same inventive concept, the present application also provides a display device, and the display device includes the driving substrate described above.

[0061] As can be seen from the above, the pixel driving circuit, the circuit driving method, the driving substrate, and the display device provided by the present application, and the circuit driving method of the embodiments of the present application are based on generating a plurality of write signals from bit data, realizing the conversion of parallel write data into a plurality of serial write signals, and by dividing the complete frame period into a plurality of sub-frames and serially outputting the corresponding write signals within each sub-frame, thereby realizing the control of the lighting and extinguishing of the pixel within each sub-frame, and further controlling the grayscale display of the pixel within the frame period according to the ratio of the lighting time of the pixel within the complete frame period. At the same time, the corresponding write signal is latched within each sub-frame by the latching unit, thereby realizing the stable control of the pixel within the sub-frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions in the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0063] Figure 1 It is the spectrogram of the embodiment of the present application;

[0064] Figure 2 It is the first circuit diagram of the pixel driving circuit of the embodiment of the present application;

[0065] Figure 3 It is the second circuit diagram of the pixel driving circuit of the embodiment of the present application;

[0066] Figure 4The third circuit diagram of the pixel driving circuit according to the embodiment of the present application;

[0067] Figure 5 The fourth circuit diagram of the pixel driving circuit according to the embodiment of the present application;

[0068] Figure 6 The fifth circuit diagram of the pixel driving circuit according to the embodiment of the present application;

[0069] Figure 7 The sixth circuit diagram of the pixel driving circuit according to the embodiment of the present application;

[0070] Figure 8 The schematic diagram of the circuit driving method according to the embodiment of the present application;

[0071] Figure 9 The timing diagram according to the embodiment of the present application. Detailed implementation manners

[0072] To make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0073] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be of the ordinary meanings understood by those of ordinary skill in the art to which the present application belongs. The "first", "second" and similar terms used in the embodiments of the present application do not denote any order, quantity or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or objects appearing before this term cover the elements or objects listed after this term and their equivalents, without excluding other elements or objects. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0074] As described in the background art section, the related pixel driving circuits are still difficult to meet the requirements of display devices in actual operation.

[0075] In the process of implementing the present application, the applicant found that the main problem existing in the related pixel driving circuit is that in the related pixel driving circuit, since the peak emission wavelength of the OLED (Organic Light Emitting Diode) is greatly affected by the current density (i.e., voltage), and in most OLEDs, there is a U-shaped variation relationship between the peak emission wavelength of the OLED and the current density. That is to say, at low current density, there is a negative correlation between the peak emission wavelength and the current density, and at high current density, there is a positive correlation between the peak emission wavelength and the current density, resulting in the instability of the peak emission wavelength, and further causing color deviation in the displayed color.

[0076] In Figure 1 In the specific example shown, each curve respectively represents the spectral schematic diagram of the peak emission wavelength of the OLED at different voltages. Among them, the abscissa represents the peak emission wavelength, the ordinate represents the voltage, and each curve represents light of different colors.

[0077] It can be seen that when the OLED is at different voltages, the half-width at half maximum of light of different colors is different, resulting in gray-scale color deviation. In the actual use of a display device or an OLED, it is specifically manifested as a difference in the color purity of the color, and further causing color deviation in the display.

[0078] Furthermore, the applicant found in the research that due to the persistence of vision effect, when the general display refresh rate is greater than 50Hz, it is difficult for the human eye to perceive flicker. Furthermore, when the display refresh rate is greater than 50Hz, the picture perceived by the human eye is a complete and continuous picture.

[0079] Based on this, when the display refresh rate is greater than 50Hz, within a complete frame period, after dividing the frame period into multiple sub-frames, for each pixel, by adjusting the sum of the lighting durations of the pixel within each sub-frame, the different gray scales of the pixel can be adjusted. Within the complete frame period, the longer the lighting time of the pixel, the higher the gray scale, and the shorter the lighting time, the lower the gray scale.

[0080] Among them, for different gray scales, the voltage of the OLED is constant, and the difference lies only in the difference in the lighting duration, so that the shift of the peak emission wavelength of the OLED caused by voltage change can be effectively avoided, and the stability of the color purity of the OLED when realizing different gray scale displays can be improved.

[0081] Based on this, one or more embodiments in the present application provide a pixel driving circuit, which controls the lighting time of a pixel within a complete frame period according to the specific values of each bit in the bit data based on the received write data represented by bit data, so as to control the gray scale display of the pixel within the frame period.

[0082] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0083] Referring to Figure 2 , a pixel driving circuit 1 according to an embodiment of the present application includes:

[0084] A latch unit 101, which accesses a write signal and is configured to latch the write signal within each sub-frame, generate an inverted signal having a phase opposite to that of the write signal, and output the inverted signal to control pixels in the pixel driving circuit;

[0085] A reset unit 102, which accesses a scan signal and is grounded, and is configured to discharge the pixel through the turned-on reset unit after being turned on by the scan signal, so as to reset the voltage of the pixel.

[0086] In this embodiment, at the beginning of any sub-frame, the latch unit 101 accesses the write signal corresponding to the sub-frame and latches the received write signal within the sub-frame.

[0087] Further, the latch unit 101 is made to generate an inverted signal having a phase opposite to that of the write signal within the sub-frame and output the inverted signal.

[0088] In this embodiment, within any sub-frame, the reset unit 102 accesses the scan signal and is controlled to be turned on or off by the scan signal.

[0089] Based on this, when the scan signal turns on the reset unit 102, since the reset unit 102 is grounded, the voltage of the pixel is pulled down by the turned-on reset unit 102, so that the voltage of the pixel is reset.

[0090] It should be noted that when the scan signal is at a high potential, the reset unit 102 is turned on, and the scan signal does not continuously remain at a high potential within a sub-frame, but only remains at a high potential during the write stage.

[0091] Based on this, within a sub-frame, the pixels in the pixel driving circuit can be controlled to be lit or extinguished by the corresponding inverted signal, so as to control the lighting duration of the pixels within a complete cycle, and quickly eliminate the potential residue of the pixels before each lighting.

[0092] In another embodiment of the present application, as Figure 3 shown, the pixel driving circuit 1 further includes:

[0093] An input unit 103, which is connected to the latch unit 101, accesses bit data DATA and the scan signal, and is configured to generate the write signal according to the bit data DATA, and output the write signal to the latch unit 101 after being turned on by the scan signal;

[0094] The driving unit 104 is connected to the input signal ELVDD and is connected to the latching unit 101 and the reset unit 102. It is configured to receive the inverted signal from the latching unit 101. After being enabled by the inverted signal, it uses the input signal ELVDD to light up the pixels in the pixel driving circuit. In response to determining that the reset unit 102 is enabled, it discharges through the reset unit 102.

[0095] In this embodiment, as Figure 3 shown, the input unit 103 can receive the write data, and the write data can be bit data DATA represented in binary.

[0096] Furthermore, the input unit 103 is also connected to a scan signal, and the scan signal can be used to control the opening and closing of the input unit 103.

[0097] Based on this, the input unit 103 can generate corresponding write signals for each bit in the received bit data DATA, thereby obtaining a plurality of write signals.

[0098] Furthermore, after being enabled by the scan signal, the input unit 103 can output the generated write signals to the latching unit 101 in the order of the bit positions of the corresponding bits in the bit data DATA.

[0099] Among them, when outputting the write signal, a complete frame period is divided into multiple sub-frames, and the number of sub-frames is the same as the number of bits of the bit data DATA. That is to say, for each bit, a corresponding sub-frame is divided, and within the corresponding sub-frame, the write signal corresponding to the bit is output.

[0100] In this embodiment, at the beginning of any sub-frame, the latching unit 101 receives the write signal corresponding to the sub-frame from the input unit 103 and latches the received write signal within the sub-frame.

[0101] Furthermore, the driving unit 104 is connected to the input signal ELVDD for lighting up the pixels.

[0102] In this embodiment, within each sub-frame, the driving unit 104 also receives an inverted signal from the latching unit 101.

[0103] Among them, the inverted signal can control the opening and closing of the driving unit 104. After the inverted signal controls the driving unit 104 to be enabled, the driving unit 104 can use the received input signal ELVDD to drive the pixels to light up.

[0104] It can be seen that in this embodiment, a write signal is generated according to bit data, thereby using the write signal to control the pixels in the pixel driving circuit, and by generating the bit data within a complete frame period into a plurality of serially output write signals, the pixels can control the lighting time according to each write signal within the complete frame period.

[0105] In another embodiment of the present application, as Figure 4 shown, the input unit 103 includes:

[0106] A serial-to-parallel conversion subunit, which accesses the bit data DATA and is configured to, within a complete frame period, generate corresponding write signals for each bit in sequence according to the bit positions of the bits in the bit data DATA, and serially output the corresponding write signals within the corresponding sub-frames in sequence;

[0107] A first transistor M1, whose source is connected to the serial-to-parallel conversion subunit, whose gate is connected to the row scanning signal, and whose drain is connected to the latch unit 101, and is configured to turn on when accessing a high-level row scanning signal within each sub-frame, access the write signal corresponding to this sub-frame from the serial-to-parallel conversion subunit, and output it to the latch unit 101;

[0108] A second transistor M2, whose source is connected to the serial-to-parallel conversion subunit, whose gate is connected to the column scanning signal, and whose drain is connected to the latch unit 101, and is configured to turn on when accessing a high-level column scanning signal within each sub-frame, access the write signal corresponding to this sub-frame from the serial-to-parallel conversion subunit, and output it to the latch unit 101.

[0109] In this embodiment, within each complete frame period, after receiving a binary bit data DATA, when writing the bit data DATA, the serial-to-parallel conversion subunit writes each bit therein in sequence.

[0110] Specifically, the serial-to-parallel conversion subunit determines the weight values of each bit in the bit data DATA, and arranges the weight values of each bit in the order of bit positions, thereby obtaining the proportional relationship of the weight values.

[0111] Based on this, according to this proportional relationship, the complete frame period is divided into a plurality of sub-frames corresponding to each bit, and the proportional relationship in duration between each sub-frame satisfies the proportional relationship of the above weight values.

[0112] In a specific example, the bit data DATA may be, for example, 8-bit binary data 10101010. Among them, in the order of bit positions, the weight values from the first bit to the last bit are respectively: 1, 2, 4, 8, 16, 32, 64, and 128, and are respectively represented as w1, w2, w3, w4, w5, w6, w7, and w8 in sequence.

[0113] Based on this, the proportional relationship of the bit weight values of each bit is: w1:w2:w3:w4:w5:w6:w7:w8 = 1:2:4:8:16:32:64:128.

[0114] Furthermore, the current complete frame period is divided into multiple sub-frames. The number of sub-frames is the same as the number of bits in the bit data DATA, and the proportional relationship of the durations between the sub-frames satisfies the above-mentioned proportional relationship of the bit weight values.

[0115] In a specific example, taking a refresh rate of 60 Hz as an example, a complete frame period is 16.667 ms, and there are 256 gray levels. For the above 8-bit bit data DATA, according to the proportional relationship of the bit weight values of w1:w2:w3:w4:w5:w6:w7:w8 = 1:2:4:8:16:32:64:128, the gray-scale control display can be completed by dividing into 8 sub-frames.

[0116] Specifically, 16.667 ms is divided into 8 sub-frames to obtain the sub-frames corresponding to each bit. The sub-frames are sequentially represented as: T1, T2, T3, T4, T5, T6, T7, and T8 in the order of the bit positions.

[0117] In this embodiment, since T1 + T2 + T3 + T4 + T5 + T6 + T7 + T8 = 16.667 ms, therefore, the duration of each sub-frame can be calculated according to the following formula:

[0118]

[0119] where n represents the nth bit, and Tn represents the duration of the sub-frame corresponding to the nth bit. In this embodiment, the duration of the sub-frame is also called the sub-frame window time.

[0120] Based on this, the durations of each sub-frame shown in Table 1 below can be obtained, where the unit of the sub-frame duration is microseconds μs.

[0121]

[0122] It can be seen that the calculated durations of each sub-frame are: T1 = 65.35948, T2 = 130.719, T3 = 261.4379, T4 = 522.8758, T5 = 1045.752, T6 = 2091.503, T7 = 4183.007, T8 = 8366.013.

[0123] In this embodiment, within each sub-frame, for the bits with a bit value of 1, a write signal with a high level is generated and output during the duration of the sub-frame, and for the bits with a bit value of 0, a write signal with a low level is generated and output during the duration of the sub-frame.

[0124] It can be seen that each bit corresponds to a write signal, and the bit data containing multiple bits represents multiple write signals. Through the parallel-to-serial conversion sub-unit, the parallel input of multiple write signals is converted into serial output and sequentially output within each sub-frame according to the order of bit positions.

[0125] In this embodiment, as Figure 4 shown, the scan signal includes a row scan signal H-Scan and a column scan signal V-Scan that are synchronized in time sequence. Among them, each pixel corresponds to a preset row scan signal H-Scan and column scan signal V-Scan respectively. Specifically, in Figure 4 the shown pixel driving circuit, the access of the row scan signal H-Scan and the column scan signal V-Scan respectively corresponds to the row and column of the pixels in the pixel driving circuit.

[0126] Furthermore, a first transistor M1 is also provided in the input unit 103. The source of the first transistor M1 is connected to the parallel-to-serial conversion sub-unit, the gate is connected to the row scan signal H-Scan, and the drain is connected to the latch unit 101.

[0127] Based on this, within each sub-frame, the first transistor M1 is turned on when the accessed row scan signal H-Scan is at a high level and turned off when the row scan signal H-Scan is at a low level.

[0128] Furthermore, when the first transistor M1 is turned on within any sub-frame, the write signal corresponding to the sub-frame is accessed from the parallel-to-serial conversion sub-unit and output to the latch unit 101 through the drain.

[0129] Furthermore, a second transistor M2 is also provided in the input unit 103. The source of M2 is connected to the parallel-to-serial conversion sub-unit, the gate is connected to the column scan signal V-Scan, and the drain is connected to the latch unit 101.

[0130] Based on this, within each sub-frame, the second transistor M2 is turned on when the accessed column scan signal V-Scan is at a high level and turned off when the column scan signal V-Scan is at a low level.

[0131] Furthermore, when the second transistor M2 is turned on within any sub-frame, the write signal corresponding to the sub-frame is accessed from the parallel-to-serial conversion sub-unit and output to the latch unit 101 through the drain.

[0132] Based on this, within each sub-frame, for the pixels that need to be controlled, the row scan signal H-Scan and the column scan signal V-Scan corresponding to the pixel can be adjusted to high-level signals with synchronized phase and timing. Accordingly, the first transistor M1 and the second transistor M2 can be turned on simultaneously.

[0133] Further, within this sub-frame, when the first transistor M1 and the second transistor M2 are turned on simultaneously, the same write signal can be accessed from the parallel-to-serial conversion sub-unit at the same time.

[0134] In this embodiment, it is necessary to ensure that the pulse width of the row scan signal H-Scan is less than or equal to the pulse width of the column scan signal V-Scan in order to write the bit data into the latch unit 101 normally, and the write signal can be correctly latched in the latch unit 101.

[0135] It can be seen that in this embodiment, through the parallel-to-serial conversion sub-unit, the bit data DATA input in parallel during the complete frame period is split into multiple write signals output serially, and by dividing the complete frame period into multiple sub-frames corresponding to the bit positions, the pixel can be lit or extinguished according to the write signal within each sub-frame, thereby adjusting the lighting time of the pixel within a complete frame period, and further realizing the adjustment of different gray-scale displays of the pixel within the complete frame period without adjusting the voltage.

[0136] In another embodiment of the present application, as Figure 5 shown, the latch unit 101 includes:

[0137] A first inverter I1, the input end of which is connected to the drain of the second transistor M2, and is configured to access the corresponding write signal from the second transistor M2 within each sub-frame, generate an inverted signal with the opposite potential to the write signal, and write it into the driving unit 104;

[0138] A second inverter I2, the input end of which is connected to the output end of the first inverter I1, the output end of the second inverter I2 is connected to the input end of the first inverter I1, and is configured to access the inverted signal from the output end of the first inverter I1 within each sub-frame, generate the write signal with the opposite potential to the inverted signal, and output it to the input end of the first inverter I1 to confirm and latch the write signal accessed by the first inverter I1;

[0139] The third inverter I3 has its input terminal connected to the drain of the first transistor I1. The output terminal of the third inverter I3 is connected to the output terminal of the first inverter I1 and the input terminal of the second inverter 2, and is configured to access the corresponding write signal from the first transistor M1 within each sub-frame, generate the inverted signal with the opposite potential to the write signal, and write it into the driving unit 104;

[0140] The first inverter I1 and the second inverter I2 are further configured that within the same sub-frame, in response to determining that one inverter generates the inverted signal and the other inverter does not generate the inverted signal, the inverted signal is not written into the driving unit 104.

[0141] In this embodiment, as Figure 5 shown, the latch unit 101 includes a first inverter I1, a second inverter I2, and a third inverter I3.

[0142] Among them, the input terminal of the first inverter I1 is connected to the second transistor M2, so that the corresponding write signal can be accessed from the second transistor M2 within any sub-frame.

[0143] Further, within this sub-frame, after the first inverter I1 accesses the corresponding write signal, it will generate an inverted signal with the opposite phase and output it to the first connection point P1 through the output terminal.

[0144] Further, as Figure 5 shown, the input terminal of the second inverter I2 is connected to the output terminal of the first inverter I1 at the first connection point P1, so that within this sub-frame, the inverted signal can be accessed from the first inverter I1 and a signal with the opposite phase to the inverted signal is generated, that is, the write signal is generated.

[0145] Further, the output terminal of the second inverter I2 is connected to the input terminal of the first inverter I1, so that within this sub-frame, the second inverter I2 can input the generated write signal into the first inverter I1.

[0146] It can be seen that within this sub-frame, by inputting the generated write signal into the first inverter I1 through the second inverter I2, the write signal received by the first inverter I1 from the second transistor M2 can be further strengthened and latched, and after one sub-frame, when the first inverter I1 accesses the write signal of the next sub-frame, the latching of the previous write signal ends.

[0147] Further, the input terminal of the third inverter I3 is connected to the first transistor M1, and the output terminal is connected to the output terminal of the first inverter I1 at the first connection point P1 and is also connected to the input terminal of the second inverter I2.

[0148] Based on this, within any sub-frame, the third inverter I3 can access the corresponding write signal from the first transistor M1, generate an inverted signal with an opposite phase, and output it through the output terminal. Accordingly, both the third inverter I3 and the first inverter I1 output the same inverted signal, further strengthening and confirming the inverted signal accessed by the second inverter I2.

[0149] Furthermore, the third inverter I3 and the first inverter I1 simultaneously output the inverted signal to the first connection point P1, and the inverted signal is output to the driving unit 104 through the first connection point P1.

[0150] Among them, when the first transistor M1 does not access the high-level row scanning signal and / or the second transistor M2 does not access the high-level column scanning signal, it means that there is no need to control the pixel in this pixel driving circuit. At this time, at least one of the first transistor M1 and the second transistor M2 remains off, resulting in the first connection point P1 being unable to access the normal inverted signal, thereby controlling the pixel in the driving unit 104.

[0151] It can be seen that in this embodiment, by connecting the output terminal of the first inverter I1 to the input terminal of the second inverter I2, the write signals received by the first inverter I1 and the third inverter I3 are latched within each sub-frame, so that before the pixel writes the next inverted signal in the next sub-frame, in the current sub-frame, the current inverted signal remains unchanged, maintaining the pixel gray level stable in the current sub-frame.

[0152] In another embodiment of the present application, Figure 6 As shown, the driving unit 104 includes:

[0153] A third transistor M3, with its gate accessing the driving signal and its source connected to the input signal ELVDD, is configured to be turned on by the accessed driving signal EM and output the input signal ELVDD after being turned on;

[0154] A fourth transistor M4, with its gate connected to the output terminal of the first inverter I1 and the output terminal of the third inverter I3, and its source connected to the drain of the third transistor M3, is configured to access the inverted signal from the first inverter I1 and the third inverter I3 within each sub-frame and be controlled to turn on or off by the inverted signal. When turned on, it accesses the input signal ELVDD from the drain of the third transistor M3 and outputs it;

[0155] A light-emitting diode, with its anode connected to the drain of the fourth transistor M4, is configured to access the input signal ELVDD from the drain of the fourth transistor M4 within each sub-frame when the fourth transistor M4 is turned on, and be driven by the input signal ELVDD.

[0156] In this embodiment, as Figure 6 shown, a third transistor M3 is provided in the driving unit 104, whose source is connected to the input signal ELVDD, and whose gate is connected to the driving signal EM.

[0157] Among them, the input signal ELVDD can also be input to the source of the third transistor M3 through the constant current circuit Iref; the driving signal EM can be a PWM (Pulse Width Modulation) control signal.

[0158] Based on this, the third transistor M3 is controlled by the driving signal EM, turns on when the driving signal EM is at a high level, and turns off when the driving signal EM is at a low level.

[0159] Further, when the third transistor M3 is turned on, the input signal ELVDD can be written into the fourth transistor M4.

[0160] Further, the source of the fourth transistor M4 in the driving unit 104 is connected to the drain of the third transistor M3, the gate is connected to the first connection point P1, and the drain is connected to the anode of the light-emitting diode.

[0161] In a specific example, the light-emitting diode can be an organic light-emitting diode, that is, an OLED.

[0162] Based on this, the fourth transistor M4 is controlled to turn on or off by the inverted signal of the first connection point P1, turns on when the inverted signal is at a high level, and turns off when the inverted signal is at a low level.

[0163] Further, within any sub-frame in a complete frame period, when the fourth transistor M4 is turned on, the input signal ELVDD accessed from the third transistor M3 is written into the anode of the OLED, thereby driving the OLED.

[0164] It can be seen that within each sub-frame, whether the fourth transistor M4 can access a high potential from the first connection point P1 is determined by the inverted signal output by the latch unit 101, and the potential of the inverted signal is determined by the write signal accessed within this sub-frame. Therefore, through the serial-to-parallel conversion sub-unit, a complete frame period is divided into multiple sub-frames, and the write signal of each sub-frame is controlled by bit data, thereby controlling whether the fourth transistor M4 is turned on within this sub-frame, and further controlling whether the pixel is lit.

[0165] Further, within a complete frame period, pixels are lit in some sub-frames and extinguished in other sub-frames. Therefore, the lighting time of the pixels is the sum of the durations of the sub-frames in which the pixels are lit. Furthermore, by adjusting the write signal corresponding to each sub-frame, the lighting time of the pixels within the complete frame period can be adjusted. As described above, adjusting the lighting time of the pixels within the frame period can achieve the adjustment of different gray-scale displays of the pixels.

[0166] In another embodiment of the present application, as Figure 7 shown, the reset unit 102 includes:

[0167] A gate circuit component A1, which accesses the row scan signal and the column scan signal, is configured to output a high-potential logic signal in response to determining that both the row scan signal and the column scan signal are at a high potential;

[0168] A fifth transistor M5, whose gate is connected to the gate circuit component, source is connected to the anode of the light-emitting diode, and drain is grounded, is configured to conduct in response to determining that a high-potential logic signal is accessed from the gate circuit component, and the anode voltage of the light-emitting diode discharges through the conducting fifth transistor, so that the voltage of the anode is reset to a low potential.

[0169] Among them, the gate circuit component A1 is a component that executes AND gate logic and can be, for example, a diode or the like.

[0170] In this embodiment, the input terminals of the gate circuit component A1 are connected to the row scan signal H-Scan and the column scan signal V-Scan, and its output terminal is connected to the gate of the fifth transistor M5.

[0171] Further, the source of the fifth transistor M5 is connected to the anode of the OLED, and its drain is grounded. That is to say, when the fifth transistor M5 conducts, the source is grounded.

[0172] Based on this, when both the row scan signal H-Scan and the column scan signal V-Scan are at a high potential, the gate circuit component A1 outputs a high potential due to executing AND gate logic. When one or more of the row scan signal H-Scan and the column scan signal V-Scan are at a low potential, the gate circuit component A1 does not output a high potential.

[0173] Further, when the gate circuit component A1 outputs a high potential, the fifth transistor M5 is turned on due to the high potential being applied to its gate.

[0174] Based on this, the anode of the OLED will be grounded, and further the voltage of the anode of the OLED will be pulled down, thereby realizing the reset of the voltage of the anode of the OLED.

[0175] It should be noted that, in this embodiment, during the writing stage within each sub-frame, when both the row scan signal H-Scan and the column scan signal V-Scan are at a high potential, while at other times within this sub-frame, both the row scan signal H-Scan and the column scan signal V-Scan are at a low potential.

[0176] It can be seen that during the writing stage within each sub-frame, before the write signal is written into the latch unit 101, the fifth transistor M5 is turned on, and thus the potential remaining on the OLED anode after the previous lighting will be output through the grounded fifth transistor M5, thereby achieving the elimination of potential residue caused by the previous scan signal.

[0177] For the convenience of description, when describing the above device, it is divided into various modules according to functions for separate description. Of course, when implementing the embodiments of the present application, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0178] Based on the same inventive concept, corresponding to the circuit of any of the above embodiments, an embodiment of the present application also provides a circuit driving method.

[0179] Refer to Figure 8 , a circuit driving method according to an embodiment of the present application is used to drive the pixel driving circuit of any of the foregoing embodiments. As described above, the pixel driving circuit includes a latch unit 101, a reset unit 102, an input unit 103, and a driving unit 104.

[0180] Among them, the latch unit 101 includes a first inverter I1, a second inverter I2, and a third inverter I3; the reset unit includes a gate circuit component and a fifth transistor M5; the input unit 103 includes a parallel-to-serial conversion sub-unit, a first transistor M1, and a second transistor M2; the driving unit 104 includes a third transistor M3, a fourth transistor M4, and a light-emitting diode, and the light-emitting diode can also be an OLED.

[0181] The circuit driving method of this embodiment specifically includes the following steps:

[0182] Step S801: Make the input unit access the bit data and the scan signal, generate the write signal according to the bit data, and after being enabled by the scan signal, output the write signal to the latch unit.

[0183] Step S802: Make the driving unit access the input signal, access the inverted signal from the latch unit, after being enabled by the inverted signal, use the input signal to light the pixel in the pixel driving circuit, and in response to determining that the reset unit is enabled, discharge through the reset unit.

[0184] Step S701: Connect the input unit 103 to the bit data DATA and the scan signal, generate a write signal according to the bit data DATA, and output the write signal after being enabled by the scan signal.

[0185] In this embodiment, the input unit 103 can be connected to write data, and the write data can be bit data DATA represented in binary.

[0186] Furthermore, the input unit 103 is also connected to a scan signal, which can be used to control the opening and closing of the input unit 103.

[0187] Based on this, the input unit 103 is made to generate corresponding write signals for each bit in the bit data DATA, thereby obtaining a plurality of write signals.

[0188] Furthermore, after the input unit 103 is enabled by the scan signal, the generated write signals can be output to the latch unit 101 in sequence according to the bit positions of the corresponding bits in the bit data DATA.

[0189] Among them, when outputting the write signal, the input DNA element divides a complete frame period into a plurality of sub - frames, and the number of sub - frames is the same as the number of bits of the bit data DATA. That is to say, for each bit, a corresponding sub - frame is divided, and within the corresponding sub - frame, the write signal corresponding to the bit is output.

[0190] Step S702: Make the latch unit 101 connected to the input unit 103 receive the write signal from the input unit 103, latch the write signal within each sub - frame, generate an inverted signal with a phase opposite to that of the write signal and output it to control the pixels in the pixel driving circuit.

[0191] In this embodiment, at the beginning of any sub - frame, the latch unit 101 is made to receive the write signal corresponding to the sub - frame from the input unit 103 and latch the received write signal within the sub - frame.

[0192] Furthermore, the latch unit 101 is made to generate an inverted signal with a phase opposite to that of the write signal within the sub - frame and output the inverted signal.

[0193] Based on this, within a sub - frame, the pixels in the pixel driving circuit can be controlled to be lit or extinguished through the corresponding inverted signal.

[0194] In another embodiment of the present application, the driving unit 104 receives the inverted signal from the latch unit 101, thereby using the inverted signal to control the lighting or extinguishing of the pixels.

[0195] In this embodiment, the driving unit 104 is connected to the input signal ELVDD for lighting the pixel.

[0196] Further, within each sub-frame, the driving unit 104 also receives an inverted signal from the latching unit 101.

[0197] Wherein, the inverted signal can control the turning on and off of the driving unit 104. After the inverted signal controls the driving unit 104 to turn on, the driving unit 104 can use the accessed input signal ELVDD to drive the pixel to light up.

[0198] In another embodiment of the present application, generating a write signal according to the bit data DATA and outputting the write signal after being enabled by the scan signal includes:

[0199] Within a complete frame period, the parallel-to-serial conversion subunit in the input unit 103 generates corresponding write signals for each bit in sequence according to the bit positions of the bits in the bit data DATA, and sequentially serially outputs the corresponding write signals to the first transistor M1 and the second transistor M2 in the input unit 103 within the corresponding sub-frames;

[0200] Within each sub-frame, the first transistor M1 is enabled by the row scan signal, and the second transistor M2 is enabled by the column scan signal synchronized with the row scan signal. The first transistor M1 and the second transistor M2 are made to synchronously receive the corresponding write signals and output them to the latching unit 101.

[0201] In this embodiment, within each complete frame period, the parallel-to-serial conversion subunit receives a binary bit data DATA and writes it to the first transistor M1 and the second transistor M2. When writing the bit data DATA, each bit is written in sequence.

[0202] Specifically, the parallel-to-serial conversion subunit determines the weight values of each bit in the bit data DATA, and arranges the weight values of each bit in the order of bit positions, thereby obtaining the proportional relationship of the weight values.

[0203] Based on this, according to this proportional relationship, the complete frame period is divided into multiple sub-frames corresponding to each bit, and the proportional relationship of the durations between the sub-frames satisfies the above proportional relationship of the weight values.

[0204] In a specific example, the bit data DATA can be, for example, an 8-bit binary data 10101010. Among them, in the order of bit positions, the weight values from the first bit to the last bit are: 1, 2, 4, 8, 16, 32, 64, and 128, and are respectively represented as w1, w2, w3, w4, w5, w6, w7, and w8 in sequence.

[0205] Based on this, the proportional relationship of the bit weight values of each bit is: w1:w2:w3:w4:w5:w6:w7:w8 = 1:2:4:8:16:32:64:128.

[0206] Further, the current complete frame period is divided into multiple sub-frames. The number of sub-frames is the same as the number of bits in the bit data DATA, and the proportional relationship of the durations between the sub-frames satisfies the above-mentioned proportional relationship of bit weight values.

[0207] In a specific example, taking a refresh rate of 60Hz as an example, a complete frame period is 16.667ms, and there are 256 gray levels. For the above-mentioned 8-bit bit data DATA, according to the proportional relationship of bit weight values of w1:w2:w3:w4:w5:w6:w7:w8 = 1:2:4:8:16:32:64:128, gray-scale control display can be completed by dividing into 8 sub-frames.

[0208] Specifically, 16.667ms is divided into 8 sub-frames to obtain the sub-frames corresponding to each bit. The sub-frames are sequentially represented in the order of bit positions as: T1, T2, T3, T4, T5, T6, T7, and T8.

[0209] In this embodiment, since T1 + T2 + T3 + T4 + T5 + T6 + T7 + T8 = 16.667ms, therefore, the duration of each sub-frame can be calculated according to the following formula:

[0210]

[0211] Where n represents the nth bit, Tn represents the duration of the sub-frame corresponding to the nth bit, and the duration of the sub-frame in this embodiment is also called the sub-frame window time.

[0212] Based on this, the calculated durations of each sub-frame are: T1 = 65.35948, T2 = 130.719, T3 = 261.4379, T4 = 522.8758, T5 = 1045.752, T6 = 2091.503, T7 = 4183.007, T8 = 8366.013.

[0213] In this embodiment, within each sub-frame, for the bit with a bit value of 1, a high-level write signal is generated and output within the duration of the sub-frame, and for the bit with a bit value of 0, a low-level write signal is generated and output within the duration of the sub-frame.

[0214] It can be seen that each bit corresponds to a write signal, and bit data containing multiple bits represents multiple write signals. Through the parallel-to-serial conversion sub-unit, the parallel input of multiple write signals is converted into serial output and sequentially output within each sub-frame in the order of bit positions.

[0215] In this embodiment, the scan signals include a row scan signal H-Scan and a column scan signal V-Scan that are synchronized with the same timing as in the previous embodiment. Among them, each pixel corresponds to a preset row scan signal H-Scan and column scan signal V-Scan respectively. That is to say, the row scan signal H-Scan and column scan signal V-Scan accessed by the pixel driving circuit respectively correspond to the row and column of the pixels in the pixel driving circuit.

[0216] In this embodiment, within each sub-frame, the first transistor M1 is turned on when the accessed row scan signal H-Scan is at a high level and turned off when the row scan signal H-Scan is at a low level.

[0217] Further, after the first transistor M1 is turned on in any sub-frame, the write signal corresponding to this sub-frame is accessed from the parallel-to-serial conversion sub-unit and output to the latch unit 101 through the drain.

[0218] Further, within each sub-frame, the second transistor M2 is turned on when the accessed column scan signal V-Scan is at a high level and turned off when the column scan signal V-Scan is at a low level.

[0219] Further, after the second transistor M2 is turned on in any sub-frame, the write signal corresponding to this sub-frame is accessed from the parallel-to-serial conversion sub-unit and output to the latch unit 101 through the drain.

[0220] Based on this, within each sub-frame, for the pixel to be controlled, the row scan signal H-Scan and column scan signal V-Scan corresponding to this pixel can be adjusted to high-level signals with the same phase and timing. Accordingly, the first transistor M1 and the second transistor M2 can be turned on simultaneously.

[0221] Further, within this sub-frame, when the first transistor M1 and the second transistor M2 are turned on simultaneously, the same write signal can be accessed from the parallel-to-serial conversion sub-unit at the same time.

[0222] In this embodiment, it is necessary to ensure that the pulse width of the row scan signal H-Scan is less than or equal to the pulse width of the column scan signal V-Scan in order to write the bit data into the latch unit 101 normally and the write signal can be correctly latched in the latch unit 101.

[0223] In another embodiment of the present application, the write signal is latched within each sub-frame, and an inverted signal having a phase opposite to that of the write signal is generated and output, including:

[0224] Within each sub-frame, the first inverter I1 is connected to the corresponding write signal, an inverted signal having a potential opposite to that of the write signal is generated, and is written to the driving unit 104;

[0225] Within this sub-frame, the second inverter I2 receives the inverted signal from the first inverter I2, a write signal having a potential opposite to that of the inverted signal is generated, and is output to the first inverter I1 to confirm and latch the write signal received by the first inverter I1;

[0226] Within this sub-frame, the third inverter I3 receives the corresponding write signal from the first transistor M1, an inverted signal having a potential opposite to that of the write signal is generated, and is written to the driving unit 104;

[0227] Within this sub-frame, in response to determining that either the first inverter I1 or the second inverter I2 generates the inverted signal and the other inverter does not generate the inverted signal, the inverted signal is not written to the driving unit 104.

[0228] In this embodiment, the input terminal of the first inverter I1 can receive the corresponding write signal from the second transistor M2 within any sub-frame.

[0229] Further, within this sub-frame, after the first inverter I1 receives the corresponding write signal, an inverted signal having a phase opposite thereto is generated and output to the first connection point P1.

[0230] Further, within this sub-frame, the second inverter I2 can receive the inverted signal from the first inverter I1 and generate a signal having a phase opposite to that of the inverted signal, that is, generate a write signal.

[0231] Further, within this sub-frame, the second inverter I2 can input the generated write signal to the first inverter I1.

[0232] It can be seen that within this sub-frame, by inputting the generated write signal to the first inverter I1 through the second inverter I2, the write signal received by the first inverter I1 from the second transistor M2 can be further strengthened and latched, and after one sub-frame, when the first inverter I1 receives the write signal of the next sub-frame, the latching of the previous write signal ends.

[0233] Further, within the sub-frame, the third inverter I3 can receive the corresponding write signal from the first transistor M1, generate an inverted signal with an opposite phase, and output it. Accordingly, both the third inverter I3 and the first inverter I1 output the same inverted signal, further strengthening and confirming the inverted signal received by the second inverter I2.

[0234] Further, the third inverter I3 and the first inverter I1 simultaneously output the inverted signal to the first connection point P1, so that the inverted signal is output to the driving unit 104 through the first connection point P1.

[0235] Wherein, when the first transistor M1 does not receive a high-level row scanning signal and / or the second transistor M2 does not receive a high-level column scanning signal, it means that there is no need to control the pixel in the pixel driving circuit. At this time, at least one of the first transistor M1 and the second transistor M2 remains off, resulting in the first connection point P1 being unable to receive a normal inverted signal, thereby controlling the pixel in the driving unit 104.

[0236] In another embodiment of the present application, controlling the pixel in the pixel driving circuit includes:

[0237] Within each sub-frame of a complete frame period, controlling whether the pixel is lit within the sub-frame according to the corresponding write signal;

[0238] Using the sum of the durations of the sub-frames in which the pixel is lit to control the grayscale display of the pixel within the complete frame period.

[0239] In this embodiment, the third transistor M3 is controlled by the driving signal EM, is turned on when the driving signal EM is at a high level, and is turned off when the driving signal EM is at a low level. Among them, the driving signal EM can be a PWM (Pulse Width Modulation) control signal.

[0240] Further, the input signal ELVDD is input to the third transistor M3 through the constant current circuit Iref. When the third transistor M3 is turned on, the input signal ELVDD can be written to the fourth transistor M4.

[0241] Further, the fourth transistor M4 is controlled to be turned on or off by the inverted signal of the first connection point P1, is turned on when the inverted signal is at a high level, and is turned off when the inverted signal is at a low level.

[0242] Further, within any sub-frame of a complete frame period, when the fourth transistor M4 is turned on, the input signal ELVDD received from the third transistor M3 is written to the anode of the OLED, thereby driving the OLED.

[0243] In a specific example, based on dividing the 16.667 ms complete frame period into 8 sub-frames in the foregoing embodiment, combined with Figure 9 the timing diagram shown in Figure 9 , within each sub-frame, the pixel driving circuit 1 accesses one bit of the bit data DATA, the high-potential row scanning signal H-Scan, and the high-potential column scanning signal V-Scan at the same moment. This moment is the writing stage within each sub-frame. During the writing stage, the input unit 103 accesses one bit, the high-potential row scanning signal H-Scan, and the high-potential column scanning signal V-Scan. Furthermore, at this moment, that is, during the writing stage, the first transistor M1 and the second transistor 2 of the input unit are turned on, and the fifth transistor 5 of the reset unit 102 is turned on.

[0244] Based on this, the latching unit 101 can access one bit during the writing stage and latch it at other times after the writing stage within the corresponding sub-frame. The reset unit 102 releases the residual potential of the OLED anode during the writing stage before the latching unit 101 outputs a high potential.

[0245] In this embodiment, at the first sub-frame T1, the serial-to-parallel conversion sub-unit outputs the writing signal corresponding to the 1st bit, that is, the high-level writing signal corresponding to the bit value of 1. When both the row scanning signal H-Scan and the column scanning signal V-Scan are at a high potential, the first transistor M1 and the second transistor M2 are turned on, and the high-level writing signal is written into the first inverter I1 and the third inverter I3, and an inverted signal of low potential is generated. This inverted signal of low potential is written into the fourth transistor M4, causing the fourth transistor M4 to turn off and remain in the off state within the duration of T1, that is, within 65.35948 microseconds, so that the OLED remains extinguished within the duration of T1.

[0246] Furthermore, at the second sub-frame T2, the serial-to-parallel conversion sub-unit outputs the writing signal corresponding to the 2nd bit, that is, the low-level writing signal corresponding to the bit value of 0. When both the row scanning signal H-Scan and the column scanning signal V-Scan are at a high potential, the first transistor M1 and the second transistor M2 are turned on, and the low-level writing signal is written into the first inverter I1 and the third inverter I3, and an inverted signal of high potential is generated. This inverted signal of high potential is written into the fourth transistor M4, causing the fourth transistor M4 to turn on and remain in the on state within the duration of T2, that is, within 130.719 microseconds, so that the OLED remains lit within the duration of T2.

[0247] Further, at the third sub-frame T3, the serial-to-parallel conversion subunit outputs a write signal corresponding to the 3rd bit, that is, a high-level write signal corresponding to a bit value of 1. When both the row scan signal H-Scan and the column scan signal V-Scan are at a high potential, the first transistor M1 and the second transistor M2 are turned on, and the high-level write signal is written into the first inverter I1 and the third inverter I3, and an inverted signal of low potential is generated. This low-potential inverted signal is written into the fourth transistor M4, causing the fourth transistor M4 to turn off and remain off within the duration of T3, that is, within 261.4379 microseconds, so that the OLED remains extinguished within the duration of T3.

[0248] Further, at the fourth sub-frame T4, the serial-to-parallel conversion subunit outputs a write signal corresponding to the 4th bit, that is, a low-level write signal corresponding to a bit value of 0. When both the row scan signal H-Scan and the column scan signal V-Scan are at a high potential, the first transistor M1 and the second transistor M2 are turned on, and the low-level write signal is written into the first inverter I1 and the third inverter I3, and an inverted signal of high potential is generated. This high-potential inverted signal is written into the fourth transistor M4, causing the fourth transistor M4 to turn on and remain on within the duration of T4, that is, within 522.8758 microseconds, so that the OLED remains lit within the duration of T4.

[0249] Further, at the fifth sub-frame T5, the serial-to-parallel conversion subunit outputs a write signal corresponding to the 5th bit, that is, a high-level write signal corresponding to a bit value of 1. When both the row scan signal H-Scan and the column scan signal V-Scan are at a high potential, the first transistor M1 and the second transistor M2 are turned on, and the high-level write signal is written into the first inverter I1 and the third inverter I3, and an inverted signal of low potential is generated. This low-potential inverted signal is written into the fourth transistor M4, causing the fourth transistor M4 to turn off and remain off within the duration of T5, that is, within 1045.752 microseconds, so that the OLED remains extinguished within the duration of T5.

[0250] Further, at the sixth sub-frame T6, the serial-to-parallel conversion subunit outputs a write signal corresponding to the 6th bit, that is, a low-level write signal corresponding to a bit value of 0. When both the row scan signal H-Scan and the column scan signal V-Scan are at a high potential, the first transistor M1 and the second transistor M2 are turned on, and the low-level write signal is written into the first inverter I1 and the third inverter I3, and an inverted signal of high potential is generated. This high-potential inverted signal is written into the fourth transistor M4, causing the fourth transistor M4 to turn on and remain on within the duration of T6, that is, within 2091.503 microseconds, so that the OLED remains lit within the duration of T6.

[0251] Further, at the seventh sub-frame T7, the serial-to-parallel conversion subunit outputs a write signal corresponding to the 7th bit, that is, a high-level write signal corresponding to a bit value of 1. When both the row scan signal H-Scan and the column scan signal V-Scan are at a high potential, the first transistor M1 and the second transistor M2 are turned on, and the high-level write signal is written into the first inverter I1 and the third inverter I3, and an inverted signal of low potential is generated. This low-potential inverted signal is written into the fourth transistor M4, causing the fourth transistor M4 to turn off and remain off during the duration of T7, that is, within 4183.007 microseconds, so that the OLED remains off during the duration of T7.

[0252] Further, at the eighth sub-frame T8, the serial-to-parallel conversion subunit outputs a write signal corresponding to the 8th bit, that is, a low-level write signal corresponding to a bit value of 0. When both the row scan signal H-Scan and the column scan signal V-Scan are at a high potential, the first transistor M1 and the second transistor M2 are turned on, and the low-level write signal is written into the first inverter I1 and the third inverter I3, and an inverted signal of high potential is generated. This high-potential inverted signal is written into the fourth transistor M4, causing the fourth transistor M4 to turn on and remain on during the duration of T8, that is, within 8366.013 microseconds, so that the OLED remains lit during the duration of T8.

[0253] Based on this, within the frame period, the total time that the OLED is lit is: T2 + T4 + T6 + T8 = 11111.11 microseconds. The total time that the OLED is lit accounts for 66.67% of the entire frame period, and the gray scale display of this pixel is 170 gray levels.

[0254] Further, when it is necessary to adjust the gray scale display of this pixel, different bit data can be input to adjust the proportion of the total time that the OLED is lit within the complete frame period, so as to achieve the corresponding gray scale display.

[0255] It can be seen that within each sub-frame, whether the fourth transistor M4 can access the high potential from the first connection point P1 is determined by the inverted signal output by the latch unit 101, and the potential of the inverted signal is determined by the write signal accessed within this sub-frame. Therefore, through the serial-to-parallel conversion subunit, a complete frame period is divided into multiple sub-frames, and the write signal of each sub-frame is controlled by bit data, so as to control whether the fourth transistor M4 is turned on within this sub-frame, and further control whether the pixel is lit.

[0256] Further, within a complete frame period, pixels are lit in some sub-frames and extinguished in other sub-frames. Therefore, the lighting time of the pixels is the sum of the durations of the sub-frames in which the pixels are lit. Furthermore, by adjusting the write signals corresponding to each sub-frame, the lighting time of the pixels within the complete frame period can be adjusted. As described above, adjusting the lighting time of the pixels within the frame period can achieve the adjustment of different gray-scale displays of the pixels.

[0257] It can be seen that the circuit driving method of the embodiments of the present application is based on generating multiple write signals from bit data, realizing the conversion of parallel write data into multiple serial write signals, and by dividing the complete frame period into multiple sub-frames and serially outputting the corresponding write signals within each sub-frame, thereby realizing the control of the lighting and extinguishing of pixels within each sub-frame. Furthermore, according to the proportion of the lighting time of the pixels within the complete frame period, the gray-scale display of the pixels within the frame period is controlled. At the same time, the corresponding write signals are latched within each sub-frame through a latching unit, thereby realizing the stable control of the pixels within the sub-frame.

[0258] It should be noted that the method of the embodiments of the present application can be executed by a single device, such as a computer or a server, etc. The method of this embodiment can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In this case of a distributed scenario, one of the multiple devices can only execute one or more steps of the method of the embodiments of the present application, and these multiple devices will interact with each other to complete the described method.

[0259] It should be noted that some embodiments of the present application are described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be executed in a different order from that in the above embodiments and still achieve the desired results. Additionally, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0260] The method of the above embodiments is applied to implement the corresponding pixel driving circuit in any of the foregoing embodiments and has the beneficial effects of the corresponding method embodiments, which will not be elaborated here.

[0261] Based on the same inventive concept, corresponding to the pixel driving circuit of any of the above embodiments, the present application further provides a driving substrate, and the driving substrate includes the pixel driving circuit described in any one of the above embodiments.

[0262] Based on the same inventive concept, corresponding to the driving substrate of the above embodiment, the present application further provides a display device, and the display device includes the driving substrate described in any of the above embodiments.

[0263] Those of ordinary skill in the art should understand that: Any discussion of the above embodiments is merely exemplary and is not intended to imply that the scope of the present application (including the claims) is limited to these examples; Under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the embodiments of the present application as described above, and they are not provided in detail for the sake of brevity.

[0264] In addition, for the sake of simplicity of explanation and discussion, and in order not to make the embodiments of the present application difficult to understand, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. In addition, the devices may be shown in block diagram form in order to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present application are to be implemented (i.e., these details should be completely within the understanding of those skilled in the art). In the case where specific details (such as circuits) are set forth to describe the exemplary embodiments of the present application, it will be apparent to those skilled in the art that the embodiments of the present application can be implemented without these specific details or with variations of these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0265] Although the present application has been described in connection with specific embodiments of the present application, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art based on the foregoing description. For example, other memory architectures (such as dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0266] The embodiments of the present application are intended to cover all such alternatives, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application shall be included within the protection scope of the present application.

Claims

1. A pixel driving circuit, characterized in that: include: A latch unit receives a write signal and is configured to latch the write signal in each subframe, generate and output an inverted signal having a phase opposite to that of the write signal, so as to control a pixel in the pixel driving circuit; A reset unit is connected to the scanning signal and grounded, and is configured such that after being turned on by the scanning signal, the pixel discharges through the turned-on reset unit to reset the voltage of the pixel; The pixel driving circuit further includes: An input unit connected to the latch unit, receiving the bit data and the scan signal, and configured to generate the write signal according to the bit data, and output the write signal to the latch unit after being turned on by the scan signal; a driving unit, receiving an input signal and connected to the latch unit and the reset unit, configured to receive the inverted signal from the latch unit, and after being turned on by the inverted signal, use the input signal to light up the pixel in the pixel driving circuit, and discharge through the reset unit in response to determining that the reset unit is turned on; the scanning signal includes a row scanning signal and a column scanning signal with timing synchronization; The input unit comprises: The parallel-to-serial conversion subunit is connected to the bit data and is configured to generate a corresponding write signal for each bit in turn according to the bit position of each bit in the bit data within a complete frame period, and sequentially output the corresponding write signal in series within the corresponding subframe; A first transistor, having a source connected to the parallel-to-serial conversion subunit, a gate connected to the row scanning signal, and a drain connected to the latch unit, and configured to be turned on when a high-level row scanning signal is connected in each subframe, to connect a write signal corresponding to the subframe from the parallel-to-serial conversion subunit, and to output the write signal to the latch unit; a second transistor, having a source connected to the parallel-to-serial conversion subunit, a gate connected to the column scanning signal, a drain connected to the latch unit, and configured to be turned on when a high-level column scanning signal is connected in each subframe, to connect a write signal corresponding to the subframe from the parallel-to-serial conversion subunit, and to output the write signal to the latch unit; The latch unit comprises: A first inverter, whose input terminal is connected to the drain of the second transistor, and is configured to, in each subframe, receive a corresponding write signal from the second transistor, generate an inverted signal with a potential opposite to that of the write signal, and write the inverted signal to the drive unit; a second inverter, whose input end is connected to the output end of the first inverter, whose output end is connected to the input end of the first inverter, and configured to, in each subframe, receive the inverted signal from the output end of the first inverter, generate the write signal with a potential opposite to that of the inverted signal, and output it to the input end of the first inverter, so as to confirm and latch the write signal received by the first inverter; a third inverter, whose input end is connected to the drain of the first transistor, whose output end is connected to the output end of the first inverter and the input end of the second inverter, and configured to, in each subframe, receive the corresponding write signal from the first transistor, generate the inverted signal with a potential opposite to that of the write signal, and write it into the driving unit; The first inverter and the second inverter are further configured to, in the same subframe, not write the inverted signal to the driving unit in response to determining that any one inverter generates the inverted signal and the other inverter does not generate the inverted signal.

2. The circuit according to claim 1, characterized in that The parallel-to-serial conversion subunit is further configured as: In response to receiving the bit data, determining a proportional relationship between bit weights of each bit in the bit data; Dividing the complete frame period according to the proportional relationship to obtain subframes corresponding to each bit, the duration ratio between the subframes satisfying the proportional relationship; In response to determining that the value of the bit is 1, a high-level write signal is generated and output in the corresponding subframe; In response to determining that the value of the bit is 0, a low-level write signal is generated and output in the corresponding subframe.

3. The circuit according to claim 1, characterized in that The driving unit comprises: A third transistor, a gate of which is connected to a driving signal, a source of which is connected to an input signal, and is configured to be turned on by the connected driving signal and output the input signal after being turned on; a fourth transistor, having a gate connected to the output terminal of the first inverter and the output terminal of the third inverter, and a source connected to the drain of the third transistor, configured to, in each subframe, receive the inverted signal from the first inverter and the third inverter, and be turned on or off by the inverted signal, and when turned on, receive the input signal from the drain of the third transistor and output it; The light emitting diode has an anode connected to the drain of the fourth transistor and is configured to receive the input signal from the drain of the fourth transistor and be driven by the input signal in each subframe when the fourth transistor is turned on.

4. The circuit according to claim 3, characterized in that The reset unit comprises: A gate circuit component, connected to the row scan signal and the column scan signal, configured to output a high-potential logic signal in response to determining that the row scan signal and the column scan signal are both high-potential; A fifth transistor has a gate connected to the gate circuit component, a source connected to the anode of the light-emitting diode, and a drain connected to the ground. The fifth transistor is configured to be turned on in response to determining that the high-potential logic signal is connected from the gate circuit component, and the anode voltage of the light-emitting diode is discharged through the turned-on fifth transistor to reset the anode voltage to a low potential.

5. A circuit driving method for driving the pixel driving circuit according to any one of claims 1 to 4, characterized in that: include: Allowing the latch unit to receive a write signal, latch the write signal in each subframe, generate and output an inverted signal with a phase opposite to the write signal, so as to control the pixel in the pixel driving circuit; The reset unit is connected to the scanning signal and grounded. After being turned on by the scanning signal, the pixel is discharged through the turned-on reset unit to reset the voltage of the pixel; The pixel driving circuit further includes an input unit and a driving unit; The method comprises: The input unit is connected to the bit data and the scan signal, and the write signal is generated according to the bit data. After being turned on by the scan signal, the write signal is output to the latch unit; The driving unit is connected to the input signal, and the inverted signal is connected from the latch unit. After being turned on by the inverted signal, the pixel in the pixel driving circuit is lit up by the input signal, and in response to determining that the reset unit is turned on, the reset unit is discharged; the scanning signal includes a row scanning signal and a column scanning signal; The step of causing the input unit to generate the write signal according to the bit data, starting the write signal according to the bit data by the scan signal, and outputting the write signal to the latch unit after being started by the scan signal comprises: In a complete frame period, the parallel-to-serial conversion subunit in the input unit generates a corresponding write signal for each bit in turn according to the bit position of each bit in the bit data, and sequentially outputs the corresponding write signal in series to the first transistor and the second transistor in the input unit in the corresponding subframe; In each subframe, the first transistor is turned on by the row scanning signal, and the second transistor is turned on by the column scanning signal synchronized with the row scanning signal, so that the first transistor and the second transistor synchronously receive the corresponding write signal and output it to the latch unit; The latch unit includes a first inverter, a second inverter and a third inverter; The latching of the write signal in each subframe, generating and outputting an inverted signal with a phase opposite to that of the write signal, comprises: In each subframe, the first inverter is connected to a corresponding write signal to generate an inverted signal with a potential opposite to that of the write signal, and writes the inverted signal to the drive unit; In this subframe, the second inverter receives the inverted signal from the first inverter, generates the write signal with a potential opposite to the inverted signal, and outputs it to the first inverter to confirm and latch the write signal received by the first inverter; In the subframe, the third inverter is controlled to receive the corresponding write signal from the first transistor, generate the inverted signal with a potential opposite to the write signal, and write the inverted signal to the drive unit; In the subframe, in response to determining that any one of the first inverter and the second inverter generates the inversion signal and the other inverter does not generate the inversion signal, the inversion signal is not written to the driving unit.

6. The method according to claim 5, characterized in that The step of sequentially generating a corresponding write signal for each bit according to the bit position of each bit in the bit data includes: In response to receiving the bit data, determining a proportional relationship between bit weights of each bit in the bit data; Dividing the complete frame period according to the proportional relationship to obtain subframes corresponding to each bit, the duration ratio between the subframes satisfying the proportional relationship; In response to determining that the value of the bit is 1, a high-level write signal is generated in the corresponding subframe; In response to determining that the value of the bit is 0, a low-level write signal is generated in the corresponding subframe.

7. The method according to claim 5, characterized in that The controlling of the pixels in the pixel driving circuit comprises: In each subframe of a complete frame period, controlling whether the pixel is lit in the subframe according to the corresponding write signal; The sum of the durations of the subframes for lighting up the pixel is used to control the grayscale display of the pixel within the complete frame period.

8. A driving substrate, characterized in that: The driving substrate includes a plurality of pixel driving circuits as described in any one of claims 1 to 4.

9. A display device, characterized in that: Comprising the driving substrate as claimed in claim 8.

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