An in-plane switching pixel driving circuit for an ips / ffs panel

Abstract

The application discloses an in-plane switching pixel driving circuit for an IPS / FFS panel, comprising a first transistor, a first pre-storage capacitor, a second transistor, a pixel capacitor, a third transistor, a second pre-storage capacitor and a fourth transistor, wherein a first source-drain electrode of the first transistor is coupled to a first data signal line, a second source-drain electrode is coupled to a first source-drain electrode of the second transistor and one end of the first pre-storage capacitor; a second source-drain electrode of the second transistor is coupled to one end of the pixel capacitor; a first source-drain electrode of the fourth transistor is coupled to a second data signal line, a second source-drain electrode is coupled to a first source-drain electrode of the third transistor and one end of the second pre-storage capacitor; and a second source-drain electrode of the third transistor is coupled to the other end of the pixel capacitor.

Description

Technical Field

[0001] This invention relates to the field of pixel driving technology, and more specifically to an in-plane switching pixel driving circuit for IPS / FFS panels. Background Technology

[0002] Field sequential or color sequential display driving technology leverages the persistence of vision to directly mix RGB three-color light sources, achieving full-color display effects. It eliminates the need for color filters, thus improving light source utilization and reducing power consumption.

[0003] Traditional 1T2C pixel circuits, for 1920*1080 resolution products, have a gate signal activation cycle of 2µs per row. Enabling all 1080 rows to form one frame requires approximately 2ms. For 60Hz products, RGB subframes require a 180Hz refresh rate to achieve equivalent smoothness. Each subframe takes approximately 1 / 180 ≈ 5.56ms, leaving about 3.6ms for the backlight to illuminate and display R, G, B. Without considering LCD latency, or using ultra-fast ferroelectric or blue phase LCDs with µs-level response, the time utilization rate is 3.6 / 5.56 ≈ 64.7%. Considering LCD latency and providing 1ms for inversion, the time utilization rate is 2.6 / 5.56 ≈ 46.7%. Since the field sequence display time utilization rate affects overall brightness, improving the backlight display time utilization rate is beneficial for reducing costs and increasing display brightness.

[0004] In summary, traditional pixel driving circuits suffer from short illumination time. Summary of the Invention

[0005] In view of this, the present invention provides an in-plane switching pixel driving circuit for IPS / FFS panels, which solves the problem of short lamp-on time in traditional pixel driving circuits by improving the circuit structure and driving timing.

[0006] To address the above problems, the technical solution of this invention is to employ an in-plane switching pixel driving circuit for an IPS / FFS panel, comprising: a first transistor, a first pre-storage capacitor, a second transistor, a pixel capacitor, a third transistor, a second pre-storage capacitor, and a fourth transistor. The first source-drain of the first transistor is coupled to a first data signal line, and the second source-drain is coupled to the first source-drain of the second transistor and one end of the first pre-storage capacitor. The second source-drain of the second transistor is coupled to one end of the pixel capacitor. The first source-drain of the fourth transistor is coupled to a second data signal line, and the second source-drain is coupled to the first source-drain of the third transistor and one end of the second pre-storage capacitor. The second source-drain of the third transistor is coupled to the other end of the pixel capacitor.

[0007] Optionally, when the first transistor, the second transistor, the third transistor, and the fourth transistor are all N-type MOS transistors, the gates of the first transistor and the fourth transistor are both coupled to the control signal line, the gate of the second transistor is coupled to the first transfer signal line, and the gate of the third transistor is coupled to the second transfer signal line.

[0008] Optionally, when the first transistor, the second transistor, and the fourth transistor are all N-type MOS transistors and the third transistor is a P-type MOS transistor, the gates of the first transistor and the fourth transistor are both coupled to the control signal line, and the gates of the second transistor and the third transistor are coupled to the first transfer signal line.

[0009] Optionally, the ends of the first and second pre-storage capacitors furthest from the transistor are both coupled to a common signal line.

[0010] Optionally, the driving timing of the pixel driving circuit is configured as follows: during the backlight-on stage of the Nth frame, the control signal jumps to a high potential line by line, the first transistor and the fourth transistor are turned on synchronously, the first data signal line stores the first data signal containing the gray level voltage into the first pre-storage capacitor through the first transistor, the second data signal line stores the second data signal containing the reference voltage into the second pre-storage capacitor through the fourth transistor, and then enters the backlight-off stage of the Nth frame.

[0011] Optionally, during the backlight off phase of the Nth frame, the second transfer signal jumps to a high potential, the third transistor turns on, and after the second pre-storage capacitor transmits a second data signal containing a reference voltage to one end of the pixel capacitor through the third transistor, the second transfer signal jumps back to a normal potential, and the third transistor turns off; the first transfer signal jumps to a high potential, the second transistor turns on, and after the first pre-storage capacitor transmits a first data signal containing a grayscale voltage to the other end of the pixel capacitor through the second transistor, the first transfer signal jumps back to a normal potential, the second transistor turns off, and the backlight on phase of the N+1th frame begins.

[0012] Optionally, during the backlight-on phase of the (N+1)th frame, the control signal jumps to a high potential line by line, the first transistor and the fourth transistor turn on synchronously, the first data signal line stores the first data signal containing the reference voltage into the first pre-storage capacitor through the first transistor, and the second data signal line stores the second data signal containing the grayscale voltage into the second pre-storage capacitor through the fourth transistor, thus entering the backlight-off phase of the (N+1)th frame; during the backlight-off phase of the (N+1)th frame, the first transfer signal jumps to a high potential, the second transistor turns on, the first pre-storage capacitor transmits the first data signal containing the reference voltage to one end of the pixel capacitor through the second transistor, the first transfer signal jumps back to the normal potential, and the second transistor turns off; the second transfer signal jumps to a high potential, the third transistor turns on, the second pre-storage capacitor transmits the second data signal containing the grayscale voltage to the other end of the pixel capacitor through the third transistor, the second transfer signal jumps back to the normal potential, and the third transistor turns off, thus entering the backlight-on phase of the (N+2)th frame.

[0013] Optionally, the driving timing of the pixel driving circuit is configured as follows: during the backlight-on stage of the Nth frame, the control signal jumps to a high potential line by line, the first transistor and the fourth transistor are turned on synchronously, the first data signal line stores the first data signal containing the gray level voltage into the first pre-storage capacitor through the first transistor, the second data signal line stores the second data signal containing the reference voltage into the second pre-storage capacitor through the fourth transistor, and then enters the backlight-off stage of the Nth frame.

[0014] Optionally, during the backlight off phase of the Nth frame, the first transfer signal jumps to a low potential, the third transistor turns on, and after the second pre-storage capacitor transmits a second data signal containing a reference voltage to one end of the pixel capacitor through the third transistor, the second transfer signal jumps back to a high potential. At the same time, the third transistor turns off and the second transistor turns on. After the first pre-storage capacitor transmits a first data signal containing a grayscale voltage to the other end of the pixel capacitor through the second transistor, the first transfer signal jumps back to a normal potential, the second transistor turns off, and the backlight on phase of the N+1th frame begins.

[0015] Optionally, during the backlight-on phase of the N+1th frame, the control signal jumps to a high potential line by line, the first transistor and the fourth transistor turn on synchronously, the first data signal line stores the first data signal containing the reference voltage into the first pre-storage capacitor through the first transistor, and the second data signal line stores the second data signal containing the grayscale voltage into the second pre-storage capacitor through the fourth transistor, thus entering the backlight-off phase of the N+1th frame; during the backlight-off phase of the N+1th frame, the first transfer signal jumps to a high potential, the second transistor turns on, the first pre-storage capacitor transmits the first data signal containing the reference voltage to one end of the pixel capacitor through the second transistor, the first transfer signal jumps to a low potential, the second transistor turns off, and simultaneously the third transistor turns on, the second pre-storage capacitor transmits the second data signal containing the grayscale voltage to the other end of the pixel capacitor through the third transistor, the first transfer signal jumps back to the normal potential, the third transistor turns off, thus entering the backlight-on phase of the N+2th frame.

[0016] The primary improvement of this invention is the provision of an in-plane switching pixel driving circuit for IPS / FFS panels. By setting a pre-storage capacitor in conjunction with a transistor, grayscale voltage is stored in the pre-storage capacitor during the backlight emission time of the current frame. This enables all pixels to synchronously transfer grayscale voltage when the backlight is off, greatly reducing the pixel voltage writing time and relatively increasing the backlight emission time.

[0017] Furthermore, since the present invention can write grayscale voltage through any data signal line and reset through another data signal line in any frame, the IC voltage range of the liquid crystal display device is [0, Vop-max] regardless of whether the frame is a positive or negative frame, while the IC voltage range of the traditional IT2C circuit is [-Vop-max, Vop-max]. Therefore, the present invention can also significantly reduce power consumption and reduce driving difficulty. Attached Figure Description

[0018] Figure 1 This is a simplified circuit diagram of an in-plane switching pixel driving circuit for an IPS / FFS panel according to the present invention.

[0019] Figure 2 This is a simplified driving timing diagram of an in-plane switching pixel driving circuit for an IPS / FFS panel according to the present invention.

[0020] Figure 3 This is a simplified circuit diagram of a pixel driving circuit according to a preferred embodiment of the present invention;

[0021] Figure 4 This is a simplified driving timing diagram of a pixel driving circuit according to a preferred embodiment of the present invention;

[0022] Figure 5 This is an example diagram of the pixel structure used in the pixel driving circuit of the present invention. Detailed Implementation

[0023] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0025] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0026] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0028] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0029] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0030] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0031] Specifically, such as Figure 1 As shown, an in-plane switching pixel driving circuit for an IPS / FFS panel includes: a first transistor T1, a first pre-storage capacitor Cst1, a second transistor T2, a pixel capacitor Clc, a third transistor T3, a second pre-storage capacitor Cst2, and a fourth transistor T4. The first source-drain of the first transistor T1 is coupled to a first data signal line Data1, and its second source-drain is coupled to the first source-drain of the second transistor T2 and one end of the first pre-storage capacitor Cst1. The second source-drain of the second transistor T2 is coupled to one end of the pixel capacitor Clc. The first source-drain of the fourth transistor T4 is coupled to a second data signal line Data2, and its second source-drain is coupled to the first source-drain of the third transistor T3 and one end of the second pre-storage capacitor Cst2. The second source-drain of the third transistor T3 is coupled to the other end of the pixel capacitor Clc. The ends of the first pre-storage capacitor Cst1 and the second pre-storage capacitor Cst2 furthest from the transistors are both coupled to a common signal line Com.

[0032] Furthermore, when the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all N-type MOS transistors, the gates of the first transistor T1 and the fourth transistor T4 are both coupled to the control signal line Scan, the gate of the second transistor T2 is coupled to the first transfer signal line Tran1, and the gate of the third transistor T3 is coupled to the second transfer signal line Tran2.

[0033] Furthermore, such as Figure 2 As shown, the driving timing of the pixel driving circuit is configured as follows:

[0034] In the backlight-on phase of frame N (N=1 in the diagram), the control signal transitions to a high level line by line. The first transistor T1 and the fourth transistor T4 are simultaneously turned on. The first data signal line data1 stores the first data signal, containing the grayscale voltage, into the first pre-storage capacitor Cst1 via the first transistor T1. The second data signal line data2 stores the second data signal, containing the reference voltage, into the second pre-storage capacitor Cst2 via the fourth transistor T4. Then, the backlight-off phase of frame N begins. This completes the pre-storage of the grayscale voltage and reference voltage for each pixel in the next frame after the backlight-on phase.

[0035] During the backlight-off phase of frame N, the second transfer signal jumps to a high potential, the third transistor T3 turns on, and the second pre-storage capacitor Cst2 transmits a second data signal containing the reference voltage to one end of the pixel capacitor Clc through the third transistor T3. Then, the second transfer signal jumps back to a normal potential, and the third transistor T3 turns off. The first transfer signal jumps to a high potential, the second transistor T2 turns on, and the first pre-storage capacitor Cst1 transmits a first data signal containing the grayscale voltage to the other end of the pixel capacitor Clc through the second transistor T2. Then, the first transfer signal jumps back to a normal potential, and the second transistor T2 turns off, entering the backlight-on phase of frame N+1. Thus, the writing of the grayscale voltage and reference voltage for each pixel in the next frame is completed during the backlight-off phase.

[0036] During the backlight-on phase of frame N+1, the control signal transitions to a high level line by line, and the first transistor T1 and the fourth transistor T4 are simultaneously turned on. The first data signal line data1 stores the first data signal, including the reference voltage, into the first pre-storage capacitor Cst1 through the first transistor T1, and the second data signal line data2 stores the second data signal, including the grayscale voltage, into the second pre-storage capacitor Cst2 through the fourth transistor T4, thus entering the backlight-off phase of frame N+1. This completes the pre-storage of the grayscale voltage and reference voltage for each pixel in the next frame during the backlight-on phase.

[0037] During the backlight-off phase of frame N+1, the first transfer signal jumps to a high potential, the second transistor T2 turns on, and the first pre-storage capacitor Cst1 transmits a first data signal containing the reference voltage to one end of the pixel capacitor Clc through the second transistor T2. Then, the first transfer signal jumps back to a normal potential, and the second transistor T2 turns off. The second transfer signal then jumps to a high potential, the third transistor T3 turns on, and the second pre-storage capacitor Cst2 transmits a second data signal containing the grayscale voltage to the other end of the pixel capacitor Clc through the third transistor T3. Then, the second transfer signal jumps back to a normal potential, and the third transistor T3 turns off, entering the backlight-on phase of frame N+2. The purpose of resetting the pixel capacitor Clc before grayscale voltage transfer is to reduce the influence of charge sharing on the grayscale voltage and avoid inaccurate grayscale voltage on the pixel capacitor Clc during the backlight-on phase. This allows the writing of the grayscale voltage and reference voltage for each pixel in the next frame to be completed during the backlight-off phase.

[0038] It should be noted that in this embodiment, high potential is defined as a potential higher than the reference voltage that ensures the N-type MOS transistor is turned on after writing.

[0039] It should be noted that N is an odd number and a positive integer, which can be configured as 1, 3, 5, 7... in the above embodiments.

[0040] It should be noted that the pixel driving circuit claimed in this invention can be used in IPS / FFS panels, for example, in... Figure 5 This diagram illustrates a simplified single-domain pixel structure, using a positive liquid crystal as an example. Taking X as the initial alignment direction, in the Nth frame, the electric field direction will be along the Y-axis. Due to the electrode intersection, the electric field direction tends from the high-voltage Vpixel electrode to the reset Vpixel2 electrode (Com). In the (N+1)th frame, the electrode potential reverses, thus the electric field signal also reverses. During this electric field reversal, the polarity of the liquid crystal electron cloud reverses, preventing display failure caused by liquid crystal polarity aging.

[0041] Furthermore, to facilitate understanding of how the pixel driving circuit claimed in this invention reduces the data range, the data range during its operation is quantitatively explained below: In a traditional 1T2C circuit, the data range is [Vcom-Vop_max, Vcom+Vop_max], with an overall amplitude of 2Vop_max, which will not be elaborated further. However, in this embodiment, there are two types of charge sharing:

[0042] Reset charge sharing. This is achieved by sharing the charge of Clc to the reset Cst. Let the pixel electrode voltage be Vpixel_N-1, the reset voltage be Vreset, and the reference electrode be Vcom. When the charge stored in Clc is shared to Cst2: Clc(Vpixel-Vcom) = (Clc+Cst2)(Vreset-Vcom). Vreset = Clc / (Clc+Cst2)*(Vpixel-Vcom)+Vcom. When Cst2 >> Clc, Vreset ≈ Vcom. This can also be visualized as a small capacitor charging a large capacitor, causing the charge in the small capacitor to decrease.

[0043] Data charge sharing. The pixel electrode voltage after sharing at one end of the pixel capacitor connected to the second transistor T2 is set to Vpixel_N, and the pre-stored signal Cst1 is Vdata. When T2 is turned on, Cst1 and Clc share charge: Cst1(Vdata-Vcom)=(Cst1+Clc)(Vpixel_N-Vcom); Vdata=(1+Clc / Cst1)(Vpixel_N-Vcom)+Vcom. When Cst1>>Clc, Vdata=Vpixel. It can be seen that Vpixel's maximum value is Vop_max, and due to electrode reversal, Vdata range=Vop_max. Compared to the traditional scheme, the data range is reduced by 1 / 2.

[0044] Furthermore, to reduce the difficulty of driving the process, Cst1 can be set to Cst2, and Data1 and Data2 can be controlled separately by dual ICs. This drives the writing of data signals for the Nth and N+1th frames respectively, while simultaneously writing reset signals for the N-1th and Nth frames. In this case, the data output of the ICs will be halved. Because the display and data writing stages are separated, full-field illumination can be achieved, separating computation and display, and making it easier to achieve high resolution.

[0045] This invention, by using a pre-storage capacitor in conjunction with a transistor, enables the storage of grayscale voltages during the backlight illumination time of the current frame. This allows all pixels to synchronously transfer grayscale voltages when the backlight is off, significantly reducing pixel voltage write time and relatively increasing backlight illumination time. Furthermore, because this invention can simultaneously write grayscale voltages via one data signal line and reset via another data signal line in any frame, the IC voltage range of the liquid crystal display device is [0, Vop-max] regardless of whether the frame is positive or negative. In contrast, the IC voltage range of a traditional IT2C circuit is [-Vop-max, Vop-max]. Therefore, this invention also significantly reduces power consumption and simplifies driving.

[0046] The present invention also provides a pixel driving circuit according to a preferred embodiment, specifically, as follows: Figure 3 As shown, when the first transistor T1, the second transistor T2, and the fourth transistor T4 are all N-type MOS transistors, and the third transistor T3 is a P-type MOS transistor, the gates of the first transistor T1 and the fourth transistor T4 are both coupled to the control signal line Scan, and the gates of the second transistor T2 and the third transistor T3 are coupled to the first transfer signal line Tran1.

[0047] Furthermore, the first data signal line (data1) and the second data signal line (data2) can be stacked vertically with an insulating layer in between. Since they are driven separately, and one of the signal lines is used to write the reference voltage, their interference is weak, and the interference of the data signal on the pixel electrode can be reduced, further improving space utilization.

[0048] Furthermore, such as Figure 4 As shown, the driving timing of this preferred embodiment is configured as follows:

[0049] During the backlight-on phase of frame N, the control signal transitions to a high level line by line, and the first transistor T1 and the fourth transistor T4 are simultaneously turned on. The first data signal line data1 stores the first data signal containing the grayscale voltage into the first pre-storage capacitor Cst1 through the first transistor T1, and the second data signal line data2 stores the second data signal containing the reference voltage into the second pre-storage capacitor Cst2 through the fourth transistor T4, thus entering the backlight-off phase of frame N. This completes the pre-storage of the grayscale voltage and reference voltage for each pixel in the next frame during the backlight-on phase.

[0050] During the backlight-off phase of frame N, the first transfer signal transitions to a low level, the third transistor T3 turns on, and the second pre-storage capacitor Cst2 transmits a second data signal containing the reference voltage to one end of the pixel capacitor Clc via the third transistor T3. Then, the second transfer signal transitions back to a high level, and the third transistor T3 turns off. Simultaneously, the second transistor T2 turns on, and the first pre-storage capacitor Cst1 transmits a first data signal containing the grayscale voltage to the other end of the pixel capacitor Clc via the second transistor T2. Then, the first transfer signal transitions back to a normal level, the second transistor T2 turns off, and the backlight-on phase of frame N+1 begins. Thus, the grayscale voltage and reference voltage of each pixel in the next frame are written during the backlight-off phase.

[0051] During the backlight-on phase of frame N+1, the control signal transitions to a high level line by line, and the first transistor T1 and the fourth transistor T4 are simultaneously turned on. The first data signal line data1 stores the first data signal, including the reference voltage, into the first pre-storage capacitor Cst1 through the first transistor T1, and the second data signal line data2 stores the second data signal, including the grayscale voltage, into the second pre-storage capacitor Cst2 through the fourth transistor T4, thus entering the backlight-off phase of frame N+1. This completes the pre-storage of the grayscale voltage and reference voltage for each pixel in the next frame during the backlight-on phase.

[0052] During the backlight-off phase of frame N+1, the first transfer signal jumps to a high potential, the second transistor T2 turns on, and the first pre-storage capacitor Cst1 transmits a first data signal containing the reference voltage to one end of the pixel capacitor Clc through the second transistor T2. Then, the first transfer signal jumps to a low potential, and the second transistor T2 turns off. Simultaneously, the third transistor T3 turns on, and the second pre-storage capacitor Cst2 transmits a second data signal containing the grayscale voltage to the other end of the pixel capacitor Clc through the third transistor T3. Then, the first transfer signal jumps back to a normal potential, the third transistor T3 turns off, and the backlight-on phase of frame N+2 begins. Thus, the writing of the grayscale voltage and reference voltage for each pixel in the next frame is completed during the backlight-off phase.

[0053] It should be noted that in this embodiment, a high potential is defined as a potential higher than the reference voltage that ensures the N-type MOSFET is in the on state after writing; a low potential is defined as a potential lower than the reference voltage that ensures the P-type MOSFET is in the on state after writing; and a normal potential is defined as a potential that ensures both the N-type MOSFET and the P-type MOSFET are in the off state.

[0054] It should be noted that in the various embodiments of this application, R, G, and B three-color light are emitted frame by frame by backlight, and the visual persistence effect of the human eye is used to realize the display of color images. The order of R, G, and B backlight can be interchanged.

[0055] The above describes an in-plane switching pixel driving circuit for an IPS / FFS panel provided by embodiments of the present invention. The various embodiments are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0056] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can implement the described functions using different methods for each specific application, but such implementation should not be considered beyond the scope of the invention. The steps of the methods or algorithms described in connection with the embodiments disclosed herein can be implemented directly in hardware, software modules executed by a processor, or a combination of both. Software modules can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

Claims

1. An in-plane switching pixel driving circuit for an IPS / FFS panel, characterized in that, include: The system comprises a first transistor (T1), a first pre-storage capacitor (Cst1), a second transistor (T2), a pixel capacitor (Clc), a third transistor (T3), a second pre-storage capacitor (Cst2), and a fourth transistor (T4). The first source and drain of the first transistor (T1) are coupled to a first data signal line (Data1), and its second source and drain are coupled to the first source and drain of the second transistor (T2) and one end of the first pre-storage capacitor (Cst1). The second source and drain of the second transistor (T2) are coupled to one end of the pixel capacitor (Clc). The first source and drain of the fourth transistor (T4) are coupled to the second data signal line (Data2), and its second source and drain are coupled to the second source and drain of the first transistor (T1) and one end of the first pre-storage capacitor (Cst1). The drain of the transistor is coupled to the first source-drain of the third transistor (T3) and one end of the second pre-storage capacitor (Cst2); the second source-drain of the third transistor (T3) is coupled to the other end of the pixel capacitor (Clc). When the first transistor (T1), the second transistor (T2), the third transistor (T3), and the fourth transistor (T4) are all N-type MOS transistors, the gates of the first transistor (T1) and the fourth transistor (T4) are coupled to the control signal line (Scan), the gate of the second transistor (T2) is coupled to the first transfer signal line (Tran1), and the gate of the third transistor (T3) is coupled to the second transfer signal line (Tran2). The driving timing of the pixel driving circuit is configured as follows: During the backlight-on phase of the Nth frame, the control signal jumps to a high potential line by line, the first transistor (T1) and the fourth transistor (T4) are turned on synchronously, the first data signal line (Data1) stores the first data signal containing grayscale voltage to the first pre-storage capacitor (Cst1) through the first transistor (T1), and the second data signal line (Data2) stores the second data signal containing reference voltage to the second pre-storage capacitor (Cst2) through the fourth transistor (T4), and enters the backlight-off phase of the Nth frame; During the backlight-off phase of the Nth frame, the second transfer signal jumps to a high potential, the third transistor (T3) is turned on, the second pre-storage capacitor (Cst2) transmits the second data signal containing reference voltage to one end of the pixel capacitor (Clc) through the third transistor (T3), the second transfer signal jumps back to the normal potential, and the third transistor (T3) is turned off; When the first transfer signal jumps to a high potential, the second transistor (T2) turns on. After the first pre-storage capacitor (Cst1) transmits the first data signal containing the grayscale voltage to the other end of the pixel capacitor (Clc) through the second transistor (T2), the first transfer signal jumps back to the normal potential, the second transistor (T2) turns off, and the backlight on stage of the N+1th frame begins.

2. The pixel driving circuit according to claim 1, characterized in that, When the first transistor (T1), the second transistor (T2), and the fourth transistor (T4) are all N-type MOS transistors and the third transistor (T3) is a P-type MOS transistor, the gates of the first transistor (T1) and the fourth transistor (T4) are coupled to the control signal line (Scan), and the gates of the second transistor (T2) and the third transistor (T3) are coupled to the first transfer signal line (Tran1).

3. The pixel driving circuit according to claim 1 or 2, characterized in that, The ends of the first pre-storage capacitor (Cst1) and the second pre-storage capacitor (Cst2) furthest from the transistor are both coupled to the common signal line (Com).

4. The pixel driving circuit according to claim 1, characterized in that, During the backlight-on phase of the N+1th frame, the control signal jumps to a high potential line by line, and the first transistor (T1) and the fourth transistor (T4) are turned on synchronously. The first data signal line (Data1) stores the first data signal containing the reference voltage into the first pre-storage capacitor (Cst1) through the first transistor (T1), and the second data signal line (Data2) stores the second data signal containing the grayscale voltage into the second pre-storage capacitor (Cst2) through the fourth transistor (T4), thus entering the backlight-off phase of the N+1th frame. During the backlight off phase of the N+1th frame, the first transfer signal jumps to a high potential, the second transistor (T2) turns on, and the first pre-storage capacitor (Cst1) transmits the first data signal containing the reference voltage to one end of the pixel capacitor (Clc) through the second transistor (T2). Then, the first transfer signal jumps back to the normal potential, and the second transistor (T2) turns off. When the second transfer signal jumps to a high potential, the third transistor (T3) turns on. After the second pre-storage capacitor (Cst2) transmits the second data signal containing the grayscale voltage to the other end of the pixel capacitor (Clc) through the third transistor (T3), the second transfer signal jumps back to the normal potential, the third transistor (T3) turns off, and the backlight on stage of the N+2 frame begins.

5. The pixel driving circuit according to claim 2, characterized in that, The driving timing of the pixel driving circuit is configured as follows: During the backlight-on phase of the Nth frame, the control signal jumps to a high potential line by line, and the first transistor (T1) and the fourth transistor (T4) are turned on synchronously. The first data signal line (Data1) stores the first data signal containing the grayscale voltage into the first pre-storage capacitor (Cst1) through the first transistor (T1), and the second data signal line (Data2) stores the second data signal containing the reference voltage into the second pre-storage capacitor (Cst2) through the fourth transistor (T4), thus entering the backlight-off phase of the Nth frame.

6. The pixel driving circuit according to claim 5, characterized in that, During the backlight off phase of frame N, the first transfer signal jumps to a low potential, the third transistor (T3) turns on, and the second pre-storage capacitor (Cst2) transmits a second data signal containing a reference voltage to one end of the pixel capacitor (Clc) through the third transistor (T3). Then, the second transfer signal jumps back to a high potential, the third transistor (T3) turns off, and the second transistor (T2) turns on. The first pre-storage capacitor (Cst1) transmits a first data signal containing a grayscale voltage to the other end of the pixel capacitor (Clc) through the second transistor (T2). Then, the first transfer signal jumps back to a normal potential, the second transistor (T2) turns off, and the backlight on phase of frame N+1 begins.

7. The pixel driving circuit according to claim 1, characterized in that, During the backlight-on phase of the N+1th frame, the control signal jumps to a high potential line by line, and the first transistor (T1) and the fourth transistor (T4) are turned on synchronously. The first data signal line (Data1) stores the first data signal containing the reference voltage into the first pre-storage capacitor (Cst1) through the first transistor (T1), and the second data signal line (Data2) stores the second data signal containing the grayscale voltage into the second pre-storage capacitor (Cst2) through the fourth transistor (T4), thus entering the backlight-off phase of the N+1th frame. During the backlight off phase of frame N+1, the first transfer signal jumps to a high potential, the second transistor (T2) turns on, and the first pre-storage capacitor (Cst1) transmits a first data signal containing a reference voltage to one end of the pixel capacitor (Clc) through the second transistor (T2). Then, the first transfer signal jumps to a low potential, the second transistor (T2) turns off, and the third transistor (T3) turns on. The second pre-storage capacitor (Cst2) transmits a second data signal containing a grayscale voltage to the other end of the pixel capacitor (Clc) through the third transistor (T3). Then, the first transfer signal jumps back to a normal potential, the third transistor (T3) turns off, and the backlight on phase of frame N+2 begins.

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