Semiconductor structure and method of fabrication
By forming conductive pillars in front of the isolation structure as a height difference compensation, the problems of insufficient etching and material diffusion in the contact structure of the semiconductor structure are solved, thereby improving the yield and electrical connection stability of the semiconductor structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2023-04-04
- Publication Date
- 2026-07-28
AI Technical Summary
In the existing technology, the yield of semiconductor structures is poor, especially in the process of shrinking the feature size of MOSFET devices. Insufficient etching and etching misalignment of the contact structure lead to connection failure, and material diffusion affects performance.
Before forming the isolation structure, conductive pillars are first formed as compensation for the height difference. The morphology and size of the contact structure are controlled through two process steps. The conductive pillars are part of the contact structure and act as a diffusion barrier layer to prevent material diffusion and improve the contact area and stability.
By controlling the morphology and size of the contact structure through two process steps, insufficient etching and material diffusion are avoided, thereby improving the yield of semiconductor structures and the stability of electrical connections.
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Figure CN118824939B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and its fabrication method. Background Technology
[0002] With the continuous development of integrated circuit manufacturing technology, in order to improve the integration density of integrated circuits, while increasing the operating speed of memory and reducing its power consumption, for example, the feature size of metal-oxide-semiconductor field-effect transistor (MOSFET) devices is constantly shrinking, and MOSFET devices face a series of challenges.
[0003] MOSFET devices include vertical memory transistors, which are formed in the overlapping region where bit lines and word lines intersect. A vertical memory transistor has a width of 3F perpendicular to the word line and a width of 2F perpendicular to the bit line. The area required for a memory transistor on the substrate is 6F² (3F*2F, i.e., a 3×2 buried word line structure), where F is the minimum feature size. Vertical memory transistors reduce the horizontal linewidth by increasing the vertical linewidth, but this also results in a larger height difference between the contact plugs forming the connection array region and the peripheral region, thus introducing new problems.
[0004] Improving the yield of semiconductor structures with fewer fabrication steps has become an important problem that needs to be solved by those skilled in the art. Summary of the Invention
[0005] This disclosure provides a semiconductor structure and a method for its fabrication, which at least helps to improve the yield of the semiconductor structure.
[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate, the substrate including an array region and a peripheral region, wherein the surface of the array region has a first conductive structure and the surface of the peripheral region has a second conductive structure, the top surface of the first conductive structure being higher than the top surface of the second conductive structure; forming a conductive pillar, the conductive pillar being located on the top surface of the second conductive structure and electrically connected to the second conductive structure; forming an isolation structure, the isolation structure covering the surfaces of the substrate, the first conductive structure, the second conductive structure, and the conductive pillar; patterning the isolation structure to form a first groove and a second groove, the bottom of the first groove exposing the top surface of the first conductive structure, and the bottom of the second groove exposing a portion of the top surface of the conductive pillar; etching a portion of the thickness of the conductive pillar along the second groove to form a third groove, the sidewalls of the third groove retaining a portion of the width of the conductive pillar; and forming a first connecting pillar filling the first groove and a second connecting pillar filling the second groove and the third groove.
[0007] In some embodiments, the third groove is formed using an anisotropic etching process.
[0008] In some embodiments, the process steps for forming the third groove include: etching the conductive pillar using an anisotropic etching process until the bottom of the formed third groove exposes the top surface of the second conductive structure.
[0009] In some embodiments, the distance between the axis of the third groove and the axis of the second groove is less than the width of the conductive post located on the top sidewall of the third groove away from the substrate.
[0010] In some embodiments, the axis of the third groove overlaps with the axis of the second groove or deviates from the axis of the third groove by less than 1 / 5 of the width of the third groove.
[0011] In some embodiments, before forming the first groove and the second groove, the method further includes: forming at least one mask layer on the top surface of the isolation structure, using the mask layer as a mask, and etching the isolation structure to form the first groove and the second groove.
[0012] In some embodiments, the ratio between the height difference between the first conductive structure and the second conductive structure and the height of the conductive pillar is 1 to 3 along a direction perpendicular to the surface of the substrate.
[0013] In some embodiments, in a direction parallel to the surface of the substrate, the width of the bottom of the second groove is 1 to 3 times the maximum width of the third groove.
[0014] According to some embodiments of this disclosure, another aspect of this disclosure provides a semiconductor structure, including: a substrate, the substrate including an array region and a peripheral region, wherein the surface of the array region has a first conductive structure, the surface of the peripheral region has a second conductive structure, and the top surface of the first conductive structure is higher than the top surface of the second conductive structure; a conductive pillar, the conductive pillar being located on the top surface of the second conductive structure and in electrical contact with the second conductive structure; an isolation structure, the isolation structure covering the surfaces of the substrate, the first conductive structure, the second conductive structure, and the conductive pillar; a first connecting pillar, the first connecting pillar being located within the isolation structure and on the surface of the first conductive structure; and a second connecting pillar, the second connecting pillar being located within the isolation structure and on the second conductive structure, the conductive pillar surrounding the bottom side of the second connecting pillar.
[0015] In some embodiments, along a direction parallel to the surface of the substrate, the axis of the second connecting post overlaps with or deviates from the axis of the conductive post by less than 1 / 5 of the width of the second connecting post.
[0016] In some embodiments, the ratio between the height difference between the first conductive structure and the second conductive structure and the height of the conductive pillar is 1 to 3 along a direction perpendicular to the surface of the substrate.
[0017] The technical solutions provided in this disclosure have at least the following advantages:
[0018] In the technical solution provided by this disclosure, conductive pillars are formed before the isolation structure is formed. These conductive pillars can compensate for the height difference between the first and second connecting pillars. By changing the aspect ratio holes in the peripheral region from a single process step to two, the morphology and size of the contact structure can be controlled more accurately, avoiding problems such as insufficient etching or etching misalignment. It also avoids damage to the first conductive structure caused by the height difference between the holes in the peripheral region and the array region when etching the array region and the peripheral region simultaneously. After forming the second groove, a third groove is formed along the conductive pillar etched from the second groove. A portion of the width of the conductive pillar is retained on the sidewall of the third groove. The conductive pillar serves as part of the contact structure and also as a diffusion barrier layer, preventing the material of the second connecting pillar from diffusing into the isolation structure and the substrate, thus improving the yield of the semiconductor structure. Furthermore, due to the etching effect, the width of the formed holes tends to decrease towards the substrate. The retained conductive pillars can increase the contact area between the peripheral region contact structure and the second conductive structure, while avoiding the risk of electrical contact between the second connecting pillars far from the substrate. Here, "hole" refers to any one of the first groove, the second groove, and the third groove. Attached Figure Description
[0019] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0020] Figures 1 to 10 This is a schematic diagram of the semiconductor structure corresponding to each step in the method for preparing a semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation
[0021] As can be seen from the background technology, the yield of current semiconductor structures is not good.
[0022] Analysis revealed that one reason for the poor yield of semiconductor structures is that, due to advancements in advanced manufacturing processes, to improve the integration density and power of DRAM, 2D cell devices have been transformed into 3D stacked devices. This has led to a continuous increase in the height of the cell devices and the length of the contact structures. High aspect ratio vias often experience insufficient etching, resulting in open circuits between the contact structures and the conductive structures within the substrate. Furthermore, the materials forming the interconnects are generally diffusive tungsten and copper. With numerous conductive structures on the substrate surface, the diffused copper or tungsten can affect the performance of the semiconductor structure, thus impacting its yield.
[0023] This disclosure provides a method for fabricating a semiconductor structure. Conductive pillars are formed before forming the isolation structure. These conductive pillars can compensate for the height difference between the first and second connecting pillars. By changing the high aspect ratio holes in the peripheral region from a single process step to two, the morphology and size of the contact structure can be more accurately controlled, avoiding problems such as insufficient etching or etching misalignment. It also avoids damage to the first conductive structure caused by the height difference between the holes in the peripheral region and the array region when etching the array region and the peripheral region simultaneously. After forming the second groove, a third groove is formed by etching the conductive pillars along the portion of the second groove. A portion of the width of the conductive pillars is retained on the sidewalls of the third groove. These conductive pillars serve as part of the contact structure and also as a diffusion barrier layer, preventing material from the second connecting pillars from diffusing into the isolation structure and the substrate, thus improving the yield of the semiconductor structure. Furthermore, due to the etching effect, the width of the formed holes tends to decrease towards the substrate. The retained conductive pillars can increase the contact area between the peripheral region contact structure and the second conductive structure, while avoiding the risk of electrical contact between the second connecting pillars far from the substrate. Here, "hole" refers to any one of the first groove, the second groove, and the third groove.
[0024] Figures 1 to 10 This is a schematic diagram of the semiconductor structure corresponding to each step in the method for preparing a semiconductor structure according to an embodiment of the present disclosure.
[0025] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.
[0026] refer to Figure 1 The preparation method includes: providing a substrate 100, the substrate 100 including an array region 101 and a peripheral region 102, and the surface of the array region 101 having a first conductive structure 110, the surface of the peripheral region 102 having a second conductive structure 120, and the top surface of the first conductive structure 110 being higher than the top surface of the second conductive structure 120.
[0027] In some embodiments, the semiconductor structure can be a memory. The semiconductor structure includes an array region 101 and a peripheral region 102, with the peripheral region 102 surrounding the array region 101. The array region 101 is the core region of the memory, used for storing data; the peripheral region 102 is the control region of the memory, used for controlling the writing and reading of data in the array region 101. The array region 101 includes a storage capacitor and a switching transistor, wherein the storage capacitor is used to store data; the switching transistor in the array region 101 is used to control the input and output of data in the storage capacitor. The peripheral region 102 also includes a switching transistor, used to form a control circuit to control the writing and reading of data in the array region.
[0028] In some embodiments, the pattern density of the array region 101 is greater than the pattern density of the peripheral region 102. The array region 101 and the peripheral region 102 may include a plurality of spaced array structures formed on the substrate 100, and the array structures may be isolation structures or conductive structures.
[0029] In some embodiments, the array region 101 includes a plurality of spaced first conductive structures 110 located on the substrate 100. The first conductive structures 110 may be storage capacitors. A semiconductor layer 112 is located on the substrate 100, and the semiconductor layer 112 is part of the first conductive structures 110, i.e., the semiconductor layer 112 is part of the capacitor structure. The storage capacitor also includes a lower electrode 111, which may be a U-groove design, with the semiconductor layer 112 located within the U-groove and on the surface of the lower electrode 111.
[0030] In some embodiments, multiple storage capacitors share a common semiconductor layer 112, reducing the isolation structure between adjacent storage capacitors and increasing the storage area of the semiconductor layer 112. This is beneficial for increasing the storage area of the storage capacitors and improving the storage density of the integrated circuit. The semiconductor layer 112 can be made of polycrystalline silicon and is doped with N-type or P-type dopant elements. These N-type or P-type dopant elements can act as charge carriers, increasing the number of majority charge carriers and thus improving the mobility of majority charge carriers. This allows for good contact between the semiconductor layer 112 and the lower electrode 111, thereby reducing the contact resistance of the semiconductor structure. The lower electrode 111 can be made of tungsten, tantalum, tantalum nitride, or silver. The N-type dopant element can be a group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As), while the P-type dopant element can be a group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In).
[0031] In some embodiments, a dielectric layer (not shown) is further provided between the semiconductor layer 112 and the lower electrode 111. The dielectric layer is made of any one or more of silicon oxide, silicon nitride, and high-k materials. High-k materials may include hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanate.
[0032] In some embodiments, the second conductive structure 120 is a contact structure of the gate structure, a contact structure of the source, or a contact structure of the drain. The material of the second conductive structure 120 can be tungsten, tantalum, tantalum nitride, or silver. The low self-resistance of the metal is beneficial to reducing the contact resistance between the second conductive structure 120 and the source or drain.
[0033] In some embodiments, the end of the second conductive structure 120 away from the substrate 100 also serves as a pad. The size of the end of the second conductive structure 120 away from the substrate 100 is larger than the size of other areas of the second conductive structure 120. This is because the position of the pad is used as an alignment reference for the conductive structure subsequently formed thereon. The larger size of the pad also helps to reduce the contact resistance between the second conductive structure 120 and the conductive structure located thereon, and improve the contact performance.
[0034] In some embodiments, the semiconductor structure further includes an active layer 103, which is located within the substrate 100 of the array region 101 and the peripheral region 102. The active layer 103 may include a channel region and source and drain electrodes located on both sides of the channel region. The second conductive structure 120 is electrically connected to the source or drain electrode of the active layer 103.
[0035] In some embodiments, the semiconductor structure further includes a first isolation layer 104, which is located within the substrate 100 of the array region 101 and the peripheral region 102, and is located between adjacent active layers 103. The first isolation layer 104 may be a first isolation layer made of insulating material or a shallow trench isolation structure (STI).
[0036] In some embodiments, the surface of the substrate 100 has a second isolation layer 106, which is located in the array region 101 and the peripheral region 102. The second conductive structure 120 is located within the second isolation layer 106 in the peripheral region 102. The material of the second isolation layer 106 may be silicon oxide, silicon nitride, silicon carbonitride, or other materials with a high dielectric constant.
[0037] Among them, such as Figure 1 As shown, the second insulating layer 106 may cover the top surface of the second conductive structure 120. In some embodiments, the second insulating layer 106 exposes the top surface of the second conductive structure 120.
[0038] In some embodiments, the substrate 100 of the array region 101 has an electrical connection layer 105, which is used to connect the active layer 103 and the first conductive structure 110. The electrical connection layer 105 can be a single-layer structure or a stacked barrier layer, metal layer, and metal silicide layer.
[0039] In some embodiments, the second isolation layer 106 of the peripheral region 102 further includes a gate structure 107, which is a planar gate. The gate structure 107 can be a high-dielectric metal gate (HKMG), and includes a stacked capping layer, a barrier layer, and a conductive layer. The conductive layer is made of tungsten, copper, aluminum, or other metals, and the capping layer is a work function layer. The second conductive structure 120 is located on both sides of the gate structure 107, or the second conductive structure 120 is electrically connected to the conductive layer of the gate structure 107. The gate structure 107 is located above the channel region of the active layer 103, and a gate dielectric layer (not shown) is also present between the gate structure 107 and the active layer 103. In some embodiments, the gate structure 107 can be a doped polysilicon gate to reduce the threshold voltage between the gate structure and the channel region.
[0040] Continue to refer to Figure 1 A first isolation membrane 108, a first mask 109, and a second mask 113 having a first through hole 114 are formed on the second isolation layer 106 of the outer perimeter 102.
[0041] In some embodiments, in the same etching process, the etching rate of the first isolation film 108 is different from the etching rate of the first mask 109; in the same etching process, the etching rate of the second mask 113 is different from the etching rate of the first mask 109. Embodiments of this disclosure form grooves using self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP), reducing defects in lateral layout and improving the accuracy of the grooves.
[0042] In some embodiments, the first isolation film 108 can be made of silicon dioxide. The first isolation film 108 is removed after the conductive pillars are subsequently formed. The first isolation film 108 serves as a reference for positioning and etching to form the fourth groove. Because silicon is abundant and silicon dioxide has a high melting point, allowing for a wider operating temperature range, the fabrication cost of silicon dioxide is relatively low. Furthermore, the etching options between silicon dioxide and the subsequent first mask 109 (which serves as a hard mask) are relatively wide, allowing for a high degree of precision in the morphology of the first isolation film 108.
[0043] In some embodiments, the first mask 109 is a hard mask (HM) layer, which has a low etching rate. The first mask 109 is an inorganic thin film material generated by chemical vapor deposition (CVD). The material of the first mask 109 can be amorphous carbon, titanium nitride, silicon nitride, or silicon oxynitride. For example, the material of the first mask 109 is silicon nitride. Silicon nitride is characterized by a denser structure and higher chemical stability compared to silicon dioxide, therefore, silicon nitride can be used to mask ion diffusion and slow down the etching rate.
[0044] In some embodiments, the second mask 113 is a photomask or a photoresist layer. When the second mask 113 is a photoresist layer, the photoresist material (PR / BARC) is spin-coated onto the hard mask layer, and then a photolithography process is used to form the first via 114.
[0045] In some embodiments, the shape of the first through hole 114 can be arbitrary, only requiring the bottom surface of the fourth groove subsequently etched along the first through hole 114 to expose the top surface of the second conductive structure 120, and the exposed top surface area is greater than 1 / 3 of the top surface area of the second conductive structure 120. Thus, the contact surface between the conductive post subsequently formed in the fourth groove and the second conductive structure 120 is larger, resulting in better contact performance.
[0046] It is understandable that the minimum distance between adjacent first through holes 114 is not equal to 0 in order to ensure that the conductive pillars formed subsequently do not form electrical contact.
[0047] refer to Figure 2 The preparation method includes etching a first mask 109 and a first isolation film 108 along the inner wall surface of the first through hole to form a fourth groove 115. If the second isolation layer 106 also covers the top surface of the second conductive structure 120, the step of forming the fourth groove 115 further includes etching the second isolation layer 106 until the top surface of the second conductive structure 120 is exposed.
[0048] In some embodiments, a dry etching process is used to form the fourth groove 115. The bottom of the fourth groove 115 can completely expose the top surface of the second conductive structure 120. This allows for a larger contact area between the conductive pillars subsequently formed within the fourth groove 115 and the second conductive structure 120, thereby improving the contact performance between the conductive pillars and the second conductive structure 120. Alternatively, the bottom of the fourth groove 115 can expose only 1 / 3 of the top surface of the second conductive structure 120. This increases the alignment success rate during the fabrication of the fourth groove 115, and the greater distance between adjacent conductive pillars prevents short circuits, thus improving the yield of the semiconductor structure.
[0049] In some embodiments, during the etching of the fourth groove 115, due to the isotropic nature of the etching process, a portion of the side surface of the second conductive structure 120 away from the substrate 100 is also exposed in the fourth groove 115, which can increase the contact area between the second conductive structure 120 and the conductive post and improve the contact performance between the second conductive structure 120 and the conductive post.
[0050] Continue to refer to Figure 1 and Figure 2 The preparation method includes: removing the second mask 113.
[0051] In some embodiments, the preparation method may further include: removing the second mask 113 and the first mask 109.
[0052] refer to Figure 3 The preparation method includes: forming a conductive post 116, wherein the conductive post 116 is located on the top surface of the second conductive structure 120 and is electrically connected to the second conductive structure 120. The conductive post 116 is located in the fourth groove 115 (reference). Figure 2 )Inside.
[0053] In some embodiments, the process steps for fabricating the conductive pillar 116 include: forming a continuous conductive film on the surface of the fourth groove and the first mask 109, and then using a planarization process to remove the conductive film above the top surface of the first mask 109, with the remaining conductive film serving as the conductive pillar 116. The unremoved first mask 109 can serve as a protective layer for the first isolation film 108, preventing the surface of the first isolation film 108 from having numerous etching defects. The first mask 109 can also etch a barrier layer to prevent the planarization process from etching too many conductive pillars 116.
[0054] In some embodiments, the conductive post 116 can serve as a metal barrier layer for the second connecting post, which also protects the components from damage during various processes. For example, aluminum reacts with silicon, causing damage to the interface. Therefore, if aluminum wires are to be arranged near the first insulating film or insulating structure, a barrier layer such as a titanium compound must be formed between the silicon and aluminum interface to prevent damage to the interface. If the material of the second connecting post is copper, copper is more reactive than aluminum and can react with silicon dioxide, which is more stable than silicon. If copper diffuses into the silicon dioxide, copper particles will penetrate into the oxide film, causing leakage. The conductive post 116 can prevent the above situation from occurring.
[0055] In some embodiments, the material of the conductive post 116 includes a metal nitride, such as titanium nitride, titanium, or tungsten nitride. Metal nitrides are intermetallic compounds, and their unique electronic structure and metal-like properties give the conductive post 116 excellent electronic conductivity, which can improve the electrical connection performance between the second conductive structure 120 and the second connecting post. The material of the conductive post 116 may contain the same ions as the subsequently formed second connecting post, thereby increasing the adhesion between the conductive post 116 and the second connecting post and improving their contact performance.
[0056] In some embodiments, the material of the conductive post 116 is a metal silicide. The adhesion between the metal silicide and the first isolation film 108 is good and the work function difference is small. There are fewer interface state defects between the conductive post 116 and the first isolation film 108, which helps to ensure that the morphology of the conductive post 116 is not deformed.
[0057] In some embodiments, the ratio between the height difference between the first conductive structure 110 and the second conductive structure 120 and the height of the conductive post 116 along a direction perpendicular to the surface of the substrate 100 is 1 to 3. The ratio can be 1 to 2.6, 1 to 2.3, 1 to 1.9, 1.3 to 1.8, 1.5 to 2.8, or 1.7 to 3. The height of the conductive post 116 is used to mitigate the height difference between the first plug connecting the first conductive structure 110 and the second plug connecting the second conductive structure 120, which are formed simultaneously. When the height of the conductive post 116 is within the above range, the conductive post 116 can reduce damage to the first conductive structure 110 and improve the yield of the second groove during the simultaneous formation of the first and second grooves. Due to the etching effect of the etching process itself, the sidewalls of the formed second groove are sloped. When the height of the conductive post 116 is within the above range, the size of the end of the second groove furthest from the substrate 100 can be reduced, effectively avoiding short circuits between adjacent second grooves. The height of the conductive post 116 is any height difference between the bottom surface of the conductive post 116 near the substrate 100 and the top surface of the conductive post 116 away from the substrate 100.
[0058] In some embodiments, the height of the conductive pillar 116 along the direction perpendicular to the surface of the substrate 100 is 50 nm to 600 nm. The height of the conductive pillar 116 can be 53 nm to 540 nm, 128 nm to 580 nm, 264 nm to 598 nm, 386 nm to 530 nm, 102 nm to 395 nm, 68 nm to 460 nm, or 200 nm to 540 nm. Thus, with a suitable height for the conductive pillar 116, the width of the second groove can be reduced and the yield of the second groove can be improved during the subsequent formation of the first and second grooves in the same process.
[0059] refer to Figure 4 The preparation method includes: forming an isolation structure 117, wherein the isolation structure 117 covers the surface of the substrate 100, the first conductive structure 110, the second conductive structure 120, and the conductive pillar 116.
[0060] In some embodiments, the material of the isolation structure 117 may include silicon oxide, silicon nitride, silicon oxynitride, or a material with a high dielectric constant.
[0061] The first isolation membrane 108 is part of the isolation structure 117, or both the first isolation membrane 108 and the first mask 109 are part of the isolation structure 117, in order to save process, and the first mask can improve the structural stability of the isolation structure and prevent the outer contour of the second connecting post formed later from deforming.
[0062] refer to Figure 5 The preparation method includes: forming at least one mask layer on the top surface of the isolation structure 117.
[0063] In some embodiments, a mask layer is formed, and the mask layer 122 is a hard mask layer. The material of the hard mask layer may include silicon nitride, titanium nitride, or amorphous carbon. The mask layer 122 has a second via 123.
[0064] In some embodiments, the mask layer includes a first mask layer and a second mask layer stacked together, the second mask layer having a second via, and the first mask layer or the second mask layer being a hard mask layer. For example, the first mask layer is silicon nitride, and the second mask layer is amorphous carbon.
[0065] In some embodiments, the method further includes: a third mask layer located on the surface of the second mask layer, the third mask layer having a second through-hole therein. The third mask layer is a photomask or a photoresist layer.
[0066] In this embodiment, multiple mask layers are formed on the isolation structure 117, and the accuracy of the grooves formed by etching is improved by overlaying the multiple mask layers.
[0067] refer to Figure 6 The preparation method includes: a patterned isolation structure 117 forming a first groove 125 and a second groove 126, the bottom of the first groove 125 exposing the top surface of the first conductive structure 110, and the bottom of the second groove 126 exposing part of the top surface of the conductive pillar 116.
[0068] In some embodiments, the isolation structure 117 is etched to form a first groove 125 and a second groove 126, using a mask layer as a mask.
[0069] In some embodiments, a dry etching process is used to form the first groove 125 and the second groove 126. The dry etching process parameters include: a volume ratio of etching gas to oxygen of 5:1 to 1:10, and a reaction time of 1 s to 3600 s. The etching gas includes C2F2, CF4, CH2F2, CHF3, or C4F6; wherein the ratio of fluorine content to carbon content in the etching gas ranges from 1 / 4 to 1, and the higher the fluorine content in the etching gas, the faster the etching rate of the isolation structure 117.
[0070] refer to Figure 7 or Figure 9 The preparation method includes: etching a conductive post 116 of a certain thickness along the second groove 126 to form a third groove 127, wherein the sidewall of the third groove 127 retains a conductive post 116 of a certain width.
[0071] In some embodiments, an anisotropic etching process is used to form the third groove 127. The isotropic etching process forms the third groove 127, which exposes the conductive pillars 116 on the sidewalls of the third groove 127, that is, retains a portion of the width of the conductive pillars 116, and retains the conductive pillars 116 as a diffusion barrier layer for the subsequently formed second connecting pillar.
[0072] In some embodiments, referring to 10, the process step of forming the third groove 127 includes: etching the conductive pillar 116 until the bottom of the formed third groove 127 exposes the top surface of the second conductive structure 120. Due to the inherent characteristics of the conductive pillar 116, the resistance of the material constituting the conductive pillar 116 may be less than the resistance of the material of the second connecting pillar. This reduces the proportion of the conductive pillar 116 and the electrical contact between the second connecting pillar and the second conductive structure 120, thereby reducing the resistance of the contact structure of the peripheral region 102 and the contact resistance between the contact structure and the second conductive structure 120. That is, in this embodiment of the present disclosure, the resistance of the contact structure of the peripheral region 102 and the contact resistance can be macroscopically controlled by increasing the degree of etching the conductive pillar 116.
[0073] In some embodiments, the distance between the axis of the third groove 127 and the axis of the second groove 126 is less than the width of the conductive post 116 located on the top sidewall of the third groove 127 away from the substrate 100. The sidewalls of the third groove 127 expose the conductive post 116, so that the bottom of the subsequently formed second connecting post is covered by the conductive post 116, thereby avoiding the diffusion of the metal material constituting the second connecting post and improving the yield of the semiconductor structure.
[0074] In some embodiments, the axis of the third groove 127 overlaps with the axis of the second groove 126 or deviates from it by less than 1 / 5 of the width of the third groove. A small overlap or deviation indicates that the thickness of the conductive pillars 116 on the sidewall of the third groove 127 is relatively uniform, which results in a relatively good protection effect for the isolation structure 117 and the substrate 100.
[0075] In some embodiments, in a direction parallel to the surface of the substrate 100, the width of the bottom of the second groove 126 is 1 to 3 times the maximum width of the third groove 127. The width of the bottom of the second groove 126 is 1.3 to 2.8 times, 1.5 to 2.6 times, 1.8 to 3 times, or 1.6 to 2.2 times the maximum width of the third groove 127. The width ratio between the second groove 126 and the third groove 127 is used to form the cross-sectional area of the second connecting post in the second groove 126 and the third groove 127 to reduce the resistance of the second connecting post while improving the electrical connection stability of the semiconductor structure. The ratio range is also used to ensure that each sidewall of the third groove 127 still retains a conductive post with a certain thickness.
[0076] refer to Figure 8 or Figure 10 The preparation method includes: forming a first connecting post 131 that fills the first groove and a second connecting post 132 that fills the second groove and the third groove.
[0077] In some embodiments, the material of the first connecting post 131 includes tungsten, copper, aluminum, or silver.
[0078] In some embodiments, the material of the second connecting post 132 includes tungsten, copper, aluminum, or silver.
[0079] In some embodiments, before forming the first connecting post 131 and the second connecting post 132, a metal nitride layer is formed on the inner wall surface of the first groove and the second groove to prevent metal ions from the first connecting post 131 or the second connecting post 132 from diffusing into the isolation structure and causing a short circuit in some components within the isolation structure. Furthermore, the metal nitride layer ensures that metal ions within the first connecting post 131 and the second connecting post 132 do not diffuse, and the resistance of the first connecting post 131 and the second connecting post 132 does not increase, which is beneficial for improving the electrical performance of the semiconductor structure.
[0080] In the technical solution provided by this disclosure, conductive pillars 116 are formed before the isolation structure 117 is formed. The conductive pillars 116 can be used as compensation for the height difference between the first connecting pillar 131 and the second connecting pillar 132. By changing the aspect ratio hole of the peripheral area 102 from one process step to two process steps, the morphology and size of the contact structure can be controlled more accurately, avoiding problems such as insufficient etching or etching offset in the contact structure. It can also avoid the situation where the etching damages the first conductive structure 110 due to the height difference between the hole in the peripheral area 102 and the hole in the array area 101 when the array area 101 and the peripheral area 102 are etched at the same time. After forming the second groove 126, a third groove 127 is formed along the etched portion of the conductive post 116 in the second groove 126. The sidewalls of the third groove 127 retain a portion of the width of the conductive post 116. The conductive post 116 serves as part of the contact structure and also as a diffusion barrier layer, preventing material from the second connecting post 132 from diffusing into the isolation structure 117 and the substrate 100, thus improving the yield of the semiconductor structure. Furthermore, due to the etching effect, the width of the formed hole tends to decrease towards the substrate 100. Therefore, the retained conductive post 116 can increase the contact area between the contact structure of the peripheral region 102 and the second conductive structure 120, while avoiding the risk of electrical contact between the second connecting post 132 far from the substrate 100. Here, the hole refers to any one of the first groove 125, the second groove 126, and the third groove 127.
[0081] Accordingly, this disclosure also provides a semiconductor structure prepared using the preparation method provided in the above embodiments. The same components as in the above embodiments will not be described again here.
[0082] refer to Figure 8 or Figure 10 The semiconductor structure includes an array region 101 and a peripheral region 102. The peripheral region 102 surrounds the array region 101. The array region 101 is the core area of the memory, used to store data; the peripheral region 102 is the control area of the memory, used to control the writing and reading of data in the array region 101.
[0083] In some embodiments, the semiconductor structure includes: a substrate 100, the substrate 100 including an array region 101 and a peripheral region 102, and the surface of the array region 101 having a first conductive structure 110, the surface of the peripheral region 102 having a second conductive structure 120, and the top surface of the first conductive structure 110 being higher than the top surface of the second conductive structure 120.
[0084] In some embodiments, array region 101 includes a plurality of spaced-apart first conductive structures 110 on substrate 100. The first conductive structures 110 may be storage capacitors. A semiconductor layer 112 is located on substrate 100 and is part of the first conductive structures 110, i.e., the semiconductor layer 112 is part of the capacitor structure. The storage capacitor also includes a lower electrode 111, which may be a U-groove design, with the semiconductor layer 112 located within the U-groove and on the surface of the lower electrode 111. The semiconductor layer 112 is shared among the plurality of storage capacitors.
[0085] In some embodiments, a dielectric layer (not shown) is further provided between the semiconductor layer 112 and the lower electrode 111, and the dielectric layer is made of any one or more of silicon oxide, silicon nitride, and high-k materials.
[0086] In some embodiments, the second conductive structure 120 is a contact structure of the gate structure, a contact structure of the source, or a contact structure of the drain. The material of the second conductive structure 120 can be tungsten, tantalum, tantalum nitride, or silver. The end of the second conductive structure 120 away from the substrate 100 also serves as a pad, and the size of the end of the second conductive structure 120 away from the substrate 100 is larger than the size of other areas of the second conductive structure 120.
[0087] In some embodiments, the semiconductor structure further includes an active layer 103, which is located within the substrate 100 of the array region 101 and the peripheral region 102. The active layer 103 may include a channel region and source and drain electrodes located on both sides of the channel region. The second conductive structure 120 is electrically connected to the source or drain electrode of the active layer 103.
[0088] In some embodiments, the semiconductor structure further includes a first isolation layer 104, which is located within the substrate 100 of the array region 101 and the peripheral region 102, and is located between adjacent active layers 103. The first isolation layer 104 may be a first isolation layer made of insulating material or a shallow trench isolation structure.
[0089] In some embodiments, the surface of the substrate 100 has a second isolation layer 106, which is located in the array region 101 and the peripheral region 102. The second conductive structure 120 is located within the isolation layer 106 in the peripheral region 102. The material of the second isolation layer 106 may be silicon oxide, silicon nitride, silicon carbonitride, or other materials with a high dielectric constant.
[0090] In some embodiments, the substrate 100 of the array region 101 has an electrical connection layer 105, which is used to connect the active layer 103 and the first conductive structure 110. The electrical connection layer 105 can be a single-layer structure or a stacked barrier layer, metal layer, and metal silicide layer.
[0091] In some embodiments, the second isolation layer 106 of the peripheral region 102 further includes a gate structure 107, which is a planar gate. The gate structure 107 can be a high-dielectric metal gate (HKMG) and includes a stacked capping layer, a barrier layer, and a conductive layer. The second conductive structure 120 is located on both sides of the gate structure 107, or the second conductive structure 120 is electrically connected to the conductive layer of the gate structure 107. The gate structure 107 is located above the channel region of the active layer 103, and a gate dielectric layer is further provided between the gate structure 107 and the active layer 103.
[0092] In some embodiments, the semiconductor structure includes a conductive pillar 116, which is located on the top surface of the second conductive structure 120 and is in electrical contact with the second conductive structure 120.
[0093] In some embodiments, the conductive post 116 can serve as a metal barrier layer for the second connecting post 132, and the metal barrier layer can also protect the components from damage during various processes. The material of the conductive post 116 includes a metal nitride, such as titanium nitride, titanium, or tungsten nitride. The material of the conductive post 116 may have the same ions as the second connecting post 132, thereby increasing the adhesion between the conductive post 116 and the second connecting post 132 and improving their contact performance. In some embodiments, the material of the conductive post 116 is a metal silicide.
[0094] In some embodiments, the ratio between the height difference between the first conductive structure 110 and the second conductive structure 120 and the height of the conductive post 116 along a direction perpendicular to the surface of the substrate 100 is 1 to 3. The height of the conductive post 116 is either the height difference between the contact surface between the conductive post 116 and the second conductive structure 120 and the top surface of the conductive post 116 away from the substrate 100, or any height difference between the bottom surface of the conductive post 116 near the substrate 100 and the top surface away from the substrate 100.
[0095] In some embodiments, the height of the conductive pillar 116 along the direction perpendicular to the surface of the substrate 100 is 50 nm to 600 nm. The height of the conductive pillar 116 is 53 nm to 540 nm, 128 nm to 580 nm, 264 nm to 598 nm, 386 nm to 530 nm, 102 nm to 395 nm, 68 nm to 460 nm, or 200 nm to 540 nm.
[0096] In some embodiments, the conductive post 116 may also be located on the side of the second conductive structure 120 and within the second insulating layer 106.
[0097] In some embodiments, the semiconductor structure includes an isolation structure 117 covering the surfaces of the substrate 100, the first conductive structure 110, the second conductive structure 120, and the conductive pillars 116.
[0098] In some embodiments, the isolation structure 117 may be a single-layer structure, and the material of the isolation structure may include silicon oxide, silicon nitride, silicon oxynitride, or a material with a high dielectric constant.
[0099] In some embodiments, the isolation structure 117 can be a multi-layer structure, such as an isolation structure comprising a first isolation film, a first mask, and a second isolation film stacked together. The first isolation film is located on the substrate 100 and the surface of the second conductive structure 120, the first isolation film and the first mask are located on the side of the conductive pillar 116, and the second isolation film is located on the surface of the conductive pillar 116 and the surface of the first conductive structure 110.
[0100] In some embodiments, the materials of the first and second isolation films may be silicon oxide, silicon nitride, silicon oxynitride, or materials with high dielectric constants. The material of the first mask may be silicon nitride, titanium nitride, or amorphous carbon.
[0101] In some embodiments, the semiconductor structure includes a first connection post 131, which is located within the isolation structure 117 and on the surface of the first conductive structure 110.
[0102] In some embodiments, the material of the first connecting post 131 includes tungsten, copper, aluminum, or silver. A metal nitride layer is also present between the first connecting post 131 and the isolation structure 117.
[0103] In some embodiments, the semiconductor structure includes: a second connecting post 132, the second connecting post 132 being located within the isolation structure 117 and on the second conductive structure 120, and a conductive post 116 surrounding the bottom side of the second connecting post 132.
[0104] In some embodiments, the material of the second connecting post 132 includes tungsten, copper, aluminum, or silver. A metal nitride layer is also present between the second connecting post 132 and the isolation structure 117.
[0105] In some embodiments, along a direction parallel to the surface of the substrate 100, the axis of the second connecting post 132 overlaps with the axis of the conductive post 116 or deviates from it by less than 1 / 5 of the width of the second connecting post 132.
[0106] refer to Figure 8A conductive post 116 is provided between the second connecting post 132 and the second conductive structure 120. The conductive post 116 serves as an etching protection layer to prevent the etching process from causing etching damage to the second conductive structure 120, thereby affecting the electrical performance and stability of the second conductive structure 120.
[0107] refer to Figure 10 The second connecting post 132 is in direct contact with the second conductive structure 120. By reducing the proportion of the conductive post 116 and the electrical contact between the second connecting post 132 and the second conductive structure 120, the resistance of the contact structure of the peripheral region 102 and the contact resistance between the contact structure and the second conductive structure 120 are reduced. That is, the embodiments of this disclosure can macroscopically control the resistance of the contact structure of the peripheral region 102 and the contact resistance by increasing the degree of etching the conductive post 116.
[0108] In some embodiments, the conductive pillar 116 serves as part of the contact structure and also as a diffusion barrier layer, preventing the material of the second connecting pillar 132 from diffusing into the isolation structure 117 and the substrate 100, which is beneficial for improving the yield of the semiconductor structure. Furthermore, due to the etching effect, the width of the formed second connecting pillar 132 tends to decrease along the direction close to the substrate. Therefore, the retained conductive pillar 116 can increase the contact area between the contact structure of the peripheral region 102 and the second conductive structure 120, while avoiding the risk of electrical contact between the second connecting pillars 132 far from the substrate 100.
[0109] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.
Claims
1. A method of fabricating a semiconductor structure, characterized by, include: A substrate is provided, the substrate including an array region and a peripheral region, wherein the surface of the array region has a first conductive structure, the surface of the peripheral region has a second conductive structure, and the top surface of the first conductive structure is higher than the top surface of the second conductive structure; A conductive pillar is formed, which is located on the top surface of the second conductive structure and is electrically connected to the second conductive structure. An isolation structure is formed, which covers the surfaces of the substrate, the first conductive structure, the second conductive structure, and the conductive pillars; The isolation structure is graphically represented to form a first groove and a second groove, the bottom of the first groove exposing the top surface of the first conductive structure, and the bottom of the second groove exposing the top surface of the conductive post portion; The conductive pillar is etched along the second groove until the bottom of the formed third groove exposes the top surface of the second conductive structure, and the sidewall of the third groove retains a portion of the width of the conductive pillar; A first connecting post is formed that fills the first groove and a second connecting post that fills the second groove and the third groove. The second connecting post penetrates the conductive post and is in direct contact with the second conductive structure. The conductive post surrounds the bottom side of the second connecting post and serves as a diffusion barrier layer for the second connecting post. The material of the conductive post includes metal nitride or metal silicide.
2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The process steps for forming the third groove include: etching the conductive pillar using an anisotropic etching process until the bottom of the formed third groove exposes the top surface of the second conductive structure.
3. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The distance between the axis of the third groove and the axis of the second groove is less than the width of the conductive post located on the top sidewall of the third groove away from the substrate.
4. The method of claim 3, wherein the semiconductor structure is prepared by a method comprising: The axis of the third groove overlaps with the axis of the second groove or deviates from it by less than 1 / 5 of the width of the third groove.
5. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: Before forming the first groove and the second groove, the method further includes: forming at least one mask layer on the top surface of the isolation structure, using the mask layer as a mask, and etching the isolation structure to form the first groove and the second groove.
6. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: Along a direction perpendicular to the surface of the substrate, the ratio between the height difference between the first conductive structure and the second conductive structure and the height of the conductive pillar is 1 to 3.
7. The method of claim 1, wherein the semiconductor structure is formed by a method comprising: In a direction parallel to the surface of the base, the width of the bottom of the second groove is 1 to 3 times the maximum width of the third groove.
8. A semiconductor structure, characterized by The semiconductor structure is fabricated using the method described in any one of claims 1-7, wherein the semiconductor structure comprises: The substrate includes an array region and a peripheral region, wherein the surface of the array region has a first conductive structure and the surface of the peripheral region has a second conductive structure, and the top surface of the first conductive structure is higher than the top surface of the second conductive structure. A conductive post, wherein the conductive post is located on the top surface of the second conductive structure and is in electrical contact with the second conductive structure; An isolation structure covering the surfaces of the substrate, the first conductive structure, the second conductive structure, and the conductive pillars; A first connecting post is located within the isolation structure and on the surface of the first conductive structure; The second connecting post is located within the isolation structure and on the second conductive structure. The conductive post surrounds the bottom side of the second connecting post, penetrates the conductive post and is in direct contact with the second conductive structure. The conductive post serves as a diffusion barrier layer for the second connecting post. The material of the conductive post includes metal nitrides or metal silicides.
9. The semiconductor structure of claim 8, wherein, Along a direction parallel to the surface of the substrate, the axis of the second connecting post overlaps with or deviates from the axis of the conductive post by less than 1 / 5 of the width of the second connecting post.
10. The semiconductor structure of claim 8, wherein, Along a direction perpendicular to the surface of the substrate, the ratio between the height difference between the first conductive structure and the second conductive structure and the height of the conductive pillar is 1 to 3.