Semiconductor structure and method of manufacturing the same, electronic device

Abstract

A semiconductor structure, a manufacturing method thereof and an electronic device. The semiconductor structure comprises a substrate and a stack structure on the substrate, the stack structure comprising M conductive parts stacked in sequence from top to bottom, and a first connecting part and a second connecting part arranged along a first horizontal direction, the first connecting part electrically connected with a sidewall of an i-th conductive part and a sidewall of a j-th conductive part, the second connecting part electrically connected with a sidewall of an m-th conductive part and a sidewall of an n-th conductive part, a projection of the i-th conductive part on the substrate partially overlaps with a projection of the n-th conductive part on the substrate, and a size of the i-th conductive part in the first horizontal direction is smaller than a size of the n-th conductive part in the first horizontal direction, wherein M is a positive integer greater than or equal to 4, each of i, j, m and n is a positive integer less than or equal to M, i < j, m < n, i ≠ m, and j-i = n-m. The semiconductor structure can reduce the number of conductive plugs required and reduce the area occupied by the interconnection part.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and particularly relate to a semiconductor structure, a manufacturing method thereof, and an electronic device. BACKGROUND

[0002] To improve the performance and device density of semiconductor devices, three-dimensionally stacked semiconductor devices have been developed. For example, in a three-dimensionally stacked semiconductor device, two or more transistors can be vertically stacked.

[0003] However, in manufacturing a three-dimensionally stacked semiconductor device, to realize the mutual electrical connection between the vertically stacked transistors and the mutual electrical connection between the vertically stacked transistors and other components and / or external circuits, corresponding connection / contact structures need to be provided, making the structure of the three-dimensionally stacked semiconductor device itself and the manufacturing process thereof more complex and facing various challenges. SUMMARY

[0004] According to a first aspect of embodiments of the present disclosure, a semiconductor structure is provided, comprising: a substrate and a stacked structure located on the substrate. The stacked structure comprises M conductive parts stacked in order from top to bottom, and a first connection part and a second connection part arranged along a first horizontal direction, the first connection part being electrically connected to a sidewall of an i-th conductive part and a sidewall of a j-th conductive part among the M conductive parts, the second connection part being electrically connected to a sidewall of an m-th conductive part and a sidewall of an n-th conductive part among the M conductive parts, a projection of the i-th conductive part on the substrate and a projection of the n-th conductive part on the substrate partially overlap, a size of the i-th conductive part in the first horizontal direction is smaller than a size of the n-th conductive part in the first horizontal direction, wherein M is a positive integer greater than or equal to 4, each of i, j, m, and n is a positive integer less than or equal to M, i < j, m < n, i ≠ m, and j-i = n-m.

[0005] In some embodiments, the first connection part and the second connection part are located on the same side of the M conductive parts, and a projection of the first connection part on the substrate and a projection of the second connection part on the substrate do not overlap.

[0006] In some embodiments, m > j.

[0007] In some embodiments, the first connection part and the second connection part are located on opposite sides of the M conductive parts.

[0008] In some embodiments, m > j or m < j.

[0009] In some embodiments, ji>1, the semiconductor structure further includes: a first insulating pattern, located between the i+1th conductive part to the j-1th conductive part among the M conductive parts and the first connecting part; a second insulating pattern, located between the m+1th conductive part to the n-1th conductive part among the M conductive parts and the second connecting part.

[0010] In some embodiments, the stacked structure further includes M transistors stacked sequentially, the kth conductive portion among the M conductive portions and the kth transistor among the M transistors are located at the same level and coupled to each other, where k is a positive integer, k=1, 2, 3,…, M.

[0011] In some embodiments, the stacked structure further includes M conductive lines stacked sequentially, wherein the kth conductive line among the M conductive lines is located at the same level as the kth conductive portion and the kth transistor, and the kth conductive portion is coupled to the kth transistor respectively through the kth wire.

[0012] In some embodiments, the M transistors are transistors of the same conductivity type, the first connection portion is electrically connected to the gate of one of the i-th transistor and the j-th transistor, the first connection portion is also electrically connected to the source or drain of the other of the i-th transistor and the j-th transistor, the second connection portion is electrically connected to the gate of one of the m-th transistor and the n-th transistor, and the second connection portion is also electrically connected to the source or drain of the other of the m-th transistor and the n-th transistor; or, the i-th transistor and the j-th transistor among the M transistors are transistors of different conductivity types, the first connection portion is electrically connected to the gate of the i-th transistor and the gate of the j-th transistor, the m-th transistor and the n-th transistor among the M transistors are transistors of different conductivity types, and the second connection portion is electrically connected to the gate of the m-th transistor and the gate of the n-th transistor.

[0013] According to a second aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: providing an initial semiconductor structure, wherein the initial semiconductor structure includes an initial stacking structure located on a substrate, the initial stacking structure including a plurality of levels, each level including a first layer and a second layer stacked in sequence; etching the initial stacking structure to form a stepped structure extending along a first horizontal direction, wherein the stepped structure includes a first step portion and a second step portion, the stepped structure including M levels from top to bottom, the first step portion including the i-th level to the j-th level of the M levels, the second step portion including the m-th level to the n-th level of the M levels, M being a positive integer greater than or equal to 4, each of i, j, m, and n being a positive integer less than or equal to M, i <j,m<n,i≠m,且j-i=n-m;形成第一牺牲图案和第二牺牲图案,其中,第一牺牲图案与第一台阶部的第i个层级中的第一层的侧壁和第j个层级中的第一层的侧壁相连,第二牺牲图案与第二台阶部的第m个层级中的第一层的侧壁和第n个层级中的第一层的侧壁相连;形成覆盖第一牺牲图案和第二牺牲图案的平坦化层;刻蚀初始堆叠结构位于平坦化层在第二水平方向两侧的部分,以形成垂直开口,其中,垂直开口暴露阶梯结构、第一牺牲图案和第二牺牲图案的部分侧壁,第二水平方向与第一水平方向相交;从垂直开口横向刻蚀去除阶梯结构中的M个层级中的第一层以及第一牺牲图案和第二牺牲图案,以将阶梯结构中的所述M个层级中的第一层替换为导电部,将第一牺牲图案替换为第一连接部,并将第二牺牲图案替换为第二连接部,其中,第一连接部与第i层级中的导电部的侧壁和第j层级中的导电部的侧壁电连接,第二连接部与第m层级中的导电部的侧壁和第n层级中的导电部的侧壁电连接,第i层级中的导电部在基底上的正投影与第n层级中的导电部在基底上的正投影部分交叠,第i层级中的导电部在第一水平方向上的尺寸小于第n层级中的导电部在第一水平方向上的尺寸。

[0014] In some embodiments, ji>1, etching the initial stacking structure to form a stepped structure includes: etching the initial stacking structure to form an initial stepped structure, wherein the initial stepped structure includes a first initial step portion corresponding to the first step portion and a second initial step portion corresponding to the second step portion; forming a first isolation pattern, wherein the first isolation pattern covers a sidewall of the initial stepped structure; etching the first initial step portion and the second initial step portion to expose a sidewall of the first layer in the i-th level in the first initial step portion and a sidewall of the first layer in the m-th level in the second initial step portion; forming a second isolation pattern, wherein the second isolation pattern covers a sidewall of the first layer in the i-th level in the first initial step portion and a sidewall of the first layer in the m-th level in the second initial step portion. ; Continue etching the first initial step portion and the second initial step portion to expose the side walls of the first layer in the i+1th to j-1th levels in the first initial step portion and the side walls of the first layer in the m+1th to n-1th levels in the second initial step portion; laterally etch and remove portions of the first layer in the i+1th to j-1th levels in the first initial step portion and portions of the first layer in the m+1th to n-1th levels in the second initial step portion to form corresponding horizontal openings; form an insulating pattern filling the corresponding horizontal openings; continue etching the first initial step portion and the second initial step portion to expose the side walls of the first layer in the jth level in the first initial step portion and the side walls of the first layer in the nth level in the second initial step portion; remove the second isolation pattern.

[0015] In some embodiments, the manufacturing method further includes: before removing the second isolation pattern, laterally etching and removing a portion of the first layer in the j-th level in the first stepped portion and a portion of the first layer in the n-th level in the second stepped portion.

[0016] In some embodiments, ji=1, the first connection portion and the second connection portion are located on the same side of the conductive portion in the M levels, and the manufacturing method further includes: before forming the first sacrificial pattern and the second sacrificial pattern, laterally etching and removing a portion of the first layer in the i-th level and a portion of the first layer in the j-th level in the first step portion, as well as a portion of the first layer in the m-th level and a portion of the first layer in the n-th level in the second step portion.

[0017] In some embodiments, ji=1, the first connection portion and the second connection portion are located on opposite sides of the conductive portion in the M levels; etching the initial stacking structure to form a stepped structure, including: etching the initial stacking structure to form an initial stepped structure, wherein the initial stepped structure includes a first initial step portion corresponding to the first step portion and a second initial step portion corresponding to the second step portion; forming a first isolation pattern, wherein the first isolation pattern covers the sidewalls of the initial stepped structure; etching the first initial step portion and the second initial step portion to expose the sidewalls of the first layer in the i-th level and the sidewalls of the first layer in the j-th level in the first initial step portion and the sidewalls of the first layer in the m-th level and the sidewalls of the first layer in the n-th level in the second initial step portion; and laterally etching to remove a portion of the first layer in the i-th level and a portion of the first layer in the j-th level in the first initial step portion and a portion of the first layer in the m-th level and a portion of the first layer in the n-th level in the second initial step portion.

[0018] According to a third aspect of an embodiment of the present disclosure, an electronic device is provided, comprising a processor and a memory. The memory is coupled to the processor, and at least one of the memory and the processor comprises the semiconductor structure provided in any embodiment of the present disclosure.

[0019] In the embodiments of the present disclosure, regular internal interconnection of different conductive parts is achieved by providing connecting parts within the stacked structure, thereby reducing the number of conductive plugs required and the area occupied by the interconnected parts; at the same time, these connecting parts can be formed synchronously to simplify the manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of a partial cross-sectional structure of a semiconductor structure;

[0021] Figure 2A A schematic diagram of a partial structure of a semiconductor structure provided in some embodiments of the present disclosure;

[0022] Figure 2B A schematic diagram of a partial cross-sectional structure of a semiconductor structure provided in some embodiments of the present disclosure;

[0023] Figure 2C A schematic diagram of a partial cross-sectional structure of a semiconductor structure provided in some other embodiments of the present disclosure;

[0024] Figure 2D A schematic diagram of a partial cross-sectional structure of a semiconductor structure provided in some further embodiments of the present disclosure;

[0025] Figure 2E A schematic diagram of a partial cross-sectional structure of a semiconductor structure provided in yet other embodiments of the present disclosure;

[0026] Figure 3A and Figure 3B A schematic diagram of a partial planar structure of two levels of a semiconductor structure provided in some embodiments of the present disclosure;

[0027] Figure 3C A schematic diagram of a CMOS circuit structure;

[0028] Figure 3D and Figure 3E A schematic diagram of a partial planar structure of two levels of a semiconductor structure provided in some other embodiments of the present disclosure;

[0029] Figure 3F A schematic diagram of a circuit structure of a sense amplifier (SA);

[0030] Figure 4 A schematic flow chart of a method for manufacturing a semiconductor structure provided in some embodiments of the present disclosure;

[0031] Figure 5A A schematic top view of a structure obtained according to step S100 provided in some embodiments of the present disclosure;

[0032] Figure 5B For the Figure 5A Schematic diagram of the cross section taken along line K1-K2;

[0033] Figure 6A A schematic top view of a structure obtained according to step S200 provided in some embodiments of the present disclosure;

[0034] Figure 6B For the Figure 6A A schematic cross-sectional view taken along line A1-A2 in FIG.

[0035] Figure 6C A schematic cross-sectional view of a structure obtained according to step S300 provided in some embodiments of the present disclosure;

[0036] Figure 6D A schematic cross-sectional view of a structure obtained according to step S300 provided in some other embodiments of the present disclosure;

[0037] Figure 7A A schematic cross-sectional view of a structure obtained according to step S210 provided in some embodiments of the present disclosure;

[0038] Figure 7B A schematic cross-sectional view of a structure obtained according to step S211 provided in some embodiments of the present disclosure;

[0039] Figure 7C A schematic cross-sectional view of a structure obtained according to step S212 provided in some embodiments of the present disclosure;

[0040] Figure 7D A schematic cross-sectional view of a structure obtained according to step S213 provided in some embodiments of the present disclosure;

[0041] Figure 7E A schematic cross-sectional view of a structure obtained according to step S300 provided in some other embodiments of the present disclosure;

[0042] Figure 8A A schematic cross-sectional view of a structure obtained according to step S220 provided in some embodiments of the present disclosure;

[0043] Figure 8B A schematic cross-sectional view of a structure obtained according to step S221 provided in some embodiments of the present disclosure;

[0044] Figure 8C A schematic cross-sectional view of a structure obtained according to step S222 and step S223 provided in some embodiments of the present disclosure;

[0045] Figure 8D A schematic cross-sectional view of a structure obtained according to step S224 provided in some embodiments of the present disclosure;

[0046] Figure 8E A schematic cross-sectional view of a structure obtained according to step S225 and step S226 provided in some embodiments of the present disclosure;

[0047] Figure 8F A schematic cross-sectional view of a structure obtained according to step S227 and step S228 provided in some embodiments of the present disclosure;

[0048] Figure 8G A schematic cross-sectional view of a structure obtained according to step S300 provided in some further embodiments of the present disclosure;

[0049] Figure 9A A schematic cross-sectional view of a structure obtained according to step S220 provided in some other embodiments of the present disclosure;

[0050] Figure 9B A schematic cross-sectional view of a structure obtained according to step S221 provided in some other embodiments of the present disclosure;

[0051] Figure 9C A schematic cross-sectional view of a structure obtained according to step S222 and step S223 provided in some other embodiments of the present disclosure;

[0052] Figure 9D A schematic cross-sectional view of a structure obtained according to step S224, step S225, and step S226 provided in some embodiments of the present disclosure;

[0053] Figure 9ESchematic cross-sectional view of the structure obtained according to step S227 and step S228 provided in some other embodiments of the present disclosure;

[0054] Figure 9F A schematic cross-sectional view of a structure obtained according to step S300 provided in some other embodiments of the present disclosure;

[0055] Figure 10 A schematic cross-sectional view of a structure obtained according to step S400 provided in some embodiments of the present disclosure;

[0056] Figure 11A A schematic top view of a structure obtained according to step S500 provided in some embodiments of the present disclosure;

[0057] Figure 11B For the Figure 11A A schematic cross-sectional view taken along line B1-B2 in FIG.

[0058] Figure 12 A schematic cross-sectional view of a structure obtained according to step S600 provided in some embodiments of the present disclosure.

[0059] Figure 13 A schematic block diagram of the structure of an electronic device provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0060] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and examples. Although the accompanying drawings illustrate exemplary implementations of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0061] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0062] It will be understood that the meanings of “on,” “over,” and “over” throughout this disclosure should be interpreted in the broadest manner, such that “on” not only means being “on” something with no intervening features or layers (i.e., directly on something), but also includes being “on” something with intervening features or layers.

[0063] In the embodiments of the present disclosure, the terms "first," "second," "third," etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0064] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is smaller than the extent of the lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is smaller than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0065] In the embodiments of the present disclosure, the term "coupling" refers to two (or more) conductive structures being operably connected to each other. Depending on actual needs, it may include but is not limited to the following situations: 1) the two conductive structures are directly electrically connected; 2) the two conductive structures are indirectly electrically connected (through other conductive structures); 3) although the two conductive structures are not electrically connected (for example, an insulating layer is provided between the two), one of the two conductive structures can control the electrical properties of the other of the two conductive structures in response to an electrical signal, for example, the gate (or word line) is coupled with the active area (or channel area).

[0066] It should be noted that the technical solutions and technical features described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0067] Figure 1 This is a schematic diagram of a partial cross-sectional structure of a semiconductor structure, which can be used as a part of a three-dimensional stacked semiconductor device to realize the mutual electrical connection between transistors and / or other components in the three-dimensional stacked semiconductor device and the electrical connection between transistors and / or other components in the three-dimensional stacked semiconductor device and external circuits. Figure 1 As shown, the semiconductor structure includes a plurality of conductive layers CL1-CL8 stacked on a substrate 100, and the ends of the plurality of conductive layers CL1-CL8 are formed into a stepped structure; through the conductive layers CL1-CL8 and the conductive plugs CP1-CP8 located on the ends of the conductive layers CL1-CL8, the mutual electrical connection between the transistors and / or other components in the three-dimensional stacked semiconductor device and the electrical connection between the transistors and / or other components in the three-dimensional stacked semiconductor device and the external circuit can be achieved. In other words, in order to achieve the above-mentioned electrical connection, it is usually necessary to provide a stepped structure, a conductive plug and an external winding. Currently, with the increase in the number of stacked layers in the three-dimensional stacked semiconductor device, the area occupied by the interconnection part (i.e., the conductive plug and the stepped structure) increases sharply, which is not conducive to the miniaturization of the device.

[0068] It should be noted that Figure 1The number of conductive layers and the number of conductive plugs are exemplary; in addition, it can be understood that Figure 1 The unmarked layers are dielectric layers and / or insulating layers.

[0069] At least some embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a substrate and a stacked structure located on the substrate. The stacked structure includes M conductive parts stacked in sequence from top to bottom and a first connecting part and a second connecting part arranged along a first horizontal direction, the first connecting part is electrically connected to the side wall of the i-th conductive part and the side wall of the j-th conductive part among the M conductive parts, the second connecting part is electrically connected to the side wall of the m-th conductive part and the side wall of the n-th conductive part among the M conductive parts, the orthographic projection of the i-th conductive part on the substrate partially overlaps with the orthographic projection of the n-th conductive part on the substrate, the size of the i-th conductive part in the first horizontal direction is smaller than the size of the n-th conductive part in the first horizontal direction, wherein M is a positive integer greater than or equal to 4, each of i, j, m, and n is a positive integer less than or equal to M, and i <j,m<n,i≠m,且j-i=n-m。在本公开的实施例中,通过设置在堆叠结构内的连接部实现不同导电部的有规律的内部互连,从而可以减少需要用到的导电插塞的数量,并减少互连部分的占用面积;同时,这些连接部可以同步形成以简化制造工艺。

[0070] Figure 2A A schematic diagram of a partial structure of a semiconductor structure provided in some embodiments of the present disclosure; Figure 2B A schematic diagram of a partial cross-sectional structure of a semiconductor structure provided in some embodiments of the present disclosure; Figure 2C A schematic diagram of a partial cross-sectional structure of a semiconductor structure provided in some other embodiments of the present disclosure; Figure 2D A schematic diagram of a partial cross-sectional structure of a semiconductor structure provided in some further embodiments of the present disclosure; Figure 2E A partial cross-sectional structural schematic diagram of a semiconductor structure provided in some further embodiments of the present disclosure.

[0071] For example, combined with Figures 2A-2EAs shown, the semiconductor structure provided by the embodiment of the present disclosure may include a substrate 100 and a stacked structure located on the substrate 100. The stacked structure includes M conductive portions stacked sequentially from top to bottom (as shown in the conductive portions 201-208 in the figure) and a first connecting portion and a second connecting portion arranged along a first horizontal direction X, the first connecting portion (which may be denoted as Cij) being electrically connected to the sidewall of the i-th conductive portion and the sidewall of the j-th conductive portion among the M conductive portions, the second connecting portion (which may be denoted as Cmn) being electrically connected to the sidewall of the m-th conductive portion and the sidewall of the n-th conductive portion among the M conductive portions, the orthographic projection of the i-th conductive portion on the substrate partially overlaps with the orthographic projection of the n-th conductive portion on the substrate, the size of the i-th conductive portion in the first horizontal direction X is smaller than the size of the n-th conductive portion in the first horizontal direction X, wherein M is a positive integer greater than or equal to 4, each of i, j, m, and n is a positive integer less than or equal to M, and i <j,m<n,i≠m,且j-i=n-m。

[0072] For example, the material of the conductive parts 201 - 208 may include but is not limited to titanium nitride and / or tungsten, etc. For example, the material of the first connection part Cij and the second connection part Cmn may include but is not limited to titanium nitride and / or tungsten, etc.

[0073] For example, the first connection portion Cij and the i-th conductive portion and the j-th conductive portion may be integrally formed. For example, the second connection portion Cmn and the m-th conductive portion and the n-th conductive portion may be integrally formed.

[0074] Indicatively, in Figures 2A-2E In the example shown, M=8, but this should not be considered as a limitation of the present disclosure.

[0075] For example, in some examples, ji=1. Schematically, Figure 2A and Figure 2B shows a case where ji=1, Figure 2C Another case where ji=1 is shown. For example, Figure 2A and Figure 2B The examples shown and Figure 2CIn the example shown, any two of the connections C12, C34, C56, and C78 can be selected, with the one farther from the substrate 100 serving as the first connection and the other closer to the substrate 100 serving as the second connection. Taking connections C12 and C34 as the first and second connection, respectively, the first connection C12 is electrically connected to the sidewall of the first conductive portion 201 and the sidewall of the second conductive portion 202 (i.e., i=1, j=2), the second connection C34 is electrically connected to the sidewall of the third conductive portion 203 and the sidewall of the fourth conductive portion 204 (i.e., m=3, n=4), the orthographic projection of the first conductive portion 201 on the substrate 100 partially overlaps the orthographic projection of the fourth conductive portion 204 on the substrate 100, and the dimension of the first conductive portion 201 in the first horizontal direction X is smaller than the dimension of the fourth conductive portion 204 in the first horizontal direction X. It should be noted that, in practical applications, part or all of the above-mentioned connecting parts C12, C34, C56, and C78 can be provided in the semiconductor structure as needed.

[0076] For example, in other examples, ji>1 and m>j. Schematically, Figure 2D A case where ji=3 and m>j is shown. Figure 2D In the example shown, the first connection portion C14 is electrically connected to the side wall of the first conductive portion 201 and the side wall of the fourth conductive portion 204 (i.e., i=1, j=4), the second connection portion C58 is electrically connected to the side wall of the fifth conductive portion 205 and the side wall of the eighth conductive portion 208 (i.e., m=5, n=8), the orthographic projection of the first conductive portion 201 on the substrate 100 partially overlaps with the orthographic projection of the eighth conductive portion 208 on the substrate 100, and the size of the first conductive portion 201 in the first horizontal direction X is smaller than the size of the eighth conductive portion 208 in the first horizontal direction X.

[0077] For example, in some further examples, ji>1 and m <j。示意性的, Figure 2E It shows that ji=2 and m <j的一种情形。例如,在 Figure 2E In the example shown, the connection portions C13 and C24 can be used as the first connection portion and the second connection portion, respectively. The first connection portion C13 is electrically connected to the side wall of the first conductive portion 201 and the side wall of the third conductive portion 203 (i.e., i=1, j=3), and the second connection portion C24 is electrically connected to the side wall of the second conductive portion 202 and the side wall of the fourth conductive portion 204 (i.e., m=2, n=4). The orthographic projection of the first conductive portion 201 on the substrate 100 partially overlaps with the orthographic projection of the fourth conductive portion 204 on the substrate 100. The size of the first conductive portion 201 in the first horizontal direction X is smaller than the size of the fourth conductive portion 204 in the first horizontal direction X. Of course, in Figure 2EIn the example shown, the connection parts C57 and C68 may also be used as the first connection part and the second connection part, respectively.

[0078] For example, in some embodiments, the first connecting portion and the second connecting portion are located on the same side of the M conductive portions, and the orthographic projection of the first connecting portion on the substrate does not overlap with the orthographic projection of the second connecting portion on the substrate. Figure 2B In the example shown, the connection portions C12, C34, C56, and C78 (any two of which can serve as the first connection portion and the second connection portion, respectively) are all located on the same side of the conductive portions 201-208, and the orthographic projections of the connection portions C12, C34, C56, and C78 on the substrate 100 do not overlap with each other. Figure 2D In the example shown, the first connection portion C14 and the second connection portion C58 are located on the same side of the conductive portions 201-208, and the orthographic projection of the first connection portion C14 on the substrate 100 does not overlap with the orthographic projection of the second connection portion C58 on the substrate 100. Figure 2C In the example shown, the connection parts C12 and C56 (or C34 and C78) can be regarded as the first connection part and the second connection part respectively; Figure 2E In the example shown, connections C13 and C57 (or C24 and C68) can be considered the first connection and the second connection, respectively. It is understood that when the first connection and the second connection are located on the same side of the M conductive portions, m>j, and thus the first connection and the second connection may not be coupled to each other.

[0079] For example, in some embodiments, the first connecting portion and the second connecting portion are located on opposite sides of the M conductive portions, and the orthographic projection of the first connecting portion on the substrate does not overlap with the orthographic projection of the second connecting portion on the substrate. Figure 2C In the example shown, the connection portions C12 and C34 (or C12 and C78, ​​or C34 and C56, or C56 and C78) can be used as the first connection portion and the second connection portion, respectively. The first connection portion C12 and the second connection portion C34 are located on opposite sides of the conductive portions 201-208, and the orthographic projection of the first connection portion C12 on the substrate 100 does not overlap with the orthographic projection of the second connection portion C34 on the substrate 100. For another example, in Figure 2EIn the example shown, the connection portions C13 and C24 (or C57 and C68) can be respectively used as the first connection portion and the second connection portion. The first connection portion C13 and the second connection portion C24 are located on opposite sides of the conductive portions 201-208, and the orthographic projection of the first connection portion C13 on the substrate 100 does not overlap with the orthographic projection of the second connection portion C24 on the substrate 100. It can be understood that when the first connection portion and the second connection portion are located on opposite sides of M conductive portions, m>j or m <j,从而第一连接部和第二连接部彼此之间可以不耦接;当然,也可以j=m,即第i个导电部、第j个导电部和第n个导电部通过位于相对侧的两个连接部相互电连接。

[0080] For example, in some embodiments, ji>1, in which case, the semiconductor structure may further include a first insulating pattern and a second insulating pattern, the first insulating pattern being located between the i+1th to j-1th conductive portions and the first connecting portion, and the second insulating pattern being located between the m+1th to n-1th conductive portions and the second connecting portion, so that the i+1th to j-1th conductive portions and the first connecting portion may not be coupled to each other, and the m+1th to n-1th conductive portions and the second connecting portion may not be coupled to each other. For example, in Figure 2D In the example shown, an insulating pattern SP (i.e., a first insulating pattern) is provided between each of the second conductive portion 202 and the third conductive portion 203 and the first connection portion C14, and between each of the sixth conductive portion 206 and the seventh conductive portion and the second connection portion C58. Figure 2E In the example shown, an insulating pattern SP is provided between the second conductive portion 202 and the connection portion C13, an insulating pattern SP is provided between the third conductive portion 203 and the connection portion C24, an insulating pattern SP is provided between the sixth conductive portion 206 and the connection portion C57, and an insulating pattern SP is provided between the seventh conductive portion 207 and the connection portion C68.

[0081] For example, in some embodiments, the longitudinal cross-sections of the first connecting portion and the second connecting portion may both be C-shaped (see Figure 2B 、 Figure 2D and Figure 2E For example, in other embodiments, the longitudinal cross-sections of the first connecting portion and the second connecting portion may both be in an F-shape (see Figure 2C For example, in some other embodiments, the longitudinal cross-section of one of the first connecting portion and the second connecting portion may be in the shape of a "C" (see Figure 2C The longitudinal cross-section of the other of the first and second connecting portions may be in the shape of an "F" (see Figure 2C Connection part C34 in).

[0082] It is understood that in the accompanying drawings, the first and second connecting portions are each electrically connected to two conductive portions, but the present disclosure is not limited thereto. In other words, as needed, the first and second connecting portions can each be electrically connected to three or more conductive portions, as long as certain interconnection rules are met to facilitate synchronous formation.

[0083] For example, in some embodiments, the stacked structure may also include M transistors stacked in sequence, the kth conductive portion among the M conductive portions and the kth transistor among the M transistors are located at the same level and coupled to each other, where k is a positive integer, k = 1, 2, 3, ..., M.

[0084] For example, in some embodiments, the i-th transistor and the j-th transistor among the M transistors are transistors of different conductivity types, the first connection portion electrically connects the gate of the i-th transistor and the gate of the j-th transistor, the m-th transistor and the n-th transistor among the M transistors are transistors of different conductivity types, and the second connection portion electrically connects the gate of the m-th transistor and the gate of the n-th transistor.

[0085] Figure 3A and Figure 3B A schematic diagram of a partial planar structure of two levels of a semiconductor structure provided in some embodiments of the present disclosure; Figure 3C is a schematic diagram of a CMOS circuit structure. For example, among the M transistors above, the i-th transistor can be Figure 3A The N-type transistor N0 and Figure 3B One of the P-type transistors P0 in the j-th transistor can be Figure 3A The N-type transistor N0 and Figure 3B The gate of the i-th transistor is electrically connected to the gate of the j-th transistor through the connection structure CT1 (for example, including the i-th conductive portion, the j-th conductive portion and the first connection portion Cij). Similarly, in the above-mentioned M transistors, the m-th transistor can be Figure 3A The N-type transistor N0 and Figure 3B One of the P-type transistors P0 in the n-th transistor can be Figure 3A The N-type transistor N0 and Figure 3B Another of the P-type transistors P0 in the array; the gate of the m-th transistor is electrically connected to the gate of the j-th transistor through another connection structure CT1 (for example, including the above-mentioned m-th conductive portion, the n-th conductive portion and the second connection portion Cmn).

[0086] It is understood that in the related art, in order to achieve interconnection and signal input between the gates of the stacked N-type transistor N0 and the P-type transistor P0, it is necessary to respectively provide a conductive step and a conductive plug corresponding to the gates of the two transistors (i.e., two conductive plugs); however, in the embodiment of the present disclosure, only one conductive plug corresponding to the connection portion Cij (or Cmn) is required. This reduces the number of conductive plugs required and the area occupied by the interconnection portion.

[0087] For example, Figure 3A The N-type transistor N0 in Figure 3B The P-type transistor P0 in the vertical direction to the substrate (ie Figure 2A The two are stacked in the direction Z) and connected to each other to form a Figure 3C For example, multiple CMOS can be stacked in a direction perpendicular to the substrate. For example, the arrangement of the multiple connection structures CT1 can refer to the arrangement of the multiple conductive parts and the multiple connection parts described above, which will not be repeated here.

[0088] For example, combined with Figures 3A-3C As shown, the connection structure CT2 is used to electrically connect the source and drain (source or drain) of the stacked N-type transistor N0 and the P-type transistor P0. It is understandable that the arrangement of multiple connection structures CT2 can also refer to the arrangement of the multiple conductive parts and the multiple connection parts mentioned above, and will not be repeated here.

[0089] For example, Figure 3A The N-type transistor N0 and Figure 3B The P-type transistors P0 in the embodiment can be configured as surround-gate transistors, that is, the gate Gn of the N-type transistor N0 surrounds its active area An, and the gate Gp of the P-type transistor P0 surrounds its active area Ap. The embodiments of the present disclosure include but are not limited to the above.

[0090] For example, in other embodiments, the M transistors are transistors of the same conductivity type, the first connection portion is electrically connected to the gate of one of the i-th transistor and the j-th transistor, and the first connection portion is also electrically connected to the source or drain of the other of the i-th transistor and the j-th transistor, the second connection portion is electrically connected to the gate of one of the m-th transistor and the n-th transistor, and the second connection portion is also electrically connected to the source or drain of the other of the m-th transistor and the n-th transistor.

[0091] Figure 3D and Figure 3E A schematic diagram of a partial planar structure of two levels of a semiconductor structure provided in some other embodiments of the present disclosure; Figure 3FSchematic diagram of a circuit structure of a sense amplifier (SA). For example, the above M transistors are all N-type transistors, where the i-th transistor and the j-th transistor can be respectively Figure 3D The N-type transistor N1 and Figure 3E In the N-type transistor N2, the gate of one of the i-th transistor and the j-th transistor (i.e., the transistor N1) is electrically connected to the source and drain (source or drain) of the other of the i-th transistor and the j-th transistor (i.e., the transistor N2) through a winding and a connection structure CC1 (e.g., including the i-th conductive portion, the j-th conductive portion, and the first connection portion Cij). Similarly, in the above-mentioned M transistors, the m-th transistor and the n-th transistor can be respectively Figure 3D The N-type transistor N1 and Figure 3E In the N-type transistor N2, the gate of one of the m-th transistor and the n-th transistor (i.e., the transistor N1) is electrically connected to the source and drain (source or drain) of the other of the m-th transistor and the n-th transistor (i.e., the transistor N2) through a winding and another connection structure CC1 (for example, including the above-mentioned m-th conductive portion, the n-th conductive portion and the second connection portion Cmn).

[0092] For example, Figure 3D The N-type transistor N1 and the P-type transistor P1 in Figure 3E The N-type transistor N2 and the P-type transistor P2 are stacked in a direction perpendicular to the substrate, and the four are connected to each other to form a Figure 3F As shown in the SA. Figures 3D-3F As shown, the gate of transistor P1, the gate of transistor N1, a source and drain of transistor P2, and a source and drain of transistor N2 are electrically connected to each other, the gate of transistor P2, the gate of transistor N2, a source and drain of transistor P1, and a source and drain of transistor N1 are electrically connected to each other, the other source and drain of transistor P1 and the other source and drain of transistor N1 are electrically connected to each other, and the other source and drain of transistor P2 and the other source and drain of transistor N2 are electrically connected to each other. For example, transistor P1, transistor N1, transistor P2, and transistor N2 can all be configured as wrap-around gate transistors, that is, gate G1 of transistor N1 wraps around its active area A1, gate G2 of transistor P1 wraps around its active area A2, gate G3 of transistor N2 wraps around its active area A3, and gate G4 of transistor P2 wraps around its active area A4. Embodiments of the present disclosure include but are not limited to this.

[0093] For example, multiple SAs may be stacked in a direction perpendicular to the substrate, and the M transistors may be N-type transistors (including N-type transistors N1 and N2) in the stacked SAs. Alternatively, the M transistors may be P-type transistors (including P-type transistors P1 and P2) in the stacked SAs. For example, the arrangement of the multiple connection structures CC1 may refer to the arrangement of the multiple conductive portions and the multiple connection portions described above, and will not be further described herein.

[0094] For example, combined with Figures 3D-3F As shown, the connection structure CC2 is used to electrically connect the source and drain (source or drain) of the stacked N-type transistor N1 and the N-type transistor N2. It is understandable that the arrangement of multiple connection structures CC2 can also refer to the arrangement of the multiple conductive parts and the multiple connection parts mentioned above, and will not be repeated here.

[0095] For example, combined with Figures 3D-3F As shown, connection structure CC3 is used to electrically connect the source and drain (source or drain) of stacked P-type transistors P1 and P-type transistors P2; connection structure CC4 is used to electrically connect the source and drain of P-type transistor P1 and the gate of P-type transistor P2. It is understood that the arrangement of multiple connection structures CC3 can also refer to the arrangement of multiple conductive parts and multiple connection parts described above, and the arrangement of multiple connection structures CC4 can also refer to the arrangement of multiple conductive parts and multiple connection parts described above, and will not be repeated here.

[0096] For example, in some embodiments, Figure 2A As shown, the stacked structure may further include M conductive lines stacked in sequence (as shown in the conductive lines 401-408 in the figure), wherein the kth conductive line among the M conductive lines is located at the same level as the kth conductive portion and the kth transistor, and the kth conductive portion is coupled to the kth transistor via the kth conductive line. It is understood that the conductive line here may be Figures 3A-3E A portion of the winding in the example shown.

[0097] For example, in some embodiments, the substrate 100 may include, but is not limited to, a silicon substrate, a silicon-on-insulator substrate, and the like.

[0098] For example, in some embodiments, Figures 2B-2E As shown, the stacked structure may further include a plurality of dielectric layers located on the substrate 100, the plurality of dielectric layers including an etch stop layer 105 and M dielectric patterns corresponding to the M conductive portions (as shown in the dielectric patterns 121-128 in the figure), the M conductive portions (as shown in the conductive portions 201-208 in the figure) and the M dielectric patterns are located on the etch stop layer 105 and along a direction perpendicular to the substrate 100 (i.e. Figure 2AThe dielectric patterns 121-128 may be made of the same material, such as, but not limited to, silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON). For example, the material of the etch-stop layer 105 may be different from the material of the dielectric patterns 121-128. For example, the material of the insulating pattern SP may be the same as that of the dielectric patterns 121-128, but is not limited thereto.

[0099] It should be noted that, for the sake of clarity and simplicity, some insulating layers and / or dielectric layers (such as gate dielectric layers) in the semiconductor structure are omitted in the drawings.

[0100] In the semiconductor structure provided by the embodiments of the present disclosure, regular internal interconnection of different conductive parts is achieved by providing connecting parts within the stacked structure, thereby reducing the number of conductive plugs required and reducing the area occupied by the interconnected parts; at the same time, these connecting parts can be formed synchronously to simplify the manufacturing process.

[0101] At least some embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, which can be used to manufacture the semiconductor structure in the aforementioned embodiments. Figure 4 A schematic flow chart of a method for manufacturing a semiconductor structure provided in some embodiments of the present disclosure. Figure 4 As shown, the manufacturing method may include the following steps S100 to S600.

[0102] S100: providing an initial semiconductor structure, wherein the initial semiconductor structure comprises an initial stacked structure located on a substrate, the initial stacked structure comprises a plurality of levels, and each level comprises a first layer and a second layer stacked in sequence.

[0103] Figure 5A A schematic top view of a structure obtained according to step S100 provided in some embodiments of the present disclosure; Figure 5B For the Figure 5A A schematic cross-sectional view of the K1-K2 line in FIG. Figure 5A and Figure 5BAs shown, step S100 may include: sequentially forming an etch stop layer 105, an alternating first layer 110 and a second layer 120, and a hard mask layer 125 on a substrate 100. For example, the substrate 100 may include, but is not limited to, a silicon substrate, a silicon-on-insulator substrate, etc. For example, the material of the etch stop layer 105 may include, but is not limited to, silicon carbide (SiC) or silicon carbon nitride (SiCN). For example, the first layer 110 may be a dielectric layer, and its material may include, but is not limited to, silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON). The material of the first layer 110 may also include, but is not limited to, polycrystalline silicon, amorphous silicon, etc. For example, the second layer 120 may be a dielectric layer, and its material may include, but is not limited to, silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON). For example, the material of the hard mask layer 125 may include, but is not limited to, silicon nitride (SiN), silicon carbide (SiC), or silicon carbon nitride (SiCN). It is understood that the materials of the first layer 110 , the second layer 120 and the hard mask layer 130 are usually different from each other, and there is usually a certain etching selectivity between any two of them.

[0104] For example, Figure 5B As shown, each level (eight levels T1 - T8 are shown in the figure) includes a first layer 110 and a second layer 120 located on and adjacent to the first layer 110 .

[0105] S200: Etching the initial stacking structure to form a stepped structure extending along a first horizontal direction, wherein the stepped structure includes a first step portion and a second step portion, the stepped structure includes M levels from top to bottom, the first step portion includes the i-th level to the j-th level among the M levels, and the second step portion includes the m-th level to the n-th level among the M levels.

[0106] For example, M is a positive integer greater than or equal to 4, each of i, j, m, and n is a positive integer less than or equal to M, i <j,m<n,i≠m,且j-i=n-m。

[0107] S300: forming a first sacrificial pattern and a second sacrificial pattern, wherein the first sacrificial pattern is connected to the side wall of the first layer in the i-th level of the first step portion and the side wall of the first layer in the j-th level, and the second sacrificial pattern is connected to the side wall of the first layer in the m-th level of the second step portion and the side wall of the first layer in the n-th level.

[0108] For example, in some embodiments, in order to form a semiconductor structure in which ji=1 and the first connecting portion and the second connecting portion are located on the same side of the conductive portion in M ​​levels (ie, M conductive portions), Figure 2BThe semiconductor structure shown in FIG. 1 may be formed by referring to a common step-structure formation process, forming an opening pattern that gradually increases in size along a first horizontal direction in the hard mask layer 125, and gradually etching the initial stacked structure to directly form a corresponding step structure. The step-structure formation process may refer to common related processes and will not be described in detail here.

[0109] Figure 6A A schematic top view of the structure obtained according to step S200 provided in some embodiments of the present disclosure, Figure 6B For the Figure 6A A schematic cross-sectional view of the A1-A2 line in FIG. Figure 6A and Figure 6B As shown, in Figure 5A and Figure 5B Based on the structure shown, the initial stacked structure can be etched to form a stepped structure SC extending along a first horizontal direction X. The stepped structure SC includes steps ST1-ST4. Step ST1 includes a first level T1 and a second level T2. Step ST2 includes a third level T3 and a fourth level T4. Step ST3 includes a fifth level T5 and a sixth level T6. Step ST4 includes a seventh level T7 and an eighth level T8. The first and second steps can be selected from the steps ST1-ST4 according to their definitions.

[0110] Figure 6C Schematic diagram of a cross section of the structure obtained according to step S300 provided in some embodiments of the present disclosure. Figure 6C As shown, in Figure 6B On the basis of the structure shown, the hard mask layer 125 can be removed first; then, the portion of the first layer 110 in the step portion ST1-ST4 is laterally etched; thereafter, a sacrificial material layer is conformally deposited, and the sacrificial material layer is etched back to remove the portion of the sacrificial material layer located on each top surface of the stepped structure (including the exposed top surface of the step portion ST1-ST4, and the exposed top surface of the etch stop layer 105), and the portion of the sacrificial material layer retained on the sidewall of the step portion ST1-ST4 is used as the sacrificial pattern SQ1-SQ4. The first sacrificial pattern and the second sacrificial pattern can be selected from the sacrificial patterns SQ1-SQ4 according to their definitions. That is, before forming the first sacrificial pattern and the second sacrificial pattern, the portion of the first layer in the i-th level and the portion of the first layer in the j-th level in the first step portion and the portion of the first layer in the m-th level and the portion of the first layer in the n-th level in the second step portion can be laterally etched to remove, so as to form a longitudinal cross-sectional shape of "F" (reference Figure 6C ) or "C" shape (reference Figure 6D For example, the material of the sacrificial material layer may be the same as or different from the material of the first layer 110. For example, the material of the sacrificial material layer may be different from the material of the second layer 120.

[0111] Figure 6D Schematic cross-sectional view of the structure obtained according to step S300 provided in some other embodiments of the present disclosure. Figure 6D As shown, in Figure 6C On the basis of the structure shown, the sacrificial pattern with an “F”-shaped longitudinal cross-section can be further etched to obtain sacrificial patterns SQ1 - SQ4 with a “C”-shaped longitudinal cross-section.

[0112] It is understood that in some examples, Figure 6B Based on the structure shown, a sacrificial pattern having a stripe-shaped longitudinal cross-section can be directly formed.

[0113] It is understandable that Figure 6C and Figure 6D The structure shown can be further processed to form a semiconductor structure in which ji=1 and the first connection portion and the second connection portion are located on the same side of the conductive portion in M ​​levels (ie, M conductive portions) (refer to Figure 2B semiconductor structure shown).

[0114] For example, in some other embodiments, in order to form a semiconductor structure in which ji=1 and the first connecting portion and the second connecting portion are located on opposite sides of the conductive portion in M ​​levels (ie, M conductive portions) (refer to Figure 2C The semiconductor structure shown in FIG. 1 ), step S200 may include the following steps S210 to S213 .

[0115] Step S210: etching the initial stacked structure to form an initial stepped structure, wherein the initial stepped structure includes a first initial stepped portion corresponding to the first stepped portion and a second initial stepped portion corresponding to the second stepped portion;

[0116] Step S211: forming a first isolation pattern, wherein the first isolation pattern covers the sidewalls of the initial stepped structure;

[0117] Step S212: etching the first initial step portion and the second initial step portion to expose the sidewalls of the first layer in the i-th level and the sidewalls of the first layer in the j-th level in the first initial step portion, and the sidewalls of the first layer in the m-th level and the sidewalls of the first layer in the n-th level in the second initial step portion;

[0118] Step S213 : Laterally etching and removing the first layer portion in the i-th level and the first layer portion in the j-th level in the first initial step portion, and the first layer portion in the m-th level and the first layer portion in the n-th level in the second initial step portion.

[0119] Figure 7ASchematic diagram of a cross section of the structure obtained according to step S210 provided in some embodiments of the present disclosure. Figure 7A As shown, in Figure 5B Based on the structure shown, the initial stacked structure can be etched to form an initial stepped structure, which includes initial stepped portions ST01-ST04. Initial stepped portion ST01 includes a first level T1 and a second level T2, initial stepped portion ST02 includes a third level T3 and a fourth level T4, initial stepped portion ST03 includes a fifth level T5 and a sixth level T6, and initial stepped portion ST04 includes a seventh level T7 and an eighth level T8. The first and second initial stepped portions can be selected from the initial stepped portions ST01-ST04 according to their definitions.

[0120] Figure 7B The cross-sectional schematic diagram of the structure obtained according to step S211 is provided in some embodiments of the present disclosure. Figure 7B As shown, in Figure 7A Based on the structure shown, hard mask layer 125 can be first etched to expose a portion of the top surface of initial stepped portion ST01; then, a first isolation material layer is conformally deposited and etched back to remove the portions of the first isolation material layer located on the top surfaces of the initial stepped structure (including the top surface of hard mask layer 125, the exposed top surfaces of initial stepped portions ST01-ST04, and the exposed top surface of etch-stop layer 105). The portions of the first isolation material layer remaining on the sidewalls of the initial stepped structure serve as first isolation pattern IP1. For example, the material of the first isolation material layer can be different from the material of any of etch-stop layer 105, first layer 110, second layer 120, and hard mask layer 125.

[0121] Figure 7C Schematic diagram of a cross section of the structure obtained according to step S212 provided in some embodiments of the present disclosure. Figure 7C As shown, in Figure 7B Based on the structure shown, the initial stepped portions ST01-ST04 can be simultaneously etched to expose the sidewalls of the first layer in the initial stepped portions ST01-ST04. For example, the remaining portions of the initial stepped portions ST01-ST04 can serve as corresponding stepped portions, and the remaining portion of the initial stepped structure serves as a stepped structure.

[0122] Figure 7D Schematic diagram of a cross section of the structure obtained according to step S213 provided in some embodiments of the present disclosure. Figure 7D As shown, in Figure 7CBased on the structure shown, portions of the first layer 110 in the initial stepped portions ST01-ST04 can be removed by synchronous lateral etching to obtain corresponding horizontal openings HP1. For example, the remaining portions of the initial stepped portions ST01-ST04 can serve as corresponding stepped portions, and the remaining portion of the initial stepped structure can serve as a stepped structure.

[0123] Figure 7E Schematic cross-sectional view of the structure obtained according to step S300 provided in some other embodiments of the present disclosure. Figure 7E As shown, in Figure 7D Based on the structure shown, a sacrificial material layer is conformally deposited and etched back to remove portions of the sacrificial material layer located on the top surfaces of the stepped structure (including the exposed top surfaces of the steps ST1-ST4 and the exposed top surface of the etch-stop layer 105). The portions of the sacrificial material layer remaining on the sidewalls of the steps serve as sacrificial patterns SQ5-SQ8. The first and second sacrificial patterns can be selected from the sacrificial patterns SQ5-SQ8 according to their definitions.

[0124] It is understood that in some examples, Figure 7C Based on the structure shown, a sacrificial pattern having a stripe-shaped longitudinal cross-section can be directly formed.

[0125] It is understandable that Figure 7E The structure shown can be further processed to form a semiconductor structure with ji=1 and the first and second connections located on opposite sides of the conductive portions in the M levels (ie, the M conductive portions) (refer to Figure 2C semiconductor structure shown).

[0126] For example, in some examples, Figure 7E Based on the structure shown, the first isolation pattern IP1 may be selectively etched to remove part or all of the first isolation pattern IP1, thereby improving the quality of a subsequently formed planarization layer.

[0127] For example, in some further embodiments, in order to form a semiconductor structure with ji>1 (refer to Figure 2D and Figure 2E The semiconductor structure shown in FIG. 1 ), step S200 may include the following steps S220 to S223 .

[0128] S220: etching the initial stacked structure to form an initial stepped structure, wherein the initial stepped structure includes a first initial stepped portion corresponding to the first stepped portion and a second initial stepped portion corresponding to the second stepped portion;

[0129] S221: forming a first isolation pattern, wherein the first isolation pattern covers a sidewall of the initial stepped structure;

[0130] S222: etching the first initial step portion and the second initial step portion to expose the sidewall of the first layer in the i-th level in the first initial step portion and the sidewall of the first layer in the m-th level in the second initial step portion;

[0131] S223: forming a second isolation pattern, wherein the second isolation pattern covers a sidewall of the first layer in the i-th level in the first initial stepped portion and a sidewall of the first layer in the m-th level in the second initial stepped portion;

[0132] S224: Continue etching the first initial step portion and the second initial step portion to expose sidewalls of the first layer in the (i+1)th to (j-1)th levels in the first initial step portion and sidewalls of the first layer in the (m+1)th to (n-1)th levels in the second initial step portion;

[0133] S225: Laterally etching and removing a portion of the first layer from the i+1th to j-1th levels in the first initial step portion and a portion of the first layer from the m+1th to n-1th levels in the second initial step portion to form a corresponding horizontal opening;

[0134] S226: forming an insulating pattern filling the corresponding horizontal opening;

[0135] S227: Continue etching the first initial step portion and the second initial step portion to expose the sidewall of the first layer in the j-th level in the first initial step portion and the sidewall of the first layer in the n-th level in the second initial step portion;

[0136] S228: removing the second isolation pattern.

[0137] Figure 8A Schematic cross-sectional view of the structure obtained according to step S220 provided in some embodiments of the present disclosure. Figure 8A As shown, in Figure 5B Based on the structure shown, the initial stacked structure can be etched to form an initial stepped structure. The initial stepped structure includes initial stepped portions SU1 and SU2. Initial stepped portion SU1 includes first level T1 to fourth level T4, and initial stepped portion SU2 includes fifth level T5 to eighth level T8. Initial stepped portion SU1 can serve as a first initial stepped portion, and initial stepped portion SU2 can serve as a second initial stepped portion.

[0138] Figure 8B Schematic cross-sectional view of the structure obtained according to step S221 provided in some embodiments of the present disclosure. Figure 8B As shown, in Figure 8ABased on the structure shown, the hard mask layer 125 can be first etched to expose a portion of the top surface of the initial stepped portion SU1. Then, a first isolation material layer is conformally deposited and etched back to remove the portions of the first isolation material layer located on the top surfaces of the initial stepped structure (including the top surface of the hard mask layer 125, the exposed top surfaces of the initial stepped portions SU1 and SU2, and the exposed top surface of the etch-stop layer 105). The portions of the first isolation material layer remaining on the sidewalls of the initial stepped structure serve as the first isolation pattern IP1. For example, the material of the first isolation material layer can be different from the material of any of the etch-stop layer 105, the first layer 110, the second layer 120, and the hard mask layer 125.

[0139] Figure 8C The cross-sectional view of the structure obtained according to step S222 and step S223 is provided in some embodiments of the present disclosure. Figure 8C As shown, in Figure 8B Based on the structure shown, the initial step portion SU1 (the first level T1 therein) and the initial step portion SU2 (the fifth level T5 therein) can be simultaneously etched to expose the sidewalls of the first layer 110 in the first level T1 of the initial step portion SU1 and the sidewalls of the first layer 110 in the fifth level T5 of the initial step portion SU2. Then, a second isolation pattern IP2 is formed. The second isolation pattern IP2 covers at least the sidewalls of the first layer 110 in the first level T1 of the initial step portion SU1 and the sidewalls of the first layer 110 in the fifth level T5 of the initial step portion SU2 to prevent the first layer 110 in the first level T1 of the initial step portion SU1 and the first layer 110 in the fifth level T5 of the initial step portion SU2 from being damaged in step S224. For example, the material of the second isolation pattern IP2 is different from the material of any of the etch-stop layer 105, the first layer 110, the second layer 120, and the first isolation pattern IP1. For example, the formation method of the second isolation pattern IP2 can refer to the formation method of the first isolation pattern IP1, which will not be repeated here. It is understood that during the formation of the second isolation pattern IP2, over-etching can be performed to remove the second isolation pattern at an unintended location to ensure that the second isolation pattern IP2 is formed at the intended location.

[0140] Figure 8D Schematic diagram of a cross section of the structure obtained according to step S224 provided in some embodiments of the present disclosure. Figure 8D As shown, in Figure 8CBased on the structure shown, the initial step portion SU1 (the 2nd level T2 and the 3rd level T3 therein) and the initial step portion SU2 (the 6th level T6 and the 7th level T7 therein) can continue to be etched synchronously to expose the side walls of the first layer 110 in the 2nd level T2 and the 3rd level T3 in the initial step portion SU1 and the side walls of the first layer 110 in the 6th level T6 and the 7th level T7 in the initial step portion SU2.

[0141] Figure 8E Schematic cross-sectional view of the structure obtained according to step S225 and step S226 provided in some embodiments of the present disclosure. Figure 8E As shown, in Figure 8D Based on the structure shown, portions of the first layer 110 in the second level T2 and the third level T3 of the initial step SU1, as well as portions of the first layer 110 in the sixth level T6 and the seventh level T7 of the initial step SU2, can be simultaneously removed by lateral etching to form corresponding horizontal openings. An insulating material layer is then conformally deposited to fill the horizontal openings, and the portion of the insulating material layer outside the horizontal openings is removed by etching. The portion of the insulating material layer remaining in the horizontal openings serves as the insulating pattern SP. For example, the material of the insulating pattern SP can be the same as that of the second layer 120, but is not limited thereto.

[0142] Figure 8F Schematic cross-sectional view of the structure obtained according to step S227 and step S228 provided in some embodiments of the present disclosure. Figure 8F As shown, in Figure 8EBased on the structure shown, the initial step portion SU1 and the initial step portion SU2 can be simultaneously etched to expose the sidewalls of the first layer 110 in the fourth level T4 of the initial step portion SU1 and the sidewalls of the first layer 110 in the eighth level T8 of the initial step portion SU2. Then, portions of the first layer 110 in the fourth level T4 of the initial step portion SU1 and portions of the first layer 110 in the eighth level T8 of the initial step portion SU2 are simultaneously removed by laterally etching. Thereafter, the second isolation pattern IP2 is removed to expose the sidewalls of the first layer 110 in the first level T1 of the initial step portion SU1 and the sidewalls of the first layer 110 in the fifth level T5 of the initial step portion SU2. That is, before removing the second isolation pattern, portions of the first layer in the jth level of the first step portion and portions of the first layer in the nth level of the second step portion can be laterally etched away, thereby subsequently forming a sacrificial pattern having a C-shaped or F-shaped longitudinal cross-section. For example, in some examples, the step of laterally etching away the portion of the first layer 110 in the fourth level T4 of the initial step portion SU1 and the portion of the first layer 110 in the eighth level T8 of the initial step portion SU2 can be omitted, thereby subsequently forming a sacrificial pattern having an L-shaped longitudinal cross-section. For example, the remaining portions of the initial step portions SU1 and SU2 can serve as corresponding step portions, and the remaining portion of the initial stepped structure serves as a stepped structure.

[0143] Figure 8G Schematic cross-sectional view of the structure obtained according to step S300 provided in some embodiments of the present disclosure. Figure 8G As shown, in Figure 8F On the basis of the structure shown in FIG, a first sacrificial pattern SR1 and a second sacrificial pattern SR2 can be formed. For example, the formation method of the sacrificial patterns SR1 and SR2 can refer to the aforementioned Figure 7E The formation method of the sacrificial patterns SQ5-SQ8 will not be repeated here.

[0144] It is understandable that Figure 8G The structure shown can be further processed to form a semiconductor structure in which ji>1 and the first connection portion and the second connection portion are located on the same side of the conductive portion in M ​​levels (ie, M conductive portions) (refer to Figure 2D semiconductor structure shown).

[0145] For example, in some examples, Figure 8G Based on the structure shown, the first isolation pattern IP1 may be selectively etched to remove part or all of the first isolation pattern IP1, thereby improving the quality of a subsequently formed planarization layer.

[0146] Figure 9ASchematic cross-sectional view of the structure obtained according to step S220 provided in some other embodiments of the present disclosure. Figure 9A As shown, in Figure 9B Based on the structure shown, the initial stacked structure can be etched to form an initial stepped structure, including initial step portions SU3-SU6. Initial step portion SU3 includes the first level T1 to the third level T3, initial step portion SU4 includes the second level T2 to the fourth level T4, initial step portion SU5 includes the fifth level T5 to the seventh level T7, and initial step portion SU6 includes the sixth level T6 to the eighth level T8. The first initial step portion and the second initial step portion can be selected from the initial step portions SU3-SU6 according to their definitions.

[0147] Figure 9B Schematic cross-sectional view of the structure obtained according to step S221 provided in some other embodiments of the present disclosure. Figure 9B As shown, in Figure 9A Based on the structure shown, the hard mask layer 125 can be first etched to expose a portion of the top surface of the initial stepped portion SU3. Then, a first isolation material layer is conformally deposited and etched back to remove the portions of the first isolation material layer located on the top surfaces of the initial stepped structure (including the top surface of the hard mask layer 125, the exposed top surfaces of the initial stepped portions SU3-SU6, and the exposed top surface of the etch-stop layer 105). The portions of the first isolation material layer remaining on the sidewalls of the initial stepped structure serve as the first isolation pattern IP1. For example, the material of the first isolation material layer can be different from the material of any of the etch-stop layer 105, the first layer 110, the second layer 120, and the hard mask layer 125.

[0148] Figure 9C Schematic cross-sectional view of the structure obtained according to step S222 and step S223 provided in some other embodiments of the present disclosure. Figure 9C As shown, in Figure 9BOn the basis of the structure shown, the initial step portions SU3-SU6 can be etched synchronously to expose the side walls of the first layer 110 in the 1st level T1 in the initial step portion SU3, the side walls of the first layer 110 in the 2nd level T2 in the initial step portion SU4, the side walls of the first layer 110 in the 5th level T5 in the initial step portion SU5, and the side walls of the first layer 110 in the 6th level T6 in the initial step portion SU6; then, a second isolation pattern IP2 is formed, and the second isolation pattern IP2 at least covers the side walls of the first layer 110 in the 1st level T1 in the initial step portion SU3, the side walls of the first layer 110 in the 2nd level T2 in the initial step portion SU4, the side walls of the first layer 110 in the 5th level T5 in the initial step portion SU5, and the side walls of the first layer 110 in the 6th level T6 in the initial step portion SU6. For example, the material of the second isolation pattern IP2 is different from the material of any of the etch stop layer 105, the first layer 110, the second layer 120, and the first isolation pattern IP1. It is understood that during the formation of the second isolation pattern IP2, over-etching may be performed to remove the second isolation pattern at an unintended location, thereby ensuring that the second isolation pattern IP2 is formed at the intended location.

[0149] Figure 9D Schematic cross-sectional view of the structure obtained according to step S224, step S225 and step S226 provided in some embodiments of the present disclosure. Figure 9D As shown, in Figure 9C Based on the structure shown, the initial step portions SU3-SU6 can be simultaneously etched to expose the sidewalls of the first layer 110 in the second level T2 of the initial step portion SU3, the sidewalls of the first layer 110 in the third level T3 of the initial step portion SU4, the sidewalls of the first layer 110 in the sixth level T6 of the initial step portion SU5, and the sidewalls of the first layer 110 in the seventh level T7 of the initial step portion SU6. Subsequently, portions of the first layer 110 in the second level T2 of the initial step portion SU3, the first layer 110 in the third level T3 of the initial step portion SU4, the first layer 110 in the sixth level T6 of the initial step portion SU5, and the first layer 110 in the seventh level T7 of the initial step portion SU6 can be simultaneously removed by lateral etching to form corresponding horizontal openings. Subsequently, an insulating pattern SP is formed to fill the corresponding horizontal openings. For example, the insulating pattern SP can be made of the same material as the second layer 120, but is not limited thereto.

[0150] Figure 9E Schematic cross-sectional view of the structure obtained according to step S227 and step S228 provided in some other embodiments of the present disclosure. Figure 9E As shown, in Figure 9DBased on the structure shown in FIG, the initial step portions SU3-SU6 can be further etched synchronously to expose the sidewalls of the first layer 110 in the third level T3 in the initial step portion SU3, the sidewalls of the first layer 110 in the fourth level T4 in the initial step portion SU4, the sidewalls of the first layer 110 in the seventh level T7 in the initial step portion SU5, and the sidewalls of the first layer 110 in the eighth level T8 in the initial step portion SU6; then, the first layer 110 in the third level T3 in the initial step portion SU3, the fourth level T4 in the initial step portion SU4, and the sidewalls of the first layer 110 in the eighth level T8 in the initial step portion SU6 are removed by synchronous lateral etching. The first step SU4 is then etched to remove a portion of the first layer 110 in the jth level T7 of the initial step SU5, and a portion of the first layer 110 in the eighth level T8 of the initial step SU6. The second isolation pattern IP2 is then removed to expose the sidewalls of the first layer 110 in the first level T1 of the initial step SU3, the sidewalls of the first layer 110 in the second level T2 of the initial step SU4, the sidewalls of the first layer 110 in the fifth level T5 of the initial step SU5, and the sidewalls of the first layer 110 in the sixth level T6 of the initial step SU6. That is, before removing the second isolation pattern, the portion of the first layer in the jth level of the first step and the portion of the first layer in the nth level of the second step can be laterally etched away, thereby subsequently forming a sacrificial pattern having a C-shaped or F-shaped longitudinal cross-section. For example, in some examples, the steps of lateral etching to remove portions of the first layer 110 in the third level T3 of the initial step portion SU3, portions of the first layer 110 in the fourth level T4 of the initial step portion SU4, portions of the first layer 110 in the seventh level T7 of the initial step portion SU5, and portions of the first layer 110 in the eighth level T8 of the initial step portion SU6 can be omitted, thereby subsequently forming a sacrificial pattern having an L-shaped longitudinal cross-section. For example, the remaining portions of the initial step portions SU3-SU6 can serve as corresponding step portions, and the remaining portion of the initial stepped structure serves as a stepped structure.

[0151] Figure 9F Schematic cross-sectional view of the structure obtained according to step S300 provided in some embodiments of the present disclosure. Figure 9F As shown, in Figure 9E Based on the structure shown, sacrificial patterns SR3-SR6 can be formed. For example, the formation method of sacrificial patterns SR3-SR6 can refer to the aforementioned Figure 7E The formation method of the sacrificial patterns SQ5-SQ8 in FIG. 1 is not described in detail here. The first sacrificial pattern and the second sacrificial pattern can be selected from the sacrificial patterns SR3-SR6 according to their definitions.

[0152] It is understandable that Figure 9FThe structure shown can be further processed to form a semiconductor structure with ji>1 and the first and second connecting portions located on opposite sides of the conductive portions in the M levels (ie, M conductive portions) (refer to Figure 2E semiconductor structure shown).

[0153] For example, in some examples, Figure 9F Based on the structure shown, the first isolation pattern IP1 may be selectively etched to remove part or all of the first isolation pattern IP1, thereby improving the quality of a subsequently formed planarization layer.

[0154] S400 : forming a planarization layer covering the first sacrificial pattern and the second sacrificial pattern.

[0155] Figure 10 Schematic cross-sectional view of the structure obtained according to step S400 provided in some embodiments of the present disclosure. Figure 10 As shown, in Figure 6D Based on the structure shown, a dielectric material covering the sacrificial patterns SQ1-SQ4 can be formed by a spin coating process and planarized by a chemical mechanical polishing (CMP) process to obtain a planarization layer 135. For example, the material of the planarization layer 135 can be the same as that of the second layer 120, but is not limited thereto.

[0156] S500: etching portions of the initial stacked structure located on both sides of the planarization layer in the second horizontal direction to form vertical openings, wherein the vertical openings expose portions of sidewalls of the stepped structure, the first sacrificial pattern, and the second sacrificial pattern, and the second horizontal direction intersects the first horizontal direction.

[0157] Figure 11A A schematic top view of the structure obtained according to step S500 provided in some embodiments of the present disclosure, Figure 11B For the Figure 11A Schematic diagram of the cross section taken along line B1-B2 in FIG. Figure 11A and Figure 11B As shown, in Figure 10 Based on the structure shown, portions of the initial stacked structure located on both sides of the planarization layer 135 in the second horizontal direction Y can be etched until the etch-stop layer 105 is exposed, thereby forming a vertical opening VP. The vertical opening VP exposes portions of the sidewalls of the stepped structure, the first sacrificial pattern, and the second sacrificial pattern. The second horizontal direction Y intersects the first horizontal direction X. For example, the second horizontal direction Y can be perpendicular to the first horizontal direction X.

[0158] It is understandable that along Figure 11A The cross-sectional diagram taken along line A1-A2 in FIG. Figure 10 For the sake of brevity, this disclosure omits Figure 11AA cross-sectional schematic view of the structure in A1-A2.

[0159] S600: remove the first layer of the M levels in the staircase structure and the first and second sacrificial patterns from the vertical opening by lateral etching, to replace the first layer of the M levels in the staircase structure with a conductive part, replace the first sacrificial pattern with a first connecting part, and replace the second sacrificial pattern with a second connecting part, wherein the first connecting part is electrically connected with the sidewall of the conductive part in the i-th level and the sidewall of the conductive part in the j-th level, and the second connecting part is electrically connected with the sidewall of the conductive part in the m-th level and the sidewall of the conductive part in the n-th level.

[0160] Figure 12 A cross-sectional schematic view of the structure obtained according to step S600 is provided for some embodiments of the present disclosure. For example, as shown in Figure 2B Figure 2B in which the planarization layer 135 is omitted) and Figure 12 as shown in the structure shown in Figure 11A and Figure 11B Based on the structure shown in Figure 2A , the first layer 110 of the eight levels T1-T8 in the staircase structure and the sacrificial patterns SQ1-SQ4 can be removed from the vertical opening VP by lateral etching, and the first layer 110 of the initial stack structure located in the regions R1 and R2 is also removed to form corresponding horizontal openings; then, a conductive material layer is conformally deposited to fill the above horizontal openings, and the part of the conductive material layer located outside the above horizontal openings is etched and removed, the part of the conductive material layer remaining in the horizontal openings of the staircase structure is respectively the conductive parts 201-208 and the connecting parts C12, C34, C56, C78, and the part of the conductive material layer remaining in the horizontal openings of the regions R1 and R2 is a conductive wire (for reference

[0161] It can be understood that, since the material of the first layer 110 is different from the material of the sacrificial patterns SQ1-SQ4, the first layer 110 can be removed by lateral etching first, and then the conductive parts 201-208 and the conductive wire 401-408 are formed, and then the sacrificial patterns SQ1-SQ4 are removed by lateral etching, and then the connecting parts C12, C34, C56, C78 are formed; or, the sacrificial patterns SQ1-SQ4 can be removed by lateral etching first, and then the connecting parts C12, C34, C56, C78 are formed, and then the first layer 110 is removed by lateral etching, and then the conductive parts 201-208 and the conductive wire 401-408 are formed. That is, the conductive parts and the connecting parts can be formed synchronously and integrally, or can be formed in steps and have a boundary interface. ​

[0162] It can be understood that in the structure obtained according to step S600, the first connecting portion is electrically connected to the side wall of the conductive portion in the i-th level and the side wall of the conductive portion in the j-th level, the second connecting portion is electrically connected to the side wall of the conductive portion in the m-th level and the side wall of the conductive portion in the n-th level, the orthographic projection of the conductive portion in the i-th level on the substrate partially overlaps with the orthographic projection of the conductive portion in the n-th level on the substrate, and the size of the conductive portion in the i-th level in the first horizontal direction is smaller than the size of the conductive portion in the n-th level in the first horizontal direction.

[0163] It is understood that for the remaining embodiments of the present disclosure (such as Figure 6C 、 Figure 7E 、 Figure 8G 、 Figure 9F ) The structure obtained according to step S300 provided by the invention can also obtain a corresponding semiconductor structure through processing from step S400 to step S600, which will not be described in detail here.

[0164] It should be noted that one or more steps of the above-mentioned manufacturing method may include multiple sub-steps, and these sub-steps may be executed sequentially or in parallel according to actual needs; in addition, according to actual needs, the sub-steps in different steps may be executed sequentially, in parallel or alternately.

[0165] For more details and technical effects of the manufacturing method provided by the embodiments of the present disclosure, reference may be made to the relevant descriptions in the embodiments of the semiconductor structure described above, and will not be repeated here.

[0166] At least some embodiments of the present disclosure also provide an electronic device. Figure 13 This is a schematic block diagram of the structure of an electronic device provided in some embodiments of the present disclosure. Figure 13 As shown, the electronic device 1 includes a processor 20 and a memory 10 coupled to each other, wherein at least one of the memory 10 and the processor 20 includes the semiconductor structure provided by any of the aforementioned embodiments.

[0167] For example, the processor 20 may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), etc. The memory 10 may be configured to store data to be processed by the processor 20 and / or data processed by the processor.

[0168] For example, the electronic device 1 includes but is not limited to mobile phones, tablet computers, smart bracelets, wearable electronic devices, virtual reality devices, augmented reality devices, vehicle-mounted devices, servers, workstations, etc.

[0169] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: Comprising: Providing an initial semiconductor structure, wherein the initial semiconductor structure includes an initial stacked structure located on a substrate, the initial stacked structure includes multiple levels, and each level includes a first layer and a second layer stacked in sequence; Etching the initial stacked structure to form a stepped structure extending in a first horizontal direction, wherein the stepped structure includes a first step portion and a second step portion, the stepped structure includes M levels from top to bottom, the first step portion includes the i-th level to the j-th level among the M levels, the second step portion includes the m-th level to the n-th level among the M levels, M is a positive integer greater than or equal to 4, each of i, j, m, n is a positive integer less than or equal to M, i < j, m < n, i ≠ m, and j - i = n - m; Forming a first sacrificial pattern and a second sacrificial pattern, wherein the first sacrificial pattern is connected to the sidewalls of the first layer in the i-th level and the sidewalls of the first layer in the j-th level of the first step portion, and the second sacrificial pattern is connected to the sidewalls of the first layer in the m-th level and the sidewalls of the first layer in the n-th level of the second step portion; Forming a planarization layer covering the first sacrificial pattern and the second sacrificial pattern; Etching the portions of the initial stacked structure on both sides of the planarization layer in a second horizontal direction to form vertical openings, wherein the vertical openings expose partial sidewalls of the stepped structure, the first sacrificial pattern, and the second sacrificial pattern, and the second horizontal direction intersects the first horizontal direction; Transversely etching and removing the first layer among the M levels in the stepped structure, the first sacrificial pattern, and the second sacrificial pattern from the vertical openings to replace the first layer among the M levels in the stepped structure with a conductive portion, replace the first sacrificial pattern with a first connection portion, and replace the second sacrificial pattern with a second connection portion, wherein the first connection portion is electrically connected to the sidewalls of the conductive portion in the i-th level and the sidewalls of the conductive portion in the j-th level, the second connection portion is electrically connected to the sidewalls of the conductive portion in the m-th level and the sidewalls of the conductive portion in the n-th level, the positive projection of the conductive portion in the i-th level on the substrate partially overlaps with the positive projection of the conductive portion in the n-th level on the substrate, and the size of the conductive portion in the i-th level in the first horizontal direction is smaller than the size of the conductive portion in the n-th level in the first horizontal direction.

2. The manufacturing method according to claim 1, characterized in that When j - i > 1, etching the initial stacked structure to form the stepped structure includes: Etching the initial stacked structure to form an initial stepped structure, wherein the initial stepped structure includes a first initial step portion corresponding to the first step portion and a second initial step portion corresponding to the second step portion; Forming a first isolation pattern, wherein the first isolation pattern covers the sidewalls of the initial stepped structure; Etching the first initial step portion and the second initial step portion to expose a sidewall of the first layer in the i-th level in the first initial step portion and a sidewall of the first layer in the m-th level in the second initial step portion; forming a second isolation pattern, wherein the second isolation pattern covers a sidewall of the first layer in the i-th level in the first initial stepped portion and a sidewall of the first layer in the m-th level in the second initial stepped portion; Continue etching the first initial step portion and the second initial step portion to expose sidewalls of the first layer in the (i+1)th to (j-1)th levels in the first initial step portion and sidewalls of the first layer in the (m+1)th to (n-1)th levels in the second initial step portion; Laterally etching away portions of the first layer in the (i+1)th to (j-1)th levels in the first initial step portion and portions of the first layer in the (m+1)th to (n-1)th levels in the second initial step portion to form corresponding horizontal openings; forming an insulating pattern filling the corresponding horizontal opening; Continue etching the first initial step portion and the second initial step portion to expose a sidewall of the first layer in the j-th level in the first initial step portion and a sidewall of the first layer in the n-th level in the second initial step portion; The second isolation pattern is removed.

3. The manufacturing method according to claim 2, characterized in that Also includes: Before removing the second isolation pattern, a portion of the first layer in the j-th level in the first stepped portion and a portion of the first layer in the n-th level in the second stepped portion are removed by lateral etching.

4. The manufacturing method according to claim 1, characterized in that ji=1, the first connecting portion and the second connecting portion are located on the same side of the conductive portion in the M levels, The manufacturing method further comprises: Before forming the first sacrificial pattern and the second sacrificial pattern, a portion of the first layer in the i-th level and a portion of the first layer in the j-th level in the first step portion, as well as a portion of the first layer in the m-th level and a portion of the first layer in the n-th level in the second step portion, are laterally etched away.

5. The manufacturing method according to claim 1, characterized in that ji=1, the first connection portion and the second connection portion are located on opposite sides of the conductive portion in the M levels, Etching the initial stacked structure to form the stepped structure comprises: Etching the initial stacked structure to form an initial stepped structure, wherein the initial stepped structure includes a first initial stepped portion corresponding to the first stepped portion and a second initial stepped portion corresponding to the second stepped portion; forming a first isolation pattern, wherein the first isolation pattern covers a sidewall of the initial stepped structure; Etching the first initial step portion and the second initial step portion to expose sidewalls of the first layer in the i-th level and the first layer in the j-th level in the first initial step portion, and sidewalls of the first layer in the m-th level and the first layer in the n-th level in the second initial step portion; Horizontally etch to remove a part of the first layer in the i-th level and a part of the first layer in the j-th level in the first initial step portion, and a part of the first layer in the m-th level and a part of the first layer in the n-th level in the second initial step portion.

6. A semiconductor structure, characterized in that Obtained by the manufacturing method according to any one of claims 1-5, including: A substrate; A stacked structure located on the substrate, wherein the stacked structure includes M conductive parts stacked in sequence from top to bottom, and a first connection part and a second connection part arranged along a first horizontal direction. The first connection part is electrically connected to the side walls of the i-th conductive part and the j-th conductive part among the M conductive parts, and the second connection part is electrically connected to the side walls of the m-th conductive part and the n-th conductive part among the M conductive parts. The orthographic projection of the i-th conductive part on the substrate partially overlaps with the orthographic projection of the n-th conductive part on the substrate, and the size of the i-th conductive part in the first horizontal direction is smaller than the size of the n-th conductive part in the first horizontal direction. Where M is a positive integer greater than or equal to 4, and each of i, j, m, and n is a positive integer less than or equal to M, i < j, m < n, i ≠ m, and j - i = n - m.

7. The semiconductor structure according to claim 6, wherein: The first connection part and the second connection part are located on the same side of the M conductive parts, and the orthographic projection of the first connection part on the substrate does not overlap with the orthographic projection of the second connection part on the substrate.

8. The semiconductor structure according to claim 7, wherein: m > j.

9. The semiconductor structure according to claim 6, wherein: The first connection part and the second connection part are located on opposite sides of the M conductive parts.

10. The semiconductor structure according to claim 9, wherein: m > j or m < j.

11. The semiconductor structure according to claim 10, wherein: j - i > 1, and the semiconductor structure further includes: A first insulating pattern located between the (i + 1)-th conductive part to the (j - 1)-th conductive part among the M conductive parts and the first connection part; A second insulating pattern located between the (m + 1)-th conductive part to the (n - 1)-th conductive part among the M conductive parts and the second connection part.

12. The semiconductor structure according to any one of claims 6 to 11, characterized in that: The stacked structure further includes M transistors stacked in sequence. The k-th conductive part among the M conductive parts and the k-th transistor among the M transistors are located in the same level and are coupled to each other, where k is a positive integer, k = 1, 2, 3,..., M.

13. The semiconductor structure according to claim 12, wherein: The stacked structure further includes M conductive wires stacked in sequence. The k-th conductive wire among the M conductive wires, the k-th conductive part, and the k-th transistor are located in the same level, and the k-th conductive part is respectively coupled to the k-th transistor through the k-th wire.

14. The semiconductor structure according to claim 12, wherein: The M transistors are transistors of the same conductivity type. The first connection part is electrically connected to the gate of one of the i-th transistor and the j-th transistor, and the first connection part is also electrically connected to the source or drain of the other of the i-th transistor and the j-th transistor. The second connection part is electrically connected to the gate of one of the m-th transistor and the n-th transistor, and the second connection part is also electrically connected to the source or drain of the other of the m-th transistor and the n-th transistor; or, The i-th transistor and the j-th transistor among the M transistors are transistors of different conductivity types, the first connecting portion electrically connects the gate of the i-th transistor and the gate of the j-th transistor, the m-th transistor and the n-th transistor among the M transistors are transistors of different conductivity types, and the second connecting portion electrically connects the gate of the m-th transistor and the gate of the n-th transistor.

15. An electronic device, characterized in that: include: processor; as well as A memory, wherein the memory is coupled to the processor, and at least one of the memory and the processor comprises a semiconductor structure obtained according to the manufacturing method according to any one of claims 1 to 5.

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