Half-bridge GaN enhanced switching device and preparation method thereof

Abstract

The present invention relates to the field of semiconductor technology, and specifically discloses a half-bridge GaN enhanced switching device and a preparation method thereof. The half-bridge GaN enhanced switching device includes two switching elements connected in a half-bridge; the two switching elements are horizontally arranged on the same substrate, wherein the drain and the gate of one switching element are electrically led out separately, the source is connected to the drain of the other switching element and electrically led out together, and the gate and the source of the other switching element are electrically led out separately. The conductive mechanism of the half-bridge GaN enhanced switching device is a two-dimensional electron gas, and the gate controls the conduction and shutoff of the two-dimensional electron gas, so the gate charge of the device is very small, which can ensure the high-speed switching of the device. The device as a whole presents a half-bridge connection characteristic, which ensures the application flexibility. At the same time, since the device is prepared on the same substrate, it has the characteristics of high integration, which can improve the system power density.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a half-bridge GaN enhanced switching device and a preparation method thereof. Background Art

[0002] Traditional silicon-based MOSFETs are limited by material properties and have relatively low electron mobility, while high electron mobility transistors (HEMTs) use materials such as gallium nitride (GaN) or gallium arsenide (GaAs), which have higher electron mobility than traditional silicon materials. GaN HEMT power integrated circuits are high-efficiency power tubes manufactured using gallium nitride high electron mobility transistor technology. In practical applications, they are mainly used in the form of half-bridges. However, traditional discrete devices are affected by packaging, PCB layout, etc., and half-bridge applications have low integration and low power density.

[0003] The above contents are only used to assist in understanding the technical solution of the present invention and do not constitute an admission that the above contents are prior art. Summary of the invention

[0004] The main purpose of the present invention is to provide a half-bridge GaN enhanced switching device and a preparation method thereof, aiming to solve the technical problems of low integration and low power density of half-bridge power devices in the prior art.

[0005] To achieve the above object, the present invention provides a half-bridge GaN enhanced switching device, the half-bridge GaN enhanced switching device comprising: two switching elements connected in a half-bridge;

[0006] The two switch elements are horizontally arranged on the same substrate, wherein the drain and gate of one switch element are electrically led out separately, the source is connected to the drain of another switch element and electrically led out together, and the gate and source of the other switch element are electrically led out separately.

[0007] Optionally, the switch element comprises: an intrinsic diamond substrate, a GaN buffer layer, an n-type channel layer, an intrinsic GaN layer, AlGaN, an insulating medium and a gate metal vertically from bottom to top;

[0008] The switch element further comprises: a drain metal whose bottom is arranged horizontally with the bottom of the intrinsic GaN layer;

[0009] The switch element further comprises: a source metal whose bottom is arranged horizontally with the bottom of the AlGaN;

[0010] The AlGaN layer and the intrinsic GaN layer form a conductive channel from the source metal to the n-type channel layer through a two-dimensional electron gas;

[0011] When a positive voltage is applied to the gate metal, electrons from the source metal are transferred from the two-dimensional electron gas to the conductive channel, flow along the conductive channel to the n-type channel layer, and flow laterally to the gate metal.

[0012] Optionally, the intrinsic GaN layer includes: P-type GaN and intrinsic GaN;

[0013] The bottom of the intrinsic GaN is flush with the top of the n-type channel layer and the bottom of the P-type GaN, and the top of the intrinsic GaN is flush with the AlGaN;

[0014] The p-type GaN and the intrinsic GaN form a conductive via from the AlGaN to the n-type channel layer;

[0015] The thickness of the intrinsic GaN is twice that of the P-type GaN.

[0016] Optionally, the intrinsic GaN layer includes: an insulating isolation layer and a plurality of interconnecting metals;

[0017] The insulating isolation layer is used to fill the half-bridge GaN enhanced switching device to form a rectangular section;

[0018] Each of the interconnecting metals is used to electrically lead out the drain metal, the source metal and the gate metal respectively;

[0019] The source metal of one switch element and the gate metal of another switch element are electrically led out from the same interconnection metal.

[0020] In addition, to achieve the above object, the present invention also proposes a method for preparing a half-bridge GaN enhanced switching device, which is applied to the preparation of the above half-bridge GaN enhanced switching device, and the method comprises the following steps:

[0021] Epitaxially growing an n-type GaN channel layer on an intrinsic diamond substrate with a GaN buffer layer;

[0022] Depositing an intrinsic GaN layer on the n-type GaN channel layer;

[0023] Depositing drain metal, AlGaN, source metal and insulating medium on the intrinsic GaN layer;

[0024] A gate metal is deposited on the insulating dielectric.

[0025] Optionally, the step of depositing an intrinsic GaN layer on the n-type GaN channel layer includes:

[0026] depositing a first barrier layer on the n-type GaN channel layer;

[0027] Etching an intrinsic GaN layer through hole on the first barrier layer;

[0028] An intrinsic GaN layer is deposited in the intrinsic GaN layer through hole.

[0029] Optionally, the step of depositing drain metal, AlGaN, source metal and insulating medium on the intrinsic GaN layer includes:

[0030] depositing a second barrier layer on the intrinsic GaN layer;

[0031] Etching a drain metal trench through hole flush with the bottom of the intrinsic GaN layer on the second barrier layer, and depositing a drain metal in the drain metal trench through hole;

[0032] Etching an AlGaN through hole flush with the top of the intrinsic GaN layer on the second barrier layer, and depositing AlGaN in the AlGaN through hole;

[0033] Etching a source metal through hole flush with the bottom of the AlGaN layer on the second barrier layer, and depositing a source metal in the source metal through hole;

[0034] An insulating dielectric through hole flush with the top of the AlGaN layer is etched on the second barrier layer, and an insulating dielectric is deposited in the insulating dielectric through hole.

[0035] Optionally, the step of depositing an intrinsic GaN layer in the intrinsic GaN layer through hole further includes:

[0036] Depositing a first intrinsic GaN in the through hole of the intrinsic GaN layer;

[0037] Depositing a third barrier layer on the first intrinsic GaN;

[0038] Etching a P-type GaN through hole on the third barrier layer;

[0039] Injecting P-type GaN ions into the P-type GaN through hole to form P-type GaN;

[0040] The third barrier layer is removed, and a second intrinsic GaN is deposited on the first intrinsic GaN.

[0041] Optionally, after the step of depositing a gate metal on the insulating medium, the method further includes:

[0042] Depositing an insulating isolation layer on the second intrinsic GaN;

[0043] A gate interconnection metal, a source interconnection metal and a drain interconnection metal are deposited in the insulating isolation layer.

[0044] Optionally, the step of depositing a gate interconnection metal, a source interconnection metal and a drain interconnection metal in the insulating isolation layer includes:

[0045] depositing a fourth barrier layer on the insulating isolation layer;

[0046] Etching a gate interconnection metal through hole, a source interconnection metal through hole, and a drain interconnection metal through hole on the fourth barrier layer;

[0047] A gate interconnect metal is deposited in the gate interconnect metal via, a source interconnect metal is deposited in the source interconnect metal via, and a drain interconnect metal is deposited in the drain interconnect metal via.

[0048] The technical solution of the present invention proposes a half-bridge GaN enhanced switching device and a preparation method thereof. The half-bridge GaN enhanced switching device comprises: two switching elements connected in a half-bridge; the two switching elements are horizontally arranged on the same substrate, wherein the drain and the gate of one switching element are electrically led out separately, the source is connected to the drain of the other switching element and electrically led out together, and the gate and the source of the other switching element are electrically led out separately. The conductive mechanism of the half-bridge GaN enhanced switching device is a two-dimensional electron gas, and the conduction and shutoff of the two-dimensional electron gas are controlled by the gate, so the gate charge of the device is very small, which can ensure the high-speed switching of the device. The device as a whole presents a half-bridge connection characteristic, which ensures the application flexibility. At the same time, since the device is prepared on the same substrate, it has the characteristics of high integration, which can improve the system power density. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A schematic structural diagram of a first embodiment of a half-bridge GaN enhancement mode switch device proposed by the present invention;

[0050] Figure 2 A schematic diagram of the top view of the switch device in the first embodiment of the half-bridge GaN enhancement mode switch device proposed by the present invention;

[0051] Figure 3 A schematic flow chart of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device according to the present invention;

[0052] Figure 4 A first structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device proposed by the present invention;

[0053] Figure 5 A second structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device proposed by the present invention;

[0054] Figure 6 A third structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device proposed by the present invention;

[0055] Figure 7A fourth structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device provided by the present invention;

[0056] Figure 8 A fifth structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device provided by the present invention;

[0057] Fig. 9 A sixth structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device provided by the present invention;

[0058] Fig.10 It is a seventh structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device proposed by the present invention;

[0059] Fig.11 The eighth structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device proposed by the present invention;

[0060] Fig.12 It is a ninth structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device proposed by the present invention;

[0061] Fig.13 The tenth structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device proposed by the present invention;

[0062] Fig.14 It is an eleventh structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device proposed by the present invention;

[0063] Fig.15 It is a twelfth structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device proposed by the present invention;

[0064] Fig.16 It is a thirteenth structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device provided by the present invention;

[0065] Fig.17 This is the fourteenth structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device proposed in the present invention.

[0066] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0067] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0068] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0069] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0070] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0071] Reference Figure 1 and Figure 2 , Figure 1 This is a schematic structural diagram of a first embodiment of a half-bridge GaN enhancement mode switch device proposed by the present invention. Figure 2 This is a schematic diagram of the top view of the switch device in the first embodiment of the half-bridge GaN enhanced switch device proposed by the present invention. Figure 1 A first embodiment of a half-bridge GaN enhancement mode switch device of the present invention is provided. Figure 1 for Figure 2 A cross-sectional view of the device structure cut along the dotted line.

[0072] In this embodiment, the half-bridge GaN enhanced switching device includes: two switching elements connected in a half-bridge; the two switching elements are horizontally arranged on the same substrate, wherein the drain and the gate of one switching element are electrically led out separately, the source is connected to the drain of the other switching element and electrically led out together, and the gate and the source of the other switching element are electrically led out separately.

[0073] It should be understood that the two switch elements (Q1, Q2) disposed on the same substrate both include: an intrinsic diamond substrate 10, a GaN buffer layer 20, an n-type channel layer 30, an intrinsic GaN layer 40, an AlGaN layer 50, an insulating medium 60 and a gate metal G from bottom to top; a drain metal D whose bottom is horizontally disposed with the bottom of the intrinsic GaN layer; and a source metal S whose bottom is horizontally disposed with the bottom of the AlGaN. The intrinsic GaN layer 40 includes: P-type GaN (401 in the figure) and intrinsic GaN; the bottom of the intrinsic GaN is flush with the top of the n-type channel layer 30 and the bottom of the P-type GaN, and the top of the intrinsic GaN is flush with the AlGaN; the P-type GaN and the intrinsic GaN form a conductive via from the AlGaN to the n-type channel layer 30. The thickness of the intrinsic GaN is twice that of the P-type GaN.

[0074] It should be noted that the AlGaN and the intrinsic GaN layers form a conductive channel from the source metal to the n-type channel layer through the two-dimensional electron gas; when a positive voltage is applied to the gate metal, electrons from the source metal are transmitted to the conductive channel by the two-dimensional electron gas, flow along the conductive channel to the n-type channel layer, and flow laterally to the gate metal.

[0075] In a possible implementation, the thickness of the intrinsic diamond substrate can be 500nm, the thickness of the GaN buffer layer can be 200nm, the thickness of the n-type channel layer can be 300nm, the intrinsic GaN layer can be completed by two processes with a thickness of 600nm, each process is completed with a thickness of 300nm, the thickness of the p-type GaN can be 300nm, the thickness of the AlGaN can be 200nm, the insulating dielectric material can be selected as Al2O3 with a thickness of 30nm, the gate metal thickness can be 270nm, the source metal thickness is 300nm, the distance from the drain metal of the left switching device to the leftmost side of the p-type GaN of the right switching device is ≥300nm, and under the device parameters and doping conditions, the withstand voltage level of a single device is ≥900V, and the withstand voltage of the half-bridge series device is ≥1800V.

[0076] It should be noted that the GaN buffer layer is not intentionally doped, and the natural doping concentration range is 1e14cm -3 to 5e15cm -3 The doping concentration of p-type GaN is 5e17cm -3, the ratio of Al to GaN in AlGaN is between 2:8-4:6, and the corresponding device gate conduction voltage is 1-4V. The p-type GaN structure and its corresponding doping concentration are set to form a two-dimensional electron gas from the AlGaN and intrinsic GaN layers at the upper part of the device to the n-type channel layer at the lower part of the device. The channel is controlled by the gate structure to realize the on-off control of the device structure and realize an enhanced device. Among them, the two-dimensional electron gas can be a conductive electron with very low resistivity formed at the interface between AlGaN and intrinsic GaN due to the barrier gap and its region. The electrons in this region can only move freely in two directions within the plane, and the movement in the direction perpendicular to the plane is restricted. The two-dimensional electron gas is represented by a dotted line 301 in the figure.

[0077] It should be understood that the relationship between the AlGaN ratio and the thickness of the insulating medium is to ensure that when no voltage is applied to the gate, there is no two-dimensional electron gas directly below the insulating medium, so as to achieve the enhanced characteristics of the device. When a positive voltage is applied to the device gate, electrons are formed below the device gate, and the electrons from the source are transmitted to the device gate by the two-dimensional electron gas. The electrons then flow downward along the conductive channel and flow to the drain under the action of the drain voltage. Al2O3 is selected as the insulating medium, and its thickness is 30nm to ensure the selection of gate control capability and threshold voltage. As the proportion of Al increases, the concentration of two-dimensional electron gas increases. When the thickness of Al2O3 is 30nm, zero voltage shutdown can be achieved only at the above ratio, without two-dimensional electron gas. When the thickness of aluminum oxide increases, the gate control capability decreases, affecting the device performance.

[0078] Among them, the AlGaN and intrinsic GaN layers of each switching device can form a current from the source metal to the conductive via through the two-dimensional electron gas, and have the low resistance characteristics of HEMT. The gate control mechanism is suppressed by the working mechanism of the insulating dielectric enhanced HEMT device, and has the characteristics of high switching speed. When flowing vertically in the device, the electron concentration and mobility are relatively large, which is the main source of the device's on-resistance. However, due to its low thickness, it has little effect on the device's on-resistance. The lower part of the device is n-type doped GaN, and the overall on-resistance is low, so the device as a whole presents the characteristics of high switching speed and low on-resistance.

[0079] Furthermore, the intrinsic GaN layer includes: an insulating isolation layer 70 and a plurality of interconnecting metals 80; the insulating isolation layer is used to fill the half-bridge GaN enhanced switching device to form a rectangular section; each of the interconnecting metals is used to electrically lead out the drain metal, the source metal and the gate metal respectively; wherein the source metal of one switching element and the gate metal of another switching element are electrically led out by the same interconnecting metal.

[0080] In this embodiment, the half-bridge GaN enhanced switch device includes: two switch elements connected in a half-bridge; the two switch elements are horizontally arranged on the same substrate, wherein the drain and gate of one switch element are electrically led out separately, the source is connected to the drain of the other switch element and electrically led out together, and the gate and source of the other switch element are electrically led out separately. The conductive mechanism of the half-bridge GaN enhanced switch device is two-dimensional electron gas, and the gate controls the conduction and shutoff of the two-dimensional electron gas, so the gate charge of the device is very small, which can ensure the high-speed switching of the device. The device as a whole presents a half-bridge connection characteristic, which ensures the application flexibility. At the same time, since the device is prepared on the same substrate, it has the characteristics of high integration, which can improve the system power density, and realize the half-bridge circuit required in the application on one wafer.

[0081] In addition, the present invention also provides a method for preparing a half-bridge GaN enhanced switching device. Figure 3 , Figure 3 The figure is a flow chart of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device proposed by the present invention.

[0082] In this embodiment, the method for preparing the half-bridge GaN enhancement mode switch device comprises the following steps:

[0083] Step S10: epitaxially growing an n-type GaN channel layer on the intrinsic diamond substrate with the GaN buffer layer.

[0084] Reference Figure 4 , Figure 4 This is a first structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device proposed in the present invention.

[0085] It should be noted that due to the large difference in lattice constant and thermal expansion coefficient between diamond and GaN, stress will be generated at the interface, which may cause cracks or peeling of the film. Therefore, a GaN buffer layer can be set on the intrinsic diamond substrate to reduce the lattice mismatch, thereby enhancing the adhesion of the film and the reliability of the overall device.

[0086] It should be understood that the intrinsic diamond substrate has a thickness of 500 nm, the GaN buffer layer has a thickness of 200 nm, and the n-type channel layer has a thickness of 300 nm.

[0087] Step S20: depositing an intrinsic GaN layer on the n-type GaN channel layer.

[0088] It should be noted that the intrinsic GaN layer can be completed by two processes, which can be specifically divided into the first intrinsic GaN, which is close to the n-type GaN channel layer and horizontally arranged with the P-type GaN, with a thickness of 300nm (the thickness of the P-type GaN is also 300nm). And the second intrinsic GaN, which is close to AlGaN and covers the P-type GaN and the first intrinsic GaN, has a thickness of 300nm.

[0089] Specifically, the step S20 may include:

[0090] Step S201: depositing a first barrier layer on the n-type GaN channel layer.

[0091] Step S202: etching an intrinsic GaN layer through hole on the first barrier layer.

[0092] Step S203: depositing an intrinsic GaN layer in the intrinsic GaN layer through hole.

[0093] Reference Figure 5 , Figure 5 This is a second structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device proposed in the present invention.

[0094] It should be noted that the deposited barrier layer needs to be removed when the shape transfer is performed again, and the barrier layer is re-formed. Since the barrier layer and the device material are different, they can be removed with chemical reagents without affecting other structures of the device.

[0095] Step S30: depositing drain metal, AlGaN, source metal and insulating medium on the intrinsic GaN layer.

[0096] Reference Figure 6 , Figure 6 The third structural schematic diagram of an embodiment of the method for preparing a half-bridge GaN enhanced switch device proposed in the present invention. A second barrier layer can be deposited on the first intrinsic GaN, a drain metal trench through hole flush with the bottom of the intrinsic GaN layer is etched on the second barrier layer, and a drain metal is deposited in the drain metal trench through hole. The distance from the drain metal of the left switch element to the leftmost side of the p-type GaN on the right side is ≥300nm.

[0097] Further, refer to Figure 7 and Figure 8 , Figure 7 A fourth structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device provided by the present invention; Figure 8The fifth structural schematic diagram of an embodiment of the method for preparing a half-bridge GaN enhancement mode switch device proposed in the present invention. A first intrinsic GaN can be deposited in the through hole of the intrinsic GaN layer; a third barrier layer is deposited on the first intrinsic GaN; a P-type GaN through hole is etched on the third barrier layer; P-type GaN ions are injected into the P-type GaN through hole to form P-type GaN (injection energy is 10-100kev); the third barrier layer is removed, and a second intrinsic GaN is deposited on the first intrinsic GaN.

[0098] Further, see Fig. 9 , Fig. 9 This is a sixth structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device proposed in the present invention, wherein an AlGaN through hole flush with the top of the intrinsic GaN layer is etched on the original barrier layer, and AlGaN is deposited in the AlGaN through hole, wherein the thickness of the AlGaN is 200 nm.

[0099] Further, refer to Fig.10 , Fig.10 The seventh structural schematic diagram of an embodiment of the method for preparing a half-bridge GaN enhancement mode switch device proposed by the present invention is that a source metal through hole flush with the bottom of the AlGaN is etched on the original barrier layer, and a source metal is deposited in the source metal through hole. The thickness of the source metal is 300nm.

[0100] Further, refer to Fig.11 , Fig.11 This is the eighth structural schematic diagram of an embodiment of the method for preparing a half-bridge GaN enhanced switch device proposed by the present invention, wherein an insulating medium through hole flush with the top of the AlGaN is etched on the original barrier layer, and an insulating medium is deposited in the insulating medium through hole. The insulating medium can be selected from Al2O3 with a thickness of 30nm.

[0101] Step S40: depositing gate metal on the insulating medium.

[0102] Reference Fig.12 , Fig.12 The ninth structural schematic diagram of an embodiment of the method for preparing a half-bridge GaN enhanced switch device proposed by the present invention is that a gate metal through hole flush with the top of the insulating metal is etched on the original barrier layer, and a gate metal is formed in the gate metal through hole. The thickness of the gate metal is 270nm.

[0103] Furthermore, after step S40, the following steps may be further included:

[0104] Step S50: depositing an insulating isolation layer on the second intrinsic GaN.

[0105] Reference Fig.13 , Fig.13 The tenth structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhanced switch device proposed by the present invention is a diagram in which an insulating isolation layer is deposited on the original barrier layer. The insulating isolation layer is used to fill the half-bridge GaN enhanced switch device to form a rectangular section.

[0106] Step S60: depositing gate interconnection metal, source interconnection metal and drain interconnection metal in the insulating isolation layer.

[0107] Reference Fig.14 , Fig.15 , Fig.16 and Fig.17 , Fig.14 It is an eleventh structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device proposed by the present invention; Fig.15 It is a twelfth structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device proposed by the present invention; Fig.16 It is a thirteenth structural schematic diagram of an embodiment of a method for preparing a half-bridge GaN enhancement mode switch device provided by the present invention; Fig.17 The fourteenth structural schematic diagram of an embodiment of the method for preparing a half-bridge GaN enhanced switch device proposed in the present invention is as follows. A fourth barrier layer is deposited on the insulating isolation layer; a gate interconnection metal through hole, a source interconnection metal through hole and a drain interconnection metal through hole are etched on the fourth barrier layer; a gate interconnection metal is deposited in the gate interconnection metal through hole, a source interconnection metal is deposited in the source interconnection metal through hole, and a drain interconnection metal is deposited in the drain interconnection metal through hole.

[0108] In this embodiment, the preparation method of the half-bridge GaN enhancement mode switch device may include: epitaxially growing an n-type GaN channel layer on an intrinsic diamond substrate with a GaN buffer layer; depositing a barrier layer on the first GaN channel layer, etching an intrinsic GaN layer through hole, and depositing a first intrinsic GaN layer; depositing a barrier layer on the intrinsic GaN layer, etching a drain metal trench through hole, and depositing a drain metal; removing the original barrier layer, depositing a barrier layer on the first GaN, etching a p-type GaN through hole, and performing p-type GaN ion implantation; removing the original barrier layer, depositing a barrier layer, etching an intrinsic GaN layer through hole, and depositing an intrinsic GaN layer; removing the original barrier layer, depositing a barrier layer, etching an AlG aN through hole, deposit AlGaN; remove the original barrier layer, deposit a barrier layer, etch the source metal through hole, deposit the source metal; remove the original barrier layer, deposit a barrier layer, etch the insulating dielectric through hole, deposit the insulating dielectric; remove the original barrier layer, deposit a barrier layer, etch the gate metal through hole, deposit the gate metal; remove the original barrier layer, deposit an insulating isolation layer on the second AlGaN; remove the original barrier layer, deposit a barrier layer, etch the gate interconnection metal through hole, deposit the gate interconnection metal; remove the original barrier layer, deposit a barrier layer, etch the source interconnection metal through hole, deposit the source interconnection metal; remove the original barrier layer, deposit a barrier layer, etch the drain interconnection metal through hole, and deposit the drain interconnection metal. On the basis of ensuring the low on-resistance and high switching speed of the device, the half-bridge integration of the device is realized, and the integration and power density of the device are improved on the basis of ensuring the application flexibility.

[0109] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0110] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A half-bridge GaN enhancement mode switch device, characterized in that: The half-bridge GaN enhanced switching device comprises: two switching elements connected in a half-bridge; The two switch elements are horizontally arranged on the same substrate, wherein the drain and gate of one switch element are electrically led out separately, the source is connected to the drain of the other switch element and electrically led out together, and the gate and source of the other switch element are electrically led out separately; The switch element includes: an intrinsic diamond substrate, a GaN buffer layer, an n-type channel layer, an intrinsic GaN layer, AlGaN, an insulating medium and a gate metal from bottom to top vertically; The switch element further comprises: a drain metal whose bottom is arranged horizontally with the bottom of the intrinsic GaN layer; The switch element further comprises: a source metal whose bottom is arranged horizontally with the bottom of the AlGaN; The AlGaN layer and the intrinsic GaN layer form a conductive channel from the source metal to the n-type channel layer through a two-dimensional electron gas; Setting the ratio of Al to GaN in the AlGaN to between 2:8 and 4:6 according to the gate on-voltage of the half-bridge GaN enhancement mode switch device; When a positive voltage is applied to the gate metal to reach the gate turn-on voltage, electrons from the source metal are transferred from the two-dimensional electron gas to the conductive channel, flow along the conductive channel to the n-type channel layer, and flow laterally to the drain metal; The intrinsic GaN layer includes: P-type GaN and intrinsic GaN; The bottom of the intrinsic GaN is flush with the top of the n-type channel layer and the bottom of the P-type GaN, and the top of the intrinsic GaN is flush with the AlGaN; The p-type GaN and the intrinsic GaN form a conductive via from the AlGaN to the n-type channel layer; The thickness of the intrinsic GaN is twice that of the P-type GaN.

2. The half-bridge GaN enhancement mode switch device according to claim 1, characterized in that: The intrinsic GaN layer includes: an insulating isolation layer and a plurality of interconnecting metals; The insulating isolation layer is used to fill the half-bridge GaN enhanced switching device to form a rectangular section; Each of the interconnecting metals is used to electrically lead out the drain metal, the source metal and the gate metal respectively; The source metal of one switch element and the gate metal of another switch element are electrically led out from the same interconnection metal.

3. A method for preparing a half-bridge GaN enhanced switching device, applied to the preparation of the half-bridge GaN enhanced switching device according to any one of claims 1 to 2, characterized in that: The preparation method comprises the following steps: Epitaxially growing an n-type GaN channel layer on an intrinsic diamond substrate with a GaN buffer layer; Depositing an intrinsic GaN layer on the n-type GaN channel layer; Depositing drain metal, AlGaN, source metal and insulating medium on the intrinsic GaN layer; A gate metal is deposited on the insulating dielectric.

4. The preparation method according to claim 3, characterized in that: The step of depositing an intrinsic GaN layer on the n-type GaN channel layer comprises: depositing a first barrier layer on the n-type GaN channel layer; Etching an intrinsic GaN layer through hole on the first barrier layer; An intrinsic GaN layer is deposited in the intrinsic GaN layer through hole.

5. The preparation method according to claim 4, characterized in that: The step of depositing drain metal, AlGaN, source metal and insulating medium on the intrinsic GaN layer comprises: depositing a second barrier layer on the intrinsic GaN layer; Etching a drain metal trench through hole flush with the bottom of the intrinsic GaN layer on the second barrier layer, and depositing a drain metal in the drain metal trench through hole; Etching an AlGaN through hole flush with the top of the intrinsic GaN layer on the second barrier layer, and depositing AlGaN in the AlGaN through hole; Etching a source metal through hole flush with the bottom of the AlGaN layer on the second barrier layer, and depositing a source metal in the source metal through hole; An insulating dielectric through hole flush with the top of the AlGaN layer is etched on the second barrier layer, and an insulating dielectric is deposited in the insulating dielectric through hole.

6. The preparation method according to claim 5, characterized in that: The step of depositing an intrinsic GaN layer in the intrinsic GaN layer through hole further includes: Depositing a first intrinsic GaN in the through hole of the intrinsic GaN layer; Depositing a third barrier layer on the first intrinsic GaN; Etching a P-type GaN through hole on the third barrier layer; Injecting P-type GaN ions into the P-type GaN through hole to form P-type GaN; The third barrier layer is removed, and a second intrinsic GaN is deposited on the first intrinsic GaN.

7. The preparation method according to claim 6, characterized in that: After the step of depositing a gate metal on the insulating medium, the method further comprises: Depositing an insulating isolation layer on the second intrinsic GaN; A gate interconnection metal, a source interconnection metal and a drain interconnection metal are deposited in the insulating isolation layer.

8. The preparation method according to claim 7, characterized in that: The step of depositing gate interconnection metal, source interconnection metal and drain interconnection metal in the insulating isolation layer comprises: depositing a fourth barrier layer on the insulating isolation layer; Etching a gate interconnection metal through hole, a source interconnection metal through hole, and a drain interconnection metal through hole on the fourth barrier layer; A gate interconnect metal is deposited in the gate interconnect metal via, a source interconnect metal is deposited in the source interconnect metal via, and a drain interconnect metal is deposited in the drain interconnect metal via.

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