Semiconductor structure and preparation method

Abstract

The disclosed embodiments relate to the field of semiconductors and provide a semiconductor structure and preparation method. The semiconductor structure includes: a substrate having a bit line extending along a first direction within the substrate; a semiconductor pillar located within the substrate and electrically connected to the bit line; a channel region and two doped regions located on either side of the channel region, one of the two doped regions being electrically connected to the bit line; an orthographic projection of the channel region on each of the two doped regions being located within each doped region; a word line extending along a second direction, located within the substrate, and surrounding the channel region; and a memory structure located on the substrate and electrically connected to the other of the two doped regions; wherein the first direction intersects the second direction. The disclosed semiconductor structure and preparation method can at least increase the storage density of an integrated circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] With the continuous development of integrated circuit process technology, in order to improve the integration of integrated circuits, while increasing the operating speed of memory and reducing its power consumption, the characteristic size of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) devices continues to shrink, and MOSFET devices face a series of challenges.

[0003] MOSFET devices include vertical memory transistors, which are formed in the overlapping area where the bit line and word line intersect. The width of a vertical memory transistor in the direction perpendicular to the word line is 3F, and the width in the direction perpendicular to the bit line is 2F. The area required for a memory transistor on the substrate is 6F. 2 (3F*2F, i.e. 3×2 buried word line structure), where F is the minimum feature size. However, the cell configuration size of the buried word line structure is large and the control capability is limited. Among them, "cell configuration size" refers to: for a memory cell, the cell configuration size that needs to be configured for it on the substrate, specifically including: the size that a memory cell actually needs to occupy on the substrate, and the spacing size that needs to be reserved between the memory cell and the adjacent memory cell. For example, the size occupied by N memory transistors on the substrate is M, then the cell configuration size of a memory transistor on the substrate is N / M.

[0004] How to reduce the unit configuration size and increase storage density has become an important issue that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0005] The embodiments of the present disclosure provide a semiconductor structure and a manufacturing method, which are at least beneficial for reducing the unit configuration size and improving the storage density.

[0006] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a semiconductor structure, including: a substrate, wherein the substrate has a bit line extending along a first direction; a semiconductor column, wherein the semiconductor column is located in the substrate, and the semiconductor column is electrically connected to the bit line; the semiconductor column includes a channel region and two doping regions located on both sides of the channel region, and one of the two doping regions is electrically connected to the bit line; the positive projection of the channel region in each of the two doping regions is located in each of the doping regions; a word line, wherein the word line extends along a second direction, the word line is located in the substrate, and the word line surrounds the channel region; a storage structure, wherein the storage structure is located on the substrate, and the storage structure is electrically connected to the other of the two doping regions; wherein the first direction intersects with the second direction.

[0007] In some embodiments, the semiconductor pillars are arrayed along a first direction and a second direction, the bit line is electrically connected to one doped region of each of the semiconductor pillars arranged along the first direction, and the word line surrounds the channel region of each of the semiconductor pillars arranged along the second direction.

[0008] In some embodiments, each intersection region of the bit line and the word line constitutes a transistor, the transistor includes the semiconductor column, and the two doped regions serve as a source terminal and a drain terminal of the transistor respectively.

[0009] In some embodiments, the base includes: a substrate, the bit line is located on a surface of the substrate; an isolation structure, the isolation structure is located on the surface of the substrate, and the isolation structure is located between adjacent semiconductor pillars.

[0010] In some embodiments, the word line includes a main portion and a connecting portion, the main portion is located between the two doping regions, and opposite ends of the connecting portion are respectively connected to the main portions of two adjacent semiconductor pillars.

[0011] In some embodiments, along a direction perpendicular to the surface of the substrate, an axis of the channel region overlaps with an axis of any one of the two doping regions.

[0012] According to some embodiments of the present disclosure, on the other hand, embodiments of the present disclosure further provide a method for preparing a semiconductor structure, including: providing a substrate, wherein the substrate has a bit line extending along a first direction; forming a semiconductor column, wherein the semiconductor column is located in the substrate, and the semiconductor column is electrically connected to the bit line; the semiconductor column includes a channel region and two doping regions located on both sides of the channel region, and one of the two doping regions is electrically connected to the bit line; the positive projection of the channel region in each of the two doping regions is located in each of the doping regions; forming a word line, wherein the word line extends along a second direction, the word line is located in the substrate, and the word line surrounds the channel region; forming a storage structure, wherein the storage structure is located on the substrate, and the storage structure is electrically connected to the other of the two doping regions.

[0013] In some embodiments, the process steps for forming the bit line include: providing a substrate, forming a first conductive layer on the surface of the substrate; forming a stacked first semiconductor film, a first isolation film, a second conductive layer, and a second isolation film on the surface of the first conductive layer; forming a second semiconductor film in the first isolation film, in the second conductive layer, in the second isolation film, and on the surface of the second isolation film, the second semiconductor film is located on the first semiconductor film; patterning the second semiconductor film, the second conductive layer, the first semiconductor film, and the first conductive layer to form a second groove, and the remaining first conductive layer serves as the bit line.

[0014] In some embodiments, before forming the second semiconductor film, the process further includes: patterning the first isolation film, the second conductive layer, and the second isolation film to form a first groove, wherein the bottom of the first groove exposes the first semiconductor film; and forming a continuous second semiconductor film on the surface of the first groove and the second isolation film.

[0015] In some embodiments, the process steps for forming the word line include: forming a first isolation layer, the first isolation layer is located in the second groove, and the top surface of the first isolation layer is not higher than the top surface of the second conductive layer away from the substrate; forming a third conductive layer, the third conductive layer is located in the second groove and on the surface of the first isolation layer; patterning the second semiconductor film, the second conductive layer and the first semiconductor film to form a third groove, the bottom of the third groove exposes the bit line, the extension direction of the third groove is different from the extension direction of the second groove, the remaining third conductive layer and the second conductive layer serve as the word line, and the remaining first semiconductor film and the second semiconductor film serve as the semiconductor pillar.

[0016] In some embodiments, the process steps of forming the bit lines include: providing a substrate, forming a first conductive layer on the substrate; and patterning the first conductive layer to form the bit lines arranged at intervals.

[0017] In some embodiments, after forming the first conductive layer and before patterning the first conductive layer, the process includes: forming a stacked first semiconductor film and a first spacing film on the surface of the first conductive layer, and patterning the first semiconductor film and the first spacing film while patterning the first conductive layer; the process steps of forming the semiconductor pillars and the word lines include: forming a first isolation layer, the first isolation layer is located between the spaced bit lines, the first isolation layer is away from the top surface of the substrate and is higher than the top surface of the bit lines; forming a stacked second conductive layer and a second spacing film on the surface of the first spacing film and the first isolation layer; patterning the first spacing film, the second conductive layer and the second spacing film to form a first groove, the bottom of the first groove exposing the top surface of the first semiconductor film; forming a second semiconductor film, the second semiconductor film is located in the first groove and on the surface of the first semiconductor film; patterning the second semiconductor film, the first spacing film, the second conductive layer and the second spacing film to form a third groove, the bottom of the third groove exposing the top surface of the bit line, the remaining first semiconductor film and the second semiconductor film serve as the semiconductor pillars, and the remaining second conductive layer serves as the word line.

[0018] In some embodiments, after forming the word line, the method further includes forming a second isolation layer, wherein the second isolation layer completely fills the third groove, and the second isolation layer, the substrate, and the remaining first isolation layer serve as the base.

[0019] In some embodiments, the process steps for forming the second semiconductor film include: forming a first film, wherein the first film is located in the first groove; forming a second film, wherein the second film is located on the surface of the first film and the first isolation film, wherein the first semiconductor film and the second film serve as the two doping regions, and the first film serves as the channel region, and the two doping regions and the channel region constitute the semiconductor column.

[0020] In some embodiments, a material of the first film is different from a material of at least one of the second film or the first semiconductor film.

[0021] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0022] In the semiconductor structure provided by the embodiments of the present disclosure, the bit lines extend along a first direction, and the word lines extend along a second direction, with the first and second directions intersecting. This means that the bit lines and word lines have an intersecting region in space, and this intersecting region can be used to configure the transistor structure. Compared to a case where the bit lines and word lines extend in non-intersecting directions, the semiconductor structure provided by the embodiments of the present disclosure reduces the size of the intersecting region, thereby reducing the size occupied by the bit lines and word lines. The orthographic projection of the channel region in each of the two doped regions is located within each doped region, and the word lines are located within both doped regions. Therefore, the semiconductor pillar region and the word line region overlap in space. Compared to a case where there is no overlap between the word lines and semiconductor pillars, the semiconductor structure provided by the embodiments of the present disclosure reduces the size of the overlapping region. This reduces the cell configuration size of a memory cell on the substrate, thereby increasing the storage density of the integrated circuit. Furthermore, the semiconductor structure provided by the embodiments of the present disclosure is a vertical semiconductor structure, and the word lines are not buried. Therefore, the arrangement of the word lines and bit lines does not affect critical dimensions, transistor density, manufacturing difficulty, and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A schematic diagram of a first cross-sectional structure of a semiconductor structure provided by an embodiment of the present disclosure;

[0025] Figure 2 A schematic top view of a semiconductor structure provided in one embodiment of the present disclosure;

[0026] Figure 3 for Figure 2 Schematic diagram of the first cross-sectional structure along the A1-A2 section;

[0027] Figure 4 for Figure 2 Schematic diagram of the second cross-sectional structure along the A1-A2 section;

[0028] Figures 5 to 31 This is a schematic structural diagram of the semiconductor structure corresponding to each step in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] As can be seen from the background art, the unit configuration size and storage density of current semiconductor structures need to be improved.

[0030] Embodiments of the present disclosure provide a semiconductor structure in which bit lines extend along a first direction and word lines extend along a second direction, with the first and second directions intersecting. This means that the bit lines and word lines have an intersecting region in space, and this intersecting region can be used to configure the transistor structure. Compared to a case where the bit lines and word lines extend in non-intersecting directions, the semiconductor structure provided by the present disclosure reduces the size of the intersecting region, thereby reducing the size occupied by the bit lines and word lines. The orthographic projection of the channel region in each of the two doped regions is located within each doped region, and the word lines are located within both doped regions. Therefore, the semiconductor pillar region and the word line region overlap in space. Compared to a case where there is no overlap between the word lines and semiconductor pillars, the semiconductor structure provided by the present disclosure reduces the size of the overlapping region. This reduces the cell configuration size of a memory cell on the substrate, thereby increasing the storage density of the integrated circuit. Furthermore, the semiconductor structure provided by the present disclosure is a vertical semiconductor structure, and the word lines are not buried. Therefore, the arrangement of the word lines and bit lines does not affect critical dimensions, transistor density, manufacturing difficulty, and cost.

[0031] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0032] Figure 1 A schematic diagram of a first cross-sectional structure of a semiconductor structure provided by an embodiment of the present disclosure; Figure 2 A schematic top view of a semiconductor structure provided in one embodiment of the present disclosure; Figure 3 for Figure 2 Schematic diagram of the first cross-sectional structure along the A1-A2 section; Figure 4 for Figure 2 Schematic diagram of the second cross-sectional structure along the A1-A2 section.

[0033] According to some embodiments of the present disclosure, the present disclosure provides a semiconductor structure, referring to Figure 1 The semiconductor structure includes a substrate 10 having a bit line 110 extending along a first direction X in the substrate 10 .

[0034] In some embodiments, the substrate 10 is a multi-layer structure, wherein the substrate 10 below the bit line 110 is the first portion, and the remaining area is the second portion of the substrate 10. The material of the first portion of the substrate 10 can be a semiconductor material, and the semiconductor material can include any one of silicon, germanium, silicon carbide, or silicon germanium. The first portion of the substrate 10 contains an N-type dopant element or a P-type dopant element. The N-type dopant element can be a Group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As), and the P-type dopant element can be a Group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In). The material of the second portion of the substrate 10 is an insulating material, and the insulating material can include silicon oxide, silicon nitride, or silicon oxynitride.

[0035] In some embodiments, the bit line 110 may be made of a metal material, such as silver, copper, or tungsten. Since the metal material has a low resistance, the resistance of the bit line 110 can be reduced, thereby improving the sensitivity and responsiveness of the bit line 110.

[0036] In some embodiments, when the bit line 110 is made of a metal material, a metal silicide layer is further provided between the bit line 110 and the semiconductor pillar. The metal silicide layer is used to optimize or reduce the contact resistance between the bit line 110 and the semiconductor pillar, thereby facilitating the formation of a low-resistance ohmic contact. The metal silicide layer may be made of a metal silicide, such as titanium silicide.

[0037] In some embodiments, bit line 110 may comprise a multi-layer structure comprising a first barrier layer, a conductive film, and a second barrier layer. When the conductive film is made of a metal, the first and second barrier layers act as diffusion barriers to prevent the metal material constituting bit line 110 from diffusing into substrate 10 or other devices. This diffusion of the metal reduces the concentration of metal ions in the conductive film, thereby increasing the resistance of bit line 110 and affecting the electrical performance of the semiconductor structure. Furthermore, the diffused metal ions may form electrical connections with other devices, affecting the safety and yield of the semiconductor structure. At least one of the first or second barrier layer may be made of a metal nitride, such as titanium nitride.

[0038] In some embodiments, bit line 110 is made of a semiconductor material and contains a dopant element having the same conductivity type as the dopant element in the doped region of the semiconductor pillar. When bit line 110 is made of the same material as the first portion of substrate 10, bit line 110 and the first portion of substrate 10 can be fabricated from the same original substrate, or bit line 110 can be formed by epitaxial growth based on the first portion of substrate 10.

[0039] In some embodiments, the semiconductor structure includes a semiconductor pillar 130 . The semiconductor pillar 130 is located in the substrate 10 and is electrically connected to the bit line 110 .

[0040] In some embodiments, the semiconductor pillar 130 is made of a semiconductor material, which may include silicon, germanium, or silicon germanium, and the semiconductor pillar 130 is doped with an N-type dopant element or a P-type dopant element.

[0041] In some embodiments, if the materials of the first portion of the substrate 10, the bit line 110, and the semiconductor pillar 130 are the same, there are no interface state defects or interface state thresholds between the film layers of the first portion of the substrate 10, the bit line 110, and the semiconductor pillar 130, thereby reducing the contact resistance between the bit line 110 and the semiconductor pillar 130. The doped elements located in the bit line 110 and the semiconductor pillar 130 can act as carriers, thereby accelerating the movement of carriers and obtaining a more sensitive response speed.

[0042] In some embodiments, the material of the semiconductor pillar 130 is an amorphous material. The amorphous material has gaps inside and has a high carrier mobility. This can reduce the thickness of the semiconductor pillar, reduce the line width of the semiconductor structure within a limited unit area, and further improve the storage density of the semiconductor structure. The amorphous material may include at least one of IGZO (Indium Gallium Zinc Oxide), IWO (Tungsten-doped Indium Oxide), or ITO (Indium Tin Oxide). For example, when the material of the semiconductor pillar is IGZO, the carrier mobility of IGZO is 20 to 50 times that of polysilicon, which is beneficial to improving the carrier mobility in the semiconductor pillar 130, thereby reducing the leakage current of the semiconductor structure during operation, thereby reducing the power consumption of the semiconductor structure and improving the working efficiency of the semiconductor structure.

[0043] In some embodiments, the semiconductor pillar 130 includes a channel region 132 and two doped regions 131 located on either side of the channel region 132. One of the two doped regions 131 is electrically connected to the bit line 110, and the other doped region 131 is electrically connected to the memory structure. The doping elements in the two doped regions 131 have the same conductivity type.

[0044] In some embodiments, the conductivity type of the doping element in the doping region 131 is different from the conductivity type of the doping element in the channel region 132. For example, if an N-type doping element is doped in the two doping regions 131 and a P-type doping element is doped in the channel region 132, the transistor formed by the semiconductor pillar is a junction transistor. In some embodiments, the conductivity type of the doping element in the doping region 131 is the same as the conductivity type of the doping element in the channel region 132. For example, if an N-type doping element is doped in the two doping regions 131 and an N-type doping element is doped in the channel region 132, the transistor formed by the semiconductor pillar is a junctionless transistor. The "junction" in "junctionless transistor" and "junction transistor" refers to a PN junction.

[0045] In some embodiments, the orthographic projection of the channel region 132 in each of the two doped regions 131 is located within each doped region 131. The word line 120 surrounds the channel region 132 and is located within both doped regions 131. Thus, there is a spatial overlap between the region of the semiconductor pillar 130 and the region of the word line 120. Compared to a case where there is no overlap between the word line 120 and the semiconductor pillar 130, the semiconductor structure provided by the embodiments of the present disclosure reduces the size of the overlapped region. This reduces the cell configuration size of a memory cell on the substrate, thereby increasing the storage density of the integrated circuit.

[0046] In some embodiments, the material of the channel region 132 is different from the material of the doped region 131. For example, the material of the channel region 132 is silicon germanium, and the material of the doped region 131 is silicon. The lattice constant of silicon germanium is greater than that of silicon. Due to the difference in lattice constants, the doped region 131 will generate compressive stress toward the channel region 132, thereby increasing the mobility of carriers (electrons or holes) in the channel region 132, thereby improving the drive current and the speed of the transistor.

[0047] In some embodiments, along a direction Z perpendicular to the surface of the substrate 10, the axis of the channel region 132 overlaps with the axis of any of the two doping regions 131 or deviates by ±10% of the maximum width of the channel region 132. In this way, the thickness of each portion of the word line 120 subsequently formed around the channel region 132 is relatively uniform, and the controllability of the channel region 132 is better.

[0048] The first direction X intersects the second direction Y. For example, Figure 1 The first direction X and the second direction Y in the semiconductor structure shown are perpendicular to each other. In other embodiments, the minimum angle between the first direction X and the second direction Y can be any value less than or equal to 90°.

[0049] In some embodiments, the semiconductor structure includes a word line 120 . The word line 120 extends along a second direction Y. The word line 120 is located in the substrate 10 . The word line 120 surrounds the channel region 132 .

[0050] In some embodiments, the word line 120 may be a single film layer or a three-layer film structure along a direction Z perpendicular to the surface of the substrate 10. The three-layer film structure includes a third barrier layer, a second conductive film, and a fourth barrier layer. The material of the word line 120 or the material of the second conductive film is a metal material, and the material of the third barrier layer and the fourth barrier layer is a metal nitride.

[0051] In some embodiments, word line 120 is made of a semiconductor material and contains a dopant element. The conductivity type of the dopant element is determined based on the actual requirements of the semiconductor structure. Word line 120 may be made of polysilicon. Because the band gap of polysilicon and the material of channel region 132 of semiconductor pillar 130 is similar, and the work function of polysilicon can be modified by controlling the dopant concentration, this helps reduce the threshold voltage between the gate and channel region 132. The dopant element type of the doped polysilicon can be the same as or different from the dopant element type of channel region 132 of semiconductor pillar 130.

[0052] In some embodiments, the semiconductor structure further includes a gate dielectric layer 108, and the gate dielectric layer 108 is located between the word line 120 and the channel region 132 of the semiconductor pillar 130. The gate dielectric layer 108 may be made of silicon oxynitride, silicon nitride, or a high-k material to suppress short channel effects and, therefore, tunneling leakage current. High-k materials include hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanate.

[0053] In some embodiments, the semiconductor structure further includes a first film layer 107, which is positioned between the word line 120 and the gate dielectric layer 108. When the word line 120 or the second conductive film is a metal material, the material of the first film layer 107 may be a metal nitride. The first film layer 107 acts as a metal diffusion barrier, preventing the metal material from diffusing into the gate dielectric layer 108 or even into the subsequently formed semiconductor pillars, thereby improving the yield of the semiconductor structure. When the word line is made of a semiconductor material or a metal material, the first film layer 107 may be a work function layer, regulating the threshold voltage of the channel region by controlling the work function of the gate. For example, in an NMOS gate process, the first film layer 107 is a thin layer of La2O3, which contains more negatively charged atoms. In a PMOS gate process, the first film layer 107 is a thin layer of Al2O3, which contains more positively charged atoms. The NMOS device refers to a device including a first semiconductor film doped with an N-type dopant element, and the PMOS device refers to a device including a first semiconductor film doped with a P-type dopant element.

[0054] In some embodiments, when the word line 120 is made of a semiconductor material and the first film layer 107 is made of a work function layer, a titanium nitride layer may be included between the first film layer 107 and the gate dielectric layer 108. The purpose of embedding the titanium nitride layer is to address the polysilicon gate depletion problem in the metal-embedded gate process. The embedded work function layer can also address the Fermi level pinning phenomenon. The work function layer may be a doped polysilicon layer. When the word line 120 is made of a work function material, the first film layer 107 is made of titanium nitride.

[0055] In some embodiments, each intersection region of the bit line 110 and the word line 120 constitutes a transistor. The transistor includes a semiconductor pillar 130 and two doped regions 131 serving as a source terminal and a drain terminal of the transistor, respectively.

[0056] In some embodiments, the semiconductor structure includes a storage structure 140 . The storage structure 140 is located on the substrate 10 . The storage structure 140 is electrically connected to the other doping region 131 of the two doping regions.

[0057] In some embodiments, the storage structure 140 can be arranged as follows: Figure 2 The hexagonal closest packed arrangement shown can also be arranged in an array along the first direction X and the second direction Y. The film layers of the storage structure can be any film layers, such as a conventional first electrode plate, a dielectric layer and a second electrode plate, and the first electrode plate is in electrical contact with the electrical connection layer.

[0058] In some embodiments, the semiconductor structure further includes an electrical connection layer 111, which is located between the semiconductor pillar 130 and the storage structure 140. The electrical connection layer 111 may be a metal silicide layer, which is used to reduce contact resistance and facilitate ohmic contact formation. The electrical connection layer 111 may be a metal layer, which serves as a contact plug between the storage structure 140 and the semiconductor pillar 130.

[0059] In some embodiments, the semiconductor structure further includes a first spacer 103 and a second spacer 105. The first spacer 103 is located between the word line 120 and one of the doped regions 131, and the second spacer 105 is located between the word line 120 and the other doped region 131. The first spacer 103 or the second spacer 105 can serve as a support layer for supporting components located on the first spacer 103 or the second spacer 105. The first spacer 103 or the second spacer 105 can serve as an isolation layer for insulating the word line 120 from the semiconductor pillar 130. The material of the first spacer 103 or the second spacer 105 can be silicon oxide, silicon nitride, or silicon oxynitride.

[0060] refer to Figures 2 to 4In some embodiments, a plurality of semiconductor pillars 130 are arrayed along a first direction X and a second direction Y, the bit line 110 is electrically connected to one of the doped regions 131 of each semiconductor pillar 130 arranged along the first direction X, and the word line 120 surrounds the channel region 132 of each semiconductor pillar 130 arranged along the second direction Y.

[0061] In some embodiments, the substrate 10 includes: a substrate 100, with a bit line 110 located on the surface of the substrate 100; and an isolation structure located on the surface of the substrate 100 and between adjacent semiconductor pillars 130. The first portion of the substrate 10 is the substrate 100, and the second portion of the substrate 10 is the isolation structure.

[0062] In some embodiments, the isolation structure includes a first isolation layer 113 and a second isolation layer 118. The first isolation layer 113 is located between a bit line and a semiconductor pillar and another bit line and a semiconductor pillar. The second isolation layer 118 is located between the electrical connection layer 111 and another electrical connection layer. The material of the first isolation layer 113 or the second isolation layer 117 includes silicon oxide, silicon oxynitride, or silicon nitride.

[0063] In some embodiments, reference Figure 3 The word line 120 includes a main body portion 121 and a connecting portion 122 . The main body portion 121 is located between two doping regions 131 . The opposite ends of the connecting portion 122 are respectively connected to the main bodies 121 of two adjacent semiconductor pillars 130 .

[0064] In some embodiments, the material of the main body 121 or the connecting portion 122 may include a metal material. The effect of the main body 121 or the connecting portion 122 being a metal material is the same as the effect of the word line being a metal material, and will not be repeated here.

[0065] In some embodiments, the material of the main body 121 can be the same as that of the connecting portion 122. If barrier layers are provided on the upper and lower surfaces of the main body 121, barrier layers are also provided on the upper and lower surfaces of the connecting portion 122, with the corresponding barrier layers of the main body 121 corresponding to the corresponding barrier layers of the connecting portion 122, and the corresponding barrier layers are in contact with each other. The barrier layers can form a relatively complete barrier function between the materials of the main body 121 and the connecting portion 122, ensuring that the resistance values ​​of the main body 121 and the connecting portion 122 are relatively low while maintaining high stability of the semiconductor structure.

[0066] In some embodiments, the material of the connection portion 122 is different from that of the main body 121. For example, the resistance of the material of the connection portion 122 is lower than that of the main body 121. This can reduce the resistance of the word line, improve gate control capability, and improve word line response speed. For another example, the material of the main body 121 is a work function material, the material of the connection portion 122 is a metal material, and a titanium nitride layer is provided between the connection portion 122 and the main body 121.

[0067] In some embodiments, the side surface of the main body portion 121 may be in complete contact with the side surface opposite to the connecting portion 122 , or the side surface of the main body portion 121 may be in partial contact with the side surface opposite to the connecting portion 122 .

[0068] In some embodiments, the semiconductor structure further includes a third isolation layer 119 , which is used to isolate the storage structure 140 . The third isolation layer 119 is located on the surface of the electrical connection layer 111 and the second isolation layer 118 .

[0069] The embodiment of the present disclosure provides a semiconductor structure, in which the bit line 110 is arranged to extend along a first direction X, and the word line 120 is arranged to extend along a second direction Y, and the first direction X intersects the second direction Y, that is, the bit line 110 and the word line 120 have an intersecting region in space, and this intersecting region can be used to set the transistor structure. Compared with the case where the extension directions of the bit line 110 and the word line 120 do not intersect, the semiconductor structure provided by the embodiment of the present disclosure reduces the size occupied by an intersecting region, thereby reducing the size occupied by the bit line 110 and the word line 120. The orthographic projection of the channel region 132 in each of the two doping regions 131 is located in each doping region 131, and the word line 120 is located in the two doping regions 131, so the region of the semiconductor column 130 and the region of the word line 120 have an overlapping region in space. Compared to a structure without overlapping regions between word lines 120 and semiconductor pillars 130, the semiconductor structure provided by the disclosed embodiment reduces the size of the overlapping regions. This reduces the size of the cell configuration required for each memory cell on the substrate, thereby increasing the storage density of the integrated circuit. Furthermore, the semiconductor structure provided by the disclosed embodiment is a vertical semiconductor structure, and word lines 120 are not buried. Therefore, the arrangement of word lines 120 and bit lines 110 does not affect critical dimensions, transistor density, manufacturing difficulty, or cost.

[0070] Accordingly, the present disclosure also provides a method for preparing a semiconductor structure, which is used to prepare the semiconductor structure provided in the above embodiment ( Figures 1 to 4 The semiconductor structure shown in FIG5 ) and the elements that are the same as or corresponding to the above embodiments are not described in detail here.

[0071] Figures 5 to 31This is a schematic diagram of the structure of the semiconductor structure corresponding to each step in the method for preparing the semiconductor structure provided in one embodiment of the present disclosure. Figure 5 、 Figures 7 to 10 、 Figures 12 to 15 、 Figure 17 、 Figures 19 to 27 、 Figure 29 and Figure 31 It is a schematic diagram of the cross-section structure. Figure 7 for Figure 6 Schematic diagram of the cross-section structure along the A1-A2 section, Figure 12 for Figure 11 Schematic diagram of the cross-sectional structure along the A1-A2 section; Figure 17 for Figure 16 Schematic diagram of the cross-section structure along the A1-A2 section, Figure 19 for Figure 18 Schematic diagram of the cross-section structure along the A1-A2 section, Figure 29 for Figure 28 Schematic diagram of the cross-sectional structure along the A1-A2 section; Figure 31 for Figure 30 Schematic diagram of the cross-sectional structure along the A1-A2 section.

[0072] refer to Figures 5 to 31 According to some embodiments of the present disclosure, the present disclosure also provides a method for preparing a semiconductor structure, including: providing a substrate 10, wherein the substrate 10 has a bit line 110 extending along a first direction X; forming a semiconductor pillar 130, wherein the semiconductor pillar 130 is located in the substrate 110, and the semiconductor pillar 130 is electrically connected to the bit line 110; the semiconductor pillar 130 includes a channel region 132 and two doping regions 131 located on both sides of the channel region 132, wherein one of the doping regions 131 of the two doping regions is electrically connected to the bit line 110; an orthographic projection of the channel region 132 on each of the two doping regions 131 is located in each of the doping regions 131; and forming a word line 120, wherein the word line 120 extends along a second direction Y, the word line 120 is located in the substrate 10, and the word line 120 surrounds the channel region 132.

[0073] refer to Figure 5 The preparation method includes: providing a substrate 100 and forming a first conductive layer 101 on the surface of the substrate 100.

[0074] In some embodiments, the substrate 100 may be a wafer having a regular shape. The substrate 100 may be made of a semiconductor material, which may include any one of silicon, germanium, silicon carbide, or silicon germanium.

[0075] In some embodiments, the substrate 100 contains an N-type dopant element or a P-type dopant element. The N-type dopant element may be a Group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As), and the P-type dopant element may be a Group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0076] In some embodiments, the material of the first conductive layer 101 can be a metal material, such as silver, copper, or tungsten. The first conductive layer 101 will subsequently serve as an independent bit line. When the material of the first conductive layer 101 is a metal material, the metal material has a low inherent resistance, which can reduce the inherent resistance of the bit line, thereby improving the sensitivity and responsiveness of the bit line. The first conductive layer 101 can be formed by any process including physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). The thickness of the first conductive layer 101 can be any value.

[0077] In some embodiments, when the material of the first conductive layer 101 is a metal material, a metal silicide layer may be formed on the surface of the first conductive layer 101. The metal silicide layer is used to optimize or reduce the contact resistance between the subsequently formed bit line and the semiconductor pillar, thereby facilitating the formation of a low-resistance ohmic contact. The material of the metal silicide layer includes a metal silicide, such as titanium silicide. The metal silicide layer may be formed by PVD, CVD, or ALD processes.

[0078] In some embodiments, when the material of the first conductive layer 101 is a metal material, two barrier layers are formed before and after the formation of the first conductive layer 101, one barrier layer being located between the substrate 100 and the first conductive layer 101, and the other barrier layer being located on the surface of the first conductive layer 101. The barrier layers serve as diffusion barriers to prevent the metal material constituting the first conductive layer 101 from diffusing into the substrate 100 or other devices. Firstly, the diffusion of the metal material reduces the concentration of metal ions in the first conductive layer 101, thereby increasing the resistance of the first conductive layer 101 itself and affecting the electrical performance of the semiconductor structure. Secondly, the diffused metal ions may form electrical connections with other devices, affecting the safety performance and yield of the semiconductor structure. The barrier layer material may be a metal nitride, such as titanium nitride.

[0079] In some embodiments, the barrier layer may be formed by a plasma nitridation process; alternatively, the barrier layer may be formed by a PVD, CVD, or ALD process.

[0080] In some embodiments, the material of the first conductive layer 101 is a semiconductor material, and the first conductive layer 101 contains doping elements, and the conductivity type of the doping elements is the same as the conductivity type of the doping elements in the doping region in the semiconductor column. The steps of forming the first conductive layer 101 and the substrate 100 may include: providing an original substrate, performing an ion implantation process on a portion of the thickness of the original substrate from the surface of the original substrate, the original substrate subjected to the ion implantation process serving as the first conductive layer 101, and the remaining original substrate serving as the substrate 100. In this way, the first conductive layer 101 is a semiconductor material, and there will be no interface state threshold between the first conductive layer 101 and the semiconductor column, thereby reducing the contact resistance between the first conductive layer 101 and the semiconductor column. The doping elements located in the first conductive layer and the semiconductor column can act as carriers, thereby accelerating the movement of carriers and obtaining a more sensitive response speed. The first conductive layer 101 and the substrate 100 are prepared on the same original substrate, and the first conductive layer 101 is formed by an ion implantation process on a partial thickness of the original substrate. The ion implantation process requires annealing and activation of the doping elements in the first conductive layer. Annealing can repair some defects of the first conductive layer and the substrate, thereby obtaining a better morphology, which is beneficial to reducing the resistance value of the substrate and the first conductive layer itself.

[0081] Continue to refer Figure 5 A first semiconductor film 102 , a first isolation film 103 , a second conductive layer 104 and a second isolation film 105 are stacked on the surface of the first conductive layer 101 .

[0082] In some embodiments, the material of the first semiconductor film 102 is a semiconductor material, which may include silicon, germanium, or silicon germanium, and the first semiconductor film 102 contains a doping element, which may be an N-type doping element or a P-type doping element.

[0083] In some embodiments, if the material of the first conductive layer 101 is a semiconductor material, the method for forming the first semiconductor film 102 can be an in-situ doping process. The in-situ doping process can not only ensure uniform distribution of dopant ions within the first semiconductor film 102, but also avoid the impact of diffusion and high-temperature annealing of ion implantation on the first semiconductor film 102. In some embodiments, an initial film layer can be first formed by an epitaxial growth process, PVD, CVD, or ALD, and then ion implantation and high-temperature annealing processes can be performed on the initial film layer to form the first semiconductor film 102.

[0084] In some embodiments, if the substrate 100, the first conductive layer 101, and the first semiconductor film 102 are made of the same material, the substrate 100, the first conductive layer 101, and the first semiconductor film 102 are formed from a single original substrate through different ion implantation processes. The depth and distribution of the doping impurities are controlled by controlling the energy of the ion implantation, and the concentration of the doping impurities is controlled by controlling the concentration or charge of the ion implantation. This is followed by an annealing process. This reduces the number of annealing steps required for the substrate, the first conductive layer, and the first semiconductor film. Furthermore, the ion implantation process operates at a lower temperature, minimizing thermal damage to the substrate 100, the first conductive layer 101, and the first semiconductor film 102. This prevents thermal defects caused by high-temperature diffusion and changes in the chemical composition of the substrate 100, the first conductive layer 101, and the first semiconductor film 102. Furthermore, even with large-area impurity implantation, the uniformity of the substrate 100, the first conductive layer 101, and the first semiconductor film 102 can be maintained.

[0085] In some embodiments, the material of the first semiconductor film 102 is an amorphous material. The amorphous material has gaps inside and has a high carrier mobility. This can reduce the thickness of the first semiconductor film 102, reduce the line width of the semiconductor structure within a limited unit area, and further improve the storage density of the semiconductor structure. The amorphous material may include at least one of IGZO (Indium Gallium Zinc Oxide), IWO (Tungsten-doped Indium Oxide), or ITO (Indium Tin Oxide). For example, when the material of the first semiconductor film 102 is IGZO, the carrier mobility of IGZO is 20 to 50 times that of polysilicon, which is beneficial for improving the carrier mobility in the first semiconductor film 102, thereby reducing the leakage current of the semiconductor structure during operation, thereby reducing the power consumption of the semiconductor structure and improving the operating efficiency of the semiconductor structure. The first semiconductor film 102 can be formed by PVD, CVD, or ALD processes.

[0086] In some embodiments, the first spacer 103 can serve as a support layer for supporting components located on the first spacer 103, such as word lines. The first spacer 103 can also serve as an isolation layer for insulating the word lines from the first semiconductor film 102. The material of the first spacer 103 can be silicon oxide, silicon nitride, or silicon oxynitride. The first spacer 103 can be formed by PVD, CVD, or ALD.

[0087] In some embodiments, the second conductive layer 104 can be made of a metal material, such as silver, titanium, or tungsten. The second conductive layer 104 subsequently serves as an independent word line. When the second conductive layer 104 is made of a metal material, the metal material has a low inherent resistance, which can reduce the inherent resistance of the word line, thereby improving the controllability of the gate. The second conductive layer 104 can be formed using PVD, CVD, or ALD processes. The thickness of the second conductive layer 104 can be any value.

[0088] In some embodiments, when the second conductive layer 104 is made of a metal material, two barrier layers are formed before and after the second conductive layer 104 is formed: one barrier layer is located between the first spacer 103 and the second conductive layer 104, and the other barrier layer is located between the second conductive layer 104 and the second spacer 105. These barrier layers act as diffusion barriers to prevent the metal material constituting the second conductive layer 104 from diffusing into the substrate 100 or other devices. Diffusion of the metal material reduces the concentration of metal ions in the second conductive layer 104, thereby increasing the resistance of the second conductive layer 104 and affecting the electrical performance of the semiconductor structure. Furthermore, the diffused metal ions may form electrical connections with other devices, affecting the safety and yield of the semiconductor structure. The barrier layers may be made of a metal nitride, such as titanium nitride.

[0089] In some embodiments, the material of the second conductive layer 104 is a semiconductor material and contains a dopant element. The conductivity type of the dopant element is determined based on the actual requirements of the semiconductor structure. The material of the second conductive layer 104 can be polycrystalline silicon. Since polycrystalline silicon has a similar energy gap to the material used in the channel region of the semiconductor pillar, and the work function of polycrystalline silicon can be modified by controlling the dopant concentration, it is beneficial to reduce the threshold voltage between the gate and the channel region. The dopant element type of the doped polycrystalline silicon can be the same as or different from the dopant element type of the channel region of the semiconductor pillar to be formed later.

[0090] The thickness of the second conductive layer 104 depends in part on the length of the channel region of the subsequently formed semiconductor pillar. For example, if the length of the channel region of the semiconductor pillar provided in the embodiment of the present disclosure is 180 nm, the thickness of the second conductive layer 104 is between 180 nm ± 20 nm.

[0091] In some embodiments, the second spacer film 105 can serve as a support layer for supporting components located thereon, such as memory structures and doped regions of semiconductor pillars. The second spacer film 105 can also serve as an isolation layer for insulating the word lines from the second semiconductor film. The material of the second spacer film 105 can be silicon oxide, silicon nitride, or silicon oxynitride. The second spacer film 105 can be fabricated using PVD, CVD, or ALD processes.

[0092] refer to Figures 6 to 9 The preparation method includes: patterning the first isolation film 103, the second conductive layer 104 and the second isolation film 105 to form a first groove 123, and the bottom of the first groove 123 exposes the first semiconductor film 102.

[0093] In some embodiments, the cross-sectional shape of the first groove 123 parallel to the substrate surface can be as follows: Figure 6 The through hole 106 shown is circular, and may also be elliptical, approximately circular, or any other shape. The embodiment of the present disclosure does not limit the specific morphology of the first groove 123 , as long as the bottom of the first groove 123 exposes the surface of the first semiconductor film 102 .

[0094] It is understandable that since the etching process cannot be precisely controlled to only etch the first isolation film 103 without etching the first semiconductor film 102, it is possible that a portion of the thickness of the first semiconductor film 102 may be etched, but this does not constitute a defect of the preparation method provided in the embodiment of the present disclosure.

[0095] The following references Figures 6 to 9 The steps of forming the first groove 123 are described in detail.

[0096] refer to Figure 6 and Figure 7 The preparation method includes patterning the second spacer film 105 and the second conductive layer 104 to form a through hole 106, with the bottom of the through hole 106 exposing the first spacer film 103. By etching only to the top surface of the first spacer film 103 to form the through hole 106, rather than etching to the bottom of the through hole 106 to expose the top surface of the first semiconductor film 102, the first spacer film 103 is retained as an etching protection layer to prevent the first semiconductor film 102 from being significantly damaged in subsequent etching processes, thereby improving the performance of the semiconductor pillar and thus the performance of the semiconductor structure.

[0097] It is understandable that since the etching process cannot be precisely controlled to only etch the second conductive layer 104 without causing etching damage to the second isolation film 105, it is possible that a portion of the thickness of the second isolation film 105 will be etched. This does not constitute a defect of the preparation method provided in the embodiment of the present disclosure.

[0098] In some embodiments, the method for patterning the second spacer film 105 and the second conductive layer 104 may include a dry etching process and a wet etching process. The second spacer film 105 and the second conductive layer 104 may be patterned in the same preparation process or etched in two separate etching processes.

[0099] refer to Figure 8 The preparation method includes: sequentially forming a stacked first film layer 107 and a gate dielectric layer 108 on the inner wall surface of the through hole 106 , the bottom of the through hole 106 , and the top surface of the second spacing film 105 .

[0100] In some embodiments, when the second conductive layer 104 is made of a metal material, the first film layer 107 may be made of a metal nitride. The first film layer 107 acts as a metal diffusion barrier, preventing the metal material from diffusing into the gate dielectric layer 108 or even into subsequently formed semiconductor pillars, thereby improving the yield of the semiconductor structure.

[0101] In some embodiments, when the material of the second conductive layer 104 is a semiconductor material or a metal material, the first film layer 107 can be a work function layer, and the threshold voltage of the channel region is adjusted by regulating the work function of the gate. When the material of the second conductive layer 104 is a semiconductor material, and the material of the first film layer 107 is a work function layer, a titanium nitride layer can also be included between the first film layer 107 and the gate dielectric layer 108. The purpose of embedding the titanium nitride layer is to solve the problem of polysilicon gate depletion in the metal embedded gate process. The embedded work function layer can solve the pinning phenomenon of the Fermi level. The work function layer can be a doped polysilicon layer. When the material of the second conductive layer 104 is a work function material, the material of the first film layer 107 is titanium nitride.

[0102] In some embodiments, the gate dielectric layer 108 may be made of silicon oxynitride, silicon nitride, or a high-k material to suppress short channel effects and thereby tunneling leakage current. Examples of high-k materials include hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanate.

[0103] In some embodiments, because transistors require higher gate capacitance to attract charge into the channel, reducing the thickness of the gate dielectric layer 108 can enhance the transistor's current drive capability, improving speed and power characteristics. At the same time, reducing the thickness of the gate dielectric layer 108 can exacerbate the current tunneling effect and reduce the reliability of the gate dielectric layer. When the gate dielectric layer 108 is made of a high-k dielectric material, a thicker dielectric layer can be used, resulting in higher gate oxide capacitance and, therefore, lower leakage.

[0104] It is understandable that, in the preparation method, only the gate dielectric layer 108 may be formed without forming the first film layer 107 .

[0105] refer to Figure 9 The preparation method includes etching the gate dielectric layer 108 and the first film layer 107 at the bottom of the through hole, and etching the first spacer film 103 along the inner wall of the gate dielectric layer 108 to form a first groove 123 until the bottom of the first groove 123 exposes the top surface of the first semiconductor film 102. The first groove 123 is formed using a dry etching process or a wet etching process.

[0106] Continue to refer Figure 9 The preparation method includes: etching and removing the gate dielectric layer 108 and the first film layer 107 located on the top surface of the second spacer film 105. The gate dielectric layer 108 and the first film layer 107 can be removed by a planarization process.

[0107] refer to Figure 10 The preparation method includes: forming a second semiconductor film 109 in the first isolation film 103, in the second conductive layer 104, in the second isolation film 105, and on the surface of the second isolation film 105, and the second semiconductor film 109 is located on the first semiconductor film 102.

[0108] In some embodiments, a continuous second semiconductor film 109 is formed in the first groove and on the surface of the second spacer film 105 .

[0109] In some embodiments, the second semiconductor film 109 is used as a doping region and a channel region of the semiconductor pillar. The material of the second semiconductor film 109 includes any of the above-mentioned semiconductor materials or amorphous materials.

[0110] In some embodiments, the second semiconductor film 109 may be doped with doping elements of the same conductivity type as the doping elements in the first semiconductor film 102. For example, if the first semiconductor film 102 is doped with N-type doping elements and the second semiconductor film 109 is doped with N-type doping elements, the transistor is a junctionless transistor.

[0111] In some embodiments, the second semiconductor film 109 includes two layers stacked one above the other, with the first film located within the first spacer film 103, the second conductive layer 104, and the second spacer film 105, and the second film located on the second spacer film 105 and the surface of the first film. The conductivity type of the doping element in the first film is different from the conductivity type of the doping element in the second film, and the conductivity type of the doping element in the second film is the same as the conductivity type of the doping element in the first semiconductor film 102. For example, if the first semiconductor film 102 is doped with an N-type doping element, the first film is doped with a P-type doping element, and the second film is doped with an N-type doping element, then the transistor is a junction transistor. The "junction" in "junctionless transistor" and "junction transistor" refers to a PN junction.

[0112] In some embodiments, the material of the first film is the same as that of the second film, that is, the first film and the second film are prepared in the same preparation process, that is, the second semiconductor film 109 is prepared in the same process. In this way, the process difficulty of forming the second semiconductor film 109 can be reduced and the process steps of forming the second semiconductor film 109 can be shortened. If the materials of the first film and the second film are exactly the same, there will be no defects between the interface states of different materials, and the doping elements and carriers can diffuse and migrate unimpeded in the second semiconductor film 109, thereby improving the response speed of the semiconductor column. In some embodiments, the material of the first film is different from the material of the second film or at least one of the first semiconductor films. For example, the material of the first film is germanium silicon, and the material of the second film is silicon. The lattice constant of germanium silicon is greater than the lattice constant of silicon. Due to the difference in lattice constants, the second film will generate compressive stress in the direction of the first film, thereby increasing the mobility of carriers (electrons or holes) in the channel region, thereby improving the driving current and the speed of the transistor. Among them, the first film corresponds to the channel region, and the second film corresponds to the doping region.

[0113] In some embodiments, the process steps for forming the second semiconductor film 109 include: forming a first film, the first film being located in the first groove; forming a second film, the second film being located on the surface of the first film and the first isolation film, the first semiconductor film and the second film serving as two doping regions, the first film serving as a channel region, and the two doping regions and the channel region forming a semiconductor column.

[0114] Continue to refer Figure 10 The preparation method includes: forming an electrical connection layer 111 on the top surface of the second semiconductor film 109, and the electrical connection layer 111 is used as a capacitor plug later.

[0115] In some embodiments, the electrical connection layer 111 may be a metal silicide layer, which is used to reduce contact resistance and facilitate formation of ohmic contact. The electrical connection layer 111 may be a metal layer, which is used as a contact plug between the storage structure and the semiconductor pillar.

[0116] refer to Figure 11 and Figure 12 The preparation method includes: patterning the second semiconductor film 109, the second conductive layer 104, the first semiconductor film 102 and the first conductive layer to form a second groove 112, and the remaining first conductive layer serves as the bit line 110.

[0117] In some embodiments, the second groove 112 is not only used to divide the spaced apart discrete bit lines 110, but also used to divide the semiconductor pillars or transistor structures spaced apart along the first direction X, thereby reducing the two-step patterning step to a one-step patterning step, reducing the number of masks, and helping to reduce the preparation cost.

[0118] The extending direction of the second groove 112 is the same as the extending direction of the bit line 110. It can be understood that Figure 11 The ends of the second groove 112 along the first direction X are not aligned with the ends of the electrical connection layer 111. This is because the semiconductor structure includes an array region and a peripheral region, with the peripheral region surrounding the array region. The devices in the array region are used to implement the devices in the peripheral region. The preparation method and semiconductor structure provided in the embodiments of the present disclosure only define the array region and not the peripheral region. Therefore, the area where the second groove is not aligned with the electrical connection layer is used to subsequently form the devices in the peripheral region. In some embodiments, along the first direction, the ends of the second groove are aligned with the electrical connection layer, that is, the second groove at least separates the electrical connection layer from each other along the second direction Y.

[0119] refer to Figure 13 and Figure 14 The process steps for forming word line 120 include: forming a first isolation layer 113, the first isolation layer 113 being located within the second groove 112, and the top surface of the first isolation layer 113 being no higher than the top surface of the second conductive layer 104 away from the substrate 100. This allows more space for forming the word line, and also reduces the contact area between the subsequently formed third conductive layer and the second conductive layer 104, thereby reducing the resistance of the word line itself and the contact resistance between the third conductive layer and the second conductive layer 104.

[0120] In some embodiments, the top surface of the first isolation layer 113 is higher than the top surface of the first semiconductor film 102 away from the substrate 100. This prevents electrical connection between the third conductive layer and the first semiconductor film 102 and prevents metal elements constituting the third conductive layer from diffusing into the first semiconductor film 102 and the substrate, thereby increasing the resistance of the third conductive layer and making the semiconductor structure unsafe.

[0121] refer to Figure 13 , forming a second film layer 124, which fills the second groove and the top surface of the electrical connection layer 111. In some embodiments, the top surface of the second film layer 124 away from the substrate 100 is higher than the top surface of the second conductive layer 104 away from the substrate 100.

[0122] In some embodiments, the material of the second film layer 124 includes insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride, which is used to achieve electrical insulation between the word line and the first semiconductor film 102 and the first conductive layer 101 .

[0123] refer to Figure 14 , partially etch the second film layer 124 so that the top surface of the second film layer 124 is no higher than the top surface of the second conductive layer 104 away from the substrate 100 and higher than the top surface of the first semiconductor film 102 away from the substrate 100, and the remaining second film layer 124 serves as the first isolation layer 113.

[0124] refer to Figure 15 The process steps for forming the word line 120 include: forming a third film 114, and the third film 114 is used to define the word lines that are formed subsequently and are separated from each other.

[0125] In some embodiments, the material of the third film 114 includes insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride. The third film 114 is used to achieve electrical insulation between adjacent word lines.

[0126] In some embodiments, the third film 114 serves as a sacrificial layer and is subsequently removed during wordline segmentation. The third film 114 serves to position the wordlines and transistors. In the same etching process, the etching rate of the material constituting the third film 114 and the etching rate of the material of the subsequently formed third conductive layer may differ.

[0127] refer to Figure 16 as well as Figure 17 The process steps for forming the word line include: etching a portion of the third film 114 to form a fifth groove 115, where the fifth groove 115 is located to form a portion of the word line connecting the two transistors.

[0128] The bottom of the fifth groove 115 exposes the first isolation layer 113 , and the fifth groove 115 is still part of the second groove, or it can be considered that the second groove has the third film 114 and the fifth groove 115 distributed at intervals.

[0129] refer to Figure 18 and Figure 19 The process steps for forming the word line include: forming a third conductive layer 116, the third conductive layer 116 being located in the second groove and on the surface of the first isolation layer 113. The third conductive layer 116 is also located in the fifth groove.

[0130] In some embodiments, the material of the third conductive layer 116 may include a metal material. The effect of the third conductive layer 116 being a metal material is the same as the effect of the second conductive layer 104 being a metal material, and is not repeated here.

[0131] In some embodiments, the material of the third conductive layer 116 can be the same as that of the second conductive layer 104. If barrier layers are provided on the upper and lower surfaces of the second conductive layer 104, then barrier layers are also provided on the upper and lower surfaces of the third conductive layer 116. The barrier layers corresponding to the second conductive layer 104 and the barrier layers corresponding to the third conductive layer 116 correspond one-to-one, and the corresponding barrier layers are in contact with each other. The barrier layers can provide a relatively complete barrier function between the second conductive layer 104 and the third conductive layer 116, ensuring low resistance values ​​for the second conductive layer 104 and the third conductive layer 116 while maintaining high stability of the semiconductor structure.

[0132] In some embodiments, the material of the third conductive layer 116 is different from the material of the second conductive layer 104. For example, the resistance of the material of the third conductive layer 116 is lower than that of the second conductive layer 104. This can reduce the resistance of the word line, improve gate control capability, and improve word line response speed. For another example, the material of the second conductive layer 104 is a work function material, the material of the third conductive layer 116 is a metal material, and a titanium nitride layer is provided between the second conductive layer 104 and the third conductive layer 116.

[0133] In some embodiments, the side surface of the second conductive layer 104 may be in full contact with the side surface opposite to the third conductive layer 116 , or the side surface of the second conductive layer 104 may be in partial contact with the side surface opposite to the third conductive layer 116 .

[0134] It is understood that the technical solution provided in the above embodiment first forms the spaced-apart third film and then forms the third conductive layer. The preparation method provided in the embodiment of the present disclosure may also first form the spaced-apart third conductive layer and then form the third film.

[0135] refer to Figure 28 and Figure 29 The patterned electrical connection layer 111, the second semiconductor film 109, the second conductive layer, the second spacer film 105, and the first semiconductor film 102 form a third groove 117. The bottom of the third groove 117 can expose the top surface of the bit line 110. The extension direction of the third groove 117 is different from the extension direction of the second groove. The remaining second conductive layer and the third conductive layer serve as word lines 120. The remaining first semiconductor film and the second semiconductor film serve as semiconductor pillars 130, wherein the remaining first semiconductor film serves as one of the doped regions 131, the remaining second semiconductor film located on top of the second spacer film 105 serves as another doped region 131, and the remaining second semiconductor film located within the first spacer film, the second conductive layer, and the second spacer film serves as a channel region 132. The remaining second conductive layer serves as the main body 121, and the third conductive layer serves as the connecting portion 122.

[0136] In some embodiments, the third film may be removed during the process of forming the third groove, and an integrated isolation structure may be formed in a subsequent process to achieve electrical insulation between semiconductor pillars and between word lines.

[0137] In some embodiments, the formed second groove does not overlap with the first groove, and the third groove does not overlap with the first groove, then the outer wall surface of the channel region of the semiconductor column surrounds the second conductive layer, that is, the gate structure surrounds the channel region, then the semiconductor structure is a gate-all-around (GAA) transistor, and the GAA structure can realize the four-sided wrapping of the channel region of the semiconductor by the gate, which can largely solve the problems of leakage current, capacitance effect and short channel effect caused by the reduction of the gate spacing size, reduce the area occupied by the gate line structure in the vertical direction, and is conducive to enhancing the gate control performance and improving the integration of the semiconductor structure.

[0138] It can be understood that the reason why the two ends of the third groove along the second direction Y are not aligned with the two ends of the electrical connection layer 111 is similar to the reason why the two ends of the third groove along the second direction Y are not aligned with the two ends of the electrical connection layer 111. Figure 11 The reason why the two ends of the second groove in the first direction X are not aligned with the two ends of the electrical connection layer is the same as that in FIG.

[0139] In the technical solution provided in the above embodiment, the word line is divided into two separate parts, that is, the word line includes a main body and a connecting part. The embodiment of the present disclosure also provides a preparation method. The word line is a complete whole. Figures 19 to 27 A detailed description will be given, and the same elements or features as above will not be repeated here.

[0140] refer to Figure 20 The preparation method includes: providing a substrate 100, and forming a stacked first conductive layer 101, a first semiconductor film 102 and a first isolation film 103 on the substrate 100.

[0141] refer to Figure 21 The preparation method includes patterning the first conductive layer 101, the first semiconductor film 102, and the first spacer film 103 to form fourth grooves 125. The bottom of the fourth grooves 125 exposes the surface of the substrate 100 to form spaced bit lines 110. The remaining first conductive layer 101 serves as a separate spaced bit line structure.

[0142] In some embodiments, only a first conductive layer may be formed and then patterned to form spaced bit lines; thereafter, a sacrificial layer may be formed to fill the gaps between the bit lines; a first semiconductor film and a first spacer film may be formed, and subsequent film layers may be formed. Figures 20 to 21 The preparation method reduces the step of forming a sacrificial layer and the photomask required for patterning the first semiconductor film and the first spacer film, thereby reducing the preparation difficulty and process steps, and reducing costs.

[0143] refer to Figure 22The preparation method includes forming a first isolation layer 113, the first isolation layer 113 being located between the spaced bit lines 110, the first isolation layer 113 being away from the top surface of the substrate 100 and higher than the top surface of the bit lines 110. In some embodiments, the first isolation layer is located in the fourth groove 125.

[0144] Continue to refer Figure 22 The preparation method includes: forming a stacked second conductive layer 104 and a second spacing film 105 on the surfaces of the first spacing film 103 and the first isolation layer 113.

[0145] refer to Figures 23 to 25 The preparation method includes: patterning the first isolation film 103, the second conductive layer 104 and the second isolation film 105 to form a first groove 123, the bottom of the first groove 123 exposes the top surface of the first semiconductor film 102.

[0146] In some embodiments, Figures 23 to 25 In the provided preparation method, the second spacer film and the second conductive layer are patterned to form a through hole, and the bottom of the through hole exposes the first spacer film; a stacked first film layer 107 and a gate dielectric layer 108 are sequentially formed on the inner wall surface of the through hole, the bottom of the through hole, and the top surface of the second spacer film; the gate dielectric layer 108 and the first film layer 107 at the bottom of the through hole are etched, and the first spacer film is etched along the inner wall surface of the gate dielectric layer 108 to form a first groove, until the bottom of the first groove exposes the top surface of the first semiconductor film and the Figures 6 to 9 The preparation direction is the same as in, and will not be repeated here to avoid excessive repetition.

[0147] refer to Figure 26 The preparation method includes: forming a second semiconductor film 109, the second semiconductor film 109 is located in the first groove and on the surface of the first semiconductor film 102.

[0148] Continue to refer Figure 26 The preparation method includes: forming an electrical connection layer 111 on the surface of the second semiconductor film 109.

[0149] refer to Figure 27 The preparation method includes: patterning the electrical connection layer 111 and the second semiconductor film 109 to form an eighth groove 126 , the bottom of the eighth groove 126 exposing the top surface of the second isolation film 105 or the second conductive layer 104 .

[0150] The second isolation film may be etched or not etched, and the second isolation film may serve as an etching barrier layer, an etching stop layer or a protective layer to protect the second conductive layer from etching damage.

[0151] The preparation method includes: patterning the second semiconductor film, the first isolation film 103, the second conductive layer and the second isolation film 105 to form a third groove, the bottom of the third groove exposes the top surface of the bit line 110, the remaining first semiconductor film and the second semiconductor film serve as the semiconductor column 130, and the remaining second conductive layer serves as the word line 120.

[0152] refer to Figure 30 and Figure 31 After forming the word line 120, the process further includes forming a second isolation layer 118. The second isolation layer 118 completely fills the third groove. The second isolation layer 118, the substrate 110, and the remaining first isolation layer 113 serve as the base 10. The second isolation layer 118 is made of an insulating material such as silicon nitride, silicon oxide, or silicon oxynitride, and is used to achieve electrical insulation between transistors.

[0153] refer to Figures 2 to 4 The preparation method includes: forming a third isolation layer 119, the third isolation layer 119 is located on the surface of the substrate 10; forming a storage structure 140, the storage structure 140 is located on the substrate 10 and is located in the third isolation layer 119, and the storage structure 140 is electrically connected to the other doping region 131 of the two doping regions.

[0154] In some embodiments, the storage structure 140 can be arranged as follows: Figure 2 The hexagonal closest packed arrangement shown can also be arranged in an array along the first direction and the second direction. The film layers of the storage structure 140 can be any film layers, such as a conventional first electrode plate, a dielectric layer and a second electrode plate, and the first electrode plate is in electrical contact with the electrical connection layer.

[0155] It can be understood that the method for preparing the semiconductor structure provided in the embodiment of the present disclosure prepares multiple transistor structures, but does not provide a method for preparing a single transistor structure. However, those skilled in the art can reduce the size of the preparation and remove the graphical steps for dividing the transistors according to the preparation method provided above to prepare a transistor structure.

[0156] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the scope defined in the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a bit line extending along a first direction; forming a semiconductor pillar located in the substrate and electrically connected to the bit line; the semiconductor pillar comprising a channel region and two doped regions located on either side of the channel region, one of the two doped regions being electrically connected to the bit line; and an orthographic projection of the channel region on each of the two doped regions being located within each of the doped regions; forming a word line, wherein the word line extends along a second direction, the word line is located in the substrate, and the word line surrounds the channel region; forming a storage structure, wherein the storage structure is located on the substrate and is electrically connected to the other of the two doping regions; The process steps of forming the bit line include: Providing a substrate, and forming a first conductive layer on the surface of the substrate; forming a stacked first semiconductor film, a first isolation film, a second conductive layer, and a second isolation film on a surface of the first conductive layer; forming a second semiconductor film in the first spacing film, in the second conductive layer, in the second spacing film, and on the surface of the second spacing film, wherein the second semiconductor film is located on the first semiconductor film; The second semiconductor film, the second conductive layer, the first semiconductor film and the first conductive layer are patterned to form a second groove, and the remaining first conductive layer serves as the bit line.

2. The method for preparing a semiconductor structure according to claim 1, wherein: Before forming the second semiconductor film, the method further includes: patterning the first isolation film, the second conductive layer and the second isolation film to form a first groove, wherein the bottom of the first groove exposes the first semiconductor film; and forming a continuous second semiconductor film on the surface of the first groove and the second isolation film.

3. The method for preparing a semiconductor structure according to claim 1, wherein: The process steps of forming the word line include: forming a first isolation layer, wherein the first isolation layer is located in the second groove, and a top surface of the first isolation layer is no higher than a top surface of the second conductive layer away from the substrate; forming a third conductive layer, wherein the third conductive layer is located in the second groove and on the surface of the first isolation layer; The second semiconductor film, the second conductive layer and the first semiconductor film are patterned to form a third groove, the bottom of the third groove exposes the bit line, the extension direction of the third groove is different from the extension direction of the second groove, the remaining third conductive layer and the second conductive layer serve as the word line, and the remaining first semiconductor film and the second semiconductor film serve as the semiconductor pillar.

4. The method for preparing a semiconductor structure according to claim 1, wherein: The process step of forming the bit lines further includes: patterning the first conductive layer to form the bit lines arranged at intervals; After forming the first conductive layer and before patterning the first conductive layer, the method includes: forming a stacked first semiconductor film and a first isolation film on the surface of the first conductive layer, and patterning the first semiconductor film and the first isolation film while patterning the first conductive layer; The process steps of forming the semiconductor pillar and the word line include: forming a first isolation layer, wherein the first isolation layer is located between the spaced-apart bit lines, and the first isolation layer is away from a top surface of the substrate and is higher than a top surface of the bit lines; forming a stacked second conductive layer and a second spacing film on surfaces of the first spacing film and the first isolation layer; Patterning the first spacing film, the second conductive layer, and the second spacing film to form a first groove, wherein the bottom of the first groove exposes the top surface of the first semiconductor film; A second semiconductor film is formed, and the second semiconductor film is located in the first groove and on the surface of the first semiconductor film; the second semiconductor film, the first spacing film, the second conductive layer and the second spacing film are patterned to form a third groove, and the bottom of the third groove exposes the top surface of the bit line, the remaining first semiconductor film and the second semiconductor film serve as the semiconductor column, and the remaining second conductive layer serves as the word line.

5. The method for preparing a semiconductor structure according to claim 4, wherein: After forming the word line, the method further includes forming a second isolation layer, wherein the second isolation layer completely fills the third groove, and the second isolation layer, the substrate, and the remaining first isolation layer serve as the base.

6. The method for preparing a semiconductor structure according to claim 5, wherein: The process steps for forming the second semiconductor film include: forming a first film, wherein the first film is located in the first groove; forming a second film, wherein the second film is located on the surface of the first film and the first isolation film, wherein the first semiconductor film and the second film serve as the two doping regions, and the first film serves as the channel region, and the two doping regions and the channel region constitute the semiconductor column.

7. A semiconductor structure, wherein the semiconductor structure is prepared by the preparation method according to any one of claims 1 to 6, characterized in that: include: a substrate having a bit line extending along a first direction; a semiconductor pillar located in the substrate and electrically connected to the bit line; the semiconductor pillar comprising a channel region and two doped regions located on either side of the channel region, one of the two doped regions being electrically connected to the bit line; an orthographic projection of the channel region on each of the two doped regions being located within each of the doped regions; a word line extending along a second direction, the word line being located in the substrate and surrounding the channel region; a storage structure being located on the substrate and electrically connected to the other of the two doped regions; The first direction intersects with the second direction.

8. The semiconductor structure according to claim 7, wherein: A plurality of semiconductor pillars are arrayed along a first direction and a second direction, the bit line is electrically connected to one doped region of each of the semiconductor pillars arranged along the first direction, and the word line surrounds a channel region of each of the semiconductor pillars arranged along the second direction; Each intersection region of the bit line and the word line forms a transistor. The transistor includes the semiconductor column, and the two doping regions serve as a source terminal and a drain terminal of the transistor respectively.

9. The semiconductor structure according to claim 8, wherein: The base comprises: a substrate, the bit line is located on the surface of the substrate; an isolation structure, the isolation structure is located on the surface of the substrate, and the isolation structure is located between adjacent semiconductor pillars; The word line includes a main body portion and a connecting portion. The main body portion is located between the two doping regions. Two opposite ends of the connecting portion are respectively connected to the main bodies corresponding to two adjacent semiconductor pillars.

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