Semiconductor structure and manufacturing method thereof

Abstract

The present disclosure relates to the field of semiconductors and provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a first wafer having a first surface and a second surface facing each other, the first wafer including a first gate, a first source, and a first drain, the top surface of the first gate being flush with the first surface and higher than the top surface of the first source, and the first drain being located on a side of the first gate closer to the second surface; and a second wafer having a third surface and a fourth surface facing each other and bonded to the first surface, the second wafer including a second gate, a second source, and a second drain, the second source being closer to the third surface, the top surface of the second gate being lower than the bottom surface of the second source, and the second drain being electrically connected to the first gate. This can provide a novel 2TOC semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] With the continuous growth of semiconductor market demand, semiconductor memory technology has developed rapidly. In particular, dynamic random access memory (DRAM) has occupied a leading position in the memory market. A typical DRAM cell consists of a transistor and a capacitor in a 1T1C structure. To improve cell performance and reduce cell area, a capacitor with a large capacitance per unit area is required.

[0003] With the increasing demands on DRAM cell storage performance and cell size, the 1T1C cell presents a severe challenge. Research has shown that, given a certain size and appropriate dopants, transistors can accommodate a small amount of charge without any capacitance, as the transistor gate acts as a natural capacitor. By forming a 2T0C embedded DRAM structure, a two-transistor, capacitor-free structure is created, necessitating a new 2T0C semiconductor structure. Summary of the Invention

[0004] The embodiments of the present disclosure provide a semiconductor structure, which can at least provide a new 2TOC semiconductor structure.

[0005] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a semiconductor structure, including: a first wafer having a first surface and a second surface relative to each other, the first wafer including a first transistor, the first transistor including a first gate, a first source and a first drain, the top surface of the first gate away from the second surface is flush with the first surface, the top surface of the first gate is higher than the top surface of the first source, and the first drain is located on the side of the first gate close to the second surface; a second wafer having a third surface and a fourth surface relative to each other, the fourth surface is opposite to and bonded to the first surface, the second wafer including a second transistor, the second transistor including a second gate, a second source and a second drain, the second source is closer to the third surface than the second drain, the top surface of the second gate is lower than the bottom surface of the second source, and the second drain is electrically connected to the first gate.

[0006] In some embodiments, the first gate includes: a first portion and a second portion, the first portion is located on a top surface of the second portion away from the second surface, the top surface of the first portion away from the second surface is flush with the first surface, and in a direction perpendicular to the first surface pointing to the second surface, the width of the first portion is greater than the width of the second portion.

[0007] In some embodiments, the width of the first portion is 1.5 to 2.5 times the width of the second portion.

[0008] In some embodiments, the first wafer further includes: a first word line connected to the first source; a first bit line connected to the first drain, and the first bit line is located on a side of the first word line close to the second surface.

[0009] In some embodiments, the first wafer further includes: a first dielectric layer, the first dielectric layer covering a surface of the first gate facing away from the first surface; a first channel layer, the first channel layer covering a surface of the first dielectric layer, and the first channel layer contacts a top surface of the first bit line away from the second surface.

[0010] In some embodiments, a material of the first channel layer includes indium gallium zinc oxide.

[0011] In some embodiments, the second wafer further includes: a second word line, the second word line is located on the second gate, and the second word line is away from the top surface of the second gate and flush with the third surface; a second bit line, the second bit line is connected to the second drain, and the second bit line is located on the side of the second gate close to the fourth surface.

[0012] In some embodiments, the second wafer further includes a conductive via located between the second word line and the second gate to electrically connect the second word line and the second gate.

[0013] In some embodiments, the second wafer further includes: a second dielectric layer, the second dielectric layer covering the surface of the second gate facing away from the third surface; a second channel layer, the second channel layer covering the surface of the second dielectric layer, and the bottom surface of the second channel layer close to the fourth surface is lower than the top surface of the second drain close to the third surface.

[0014] In some embodiments, a height difference between a bottom surface of the second channel layer and a top surface of the second drain is 5-10 nm.

[0015] In some embodiments, a bottom surface of the second drain away from the third surface is flush with the fourth surface, and the second drain is in direct contact with and bonded to the first gate.

[0016] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, including: forming a first wafer having a relative first surface and a second surface, the first wafer including a first transistor, the first transistor including a first gate, a first source and a first drain, the top surface of the first gate being higher than the top surface of the first source, and the first drain being located on a side of the first gate close to the second surface; forming a second wafer having a relative third surface and a fourth surface, the second wafer including a second transistor, the second transistor including a second gate, a second source and a second drain, the second source being closer to the third surface than the second drain, and the top surface of the second gate being lower than the bottom surface of the second source; bonding the first surface to the fourth surface to electrically connect the first gate and the second drain.

[0017] In some embodiments, the method of forming the first wafer includes: providing a first initial wafer, the first initial wafer including: a first substrate and a first initial isolation structure located on the first substrate, the first substrate including: a first drain and a first initial source, the first drain is located in the first initial wafer, and the top surface of the first initial source is flush with the top surface of the first substrate; etching the first initial isolation structure and the first initial source to form a first groove, the first groove exposes the top surface of the first drain, and the remaining first initial isolation structure serves as the first isolation structure, and the remaining first initial source serves as the first source; forming a first channel layer, the first channel layer is located on the inner wall of the first groove; forming a first dielectric layer, the first dielectric layer is located on the surface of the first channel layer; forming the first gate, the first gate is located on the top surface of the first dielectric layer and the first gate fills the first groove.

[0018] In some embodiments, the first initial isolation structure includes: a first initial sub-isolation layer, a second initial sub-isolation layer, and a third initial sub-isolation layer that are stacked, and the method of forming the first groove includes: a first etching process, etching the first initial isolation structure and the first initial source to form a first initial groove, the first initial groove exposing the top surface of the first drain; a second etching process, etching the third initial sub-isolation layer along the side wall of the third initial sub-isolation layer exposed by the first initial groove to form the first groove.

[0019] In some embodiments, the first initial isolation structure includes: a first initial sub-isolation layer, a second initial sub-isolation layer, and a third initial sub-isolation layer that are stacked, and the method of forming the first groove includes: etching the third initial sub-isolation layer to form a first trench, the first trench exposing the surface of the second initial sub-isolation layer; forming a sacrificial layer, the sacrificial layer filling the first trench, and the sacrificial layer also covering the surface of the third initial sub-isolation layer; etching the sacrificial layer, the second initial sub-isolation layer, the first initial sub-isolation layer and the first initial source to form a second trench, the projection of the second trench on the first substrate is located within the projection of the first trench on the first substrate; removing the sacrificial layer, and the first trench and the second trench constitute the first groove.

[0020] In some embodiments, the method for forming the second wafer includes: providing a second initial wafer, the second initial wafer including: a second substrate and a second initial isolation structure located on the second substrate, the second substrate including a second drain and a second initial source, the second drain is located in the second initial wafer, and the top surface of the second initial source is flush with the top surface of the second substrate; etching the second initial isolation structure and the second initial source to form a second groove, the remaining second initial isolation structure serves as the second isolation structure, the remaining second initial source serves as the second source, and the second groove exposes the top surface of the second drain; forming a second channel layer, the second channel layer covers the inner wall of the second groove, and the second channel layer is in contact with the surface of the second drain; forming a second dielectric layer, the second dielectric layer covers the surface of the second channel layer away from the second drain; forming a second gate, the second gate is located in the second groove, and is in contact with the second dielectric layer.

[0021] In some embodiments, after forming the second gate, the method further includes: forming a first isolation layer, the first isolation layer being located on the top surface of the second gate, and the first isolation layer and the second gate forming a receiving space; and forming a conductive through hole in the receiving space.

[0022] In some embodiments, after forming the conductive via, the method further includes: forming a second word line, where the second word line is located on a top surface of the conductive via and is electrically connected to the second gate through the conductive via.

[0023] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: the semiconductor structure includes a first wafer and a second wafer, the first wafer includes a first transistor, and the first transistor includes a first gate, a first source and a first drain, and the top surface of the first gate is flush with the first surface, thereby facilitating bonding the first gate of the first transistor to the second transistor; the second wafer includes a second transistor, and the second transistor includes a second gate, a second source and a second drain, and the top surface of the second gate is lower than the bottom surface of the second source, thereby improving the integration of the semiconductor structure while reducing the parasitic capacitance between the second gate and the second source, avoiding short circuit between the second gate and the second source, and improving the reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 A schematic structural diagram of a semiconductor structure provided in one embodiment of the present disclosure;

[0026] Figures 2 to 8 A schematic structural diagram corresponding to each step of a method for forming a first wafer provided in one embodiment of the present disclosure;

[0027] Figures 9 to 16 A schematic structural diagram corresponding to each step of a manufacturing method for forming a second wafer provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] As known from the background art, as the integration level continues to shrink, the process of forming capacitors becomes increasingly difficult.

[0029] The present disclosure provides a semiconductor structure. A first wafer includes a first transistor, a second wafer includes a second transistor, and the first gate of the first transistor is electrically connected to the second drain of the second transistor. Thus, the first gate of the first transistor can be equivalent to a capacitor, and the second transistor can be used as a transistor connected to the capacitor to form a 2T0C semiconductor structure. At the same time, by setting the top surface of the first gate of the first transistor flush with the first surface, it is convenient to bond the first gate of the first transistor to the second transistor. By setting the top surface of the second gate lower than the bottom surface of the second source, the integration of the semiconductor structure can be improved while reducing the parasitic capacitance between the second gate and the second source, and avoiding short circuit between the second gate and the second source, thereby improving the reliability of the semiconductor structure.

[0030] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0031] refer to Figure 1 , Figure 1 A schematic structural diagram of a semiconductor structure provided by the present disclosure.

[0032] In some embodiments, the semiconductor structure may include: a first wafer 100 having a first surface 101 and a second surface 102 relative to each other, the first wafer 100 including a first transistor 110, the first transistor 110 including a first gate 111, a first source 112 and a first drain 113, the top surface of the first gate 111 away from the second surface 102 is flush with the first surface 101, the top surface of the first gate 111 is higher than the top surface of the first source 112, and the first drain 113 is located on the side of the first gate 111 close to the second surface 102.

[0033] In some embodiments, the semiconductor structure may further include: a second wafer 200 having a relative third surface 201 and a fourth surface 202, the fourth surface 202 being opposite to and bonded to the first surface 101, the second wafer 200 including a second transistor 210, the second transistor 210 including a second gate 211, a second source 212 and a second drain 213, the second source 212 being closer to the third surface 201 than the second drain 213, the top surface of the second gate 211 being lower than the bottom surface of the second source 212, the third spacing being smaller than the fourth spacing, and the second drain 213 being electrically connected to the first gate 111.

[0034] By providing a first wafer 100 including a first transistor 110 and a second wafer 200 including a second transistor 210, and electrically connecting the first gate 111 of the first transistor 110 to the second drain 213 of the second transistor 210, the first gate 111 of the first transistor 110 can be equivalent to a capacitor, and the second transistor 210 can be used as a transistor connected to the capacitor to form a 2T0C semiconductor structure. At the same time, by setting the top surface of the first gate 111 of the first transistor 110 flush with the first surface 101, it is convenient to bond the first gate 111 of the first transistor 110 to the second transistor 210. By setting the top surface of the second gate 211 of the second transistor 210 lower than the bottom surface of the second source 212, the parasitic capacitance between the second gate 211 and the second source 212 can be reduced while improving the integration of the semiconductor structure, and short circuit between the second gate 211 and the second source 212 can be avoided, thereby improving the reliability of the semiconductor structure.

[0035] In some embodiments, the first wafer 100 may include a first substrate 120. The material of the first substrate 120 may include a semiconductor material, such as, but not limited to, silicon. In some embodiments, the first substrate 120 may include a base semiconductor, a compound semiconductor, or an alloy semiconductor. For example, base semiconductors include germanium; compound semiconductors include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or Group III-V semiconductor materials; and alloy semiconductors include silicon germanium, silicon germanium carbide, germanium-tin, silicon-germanium-tin, gallium arsenic phosphide, gallium indium phosphide, gallium indium arsenide, indium gallium arsenide, aluminum indium arsenide, and / or aluminum gallium arsenide. In some embodiments, the first substrate 120 may also be a silicon-on-insulator (SOI) structure, a silicon-germanium-on-insulator (SGI) structure, a germanium-on-insulator (GOI) structure, or a combination thereof.

[0036] In addition, the first substrate 120 can be doped according to design requirements (e.g., a P-type substrate or an N-type substrate). In some embodiments, the first substrate 120 can be doped with P-type dopant ions (e.g., boron ions, aluminum ions) or N-type dopant ions (e.g., phosphorus ions, arsenic ions).

[0037] In some embodiments, the first gate 111 may include a first portion 114 and a second portion 115. The first portion 114 is located on a top surface of the second portion 115 away from the second surface 102. The top surface of the first portion 114 away from the second surface 102 is flush with the first surface 101. In a direction perpendicular to the first surface 101 and directed toward the second surface 102, the width of the first portion 114 is greater than the width of the second portion 115. By configuring the first gate 111 to include the first portion 114 and the second portion 115, and the first portion 114 to be wider than the second portion 115, the surface area of ​​the first gate 111 exposed on the first wafer 100 can be increased, thereby facilitating electrical connection between the first gate 111 and the second drain 213 after the first wafer 100 and the second wafer 200 are bonded. Furthermore, the greater the width of the top surface of the first portion 114, the lower the resistance of the first portion 114, thereby reducing the resistance of the first gate 111.

[0038] In other words, the morphology of the first gate 111 can be "T"-shaped, that is, the surface area of ​​the side surface of the first gate 111 away from the second surface 102 is large, and the surface area of ​​the side surface close to the second surface 102 is small, so that it is convenient to electrically connect the first gate 111 and the second drain 213 in the semiconductor structure manufacturing process, and the reliability of the electrical connection between the first gate 111 and the second drain 213 can be improved.

[0039] In some embodiments, the width of the first portion 114 is 1.5 to 2.5 times the width of the second portion 115. For example, the width of the first portion 114 is 1.5 or 2 times the width of the second portion 115. Figure 1 In the cross-sectional view shown and in the direction perpendicular to the first surface 101 and pointing to the second surface 102, the size of the first portion 114 and the width of the second portion 115 are Figure 1 In the cross-sectional view shown and in the direction perpendicular to the first surface 101 pointing to the second surface 102, the size of the second portion 115 can be improved by setting the width of the first portion 114 to 1.5 to 2.5 times the width of the second portion 115, while avoiding the width of the top surface of the first gate 111 being too large while improving the reliability of the electrical connection between the first gate 111 and the second drain 213.

[0040] It can be understood that the smaller the width of the first part 114, the poorer the ability to improve the reliability of the electrical connection between the first gate 111 and the second drain 213. The larger the width of the first part 114, the more it will affect the arrangement of other structures in the semiconductor structure when the size of the semiconductor structure is constant. If the width of the first part 114 is less than 1.5 times the width of the second part 115, the ability to improve the reliability of the electrical connection between the first gate 111 and the second drain 213 is poor, and it may even affect the resistance of the first part 114. If the width of the first part 114 is greater than 2.5 times the width of the second part 115, the width of the first part 114 will be too large, affecting other structures in the semiconductor structure.

[0041] In some embodiments, the first wafer 100 includes a plurality of first transistors 110 , and the plurality of first transistors 110 are arranged at intervals.

[0042] In some embodiments, each first transistor 110 in the plurality of first transistors 110 includes a first portion 114 and a second portion 115. In this case, the width of the first portion 114 also needs to consider the spacing between adjacent first transistors 110. If the width of the first portion 114 is too large, the spacing between the first gates 111 of adjacent first transistors 110 will be too small, resulting in more parasitic capacitance between adjacent first transistors 110, and may also cause a short circuit between adjacent first transistors 110.

[0043] In some embodiments, the widths of the first parts 114 of the multiple first transistors 110 may be the same. The "same" here means that the widths of the first parts of the multiple first transistors 110 are exactly the same, or the width difference between the first parts 114 of different first transistors 110 is within the allowable error range. By setting the widths of the first parts 114 of the multiple first transistors 110 to be the same, the entire semiconductor structure manufacturing process can be facilitated.

[0044] In some embodiments, the widths of the first portions 114 of the plurality of first transistors 110 may be partially the same, partially different, or the widths of the first portions 114 of each of the plurality of first transistors 110 may be different. For example, the width of the first portion 114 of the first transistor 110 located at the edge of the first wafer 100 may be greater than the width of the first portion 114 of the first transistor 110 located at the center of the first wafer 100.

[0045] It should be noted that the center of the first wafer 100 here refers to the part that occupies 3 / 5 of the volume of the first wafer 100 in the radial direction of the first wafer 100, and the edge of the first wafer 100 refers to the part wrapped around the center of the first wafer 100 and away from the central axis of the first wafer 100.

[0046] In some embodiments, the semiconductor structure includes a first substrate 120 , a portion of the first gate 111 is located within the first substrate 120 , and a portion of the first gate 111 is located on the first substrate 120 .

[0047] In some embodiments, the first gate 111 includes a first portion 114 and a second portion 115 , wherein the top surface of the second portion 115 is higher than the top surface of the first substrate 120 , and the bottom surface of the second portion 115 is lower than the bottom surface of the first substrate 120 , and the first portion 114 is located on the first substrate 120 and is spaced apart from the first substrate 120 .

[0048] In some embodiments, the first wafer 100 includes a first substrate 120 , and the first source 112 is flush with a top surface of the first substrate 120 . In some embodiments, the first source 112 may be formed by doping the first substrate 120 .

[0049] In some embodiments, the first wafer 100 includes a first substrate 120 , and the first drain 113 is located in the first substrate 120 . In some embodiments, the first drain 113 may also be formed by doping the first substrate 120 .

[0050] In some embodiments, the first wafer 100 may further include: a first word line 130, the first word line 130 is connected to the first source 112; a first bit line 140, the first bit line 140 is connected to the first drain 113, and the first bit line 140 is located on the side of the first word line 130 close to the second surface 102. For the first wafer 100, the first bit line 140 and the first word line 130 are structures for reading whether the first transistor 110 stores charge. If the first gate 111 of the first transistor 110 stores charge, a high level is passed to the first bit line 140. If the high level can be read from the first word line 130, it proves that charge is stored in the first gate 111. Conversely, if a high level is passed to the first bit line 140, if the high level cannot be read from the first word line 130, it means that no charge is stored in the first gate 111.

[0051] In some embodiments, the first word line 130 may include: a first word line conductive layer and a first word line protective layer, wherein the first word line conductive layer is the portion of the first word line 130 used to transmit data information, and the first word line protective layer is the portion of the first word line 130 used to protect the first word line conductive layer.

[0052] In some embodiments, the first word line conductive layer may be a stack of multiple conductive film layers. In some embodiments, the first word line conductive layer may also be a single film layer.

[0053] In some embodiments, the material of the first word line conductive layer may be at least one of copper or tungsten.

[0054] In some embodiments, the first word line protection layer may be a stack of multiple insulating film layers. In some embodiments, the first word line protection layer may also be a single film layer.

[0055] In some embodiments, the material of the first word line protection layer may be at least one of silicon oxide or silicon nitride.

[0056] In some embodiments, the first wafer 100 may further include: a first dielectric layer 150, the first dielectric layer 150 covering a surface of the first gate 111 facing away from the first surface 101; and a first channel layer 160, the first channel layer 160 covering a surface of the first dielectric layer 150 and contacting a top surface of the first bit line 140 facing away from the second surface 102. The first dielectric layer 150 is used to isolate the first gate 111 from the first substrate 120, and also to isolate the first gate 111 from the first source 112 and the first drain 113, thereby preventing electrical connection between the first gate 111 and the first drain 113 and the first source 112. The provision of the first channel layer 160 allows for a conductive path between the first source 112 and the first drain 113.

[0057] In some embodiments, the first channel layer 160 also covers the top surface of the first drain 113 away from the second surface 102. The first channel layer 160 surrounds the outer surface of the first gate 111 to form a vertical annular channel device structure CAA (Channel-All-Around). By providing the first channel layer 160 around the outer surface of the first gate 111, the device area can be reduced and support the stacking of multi-layer semiconductor structures.

[0058] In some embodiments, the material of the first dielectric layer 150 may be a material having a relative dielectric constant greater than 7. It is understood that the higher the relative dielectric constant, the better the insulation of the first dielectric layer 150, the better the insulation performance between the first gate 111 and the first drain 113 and the first source 112, and the less likely leakage occurs between the first gate 111 and the first drain 113 and the first source 112. By setting the material of the first dielectric layer 150 to be a material having a relative dielectric constant greater than 7, the reliability of the formed capacitor structure can be improved.

[0059] It should be noted that the relative dielectric constant here means: taking the value of the absolute dielectric constant of free space or vacuum as the standard, the relative dielectric constant refers to the ratio of the absolute dielectric constant of any material to the absolute dielectric constant of free space or vacuum.

[0060] In some embodiments, the material of the first channel layer 160 may include indium gallium zinc oxide. By including indium gallium zinc oxide in the first channel layer 160, the first channel layer 160 can have higher electron mobility. As will be appreciated, higher electron mobility increases the device's information transmission capacity, enabling the use of narrower channels for information transmission, achieving higher resolution, and also offering the advantage of lower power consumption. By including indium gallium zinc oxide in the first channel layer 160, a more integrated semiconductor structure can be accommodated.

[0061] In some embodiments, the first wafer 100 may further include: a first isolation structure 170, the first isolation structure 170 is located on the top surface of the first substrate 120, and the first substrate 120 can be protected by setting the first isolation structure 170, and the adjacent first gates 111 can be isolated by forming the first isolation structure 170 to avoid short circuits between the first gates 111, and the first isolation structure 170 can also support the formed first gate 111, thereby avoiding the collapse of the first gate 111 and improving the reliability of the semiconductor structure.

[0062] In some embodiments, the first isolation structure 170 can be a multi-layer structure. Taking a three-layer structure as an example, the first isolation structure 170 can include a first sub-isolation layer 171, a second sub-isolation layer 172 and a third sub-isolation layer 173. The first sub-isolation layer 171 is located on the top surface of the first substrate 120, the second sub-isolation layer 172 is located on the top surface of the first sub-isolation layer 171, and the third sub-isolation layer 173 is located on the top surface of the second sub-isolation layer 172; in some embodiments, the first isolation structure 170 can also be a single-layer structure, which can be selected according to actual needs.

[0063] In some embodiments, the material of the first sub-isolation layer 171 may be silicon nitride, the material of the second sub-isolation layer 172 may be silicon oxide, and the material of the third sub-isolation layer 173 may be silicon nitride. That is, the first isolation structure 170 may be a NON (nitride layer-oxide layer-nitride layer) structure. By setting an oxide layer between the two nitride layers, the insulation performance of the first isolation structure 170 can be improved, that is, the insulation between the first wafer 100 and the second wafer 200 that does not require electrical connection can be improved, and the material of the nitride layer is relatively hard. By setting two nitride layers, the morphology of the first isolation structure 170 can also be improved.

[0064] In some embodiments, the first sub-isolation layer 171 , the second sub-isolation layer 172 , and the third sub-isolation layer 173 may be formed by atomic vapor deposition.

[0065] In some embodiments, the orthographic projection of the third sub-isolation layer 173 on the surface of the first substrate 120 is located within the orthographic projection of the first sub-isolation layer 171 on the surface of the first substrate 120. In other words, in a direction perpendicular to the third sub-isolation layer 173 pointing to the first sub-isolation layer 171, the width of the third sub-isolation layer 173 is smaller than the width of the first sub-isolation layer 171, thereby providing space for forming a first gate 111 having a first portion 114 and a second portion 115. That is, space is provided for the first portion 114 of the first gate 111 by shortening the width of the third sub-isolation layer 173.

[0066] In some embodiments, the orthographic projection of the second sub-isolation layer 172 on the surface of the first substrate 120 may also be located within the orthographic projection of the first sub-isolation layer 171 on the surface of the first substrate 120, that is, space is provided for the first portion 114 of the first gate 111 by shortening the width of the second sub-isolation layer 172.

[0067] In some embodiments, the second wafer 200 may further include a second substrate 220. The material of the second substrate 220 may include a semiconductor material, such as, but not limited to, silicon. In some embodiments, the second substrate 220 may include a base semiconductor, a compound semiconductor, or an alloy semiconductor. For example, base semiconductors include germanium; compound semiconductors include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or Group III-V semiconductor materials; and alloy semiconductors include silicon germanium, silicon germanium carbide, germanium-tin, silicon-germanium-tin, gallium arsenic phosphide, gallium indium phosphide, gallium indium arsenide, indium gallium arsenide, aluminum indium arsenide, and / or aluminum gallium arsenide. In some embodiments, the second substrate 220 may also be a silicon-on-insulator (SOI) structure, a silicon-germanium-on-insulator (SGI) structure, a germanium-on-insulator (GOI) structure, or a combination thereof.

[0068] In addition, the second substrate 220 can be doped according to design requirements (e.g., a P-type substrate or an N-type substrate). In some embodiments, the second substrate 220 can be doped with P-type dopant ions (e.g., boron ions, aluminum ions) or N-type dopant ions (e.g., phosphorus ions, arsenic ions).

[0069] In some embodiments, the second substrate 220 may be the same as the first substrate 120 , for example, both may be silicon substrates.

[0070] In some embodiments, the second wafer 200 includes a second substrate 220 , and the second gate 211 of the second wafer 200 is located in the second substrate 220 , that is, the top surface of the second gate 211 is lower than the top surface of the second substrate 220 , and the bottom surface of the second gate 211 is higher than the bottom surface of the second substrate 220 .

[0071] In some embodiments, by setting the top surface of the second gate 211 lower than the top surface of the second source 212, there can be no second gate 211 between adjacent second transistors 210. Since the second gate 211 has strong conductivity, by setting the top surface of the second gate 211 lower than the top surface of the second source 212, the insulation between adjacent second transistors 210 can be improved.

[0072] In some embodiments, the second wafer 200 includes a second substrate 220 , and the top surface of the second source 212 is flush with the top surface of the second substrate 220 . In some embodiments, the second source 212 may also be formed by doping the second substrate 220 .

[0073] In some embodiments, the second wafer 200 includes a second substrate 220 , and the second drain 213 is located in the second substrate 220 . In some embodiments, the second drain 213 may also be formed by doping the second substrate 220 .

[0074] In some embodiments, the second wafer 200 may further include: a second word line 230, the second word line 230 being located on the second gate 211, with the top surface of the second word line 230 away from the second gate 211 being flush with the third surface 201; and a second bit line 240, the second bit line 240 being connected to the second drain 213 and located on a side of the second gate 211 close to the fourth surface 202. For the second wafer 200, the second word line 230 and the second bit line 240 are structures for writing charge to the first transistor 110. That is, the second transistor 210 is controlled to turn on via the second word line 230, charge is transferred to the second drain 213 of the second transistor 210 via the second bit line 240, and charge is written to the first gate 111 via the second drain 213 electrically connected to the first gate 111 of the first transistor 110. Alternatively, the second transistor 210 is controlled to turn on via the second word line 230, and the charge on the first gate 111 is discharged via the second bit line 240.

[0075] In some embodiments, the second word line 230 can be the same as the first word line 130, and can include a second word line conductive layer and a second word line protective layer, wherein the second word line conductive layer is the portion of the second word line 230 used to transmit data information, and the second word line protective layer is the portion of the second word line 230 used to protect the second word line conductive layer.

[0076] In some embodiments, the second wafer 200 further includes a conductive via 250, which is located between the second word line 230 and the second gate 211 to electrically connect the second word line 230 to the second gate 211. It is understood that the top surface of the second gate 211 is lower than the top surface of the second source 212. Therefore, when forming the second word line 230, the second word line 230 cannot be directly contacted and connected to the second gate 211. Therefore, the second word line 230 and the second gate 211 must be connected through other conductive structures to achieve the purpose of the second word line 230 controlling the second gate 211. The second gate 211 and the second word line 230 can be connected through the conductive via 250, which is easy to form and can reduce the processing difficulty of the entire semiconductor structure.

[0077] In some embodiments, the second wafer 200 may further include: a second dielectric layer 260, the second dielectric layer 260 covering the surface of the second gate 211 facing away from the third surface 201; and a second channel layer 270, the second channel layer 270 covering the surface of the second dielectric layer 260, with the bottom surface of the second channel layer 270 near the fourth surface 202 being lower than the top surface of the second drain 213 near the third surface 201. The second dielectric layer 260 is used to isolate the second gate 211 from the second substrate 220, and also to isolate the second gate 211 from the second source 212 and the second drain 213, thereby preventing electrical connection between the second gate 211 and the second drain 213 and the second source 212. The second channel layer 270 allows for a conductive path between the second source 212 and the second drain 213. In some embodiments, the material of the second dielectric layer 260 can be the same as that of the first dielectric layer 150 , and both can be materials with a relative dielectric constant greater than 7.

[0078] In some embodiments, the bottom surface of the second channel layer 270 can also be lower than the top surface of the second drain 213, that is, the second channel layer 270 is also embedded in the second drain 213, thereby increasing the contact area between the second channel layer 270 and the second drain 213, thereby improving the reliability of the semiconductor structure.

[0079] In some embodiments, a height difference between a bottom surface of the second channel layer 270 and a top surface of the second drain electrode 213 is 5-10 nm. In other words, the depth of the second channel layer 270 embedded in the second drain electrode 213 is 5-10 nm. It can be understood that the greater the height difference between the bottom surface of the second channel layer 270 and the top surface of the second drain electrode 213, the larger the contact area between the second channel layer 270 and the second drain electrode 213, and the higher the efficiency of charge transmission. However, the greater the height difference between the bottom surface of the second channel layer 270 and the top surface of the second drain electrode 213, the smaller the area of ​​the second drain electrode 213 itself, which will affect the performance of the second drain electrode 213 itself. The smaller the height difference between the bottom surface of the second channel layer 270 and the top surface of the second drain electrode 213, the smaller the performance of increasing the transmission efficiency between the second channel layer 270 and the second drain electrode 213. Therefore, by setting the height difference between the bottom surface of the second channel layer 270 and the top surface of the second drain electrode 213 to 5-10 nm, a balance can be achieved between improving the transmission efficiency between the second channel layer 270 and the second drain electrode 213 and changing the performance of the second drain electrode 213 itself.

[0080] If the height difference between the bottom surface of the second channel layer 270 and the top surface of the second drain 213 is less than 5-10nm, the performance of improving the transmission efficiency between the second channel layer 270 and the second drain 213 is poor. If the height difference between the bottom surface of the second channel layer 270 and the top surface of the second drain 213 is greater than 5-10nm, it will affect the performance of the second drain 213 itself.

[0081] In some embodiments, the second channel layer 270 may have a structure similar to that of the first channel layer 160 , and the second channel layer may surround the outer surface of the second gate 211 to form a CAA structure, thereby reducing the device area and supporting the stacking of multi-layer semiconductor structures.

[0082] In some embodiments, the material of the second channel layer 270 may include indium gallium zinc oxide.

[0083] In some embodiments, the second wafer 200 may further include: a second isolation structure 310 , where the second isolation structure 310 is located on a top surface of the second source 212 away from the fourth surface 202 .

[0084] In some embodiments, the second isolation structure 310 is made of insulating materials such as silicon oxide, and can be used as a shallow trench isolation (STI) structure.

[0085] In some embodiments, the second wafer 200 may further include: a first isolation layer 280, the first isolation layer 280 is located on the top surface of the second gate 211, and forms a receiving space with the second gate 211, and the conductive through hole is located in the receiving space. By forming the first isolation layer 280, the insulation between adjacent second transistors 210 can be improved.

[0086] In some embodiments, the second wafer 200 may further include: a second isolation layer 290, which may be located between the second dielectric layer 260 and the second word line 230, thereby improving the insulation between the second word line 230 and the second source 212, and also improving the insulation between the second word line 230 and the second bit line 240.

[0087] In some embodiments, the second wafer 200 includes a second substrate 220, and the second drain 213 is located in the second substrate 220. The first wafer 100 and the second wafer 200 are bonded so that the bottom surface of the second substrate 220 is directly bonded to the first surface of the first wafer 100. The electrical connection between the second drain 213 and the first gate 111 is achieved by penetrating the conductive structure 300 of the second substrate 220.

[0088] In some embodiments, the conductive structure 300 may be a conductive pillar, a conductive via, or the like.

[0089] In some embodiments, the bottom surface of the second drain 213 away from the third surface 201 is flush with the fourth surface 202, and the second drain 213 is in direct contact with and bonded to the first gate 111. That is, the fourth surface 202 of the second wafer 200 exposes the bottom surface of the second drain 213, and the electrical connection between the second drain 213 and the first gate 111 can be achieved by directly aligning and bonding the second drain 213 and the first gate 111.

[0090] By providing a first wafer 100 including a first transistor 110 and a second wafer 200 including a second transistor 210, and electrically connecting the first gate 111 of the first transistor 110 to the second drain 213 of the second transistor 210, the first gate 111 of the first transistor 110 can be equivalent to a capacitor, and the second transistor 210 can be used as a transistor connected to the capacitor to form a 2T0C semiconductor structure. At the same time, by setting the top surface of the first gate 111 of the first transistor 110 flush with the first surface 101, it is convenient to bond the first gate 111 of the first transistor 110 to the second transistor 210. By setting the top surface of the second gate 211 of the second transistor 210 lower than the bottom surface of the second source 212, the parasitic capacitance between the second gate 211 and the second source 212 can be reduced while improving the integration of the semiconductor structure, and short circuit between the second gate 211 and the second source 212 can be avoided, thereby improving the reliability of the semiconductor structure.

[0091] Another embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure. The method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure will be described below in conjunction with the accompanying drawings. It should be noted that the parts that are the same or corresponding to the above-mentioned embodiments can refer to the corresponding description of the above-mentioned embodiments and will not be repeated below.

[0092] refer to Figures 2 to 16 and Figure 1 , Figures 2 to 16 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure.

[0093] In some embodiments, reference Figures 2 to 8 The method for manufacturing a semiconductor structure includes: forming a first wafer 100 having a first surface 101 and a second surface 102 relative to each other, the first wafer 100 including a first transistor 110, the first transistor 110 including a first gate 111, a first source 112 and a first drain 113, the top surface of the first gate 111 away from the second surface 102 is flush with the first surface 101, the top surface of the first gate 111 is higher than the top surface of the first source 112, and the first drain 113 is located on a side of the first gate 111 close to the second surface 102.

[0094] In some embodiments, reference Figures 9 to 16 The method for manufacturing the semiconductor structure may further include: forming a second wafer 200 having a third surface 201 and a fourth surface 202 relative to each other, the second wafer 200 including a second transistor 210, the second transistor 210 including a second gate 211, a second source 212 and a second drain 213, the second source 212 being closer to the third surface 201 than the second drain 213, and the top surface of the second gate 211 being lower than the bottom surface of the second source 212.

[0095] refer to Figure 1 , bonding the first surface 101 and the fourth surface 202 to electrically connect the first gate 111 and the second drain 213 .

[0096] Continue to refer Figures 2 to 8The method for forming the first wafer includes: providing a first initial wafer 103, the first initial wafer 103 including: a first substrate 120 and a first initial isolation structure 174 located on the first substrate 120, the first substrate 120 including: a first drain 113 and a first initial source 116, the first drain 113 being located in the first initial wafer 103, the top surface of the first initial source 116 being flush with the top surface of the first substrate 120; etching the first initial isolation structure 174 and the first initial source 116 to form a first groove 180, the first initial wafer 103 including: a first substrate 120 and a first initial isolation structure 174 located on the first substrate 120, the first initial source 116 being flush with the top surface of the first substrate 120; etching the first initial isolation structure 174 and the first initial source 116 to form a first groove 180, A groove 180 exposes the top surface of the first drain 113, the remaining first initial isolation structure 174 serves as the first isolation structure 170, and the remaining first initial source 116 serves as the first source 112; a first channel layer 160 is formed, and the first channel layer 160 is located on the inner wall of the first groove 180; a first dielectric layer 150 is formed, and the first dielectric layer 150 is located on the surface of the first channel layer 160; a first gate 111 is formed, and the first gate 111 is located on the top surface of the first dielectric layer 150 and the first gate 111 fills the first groove 180.

[0097] refer to Figures 2 to 6 The first initial isolation structure 174 includes a stacked first initial sub-isolation layer 175, a second initial sub-isolation layer 176, and a third initial sub-isolation layer 177. A method for forming the first recess 180 includes etching the third initial sub-isolation layer 177 to form a first trench 181, wherein the first trench 181 exposes the surface of the second initial sub-isolation layer 176; forming a sacrificial layer 190, wherein the sacrificial layer 190 completely fills the first trench 181 and also covers the surface of the third initial sub-isolation layer 177; etching the sacrificial layer 190, the second initial sub-isolation layer 176, the first initial sub-isolation layer 175, and the first initial source electrode 116 to form a second trench 182, wherein the projection of the second trench 182 on the first substrate 120 is located within the projection of the first trench 181 on the first substrate 120; and removing the sacrificial layer 190, whereby the first trench 181 and the second trench 182 form the first recess 180. In other words, the first recess 180 is formed by a damascene process. The formation of the first groove 180 provides a process basis for the subsequent formation of the first gate 111, the first dielectric layer 150 and the first channel layer 160. The first groove 180 formed by the Damascene process has a better morphology, which provides a process basis for the subsequent formation of the first gate 111 with higher reliability.

[0098] refer to Figure 2 , providing a first initial wafer 103, the first initial wafer 103 includes: a first substrate 120 and a first initial isolation structure 174 located on the first substrate 120, the first substrate 120 includes: a first drain 113 and a first initial source 116, the first drain 113 is located in the first initial wafer 103, and the top surface of the first initial source 116 is flush with the top surface of the first substrate 120.

[0099] refer to Figure 3 , the third initial sub-isolation layer 177 is etched to form a first trench 181 , and the remaining third initial sub-isolation layer 177 serves as the third sub-isolation layer 173 .

[0100] In some embodiments, the third initial sub-isolation layer 177 may be etched using a mask.

[0101] refer to Figure 4 , forming a sacrificial layer 190. In some embodiments, the material of the sacrificial layer 190 can be an insulating material different from the material of the third sub-isolation layer 173, or a photoresist, etc.

[0102] refer to Figure 5 , the sacrificial layer 190, the second initial sub-isolation layer 176, the first initial sub-isolation layer 175 and the first initial source 116 are etched to form a second trench 182, the remaining second initial sub-isolation layer 176 serves as the second sub-isolation layer 172, the remaining first initial sub-isolation layer 175 serves as the first sub-isolation layer 171, and the remaining first initial source 116 serves as the first source 112.

[0103] refer to Figure 6 , the sacrificial layer 190 is removed to expose the first trench 181 , and the first trench 181 and the second trench 182 constitute a first recess 180 .

[0104] In some embodiments, the first initial isolation structure 174 includes: a first initial sub-isolation layer 175, a second initial sub-isolation layer 176, and a third initial sub-isolation layer 177 that are stacked together, and the method of forming the first groove 180 includes: a first etching process, etching the first initial isolation structure 174 and the first initial source 116 to form a first initial groove, the first initial groove exposing the top surface of the first drain 113; a second etching process, etching the third initial sub-isolation layer 177 along the side wall of the third initial sub-isolation layer 177 exposed in the first initial groove to form a first groove 180. That is to say, the first initial groove is formed by the first etching process, and the first initial groove exposes the top surface of the first drain 113, and then the third initial sub-isolation layer is etched by the second etching process, so that a first groove 180 in a "T" shape can be formed. The first "T"-shaped groove 180 can be formed by two etching processes, thereby providing a process basis for the subsequent formation of the first gate 111 having a first part and a second part, and by forming the first groove 180 with a large top surface width, subsequent filling can be facilitated, that is, the larger the filling opening, the better the reliability of the first gate formed subsequently.

[0105] refer to Figure 7In some embodiments, the method further includes forming a first initial dielectric layer 151 , where the first initial dielectric layer 151 covers the inner wall of the first groove 180 and also covers the third sub-isolation layer 173 .

[0106] In some embodiments, the method further includes forming a first initial channel layer 161 , where the first initial channel layer 161 is located on a surface of the first initial dielectric layer 151 .

[0107] In some embodiments, the method further includes forming a first preliminary gate 117 , wherein the first preliminary gate 117 completely fills the first groove 180 and covers a top surface of the first preliminary channel layer 161 .

[0108] refer to Figure 8 , the first initial dielectric layer 151 , the first initial channel layer 161 and the first initial gate 117 are etched back, and the remaining first initial dielectric layer 151 serves as the first dielectric layer 150 , the remaining first initial channel layer 161 serves as the first channel layer 160 , and the remaining first initial gate 117 serves as the first gate 111 .

[0109] refer to Figures 9 to 13 The method for forming the second wafer 200 includes: providing a second initial wafer 203, the second initial wafer 203 including: a second substrate 220 and a second initial isolation structure 311 located on the second substrate 220, the second substrate 220 including a second drain 213 and a second initial source 214, the second drain 213 being located in the second initial wafer 203, and the top surface of the second initial source 214 being flush with the top surface of the second substrate 220; etching the second initial isolation structure 311 and the second initial source 214 to form a second groove 320, and the remaining second initial isolation structure 311 is used as A second isolation structure 310 is provided, with the remaining second initial source 214 serving as the second source 212, and the second groove 320 exposing the top surface of the second drain 213; a second channel layer 270 is formed, the second channel layer 270 covers the inner wall of the second groove 320, and the second channel layer 270 is in contact with the surface of the second drain 213; a second dielectric layer 260 is formed, the second dielectric layer 260 covers the surface of the second channel layer 270 away from the second drain 213; a second gate 211 is formed, the second gate 211 is located in the second groove 320, and is in contact with the second dielectric layer 260.

[0110] The formation of the second groove 320 provides a process basis for the subsequent formation of the second channel layer 270, the second dielectric layer 260 and the second gate 211. The formation of the second channel layer 270 can serve as a transmission channel for ions between the second source 212 and the second drain 213. The formation of the second dielectric layer 260 can isolate the second gate 211 from the second source 212 and the second drain 213, thereby preventing carriers between the second source 212 and the second drain 213 from flowing directly to the second gate 211.

[0111] refer to Figure 9 , providing a second initial wafer 203 , the second initial wafer 203 includes: a second substrate 220 and a second initial isolation structure 311 located on the second substrate 220 .

[0112] refer to Figure 10 , the second initial wafer 203 and the second initial isolation structure 311 are etched to form a second groove 320 , and the remaining second initial isolation structure 311 serves as the second isolation structure 310 . The second groove 320 exposes the surface of the second gate 211 .

[0113] In some embodiments, a portion of the second gate 211 is also etched during the etching of the second initial wafer 203 .

[0114] refer to Figure 11 , a second channel layer 270 and a second dielectric layer 260 are formed. The second channel layer 270 covers the inner wall of the second groove 320 and also covers the top surface of the second isolation structure 310 .

[0115] refer to Figure 12 , forming a second initial gate 215 , the second initial gate 215 fills the second groove 320 , and the second initial gate 215 also covers the top surface of the second dielectric layer 260 .

[0116] refer to Figure 13 , the second initial gate 215 is etched back, and the remaining second initial gate 215 serves as the second gate 211 , and the top surface of the second gate 211 is lower than the bottom surface of the second source 212 .

[0117] refer to Figure 14 and Figure 15 After forming the second gate 211, the method further includes: forming a first isolation layer 280, the first isolation layer 280 is located on the top surface of the second gate 211, and the first isolation layer 280 and the second gate 211 form an accommodation space; and forming a conductive through hole 250 in the accommodation space.

[0118] refer to Figure 14, forming a first initial isolation layer 281 , the first initial isolation layer 281 is located on the top surface of the second gate 211 and fills the second groove 320 , and the first initial isolation layer 281 also covers the top surface of the second dielectric layer 260 .

[0119] refer to Figure 15 , the first initial isolation layer 281 is etched back to expose the top surface of the second dielectric layer 260, and during the back etching process, the first initial isolation layer 281 on the top surface of the second gate 211 is also etched to expose the top surface of the second gate 211.

[0120] In some embodiments, the method for fabricating the semiconductor structure further includes forming a second isolation layer 290, wherein the second isolation layer 290 is located on a top surface of the first isolation layer 280 and also covers a portion of a top surface of the second dielectric layer 260. The second isolation layer 290 can improve the insulation between the subsequently formed second word line 230 and the second bit line 240.

[0121] In some embodiments, the method for manufacturing the semiconductor structure further includes: forming a conductive via 250 . The conductive via 250 can be used to electrically connect the second word line 230 to the second gate 211 .

[0122] refer to Figure 16 After forming the conductive via 250, the method further includes forming a second word line 230, which is located on the top surface of the conductive via 250 and is electrically connected to the second gate 211 through the conductive via 250. The second word line 230 is used to control the conduction of the second transistor 210.

[0123] In some embodiments, after forming the conductive via 250 , the process may further include etching the second substrate 220 along the fourth surface 202 to expose the bottom surface of the second drain 213 away from the third surface 201 .

[0124] refer to Figure 1 , forming a conductive structure 300 , the conductive structure 300 is located and extends from the bottom surface of the second drain 213 toward a direction away from the third surface 201 , and bonding the first wafer 100 and the second wafer 200 .

[0125] In some embodiments, the second wafer 200 includes a conductive structure 300 , and bonding the first wafer 100 and the second wafer 200 is to align and bond the conductive structure 300 to the first gate 111 .

[0126] In some embodiments, the bottom surface of the second drain 213 of the second wafer is flush with the fourth surface 202 , and bonding the first wafer 100 and the second wafer 200 is to align and bond the bottom surface of the second drain 213 with the first gate 111 .

[0127] In the embodiment of the present disclosure, a first wafer 100 having a first transistor 110 and a second wafer 200 having a second transistor 210 are formed, and the first gate electrode 111 of the first transistor 110 is electrically connected to the second drain electrode 213 of the second transistor 210, so that the first gate electrode 111 of the first transistor 110 can be equivalent to a capacitor, and the second transistor 210 can be used as a transistor connected to the capacitor to form a 2T0C semiconductor structure. At the same time, by setting the top surface of the first gate electrode 111 of the first transistor 110 to be flush with the first surface 101, it is convenient to The first gate 111 of the first transistor 110 is bonded to the second transistor 210. The spacing between the top surface of the second gate 211 of the second transistor 210 facing the third surface 201 and the fourth surface 202 is set to a third spacing, and the spacing between the bottom surface of the second source 212 facing the fourth surface 202 and the fourth surface 202 is set to a fourth spacing. The third spacing is smaller than the fourth spacing, that is, the top surface of the second gate 211 is closer to the fourth surface 202 than the bottom surface of the second source 212, thereby improving the integration and reliability of the semiconductor structure.

[0128] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that include: A first wafer having a first surface and a second surface opposite to each other, the first wafer comprising a first transistor, a first word line, and a first bit line, the first transistor comprising a first gate, a first source, and a first drain, the top surface of the first gate away from the second surface being flush with the first surface, the top surface of the first gate being higher than the top surface of the first source, the first drain being located on a side of the first gate close to the second surface, the first word line being connected to the first source, the first bit line being connected to the first drain, and the first bit line being located on a side of the first word line close to the second surface; A second wafer having a third surface and a fourth surface opposite to each other, the fourth surface being opposite to and bonded to the first surface, the second wafer including a second transistor, the second transistor including a second gate, a second source, and a second drain, the second source being closer to the third surface than the second drain, the top surface of the second gate being lower than the bottom surface of the second source, and the second drain being electrically connected to the first gate.

2. The semiconductor structure according to claim 1, wherein: The first gate includes: a first part and a second part, the first part is located on the top surface of the second part away from the second surface, the top surface of the first part away from the second surface is flush with the first surface, and in a direction perpendicular to the first surface pointing to the second surface, the width of the first part is greater than the width of the second part.

3. The semiconductor structure according to claim 2, wherein: The width of the first portion is 1.5 to 2.5 times the width of the second portion.

4. The semiconductor structure according to claim 1, wherein: The first wafer further includes: a first dielectric layer, the first dielectric layer covering a surface of the first gate facing away from the first surface; A first channel layer covers a surface of the first dielectric layer, and the first channel layer contacts a top surface of the first bit line away from the second surface.

5. The semiconductor structure according to claim 4, wherein: The material of the first channel layer includes indium gallium zinc oxide. The semiconductor structure according to claim 1 , wherein: The second wafer further includes: a second word line, the second word line being located on the second gate, and a top surface of the second word line away from the second gate being flush with the third surface; A second bit line is connected to the second drain, and the second bit line is located on a side of the second gate close to the fourth surface.

7. The semiconductor structure according to claim 6, wherein: The second wafer further includes a conductive via located between the second word line and the second gate to electrically connect the second word line and the second gate.

8. The semiconductor structure according to claim 1, wherein: The second wafer further includes: a second dielectric layer, the second dielectric layer covering a surface of the second gate facing away from the third surface; A second channel layer covers a surface of the second dielectric layer, and a bottom surface of the second channel layer close to the fourth surface is lower than a top surface of the second drain close to the third surface.

9. The semiconductor structure according to claim 8, wherein: A height difference between a bottom surface of the second channel layer and a top surface of the second drain electrode is 5-10 nm.

10. The semiconductor structure according to claim 1, wherein: A bottom surface of the second drain electrode away from the third surface is flush with the fourth surface, and the second drain electrode is in direct contact with and bonded to the first gate electrode.

11. A method for manufacturing a semiconductor structure, characterized in that: include: forming a first wafer having a first surface and a second surface opposite to each other, the first wafer including a first transistor, the first transistor including a first gate, a first source, and a first drain, wherein a top surface of the first gate is higher than a top surface of the first source, the first drain is located on a side of the first gate close to the second surface, the first gate including: a first portion and a second portion, the first portion being located on a top surface of the second portion away from the second surface, the top surface of the first portion away from the second surface being flush with the first surface, and a width of the first portion being greater than a width of the second portion in a direction perpendicular to the first surface toward the second surface; forming a second wafer having a third surface and a fourth surface opposite to each other, the second wafer including a second transistor, the second transistor including a second gate, a second source, and a second drain, the second source being closer to the third surface than the second drain, and a top surface of the second gate being lower than a bottom surface of the second source; The first surface is bonded to the fourth surface to electrically connect the first gate and the second drain.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein: The method of forming the first wafer includes: Providing a first initial wafer, the first initial wafer comprising: a first substrate and a first initial isolation structure located on the first substrate, the first substrate comprising: a first drain and a first initial source, the first drain being located within the first initial wafer, and a top surface of the first initial source being flush with a top surface of the first substrate; Etching the first initial isolation structure and the first initial source to form a first groove, wherein the first groove exposes a top surface of the first drain, and the remaining first initial isolation structure serves as a first isolation structure, and the remaining first initial source serves as a first source; forming a first channel layer, wherein the first channel layer is located on an inner wall of the first groove; forming a first dielectric layer, wherein the first dielectric layer is located on a surface of the first channel layer; The first gate is formed, where the first gate is located on the top surface of the first dielectric layer and the first gate completely fills the first groove.

13. The method for manufacturing a semiconductor structure according to claim 12, wherein: The first initial isolation structure includes: a first initial sub-isolation layer, a second initial sub-isolation layer, and a third initial sub-isolation layer that are stacked. The method of forming the first groove includes: A first etching process is performed to etch the first initial isolation structure and the first initial source to form a first initial groove, wherein the first initial groove exposes a top surface of the first drain; The second etching process is to etch the third initial sub-isolation layer along the sidewall of the third initial sub-isolation layer exposed by the first initial groove to form the first groove.

14. The method for manufacturing a semiconductor structure according to claim 12, wherein: The first initial isolation structure includes: a first initial sub-isolation layer, a second initial sub-isolation layer, and a third initial sub-isolation layer that are stacked. The method of forming the first groove includes: Etching the third initial sub-isolation layer to form a first trench, wherein the first trench exposes a surface of the second initial sub-isolation layer; forming a sacrificial layer, wherein the sacrificial layer completely fills the first trench and also covers a surface of the third initial sub-isolation layer; Etching the sacrificial layer, the second initial sub-isolation layer, the first initial sub-isolation layer, and the first initial source to form a second trench, wherein a projection of the second trench on the first substrate is located within a projection of the first trench on the first substrate; The sacrificial layer is removed, and the first trench and the second trench form the first groove.

15. The method for manufacturing a semiconductor structure according to claim 11, wherein: The method of forming the second wafer includes: Providing a second initial wafer, the second initial wafer comprising: a second substrate and a second initial isolation structure located on the second substrate, the second substrate comprising a second drain and a second initial source, the second drain being located within the second initial wafer, and a top surface of the second initial source being flush with a top surface of the second substrate; Etching the second initial isolation structure and the second initial source to form a second groove, leaving the second initial isolation structure as a second isolation structure, and the remaining second initial source as the second source, the second groove exposing a top surface of the second drain; forming a second channel layer, where the second channel layer covers an inner wall of the second groove and contacts a surface of the second drain electrode; forming a second dielectric layer, wherein the second dielectric layer covers a surface of the second channel layer away from the second drain electrode; The second gate is formed, and the second gate is located in the second groove and is in contact with and connected to the second dielectric layer.

16. The method for manufacturing a semiconductor structure according to claim 15, wherein: After forming the second gate, the method further includes: forming a first isolation layer, wherein the first isolation layer is located on a top surface of the second gate, and the first isolation layer and the second gate form an accommodation space; A conductive through hole is formed in the accommodation space.

17. The method for manufacturing a semiconductor structure according to claim 16, wherein: After forming the conductive through hole, the method further includes forming a second word line, wherein the second word line is located on a top surface of the conductive through hole and is electrically connected to the second gate through the conductive through hole.

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