A memory mapping method and related equipment

Abstract

A memory mapping method and related apparatus are disclosed. The memory mapping method includes: obtaining the memory failure line address of a first memory; enabling a matching lookup circuit to obtain an address mapping table, the address mapping table including the mapping relationship between the memory failure line address and the memory remapping line address corresponding to the memory failure line address; when the access target of the first memory is the memory failure line address, obtaining the memory remapping line address mapped by the memory failure line address through the address mapping table; wherein the memory region indicated by the memory remapping line address is located in the reserved space of the first memory; since the matching lookup circuit can be integrated into any address command output circuit or driver circuit in the memory access path of the first memory, the user can customize the integration location and the amount of redundant resources used for replacement, so as to realize multiple reversible replacements based on the address mapping table, thereby significantly reducing the memory failure rate and improving memory reliability.

Description

[0001] This application is a divisional application. The original application has the application number 202211691518.5 and the original application date is December 27, 2022. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This application relates to the field of computers, and more particularly to a memory mapping method and related equipment. Background Technology

[0003] With the development of high-performance computing, big data analytics, and in-memory databases, applications are increasingly demanding more and more memory capacity and bandwidth.

[0004] Driven by the ever-increasing demands for memory capacity density and bandwidth performance, memory manufacturing processes are constantly shrinking and interface speeds are continuously improving. However, at the same time, with process upgrades, the probability of memory errors and the memory failure rate are gradually increasing, posing a significant risk to memory reliability. Therefore, it is necessary to detect memory errors and replace the detected faulty rows. For example, current memory chip manufacturers incorporate replacement functions into their memory chips.

[0005] However, setting the replacement function in the memory chip pre-sets the redundant space for replacement, which cannot be changed. This limits the number of memory replacements and is accompanied by a certain loss of business performance, making it unable to meet the current memory failure requirements. Summary of the Invention

[0006] This application provides a memory mapping method for flexibly defining the integration location of the address mapping table and the number of redundant resources used for replacement. Based on this address mapping table, multiple reversible replacements of failed memory rows are achieved, avoiding performance loss and significantly reducing memory failure rate, thus improving memory reliability. This application also provides corresponding memory mapping circuits, computing devices, computer-readable storage media, chip systems, and computer program products.

[0007] The first aspect of this application provides a memory mapping method, which includes: obtaining the memory failure row address of a first memory (the first memory is, for example, a memory module, specifically, a Rambus in-line memory module (RIMM) memory module, a single in-line memory module (SIMM) memory module, or a dual in-line memory module (DIMM) memory module); a matching lookup circuit obtaining an address mapping table, the address mapping table including the mapping relationship between the memory failure row address and the memory remapping row address corresponding to the memory failure row address; when the access target of the first memory is the memory failure row address, obtaining the memory remapping row address mapped by the memory failure row address through the address mapping table, wherein the memory region indicated by the memory remapping row address is located in the reserved space of the first memory; and the matching lookup circuit is integrated into the memory access path of the first memory by an address command output circuit or a driver circuit.

[0008] In this application, the memory mapping method is implemented using a computing device as an example. In order to perform memory mapping, the matching lookup circuit first needs to obtain the address mapping table. The matching lookup circuit is integrated into the address command output circuit or driver circuit in the memory access path of the first memory. Specifically, the matching lookup circuit is integrated into any address command output circuit or driver circuit between the address mapping module of the memory controller and the memory chip. The memory access path of the first memory can be understood as the path from the memory controller in the processor of the computing device to the memory chip accessing the first memory.

[0009] The memory region indicated by the memory remapping row address in this application is located in the reserved space of the first memory. The reserved space of the first memory can come from the capacity of the user memory chip / particle in the first memory. That is, the reserved space is visible to the user and needs to be reserved by software. Alternatively, the reserved space can come from the redundant space designed by the memory manufacturer outside the nominal capacity of the first memory. The reserved space is outside the addressing range of the memory controller and is not visible to the user.

[0010] The first memory in this application is loaded in a computing device, which can be any computer device, server, or storage device that uses memory.

[0011] In this application, the memory mapping method can be executed during the production stage of the first memory, the startup stage of the computing device, and the operation stage of the computing device. After the address mapping table is generated, the memory address can be replaced based on the address mapping table.

[0012] To address the issue of invalid memory row addresses, one approach is for memory chip manufacturers to incorporate address replacement functionality into the chips. This involves setting up a mapping table in each chip; when a memory address is accessed that is invalid, the invalid address in the chip is replaced with a new memory address based on the mapping table. However, because the chips are packaged by the memory manufacturer, this address replacement functionality can only be pre-configured by the manufacturer and cannot be changed by the user. This limits the number of memory replacements; furthermore, setting up a replacement function for each individual memory chip results in a significant performance penalty.

[0013] In this application, the matching lookup circuit is integrated into the address command output circuit or driver circuit in the memory access path of the first memory. These circuits (e.g., the matching lookup circuit is located in the memory controller or register clock driver) are all outside the memory chip and are user-controllable circuits. When the processing chip (e.g., CPU, GPU, NPU) in the computing device accesses memory, the access request reaches the memory interface of the motherboard; then, the access request passes through the matching lookup circuit, which performs the replacement of the invalid address; finally, based on the replaced access address, the access request enters each memory chip to complete the data access.

[0014] As can be seen from the solution provided in this application, each match lookup circuit is connected to multiple particles. Therefore, setting an address mapping table in only one match lookup circuit can provide services to multiple objects (particles), avoiding the need to repeatedly set up replacement functions in each particle. Furthermore, since the match lookup circuit is user-editable, the user can customize the size of the address mapping table that the match lookup circuit can store. A larger address mapping table allows for the replacement of more invalid memory address lines and also allows for multiple replacements of invalid memory address lines. Further, since the match lookup circuit can be user-defined, this application can expand the granularity of replacement, treating multiple particles as a single replacement unit. When an invalid line is detected in a single particle, the same memory address is used to simultaneously issue replacement signals to multiple particles managed by the match lookup circuit (e.g., multiple particles in the same rank), causing invalid line replacements to occur in multiple particles. The advantage of this approach is that multiple particles can share a single record in the mapping table, instead of each particle corresponding to a separate record in the mapping table, thereby reducing the amount of data in the mapping table and saving storage space required by the mapping table. Furthermore, since the memory region indicated by the memory remapping row address in this application is located in the reserved space of the first memory, that is, the reserved space is visible to the user and can be managed by the user; therefore, the user can decide the size of the reserved space himself, for example, when the frequency of memory row failures is low, a smaller space is reserved; as the memory ages and its reliability gradually decreases, a larger space is reserved. Therefore, the solution in this application can improve memory utilization.

[0015] In this first aspect, by obtaining the memory failure line address of the first memory, the matching lookup circuit obtains an address mapping table. The address mapping table includes the mapping relationship between the memory failure line address and the memory remapping line address corresponding to the memory failure line address. When the access target of the first memory is the memory failure line address, the memory remapping line address mapped by the memory failure line address is obtained through the address mapping table. The memory region indicated by the memory remapping line address is located in the reserved space of the first memory. Since the matching lookup circuit can be integrated into any address command output circuit or driver circuit in the memory access path of the first memory, the user can customize the integration location and the number of redundant resources used for replacement to achieve multiple reversible replacements based on the address mapping table, thereby significantly reducing the memory failure rate and improving memory reliability.

[0016] In one possible implementation of the first aspect, the method further includes: obtaining a memory access address from outside the first memory; using the obtained memory access address to match the memory access address based on an address mapping table; and when a memory access address is matched in the memory invalidation line address, converting the access to the memory access address into an access to the memory remapping line address.

[0017] In this possible implementation, after the matching lookup circuit obtains the address mapping table, it can match the memory access address based on the address mapping table. When the memory access address matches the memory invalid line address in the address mapping table, the memory invalid line address is remapped to the memory remapped line address corresponding to the memory invalid line address. Finally, the memory remapped line address is accessed, and the replacement of the invalid memory address is completed, which improves the feasibility of the solution.

[0018] In one possible implementation of the first aspect, the first memory includes multiple memory chips, and the matching lookup circuit treats the multiple memory chips as a whole for row address translation. The above step of obtaining the memory remapping row address mapped by the memory failure row address through the address mapping table specifically includes: when a single memory chip has a failure row, converting the row address in the multiple memory chips into a memory remapping row address through the address mapping table, wherein the row being converted includes the failure row.

[0019] In this possible implementation, the first memory includes one or more memory channels. One or more dual in-line memory modules (DIMMs) can be inserted into a memory channel. A DIMM can be composed of one or more memory ranks. A rank includes multiple memory chips. The matching lookup circuit treats multiple memory chips as a whole for row address translation. When a single memory chip has a failed row, the matching lookup circuit uses an address mapping table to convert the row addresses in multiple memory chips into memory remapping row addresses. The rows being translated include failed rows. That is, the address mapping table operates on each chip. For example, if address A is matched in the address mapping table, the matching lookup circuit will replace address A in all chips, thereby reducing the amount of data in the mapping table and saving the storage space required by the mapping table.

[0020] In one possible implementation of the first aspect, each of the plurality of memory chips includes a plurality of memory banks, and the reserved space of the first memory includes at least one row of storage units in each of the plurality of memory banks.

[0021] In this possible implementation, a chip includes multiple memory banks or bankgroups. A bank is an array of multiple storage units. A row of storage units in a bank can be represented by a row. The reserved space of the first memory includes at least one row of storage units in each bank. That is, there is at least one row of storage units in each bank as reserved space, which allows users to customize a larger reserved space. Multiple reversible replacements can be implemented based on this address mapping table. When the frequency of memory row failures is low, a smaller space is reserved; as the memory ages and its reliability gradually decreases, a larger space is reserved, thereby improving memory utilization.

[0022] In one possible implementation of the first aspect, the address mapping table is stored in volatile memory in the match lookup circuit, and the method further includes: writing the address mapping table from the match lookup circuit to a first memory, the first memory being a non-volatile memory located in a computing device, before the first memory stops working; and loading the address mapping table in the first memory to the match lookup circuit after the first memory starts working.

[0023] In this possible implementation, the address mapping table is stored in volatile memory within the match lookup circuit. Therefore, the address mapping table needs to be written to the first non-volatile memory for persistent storage. For example, during the operation of the computing device, before the first memory stops working, the address mapping table is written from the match lookup circuit to the first memory. After the first memory starts working, the address mapping table in the first memory is loaded into the match lookup circuit, thus avoiding the problem of address mapping table loss.

[0024] In one possible implementation of the first aspect, the method further includes: during the startup process of a computing device loaded with the first memory, reading an address mapping table from the first memory and updating the address mapping table through a memory self-test of the computing device.

[0025] In this possible implementation, the persistent address mapping table can be read during the startup process of the computing device, and the address mapping table can be updated based on the memory self-test function of the computing device to promptly detect and replace faulty lines in memory, thereby improving memory reliability.

[0026] In one possible implementation of the first aspect, the volatile memory content-addressable memory, tri-state content-addressable memory, or fully connected cache is used in the match lookup circuit.

[0027] In this possible implementation, the volatile memory in the matching lookup circuit can be any one of content-addressable memory, tri-state content-addressable memory, or fully connected cache, which improves the feasibility of the solution.

[0028] In one possible implementation of the first aspect, the address mapping table is stored in a non-volatile memory within the match lookup circuit.

[0029] In this possible implementation, the address mapping table is stored in non-volatile memory within the matching lookup circuit, enabling the address mapping table in the matching lookup circuit to be persistently saved and avoiding the problem of address mapping table loss.

[0030] In one possible implementation of the first aspect, the above steps: the matching lookup circuit obtains the address mapping table, include: generating the address mapping table when the computing device loaded with the first memory starts up; and synchronizing the address mapping table to the matching lookup circuit before the computing device uses the first memory.

[0031] In this possible implementation, during the startup phase of the computing device, an address mapping table can be generated through self-testing, and the address mapping table can be synchronized to the matching lookup circuit before the computing device uses the first memory, thus avoiding the memory data migration problem that exists when synchronizing table entries after the computing device uses the first memory.

[0032] In one possible implementation of the first aspect, the above step of obtaining the memory failure line address of the first memory includes: obtaining the first memory failure log of the first memory; extracting the first memory failure features from the first memory failure log; and making a prediction based on the first memory failure features to obtain the memory failure line address of the first memory.

[0033] In this possible implementation, during the operation of the computing device, out-of-band or in-band memory error information is aggregated for offline training nodes to train the parameters of the memory failure prediction model. The trained algorithm and model can then be used for online inference to predict the evolution trend of memory failure in real time and update the address mapping table in a timely manner to reduce or even avoid the occurrence of uncorrectable errors.

[0034] In one possible implementation of the first aspect, the method further includes: performing an access test on the memory invalidation line address to determine whether the memory invalidation line address is a truly invalidation line address; when the memory invalidation line is not a truly invalidation line address, releasing the memory invalidation line address and the memory remapping line address corresponding to the memory invalidation line address from the address mapping table.

[0035] In this possible implementation, during the idle state of the computing device during operation, the memory failure row address can be re-predicted using a memory failure prediction model to determine whether the previously predicted memory failure row address is the actual failure row address. If the memory failure row address is not the actual failure row address, the memory failure row address and the memory remapping row address corresponding to the memory failure row address are released from the address mapping table. This saves redundant space in the matching lookup circuit and reserved space, enabling the system to have reversible isolation and release capabilities, reducing the prediction accuracy requirement and improving the fault prediction coverage.

[0036] In one possible implementation of the first aspect, the method further includes: sending a first command to enable stopping the acquisition of the memory invalidation line address of the first memory.

[0037] In this possible implementation, during the startup phase of the computing device, an enable switch can be set. When the second command is sent, the enable switch is turned on, a self-test is initiated, and the acquisition of the memory failure line address of the first memory is enabled. Once a memory failure is detected, it is replaced promptly. When the first command is sent, the enable switch is turned off, the self-test is disabled, and the acquisition of the memory failure line address of the first memory is stopped, thereby achieving the purpose of quickly starting the computing device.

[0038] In one possible implementation of the first aspect, the match lookup circuit is integrated into the memory controller or register clock driver in the address command output circuit or drive circuit.

[0039] In this possible implementation, the matching lookup circuit is specifically integrated into the memory controller in the processor or the register clock driver in the rank, which improves the feasibility of the solution.

[0040] In a second aspect, this application provides a memory-mapped circuit for performing the methods described in the first aspect or any possible implementation thereof. Specifically, the memory-mapped circuit includes circuits, modules, or units for performing the methods described in the first aspect or any possible implementation thereof, such as: an acquisition circuit, a matching search circuit, a read / write circuit, a generation circuit, a release circuit, and a sending circuit.

[0041] A third aspect of this application provides a computing device, which includes a motherboard, a processor, memory, and a memory-mapped circuitry as described in the second aspect or any possible implementation thereof.

[0042] The motherboard is used to detect memory failure lines and send the memory failure line addresses to the memory mapping circuit. The memory mapping circuit is integrated into the processor or memory, and the memory is used as the first memory to perform memory failure line address mapping.

[0043] The fourth aspect of this application provides a computer-readable storage medium storing one or more computer-executable instructions, wherein when the computer-executable instructions are executed by a processor, the processor performs a method as described in the first aspect or any possible implementation thereof.

[0044] The fifth aspect of this application provides a computer program product that stores one or more computer-executable instructions, wherein when the computer-executable instructions are executed by a processor, the processor executes a method as described in the first aspect or any possible implementation thereof.

[0045] A sixth aspect of this application provides a chip system including at least one processor and an interface for receiving data and / or signals. The interface is used to support a computer device in implementing the functions described in the first aspect or any possible implementation thereof. In one possible design, the chip system may further include a memory for storing necessary program instructions and data for the computer device. This chip system may be composed of chips or may include chips and other discrete devices.

[0046] In this embodiment, by obtaining the memory failure line address of the first memory, the matching lookup circuit obtains an address mapping table. The address mapping table includes the mapping relationship between the memory failure line address and the memory remapping line address corresponding to the memory failure line address. When the access target of the first memory is the memory failure line address, the memory remapping line address mapped by the memory failure line address is obtained through the address mapping table. The memory region indicated by the memory remapping line address is located in the reserved space of the first memory. Since the matching lookup circuit can be integrated into any address command output circuit or driver circuit in the memory access path of the first memory, the user can customize the integration location and the number of redundant resources used for replacement to achieve multiple reversible replacements based on the address mapping table, thereby significantly reducing the memory failure rate and improving memory reliability. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of the computer system architecture;

[0048] Figure 2 A schematic diagram of an embodiment of the memory mapping method provided in this application;

[0049] Figure 3 A flowchart illustrating the first memory production stage provided for an embodiment of this application;

[0050] Figure 4 A flowchart illustrating the startup phase of a computing device provided in an embodiment of this application;

[0051] Figure 5A flowchart illustrating the operation phase of a computing device as provided in an embodiment of this application;

[0052] Figure 6 This is a schematic diagram of the application architecture of the memory mapping method provided in the embodiments of this application;

[0053] Figure 7 A schematic diagram of an embodiment of the bidirectional lookup table provided in this application;

[0054] Figure 8 A schematic diagram of the architecture of the address mapping table provided in the embodiments of this application, which is set in the memory controller;

[0055] Figure 9 A schematic diagram of the architecture of the address mapping table provided in the embodiments of this application, which is set in the register clock driver;

[0056] Figure 10 A schematic diagram of an embodiment of the memory mapping circuit provided in this application;

[0057] Figure 11 This is a schematic diagram of one embodiment of the computing device provided in this application. Detailed Implementation

[0058] The embodiments of this application are described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. As those skilled in the art will understand, with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0059] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0060] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0061] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0062] This application provides a memory mapping method for flexibly defining the integration location of the address mapping table and the reserved amount of redundant resources for replacement. Based on this address mapping table, it enables multiple reversible replacements of memory failure rows, avoiding business performance loss, significantly reducing memory failure rate, and improving memory reliability. This application also provides corresponding memory mapping circuits, computing devices, computer-readable storage media, chip systems, and computer program products. These are described in detail below.

[0063] The following examples illustrate the application scenarios involved in the embodiments of this application.

[0064] like Figure 1 As shown, a typical von Neumann computer system comprises five main components: arithmetic, control, storage, input, and output. Storage includes main memory (RAM) and secondary storage (solid-state drives, hard disk drives, etc.). As an indispensable part of the von Neumann architecture, RAM primarily serves as working memory, storing the instructions and data required for computer operation. With the development of high-performance computing, big data analytics, and in-memory databases, applications are increasingly demanding higher memory capacity and bandwidth. Driven by the continuous requirements for memory density and bandwidth performance, memory manufacturing processes are constantly miniaturizing, and interface speeds are continuously increasing. Simultaneously, memory failure rates are gradually rising, posing significant risks to memory reliability, for example:

[0065] (1) Capacitance decreases: As the manufacturing process shrinks, the capacitance decreases (the capacitance of a 25nm process capacitor is 18fF, while the capacitance of a 17nm process capacitor drops to about 8fF). The amount of charge that a capacitor can store decreases, thus the data retention gradually decreases.

[0066] (2) Increased leakage current: The leakage current increases due to the thinning of the capacitor insulation material and the subthreshold effect of the access transistor, which reduces the data retention capacity of the memory cell.

[0067] (3) Increased coupling effect: Due to the miniaturization, capacitors, bit lines and word lines are closer to each other, increasing coupling and leading to an increased probability of data jumps caused by mutual influence between adjacent spaces.

[0068] (4) Increased row and column errors caused by process defects: As the size shrinks and the capacity density increases, the requirements for the precision of the processing technology are constantly increasing, and the density of processing defects is constantly increasing. This is manifested in the increase of early failures of dynamic random access memory (DRAM), especially the significant increase in failures where rows / columns are the characteristic fault domains.

[0069] (5) Increased transmission rate leads to increased probability of interface error: The interface rate of double data rate synchronous dynamic random-access memory (DDR SDRAM) has been increasing with each generation. Due to the use of a single-ended signal parallel bus, coupled with the influence of memory sockets, the probability of data jumps on the interface is also increasing.

[0070] Based on statistical data on memory production failures and live network faults, it can be observed that with each generation, the number of failed memory rows exceeds the memory repair capability limit. Production interception rates increase with each generation, and live network failure rates continue to rise, but the memory failure area is concentrated within a limited number of rows. Current memory chip manufacturers incorporate replacement functions into their memory chips. However, this replacement function pre-sets the redundant space used for replacement, which cannot be changed. This limits the number of memory replacements and results in some performance loss, failing to meet current memory fault requirements.

[0071] Based on this, this application provides a memory mapping method for flexibly defining the integration location of the address mapping table and flexibly defining the reserved amount of redundant resources for replacement. Based on the address mapping table, multiple reversible replacements of memory failure rows are implemented to avoid business performance loss, significantly reduce memory failure rate, and improve memory reliability.

[0072] The embodiments provided in this application will be described below in conjunction with the above application scenarios.

[0073] like Figure 2 As shown, one embodiment of the memory mapping method provided in this application includes:

[0074] 200. The baseboard management controller (BMC) performs fault line detection on multiple memory modules of the computing device. When a fault line is detected in the first memory module, the address of the fault line is provided to the basic input output system (BIOS).

[0075] In this embodiment, the BIOS instructs the memory mapping circuit of the first memory to replace the invalid lines. The memory mapping circuit includes an acquisition circuit and a matching lookup circuit. The matching lookup circuit is integrated into the address command output circuit in the memory access path of the first memory, or integrated into the driver circuit of the first memory.

[0076] Both the BMC and BIOS are located on the motherboard of the computing device. The motherboard provides memory slots for connecting multiple memory modules, including the primary memory module. Here, "motherboard" includes both a motherboard in the conventional sense and a combination of a motherboard and a backplate.

[0077] It should be noted that when the first memory is still in the production stage, it can be tested for faulty rows using other testing equipment. During the startup stage of the computing device, it can be tested for faulty rows using the BIOS of the computing device. This application embodiment does not limit the subject that performs the faulty row detection.

[0078] 201. The first memory acquisition circuit obtains the memory failure line address of the first memory from the motherboard and provides the obtained failure line address to the first memory matching lookup circuit.

[0079] The first memory module is a memory module, each memory module includes multiple memory chips, and each memory chip includes multiple memory banks.

[0080] 202. The first memory matching and lookup circuit obtains the address mapping table.

[0081] In this embodiment, the computing device first needs to enable the matching lookup circuit to obtain the address mapping table. This matching lookup circuit is integrated into the first memory, specifically located on the memory access path, such as an address command output circuit or driver circuit. Specifically, the matching lookup circuit can be integrated into any address command output circuit or driver circuit between the address mapping module of the memory controller and the DRAM chip (memory chip). The memory access path of the first memory can be understood as the path through which the processor of the computing device accesses memory, such as the path through which the memory controller of a central processing unit (CPU), data processing unit (DPU), graphics processing unit (GPU), tensor processing unit (TPU), and neural network processing unit (NPU) accesses the DRAM chip in the first memory. The address command output circuit or driver circuit in this memory access path includes the memory controller (DDR controller, DDRC) in the processor of the computing device, and also includes the registering clock driver (RCD) in the first memory. This embodiment illustrates this by exemplifying the matching lookup circuit integrated into the RCD.

[0082] Furthermore, the first memory is loaded into the computing device via a memory slot provided by the computing device's motherboard. This computing device can be any computer device, server, or storage device that uses memory. The match lookup circuit may include volatile memory, such as content addressable memory (CAM), ternary content addressable memory (TCAM), and fully associative cache, i.e., fully associative static random-access memory (SRAM) cache. The match lookup circuit may also include non-volatile memory (NVM), such as one-time programmable memory (eFuse), programmable read-only memory (PROM), electrically erasable programmable read-only memory (E2PROM), and storage class memory (SCM). This application embodiment illustrates this by including a TCAM in the match lookup circuit, where the address mapping table is stored in the TCAM, which is integrated into the RCD of the first memory.

[0083] Furthermore, the address mapping table includes a mapping relationship between memory failure row addresses and memory remapping row addresses corresponding to memory failure row addresses. The address mapping table is used to remap memory failure row addresses to memory remapping row addresses when the access target of the first memory is a memory failure row address. The memory region indicated by the memory remapping row address is located in the reserved space of the first memory. The reserved space of the first memory can come from the user DRAM chip capacity in the first memory, that is, the reserved space is visible to the user and needs to be reserved by software. In addition, the reserved space can also come from the redundant space designed by the memory manufacturer outside the nominal capacity of the first memory. The reserved space is outside the addressing range of the memory controller and is not visible to the user. This application embodiment uses the reserved space coming from the user DRAM capacity in the first memory as an example for illustration.

[0084] Furthermore, the first memory is specifically a high-speed memory, such as DDR, low-power DDR (LPDDR), graphics DDR (GDDR), high-bandwidth memory (HBM), or SCM, etc. This application embodiment uses DDR as the first memory for illustration. The first memory includes one or more memory channels. One or more dual in-line memory modules (DIMMs) can be inserted into a memory channel. A DIMM can be composed of one or more memory ranks. A rank includes multiple memory chips, also called memory particles. A chip includes multiple memory banks or bank groups. A bank is an array composed of multiple storage cells, and a row of storage cells in a bank can be represented by a row. When the memory medium is DRAM, the memory chip is also called a DRAM particle.

[0085] Furthermore, the matching lookup circuit treats multiple memory chips as a whole for row address translation. When a single memory chip has a failed row, the matching lookup circuit uses an address mapping table to convert the row addresses in multiple memory chips into memory remapped row addresses. The converted rows include failed rows; that is, the address mapping table operates on each chip, and the matching lookup circuit replaces the memory failed row addresses in all chips. The reserved space in the first memory includes at least one row from each of the multiple memory banks, meaning each bank has at least one row of storage units as reserved space. This allows users to customize larger reserved spaces and enables multiple reversible replacements based on the address mapping table.

[0086] In this embodiment, since the matching lookup circuit is integrated into the address command output circuit or driver circuit in the memory access path of the first memory, the user can customize the size and integration position of the matching lookup circuit in the address command output circuit or driver circuit in the memory access path, that is, customize the size and integration position of the address mapping table. The larger the custom address mapping table is, the more memory remapping row addresses there are, and the larger the reserved space for redundant resources is. The above size and position can be flexibly customized by the user according to the needs and actual situation.

[0087] In the memory mapping method provided in this application embodiment, steps 201 and 202 can be executed independently in multiple scenarios, which will be described separately below. That is, memory row mapping and replacement can be performed during the memory manufacturer's memory production phase, the computing device startup phase, and the computing device's business operation phase, each with corresponding technical effects. Memory row mapping and replacement can be performed in one or more of these three scenarios.

[0088] I. First Stage of Memory Production

[0089] like Figure 3 As shown, during the production stage of the first memory, the memory failure line address of the first memory can be obtained through a testing device (which serves as a computing device and is the execution subject of the method embodiment of this application). Specifically, a smart memory test (SMT) is performed, and early failures are triggered in advance based on a screening aging algorithm. Once a memory error is detected, the corresponding memory failure line address is recorded, a memory remapping line address is allocated to the memory failure line address, and an address mapping table is generated in the matching lookup circuit according to a predetermined format to improve the memory production pass rate.

[0090] Furthermore, since TCAM is a volatile memory, an NVM, such as eFuse, can be added to the first memory, and the address mapping table generated at this time can be written to the eFuse in the RCD. The address mapping table generated during the production of the first memory is permanently followed by the built-in eFuse as unique information of the first memory. Usually, the eFuse programming interface is not exposed to users on the live network to prevent user misoperation. Since the eFuse is used to persistently store the address mapping table determined when the first memory fails during production, the address mapping table also needs to be persisted to other non-volatile media.

[0091] Specifically, after the first memory is loaded into the computing device, the address mapping table in eFuse needs to be synchronized to the first memory of the computing device. The first memory is NVM, which can be integrated into the RCD chip, the module printed circuit board (PCB), and the system motherboard, etc. The processor of the computing device needs to check whether the address mapping table in eFuse has been synchronized to the NVM of the computing device. Only after successful synchronization can the computing device use the first memory, at which point the first memory is ready for use.

[0092] The address mapping table obtained during the memory production stage can be stored in the non-volatile storage medium of the memory module. When the memory is used by the user, the user can obtain the address mapping table from the non-volatile storage medium and add newly discovered faulty lines to the address mapping table during the memory self-test during the computing device startup phase.

[0093] II. Computer device startup phase

[0094] like Figure 4 As shown, the user installs memory in the computing device. An enable switch can be set in the computing device (containing the first memory). When the second command is sent, the enable switch is turned on, initiating a self-test and enabling the acquisition of the memory failure line address of the first memory. If a memory failure is detected, it is promptly replaced. When the first command is sent, the enable switch is turned off, the self-test is disabled, and the acquisition of the memory failure line address of the first memory is stopped, thus achieving the purpose of quickly starting the computing device.

[0095] When the computing device starts up, after sending the first command, specifically during the pre-extensible firmware interface initialization (PEI) phase, the computing device's BIOS performs a full-space memory check, such as performing a memory build-in-self test (Mbist). If a memory error is detected, the corresponding memory failure line address needs to be recorded, and a memory remapping line address needs to be allocated in the reserved space for the memory failure line address. An address mapping table is generated in the matching lookup circuit according to a predetermined format, and the address mapping table in TCAM is synchronized to the system persistent NVM backup in the computing device, such as the onboard serial peripheral interface (SPI) flash.

[0096] Furthermore, during the startup process of the computing device equipped with the first memory, the address mapping table is read from the first memory and updated through the memory self-test of the computing device. Specifically, during the PEI stage at startup of the computing device, the address mapping table in the first memory NVM of the computing device, the address mapping table recorded by eFuse during the first memory production stage, and the address mapping table generated by the memory self-test during the PEI stage at startup of the computing device are read using the product serial number (SN) of the first memory as a unique identifier, and the information is combined. In the address mapping tables of the three records mentioned above, entries for different rows are directly merged (Rd-Merge). If a memory failure row address has been replaced multiple times, that is, if the replacement information for a row exists in two or more record locations simultaneously, the address mapping table with the higher confidence priority is used for overwriting. The confidence priority is NVM > eFuse > PEI self-test. For example, if the memory failure row address is A1, the corresponding memory remapping row address in the address mapping table record in NVM is B1, the corresponding memory remapping row address in the address mapping table of the eFuse record is B2, and the corresponding memory remapping row address in the address mapping table of the memory self-test record in the PEI stage is B3, then the memory remapping row address corresponding to the memory failure row address A1 is finally determined to be B1, and it is synchronized to the matching lookup circuit TCAM. Since the computing device has not yet used the first memory at this time, the memory data migration problem is avoided. Finally, in the DXE stage, the merged address mapping table is written into the first memory NVM.

[0097] Optionally, if the reserved space comes from the user DRAM capacity in the first memory, the system memory mapping relationship and memory segment attributes can be defined through memory descriptors during the BIOS address mapping (memory map) stage when the computing device starts up. This information is then passed to the operating system (OS) of the computing device through the Advanced Configuration and Power Interface (ACPI) interface. The aforementioned reserved space can be reported with the `reserve` attribute during the memory map stage. It should be noted that since the memory map is a startup service, it exits during computing device runtime and cannot be woken up. Therefore, it is impossible to set reserved space for hot-inserted memory during runtime. However, when the reserved space comes from redundant space designed by the memory manufacturer beyond the nominal capacity of the first memory, this step does not need to be performed during computing device startup.

[0098] III. Computer Equipment Operation Phase

[0099] like Figure 5As shown, when the computing device is running, the first memory fault log of the first memory is obtained, the first memory fault features are extracted from the first memory fault log, and prediction is made based on the first memory fault features to obtain the memory failure line address of the first memory.

[0100] Specifically, such as Figure 6 As shown, the computing device includes an application (APP), an OS, a BIOS, and a CPU. The CPU contains a memory controller. The computing device collects in-band information (management control information and service carrying information are transmitted through the same logical channel) through the board management agent in the OS, i.e., information collected through the data channel, and out-of-band information (transmitted through different logical channels) collected by the baseboard management controller (BMC) in the computing device, i.e., information collected through an additional channel on the data channel. This information is aggregated in real time in the BMC as the first memory fault log to form a federal diagnosemodule (FDM) log. The FDM log records the bit transition information of a certain row in the first memory. The memory fault prediction engine deployed in the BMC can use the first memory fault features (memory instant fault features) extracted from the FDM log to predict which rows in the first memory will fail (which can be understood as risk rows), and finally obtain the memory failure row address of the first memory.

[0101] It should be understood that the address mapping table generated during the operation of a computing device can be dynamically replaced and released, and is not permanent. Therefore, the accuracy requirements for fault prediction can be reduced, thereby improving coverage.

[0102] If the memory failure prediction engine predicts a high risk of failure for a particular row, the BMC records the risky row information. During reliability, availability, and serviceability (RAS) interrupt handling, the BIOS queries the BMC via the Intelligent Platform Management Interface (IPMI) to check for risky row warnings. If a warning is found, the BIOS initiates a row replacement process, allocating memory remapping row addresses in reserved space for the memory failure row addresses and generating a new address mapping table. Furthermore, performing row replacement in the address mapping table while the computing device is in use requires not only modifying the mapping relationships in the address mapping table but also copying data.

[0103] The fault prediction reports the media row address, requiring the calculation of the physical address that the BIOS can operate on. Since the sum of all DRAM capacities is equal to the DRAM space size reported by the BIOS, there is a one-to-one mapping between physical addresses and media addresses. Therefore, a reversible reverse mapping exists to convert from media address to physical address. Thus, the physical address corresponding to the first address of the row can be calculated as the copy start address, and the size of the continuous address range involved in the row can be calculated using the number of interleaved channels. Data copying can be implemented directly in the BIOS using the memory copy function (memcpy), which internally performs reading, error correction, and writing at the cache line (CL) granularity. The previously calculated physical address is used as the copy start address, and the continuous address range is used as the copy length. The data corresponding to the memory fault row address is directly copied to the allocated memory remapping row address. After copying, a new address mapping table is generated by merging it with the address mapping table recorded in the NVM in the first memory according to a predefined format. This new address mapping table is then overwritten and written to the TCAM via the I3C bus, and subsequently overwritten into the system NVM.

[0104] It should be noted that after completing the above operations, if the computing device still reports an error even after replacing a memory invalid line address, it indicates that the memory remapping line address to which that line address was remapped has become invalid. Further updates to the memory remapping line address are needed to remap it to another redundant line. After the mapping relationship in the address mapping table is successfully modified, subsequent accesses to the memory invalid line address will be redirected to the memory remapping line address because the underlying mapping has been changed.

[0105] In this embodiment, the BMC aggregates out-of-band or in-band memory error information for offline training nodes to train the memory failure prediction model. The trained algorithm and model can then be used for online inference to predict the evolution trend of memory failure in real time, and notify the BIOS to generate a new address mapping table in a timely manner, thereby reducing or even avoiding the occurrence of uncorrectable errors (UCE).

[0106] Refer to together Figure 6As can be seen, the computing device accesses multiple DIMMs in the first memory through the memory controller. Each DIMM includes multiple memory chips (e.g., chip0-chip10 in a rank), an RCD, and a serial presence detect hub (SPD Hub). Each memory chip includes multiple memory banks (e.g., bank0). The RCD is equipped with a TCAM and an eFuse. When the first memory starts working / powers on, the TCAM loads the address mapping table from the eFuse. When the first memory stops working / powers off, the TCAM synchronizes the address mapping table to the eFuse or the computing device's system NVM to achieve persistent storage. The memory access address is transmitted from the memory controller to the TCAM in the RCD through the DIMM's gold fingers for matching. The memory failure line address in the memory bank is remapped to the memory remapped line address before access. For example, the memory failure line address is remapped to the memory remapped line address located in the same bank.

[0107] Furthermore, before the first memory stops working, that is, before the computing device stops working, the address mapping table needs to be written from the matching lookup circuit to the first memory. After the first memory starts working, that is, after the computing device starts working, the address mapping table in the first memory is loaded into the matching lookup circuit, thereby realizing the persistent storage and updating of the address mapping table.

[0108] Furthermore, when the computing device is idle, risk confirmation and release can be performed by obtaining the same memory failure row address. That is, the memory failure row address is accessed for testing to obtain the second memory failure log of the first memory. Then, the second memory failure feature is extracted from the second memory failure log. Based on the second memory failure feature, a prediction is made to determine whether the memory failure row address is the actual failure row address. When the predicted row failure risk of the memory failure row address is low, it is determined that the memory failure row address is not the actual failure row address. The memory failure row address and the memory remapping row address corresponding to the memory failure row address are released from the address mapping table, thereby saving redundant space in TCAM and reserved space. This enables the system to have reversible isolation and release capabilities, reduces the prediction accuracy requirements, and improves the fault prediction coverage.

[0109] Optionally, for risk confirmation and release, a TCAM bypass switch can be designed in the RCD. Configured via register enable, enabling the TCAM bypass switch prevents memory access from querying matching TCAMs, thus allowing access to replaced invalid line addresses. Furthermore, as... Figure 7As shown, a bidirectional lookup table can also be designed to automatically determine whether it is a business access or a risk stress test confirmation based on the input address range. Taking the bidirectional lookup table set on RCD as an example, if the input row address range is within the user address space (e.g., 0-10000), a forward lookup is performed, mapping the memory failure row address to the memory remapping row address; if the input row address range is within the reserved space address (e.g., 10000-11000), a reverse lookup is performed, mapping the memory remapping row address to the memory failure row address, determining whether access can be successful, and thus performing a stress test on the memory failure row address to achieve secondary risk confirmation, thereby determining whether the memory failure row address is a real row failure and whether it needs to be released.

[0110] like Figure 8 As shown in the embodiments of this application, the TCAM provided can also be integrated into the memory controller of the processor of the first device. This memory controller includes at least a RAS module, a scheduler, an address mapping module, and a physical layer (PHY). The memory controller is connected to the HA. The RAS module implements the RAS characteristics of the memory subsystem. The scheduler is used for efficient and high-quality-of-service (QoS) scheduling of memory access tasks. The address mapping module performs the conversion from system media address to DDR physical address, ensuring memory access conforms to the DDR protocol. It sends the memory access address to the PHY via the DDR PHY Interface (DFI) protocol. The PHY connects to the off-chip DDR SDRAM via input / output interfaces (I / O), converting the DFI protocol to the DDR protocol and maximizing the sampling window through fine-tuning of interface timing and calibration of interface characteristics. Furthermore, the address mapping module includes a TCAM and an NVM. When the first memory starts working / powers on, the TCAM loads the address mapping table from the NVM. When the first memory stops working / powers down, the TCAM synchronizes the address mapping table to the NVM for persistent storage.

[0111] 203. Obtain the memory access address from outside the first memory.

[0112] The access is initiated by a processor in the computing device that has memory access rights. The processor acting as the external accessor can be, for example, a CPU, GPU, DPU, or NPU.

[0113] 204. The memory mapping circuit uses the acquired memory access address to match the memory access address based on the address mapping table.

[0114] 205. When a memory access address is matched in the memory invalidation line address, the memory mapping circuit will convert the access to the memory access address into an access to the memory remapped line address.

[0115] For read access, the data in the remapped row address is returned to the external accessor in step 203. For write access, the data is written to the remapped row address, and a write success response is returned to the external accessor in step 203.

[0116] In step 202, regardless of which stage the address mapping table is generated at, it needs to be used for matching when accessing memory. First, the memory access address from outside the first memory is obtained. This memory access address can be sent by the processor of the computing device, specifically the bankgroup, bank, or row information input in the input command address (DCA). Then, the memory access address is matched based on the address mapping table. When the access target of the first memory is a memory invalidation row address, the memory remapping row address mapped to the memory invalidation row address is obtained through the address mapping table. It should be understood that steps 202-205 are specifically executed by the matching and lookup circuitry in the computing device.

[0117] For example, the address mapping table shown in Table 1 includes 4 sets of mapping relationships, where A is used to indicate a failed row in a certain bank in the first memory, and B is used to indicate the corresponding remapped row in the same bank in the first memory. For example, A1 indicates the first row in bank0 (e.g., row1), B1 indicates the last row in bank0 (e.g., row100), A2 indicates the second row in bank1, B2 indicates the last row in bank1, A3 indicates the second row in bank2, B3 indicates the second to last row in bank2, A4 indicates the first row in bank3, and B4 indicates the third to last row in bank3.

[0118] Table 1

[0119] Memory invalid line address Memory remapped line address A1 B1 A2 B2 A3 B3 A4 B4

[0120] Specifically, such as Figure 9As shown, the memory access address is input to the first memory from the memory access path. When the memory access address reaches the TCAM in the RCD through the DDR C / A bus, matching (TCAM search) begins. When the memory access address matches the memory failure row address in the address mapping table, for example, when the memory access address is A1, it can be understood that the memory access address has a row failure. The TCAM hits, that is, the match is successful. The memory failure row address in DRAM is remapped to the memory remapped row address B1 corresponding to the memory failure row address. The subsequent access target is replaced with the memory remapped row address B1, that is, the data corresponding to the memory remapped row address B1 is read through the DDR data bus. When the memory access address is A5, it cannot be matched in the address mapping table, which can be understood as the TCAM missing. The subsequent access target is still the memory access address A5, and the data corresponding to the memory access address A5 is read directly through the DDR data bus.

[0121] In this embodiment, the memory failure line address of the first memory is obtained, and an address mapping table is generated in the matching lookup circuit. The address mapping table includes the memory failure line address and the memory remapping line address corresponding to the memory failure line address. The address mapping table is used to remap the memory failure line address to the memory remapping line address when the access target of the first memory is the memory failure line address. The memory region indicated by the memory remapping line address is located in the reserved space of the first memory. Since the matching lookup circuit is integrated into the address command output circuit or driver circuit in the memory access path of the first memory, the user can flexibly define the integration location of the address mapping table and the amount of redundant resource reservation, and realize multiple reversible replacements based on the address mapping table without restarting the system. Neither the kernel mode nor the user mode is aware of it, avoiding loss of business performance, thereby significantly reducing the memory failure rate and improving memory reliability.

[0122] The memory mapping method provided in the embodiments of this application has been described above. The related devices provided in the embodiments of this application are described below with reference to the accompanying drawings.

[0123] like Figure 10 As shown, one embodiment of the memory mapping circuit 1000 provided in this application includes:

[0124] The acquisition circuit 1001 is used to acquire the memory invalid line address of the first memory; the acquisition unit 1001 can execute step 201 in the above method embodiment.

[0125] The matching lookup circuit 1002 is used to obtain the memory failure line address from the acquisition circuit 1001. The matching lookup circuit 1002 is also used to obtain an address mapping table, which includes the mapping relationship between memory failure line addresses and memory remapping line addresses corresponding to those memory failure line addresses. When the access target of the first memory is a memory failure line address, the matching lookup circuit 1002 is used to obtain the memory remapping line address mapped to the memory failure line address through the address mapping table. The memory region indicated by the memory remapping line address is located in the reserved space of the first memory. The matching lookup circuit is integrated into the address command output circuit or driver circuit in the memory access path of the first memory. This matching lookup circuit 1002 can execute step 202 in the above method embodiment.

[0126] Optionally, the memory mapping circuit 1000 is integrated into memory, which includes multiple memory chips for providing reserved space; or, the memory mapping circuit 1000 is integrated into a processor, which is any one of a central processing unit (CPU), a data processing unit (DPU), an embedded neural network processor (NPU), a graphics processing unit (GPU), or a tensor processor (TPU).

[0127] Optionally, the matching lookup circuit 1002 is also used to obtain a memory access address from outside the first memory; use the obtained memory access address to match the memory access address based on the address mapping table; when a memory access address is matched in the memory invalid line address, the access to the memory access address is converted to the access to the memory remapped line address.

[0128] Optionally, the first memory includes multiple memory chips, and the matching lookup circuit 1002 treats the multiple memory chips as a whole for row address translation. Specifically, when a single memory chip has a failed row, the matching lookup circuit 1002 is used to convert the row address in the multiple memory chips into a memory remapping row address through an address mapping table, wherein the converted row includes the failed row.

[0129] Optionally, each of the multiple memory chips includes multiple memory banks, and the reserved space of the first memory includes at least one row of each of the multiple memory banks.

[0130] Optionally, the address mapping table is stored in volatile memory in the matching lookup circuit 1002. The memory mapping circuit 1000 also includes a read-write circuit 1003, which is used to write the address mapping table from the matching lookup circuit 1002 to the first memory before the first memory stops working. The first memory is a non-volatile memory located in the computing device. The read-write unit 1004 is also used to load the address mapping table in the first memory to the matching lookup circuit 1002 after the first memory starts working.

[0131] Optionally, during the startup process of the computing device loaded with the first memory, the read / write circuit 1003 is also used to read the address mapping table from the first memory and update the address mapping table through the memory self-test of the computing device.

[0132] Optionally, the volatile memory in the match lookup circuit 1002 can be a content-addressable memory, a tri-state content-addressable memory, or a fully associative cache.

[0133] Optionally, the address mapping table is stored in non-volatile memory in the match lookup circuit 1002.

[0134] Optionally, the memory mapping circuit 1000 further includes a generation circuit 1004, which generates an address mapping table when the computing device loaded with the first memory starts up; and synchronizes the address mapping table to the matching lookup circuit 1002 before the computing device uses the first memory.

[0135] Optionally, the acquisition unit 1001 is specifically used to acquire the first memory fault log of the first memory; extract the first memory fault features from the first memory fault log; and make a prediction based on the first memory fault features to obtain the memory failure line address of the first memory.

[0136] Optionally, the memory mapping circuit 1000 further includes a release circuit 1005, which is used to perform an access test on the memory failure row address to determine whether the memory failure row address is a real failure row address; when the memory failure row address is not a real failure row address, the memory failure row address and the memory remapping row address corresponding to the memory failure row address are released from the address mapping table.

[0137] Optionally, the memory mapping circuit 1000 further includes a sending circuit 1006, which is used to send a first command to enable the cessation of acquiring the memory invalid line address of the first memory.

[0138] Optionally, the match lookup circuit 1002 is integrated into the memory controller or register clock driver in the address command output circuit or drive circuit.

[0139] The memory mapping circuit 1000 provided in this application embodiment can be understood by referring to the relevant content in the foregoing memory mapping method embodiment section, and will not be repeated here.

[0140] Figure 11 The diagram shown illustrates a possible logical structure of a computing device provided in an embodiment of this application. The computing device includes a motherboard 1101, a processor 1102, memory 1103, and a memory mapping circuit 1104.

[0141] The motherboard 1101 is used to detect memory fault lines and send the address of the faulty memory line to the memory mapping circuit 1104. The memory mapping circuit 1104 is integrated into the processor 1102 or the memory 1103 (e.g., Figure 11 The memory mapping circuit 1104 shown is integrated into the memory 1103. The memory mapping circuit 1104 is used to perform the above-described... Figures 2 to 9 In the memory mapping method described in some embodiments, memory 1103 is used as the first memory to perform memory invalidation line address mapping.

[0142] Specifically, the memory 1103 is the first memory in the method embodiment, and the memory mapping circuit 1104 includes the matching lookup circuit in the method embodiment, specifically a memory controller or a register clock driver, or the memory mapping circuit 1104 includes... Figure 10 The acquisition circuit 1001, matching and searching circuit 1002, reading and writing circuit 1003, generating circuit 1004, releasing circuit 1005, and sending circuit 1006 shown, and the memory mapping circuit 1104 can perform the above-described memory mapping method on the memory 1103.

[0143] In another embodiment of this application, a computer-readable storage medium is also provided, which stores computer-executable instructions. When at least one processor of the device executes the computer-executable instructions, the device performs the aforementioned... Figures 2 to 9 The memory mapping method described in some embodiments.

[0144] In another embodiment of this application, a computer program product is also provided, comprising computer-executable instructions stored in a computer-readable storage medium; at least one processor of the device can read the computer-executable instructions from the computer-readable storage medium, and the at least one processor executes the computer-executable instructions to cause the device to perform the above-described actions. Figures 2 to 9 The memory mapping method described in some embodiments.

[0145] In another embodiment of this application, a chip system is also provided, the chip system including at least one processor and an interface, the interface being used to receive data and / or signals, and the at least one processor being used to support the implementation of the above. Figures 2 to 9 The memory mapping method described in some embodiments. In one possible design, the chip system may further include a memory for storing program instructions and data necessary for the computer device. The chip system may be composed of chips or may include chips and other discrete devices.

[0146] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0147] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0148] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0149] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0150] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0151] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A memory mapping method, characterized in that, Applied to memory, the memory including memory-mapped circuitry, the memory being connected to a processor, the method includes: Obtain the memory access address of the processor accessing memory; According to the address mapping table set in the matching lookup circuit of the memory mapping circuit, the memory access address is determined to be the memory failure line address. The address mapping table includes the correspondence between the memory failure line address and the memory remapping line address. The memory region indicated by the memory remapping line address is located in the reserved space of the memory. The address mapping table corresponds to multiple memory chips in the memory. The reserved space of the memory comes from the multiple memory chips of the memory. Obtain the memory remapping line address corresponding to the memory invalidation line address.

2. The method according to claim 1, characterized in that, The reserved space is a portion of the actual used storage space of the memory; or the reserved space is the storage space in the memory other than the actual used storage space.

3. The method according to claim 2, characterized in that, The address mapping table is stored in volatile memory within the memory mapping circuit, and the method further includes: Before the first memory stops working, the address mapping table is written from the memory mapping circuit into the first memory, which is a non-volatile memory; After the first memory starts working, the address mapping table in the first memory is loaded into the memory mapping circuit.

4. The method according to claim 3, characterized in that, The method further includes: During the startup process of the computing device containing the memory, the address mapping table is updated.

5. The method according to claim 4, characterized in that, The volatile memory is a content-addressable memory, a tri-state content-addressable memory, or a fully associative cache.

6. The method according to claim 2, characterized in that, The address mapping table is stored in non-volatile memory within the memory mapping circuit.

7. The method according to any one of claims 1-6, characterized in that, The method further includes: An access test is performed on the memory failure line address to determine whether the memory failure line address is a truly failed line address; When the memory failure row address is not the actual failure row address, the memory failure row address and the memory remapping row address corresponding to the memory failure row address are released from the address mapping table.

8. The method according to any one of claims 1-6, characterized in that, The address mapping table is integrated into the memory controller or the register clock driver.

9. A memory mapping circuit, characterized in that, Applied to memory, the memory including memory mapping circuitry, the memory being connected to a processor, the memory mapping circuitry including: The acquisition circuit is used to acquire the memory access address of the processor accessing memory; A determining circuit is used to determine that the memory access address is a memory failure line address according to the address mapping table set in the matching lookup circuit of the memory mapping circuit. The address mapping table includes the correspondence between the memory failure line address and the memory remapping line address. The memory region indicated by the memory remapping line address is located in the reserved space of the memory. The address mapping table corresponds to multiple memory chips in the memory. The reserved space of the memory comes from the multiple memory chips of the memory. An acquisition circuit is used to acquire the memory remapping row address corresponding to the memory invalidation row address.

10. The circuit according to claim 9, characterized in that, The reserved space is a portion of the actual used storage space of the memory; or the reserved space is the storage space in the memory other than the actual used storage space.

11. The circuit according to claim 10, characterized in that, The address mapping table is stored in volatile memory within the memory mapping circuit, which further includes: A read / write circuit is used to write the address mapping table from the memory mapping circuit into a first memory, which is a non-volatile memory, before the first memory stops working. The read / write circuit is also used to load the address mapping table in the first memory into the memory mapping circuit after the first memory starts working.

12. The circuit according to claim 11, characterized in that, The circuit also includes: An update circuit is used to update the address mapping table during the startup process of a computing device loaded with the memory.

13. The circuit according to claim 12, characterized in that, The volatile memory in the address command output circuit or driver circuit is a content-addressable memory, a tri-state content-addressable memory, or a fully associative cache.

14. The circuit according to claim 10, characterized in that, The address mapping table is stored in non-volatile memory within the memory mapping circuit.

15. The circuit according to any one of claims 9-14, characterized in that, The circuit also includes: A release circuit is used to perform an access test on the memory failure row address to determine whether the memory failure row address is a truly failed row address; when the memory failure row address is not a truly failed row address, the memory failure row address and the memory remapping row address corresponding to the memory failure row address are released from the address mapping table.

16. The circuit according to any one of claims 9-14, characterized in that, The address mapping table is integrated in the memory controller or the register clock driver.

17. A computing device, characterized in that, include: The memory and the processor, wherein the memory includes memory-mapped circuitry and the memory is connected to the processor; The memory is used to: obtain the memory access address used by the processor to access the memory; The memory is also used to: determine the memory access address as a memory failure line address according to the address mapping table set in the matching lookup circuit of the memory mapping circuit, wherein the address mapping table includes the correspondence between the memory failure line address and the memory remapping line address, the memory region indicated by the memory remapping line address is located in the reserved space of the memory, the address mapping table corresponds to multiple memory chips in the memory, and the reserved space of the memory comes from the multiple memory chips of the memory; The memory is also used to: obtain the memory remapping line address corresponding to the memory failure line address.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1-8.

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