Matrix transposition unit, computing device, matrix transposition method and medium

Abstract

The present application provides a matrix transposition unit, a computing device, a matrix transposition method and a medium, wherein the transposition unit comprises: a first buffer, used to read the data of the divided matrix to be transposed from a global buffer; a delay unit, used to delay the data read from the first buffer by different clock cycles according to the byte; a shift register, used to shift the delayed data to obtain the data after matrix transposition; and a second buffer, used to read the transposed data from the shift register and write it into the global buffer.

Description

Technical Field

[0001] The present application relates to the field of hardware architecture technology, and in particular to a matrix transposition unit, a computing device, a matrix transposition method and a medium. Background Art

[0002] In large language models based on the Transformer algorithm, matrix transposition, as a core component of matrix operations, plays a vital role in a variety of algorithms and applications. In particular, when processing large language models, if the activation matrix is ​​stored in row-first format, when performing the SV operation in the attention calculation, the matrix must be transposed to column-first format for subsequent matrix multiplication calculations.

[0003] Traditional matrix transposition operations mostly rely on central processing units (CPUs). However, due to the limited parallel processing capabilities of CPUs, when processing large-scale matrices, their operation speed and efficiency may not meet the requirements of real-time or high-performance computing. To overcome this challenge, a matrix transposition hardware unit was designed. This hardware unit is specially optimized for matrix transposition operations, and significantly improves operation speed and energy efficiency through highly parallel computing and optimized data flow.

[0004] In large language models, using a matrix transposition hardware unit to perform a transposition operation followed by a general matrix multiplication (GEMM) operation can effectively reduce the demand for computing and storage resources, thereby achieving lower energy consumption and higher inference performance. This optimization is of great significance for achieving efficient and real-time natural language processing tasks.

[0005] In the related art, the implementation of matrix transposition mainly relies on the graphics processing unit (GPU) for calculation. Although the GPU is more efficient than the central processing unit (CPU) in matrix transposition, due to the universality of the computing architecture (for example, CUDA (Compute Unified Device Architecture) core) design, when it is used for matrix transposition, it cannot perform other computing tasks at the same time, which leads to relatively high resource consumption.

[0006] In addition, some matrix transposition modules may use dedicated hardware accelerators. However, due to insufficient algorithm optimization or unreasonable hardware design, these modules will have low resource utilization during the transposition process. This is manifested as the "bubble" phenomenon during the transposition process, that is, the hardware resources are not fully utilized, and the advantages of hardware acceleration cannot be fully utilized. Summary of the invention

[0007] The present application provides a matrix transposition unit, a computing device, a matrix transposition method and a computer-readable storage medium, which solve the problem of low resource utilization in the matrix transposition process caused by insufficient algorithm optimization or unreasonable hardware design in the prior art.

[0008] In order to achieve the above objectives, this application adopts the following technical solutions:

[0009] In a first aspect, a matrix transposition unit is provided, the matrix transposition unit comprising:

[0010] A first buffer is used to read the data of the divided matrix to be transposed from the global buffer;

[0011] A delay unit, used for delaying the data read from the first buffer by different clock cycles according to bytes;

[0012] A shift register, used for shifting the delayed data to obtain matrix transposed data;

[0013] The second buffer is used to read the transposed data from the shift register and write the transposed data into the global buffer.

[0014] Optionally, the divided matrix to be transposed is a plurality of sub-matrices to be transposed into which the entire matrix to be transposed is divided according to a preset transposition granularity.

[0015] Optionally, the delay unit delays the data read from the first buffer in sequence from low to high bytes.

[0016] Optionally, the delayed clock cycles corresponding to the bytes from low to high increase sequentially from 1 clock cycle to a clock cycle that is the same as the data width.

[0017] Optionally, the data width is the number of bytes of the data.

[0018] Optionally, the delay unit and the shift register are both implemented by a plurality of D flip-flops having a pipeline structure.

[0019] Optionally, the size of the shift register is the same as the size of the transposition granularity.

[0020] Optionally, when the second buffer writes the transposed data into the global buffer, the first buffer may perform a read operation, and the shift register may perform a shift operation.

[0021] In a second aspect, a computing device is provided, the computing device comprising:

[0022] A memory, used for storing matrix transposition instructions to be executed;

[0023] A matrix transposition unit as described in any one of the first aspects;

[0024] The processing unit is used to load the matrix transposition instruction to be executed and distribute the matrix transposition instruction to be executed to the matrix transposition unit.

[0025] In a third aspect, a matrix transposition method is provided, the matrix transposition method comprising: dividing a matrix to be transposed into sub-matrices according to a transposition granularity;

[0026] Read the divided sub-matrix data into the first buffer;

[0027] The data passing through the first buffer is read into the delay unit, and the delay unit performs delays of different periods according to the size of the byte;

[0028] The delayed data is written into the shift register, and the shift register shifts the delayed data;

[0029] The second buffer reads the shifted data from the shift register and writes it to the global buffer.

[0030] Optionally, reading the divided sub-matrix data into the first buffer includes: when reading a row of a sub-matrix of the matrix from the global buffer to the first buffer without interval, obtaining the row source address of the matrix through multiple first counters and the base address of the source address.

[0031] Optionally, the second buffer reads the shifted data from the shift register and writes the shifted data into the global buffer, comprising: obtaining the row destination address of the matrix through a plurality of second counters and a base address of the destination address.

[0032] Optionally, the first counter is independent of the second counter.

[0033] According to a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the method according to any one of the third aspects is implemented.

[0034] A matrix transposition unit provided in an embodiment of the present application reads the divided matrix data to be transposed from a global buffer through a first buffer, a delay unit delays the data read from the first buffer by different clock cycles according to the byte from low to high, a shift register shifts the delayed data, and a second buffer reads the transposed data from the shift register and writes it into the global buffer. In an embodiment of the present application, both the delay unit and the shift register may include a plurality of triggers having a pipeline structure, so when writing data to the global buffer, the first buffer may continue to read data, and the shift register may continue to shift. Thereby, the idle time of the hardware unit is eliminated, and data is read, shifted, and written back, forming a pipeline process, thereby improving the utilization rate of the hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of a matrix transposition unit structure provided in an embodiment of the present application;

[0036] Figure 2 A data flow diagram of a matrix transposition unit provided in an embodiment of the present application;

[0037] Figure 3 A schematic diagram of a matrix transposition method process provided in an embodiment of the present application;

[0038] Figure 4 A flowchart of an address and instruction matching method for matrix transposition provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] In the following description, for the purpose of illustration rather than limitation, specific details such as specific system structures, technologies, etc. are proposed to provide a thorough understanding of the present application embodiments. However, it should be clear to those skilled in the art that the present application can also be implemented in other embodiments without these specific details. In other cases, the detailed description of well-known matrix transposition methods and matrix calculations is omitted to prevent unnecessary details from hindering the description of the present application.

[0040] The terms used in the following embodiments are only for the purpose of describing specific embodiments and are not intended to be limiting of the present application. As used in the specification and appended claims of the present application, the singular expressions "a", "said", "above", and "the" are intended to also include expressions such as "one or more", unless the context clearly indicates otherwise.

[0041] In large language models based on the Transformer algorithm, matrix transposition, as a core component of matrix operations, plays a vital role in a variety of algorithms and applications. In particular, when processing large language models, if the activation matrix is ​​stored in row-major format, when performing the SV operation in the attention calculation, the matrix must be transposed to column-major format for subsequent matrix multiplication calculations.

[0042] Traditional matrix transposition operations mostly rely on central processing units (CPUs). However, due to the limited parallel processing capabilities of CPUs, when processing large-scale matrices, their operation speed and efficiency may not meet the requirements of real-time or high-performance computing. To overcome this challenge, a matrix transposition hardware unit was designed. This hardware unit is specially optimized for matrix transposition operations, and significantly improves operation speed and energy efficiency through highly parallel computing and optimized data flow.

[0043] In large language models, using a matrix transposition hardware unit to perform a transposition operation followed by a general matrix multiplication (GEMM) operation can effectively reduce the demand for computing and storage resources, thereby achieving lower energy consumption and higher inference performance. This optimization is of great significance for achieving efficient and real-time natural language processing tasks.

[0044] In the related art, the implementation of matrix transposition mainly relies on the graphics processing unit (GPU) for calculation. Although the GPU is more efficient than the central processing unit (CPU) in matrix transposition, due to the universality of the design of the computing architecture (for example, NVIDIA's CUDA (Compute Unified Device Architecture) core), when it is used for matrix transposition, it cannot perform other computing tasks at the same time, which leads to relatively high resource consumption.

[0045] In addition, some matrix transposition modules may use dedicated hardware accelerators. However, due to insufficient algorithm optimization or unreasonable hardware design, these modules will have low resource utilization during the transposition process. This is manifested as the "bubble" phenomenon during the transposition process, that is, the hardware resources are not fully utilized, and the advantages of hardware acceleration cannot be fully utilized.

[0046] Therefore, the embodiment of the present application proposes a matrix transposition unit, which reads the divided matrix data to be transposed from the global buffer through the first buffer, the delay unit delays the data read from the first buffer by different clock cycles according to the byte from low to high, the shift register shifts the delayed data, and the second buffer reads the transposed data from the shift register and writes it to the global buffer. In the embodiment of the present application, the delay unit and the shift register can both include multiple triggers containing a pipeline structure, so when writing data to the global buffer, the first buffer can continue to read data, and the shift register can continue to shift. Thereby eliminating the idle time of the hardware unit, reading data, shifting, and writing back data, forming a pipeline process, and improving the utilization rate of the hardware.

[0047] The following first introduces the application scenarios involved in the matrix transposition unit provided in the embodiment of the present application. The application scenarios for implementing matrix transposition mainly involve tasks that require large-scale parallel computing and processing, especially in the fields of high-performance computing, machine learning, and deep learning. The following are several specific application scenario examples:

[0048] High-performance computing (HPC): In scientific computing, it is often necessary to process large-scale matrix operations, such as linear algebra operations, numerical analysis, etc. The matrix transposition unit can significantly accelerate operations such as matrix transposition through its highly parallel computing power and efficient memory access mode, thereby accelerating the overall performance of scientific computing.

[0049] Machine learning: In machine learning, matrix transposition is one of the common operations, especially in data preprocessing and feature engineering. The matrix transposition unit can realize efficient matrix transposition operations through programming models, accelerating the training and inference process of machine learning algorithms.

[0050] Deep learning: Deep learning models, such as convolutional neural networks (CNNs) and recurrent neural networks (RNNs), require a large number of matrix operations, including matrix transposition, when processing tasks such as images, speech, and natural language. The matrix transposition unit, as the main computing unit of the deep learning model, efficiently implements matrix transposition, thereby accelerating the training and inference of the deep learning model.

[0051] Image processing: In image processing, matrix transposition is often used for tasks such as image transformation, filtering, and feature extraction. The matrix transposition unit can efficiently process large-scale image data and achieve fast matrix transposition operations through its powerful parallel computing capabilities.

[0052] Signal processing: In the field of signal processing, matrix transposition is often used in signal processing algorithms, such as Fourier transform, filtering, etc. The matrix transposition unit can accelerate the matrix transposition operation in these algorithms and improve the speed and efficiency of signal processing.

[0053] The following is an introduction to the matrix transposition unit in the above application scenario.

[0054] Figure 1 A schematic diagram of a matrix transposition unit structure provided in an embodiment of the present application is provided as an example rather than a limitation. The matrix transposition unit can be applied to the above application scenarios. Figure 2 The matrix transposition unit 10 includes: a buffer 101 (a first buffer), a delay unit 102, a shift register 103 and a buffer 104 (a second buffer).

[0055] It should be noted that in the present application, the transposition of matrix A is used as an example for illustration, B=AT, wherein the data of matrix A and the transposed matrix B are both stored in the global buffer.

[0056] In the embodiments of the present application, for the purpose of illustrating, data is stored in 8 bits (1 byte) to store an integer, but the present application does not impose any specific restrictions on the specific storage format of the data.

[0057] The size of matrix A is M*K, where M and K are positive integers. Matrix A is divided into sub-matrices for transposition. The size of the sub-matrix that can be transposed each time (transposition granularity) is M0*K0, where M0 and K0 are positive integers and M0 is less than M, and K0 is less than K, where M0 and K0 can be preset, for example, 3, 4, 8, 16, etc. MX and KX represent the number of transposed sub-matrices into which the matrix to be transposed can be split in the two dimensions of M and K, respectively. For example, in the embodiment of the present application, M=512, K=256, M0=16, K0=16. Then MX=32, KX=16. The embodiment of the present application does not specifically limit the size of matrix A and the transposed sub-matrix.

[0058] exist Figure 1 In the transposition unit shown, the matrix data to be transposed cached in the global buffer passes through the buffer 101 and then enters the delay unit 102, and enters the shift register 103 after being delayed by the delay unit 102. After passing through the shift register, the matrix data is transposed, and the transposed data is output to the global buffer for storage through the second buffer 104.

[0059] It should be noted that both the buffer 101 and the buffer 104 can be first-in-first-out (FIFO) buffers, which can ensure the order and integrity of data.

[0060] Figure 1 The matrix transposition unit shown may also include a controller, Figure 1 Not shown in the figure, the controller shown can be used to control the buffer 101 (first buffer), the delay unit 102, the shift register 103 and the buffer 104 (second buffer).

[0061] The first buffer 101 is used to read the data to be transposed from the global buffer. It should be noted that the data read from the first buffer 101 is the data of the sub-matrix divided according to the transposition granularity.

[0062] The delay unit 102 is used to perform a parallel delay operation on the data in the FIFO (first in first out) buffer. In the embodiment of the present application, for illustration, the width of the data to be subjected to the parallel delay operation is 16 bytes, but the embodiment of the present application does not specifically limit the specific data width.

[0063] For data in a 16-byte FIFO buffer, the maximum number of delay units is M0, and each delay unit is responsible for delaying one byte. The delay operation starts from the lowest byte, delaying 1 clock cycle to the highest byte by 16 clock cycles. To achieve this delay sequence, each delay unit requires a corresponding number of D flip-flops. When M0 is 16, it can be calculated that the total number of D flip-flops required from the lowest byte to the highest byte is (1+2+...+15+16)×8=1088.

[0064] The shift register 103 is used to perform a shift operation on the delayed data, and the delayed data then enters the shift register. The shift register is configured as a matrix structure of M0*K0, for example, it can be: 16*16. During the shift process, the register completes the transposition operation of the matrix.

[0065] The second buffer 104 is used to read the transposed data from the shift register and write it into the global buffer. The data after the transposition operation is completed is written into the global buffer through the FIFO buffer to realize the sequential storage and transmission of the data. The delay unit and the shift register can be composed of a plurality of D flip-flops with a pipeline structure, so that new data can be continuously read and shifted while writing back the data. This parallel processing mode eliminates the idle time of the hardware unit, forms a pipeline operation of reading data, shifting, and writing back data, thereby significantly improving the utilization rate and overall performance of the hardware.

[0066] The following is an introduction to the data flow of the matrix transposition unit provided in the embodiment of the present application. Figure 2 .

[0067] like Figure 2 The data to be transposed stored in the global buffer is divided into multiple (in Figure 2 In the embodiment shown, the submatrix is ​​divided into three submatrices) and the submatrix is ​​transposed (in Figure 2 In the embodiment shown, the transposition granularity is 3*3, that is, M0=3, K0=3). The elements in the first sub-matrix to be transposed are read into the first buffer 101 in the order of row sorting; Figure 2 In the embodiment shown, the number of delay units is M0, that is, 3. The data that enters the first buffer 101 in row order enters the delay unit in a first-in-first-out order. The delay operation starts from the lowest byte, and delays by 1 clock cycle to the highest byte by 3 clock cycles. The delayed data then enters the shift register, which is configured as a matrix structure of M0*K0, for example, 3*3.

[0068] like Figure 2 As shown, the data entering the first buffer in the first clock cycle is "1", "2", "3", the data entering the buffer in the second clock cycle is "4", "5", "6", and the data entering the first buffer in the third clock cycle is "7", "8", "9". The corresponding "1", "2", "3" are delayed by one clock cycle by the delay unit, "4", "5", "6" are delayed by two clock cycles, and "7", "8", "9" are delayed by three clock cycles. The delayed data enters the shift register from Figure 2 It can be seen that the matrix transposition is completed after the shift register is shifted.

[0069] Furthermore, the data after matrix transposition is completed is written into the global buffer for storage via the second buffer, wherein the second buffer may also be a FIFO buffer.

[0070] pass Figure 2 It can be seen from the embodiment shown that the data read into the first buffer in the first clock cycle is "1", "2", "3", the data read into the second clock cycle is "4", "5", "6", and the data read into the third clock cycle is "7", "8", "9". The data written into the shift register in the fourth clock cycle is "1", "4", "7". That is, the data read into the shift register in three clock cycles is written into the shift register in one clock cycle.

[0071] It should be noted that in the embodiments of the present application, both the delay unit and the shift register may include multiple triggers with a pipeline structure, so when writing data to the global buffer, the first buffer can continue to read data, and the shift register can continue to shift. This eliminates the idle time of the hardware unit, reads data, shifts, and writes back data, forming a pipeline process, and improving the utilization of the hardware.

[0072] like Figure 2As shown, in the 4th clock cycle, the 1st row of data in the shift register is transposed, and in the 5th clock cycle, the 2nd row of data in the shift register is transposed, and so on. In the 6th clock cycle, the 3rd row of data in the shift register is transposed, and the transposition of the first M0*K0 sub-matrix is ​​completed. In the 7th clock cycle, the transposition of the next M0*K0 sub-matrix begins, and the shift register jumps back to the 1st row of data to complete the transposition, until the last M0*K0 block is transposed, and the M*K matrix transposition is completed.

[0073] In summary, the matrix transposition unit provided in the embodiment of the present application reads the divided matrix data to be transposed from the global buffer through the first buffer, the delay unit delays the data read from the first buffer by different clock cycles according to the byte from low to high, the shift register shifts the delayed data, and the second buffer reads the transposed data from the shift register and writes it to the global buffer. In the embodiment of the present application, the delay unit and the shift register may include multiple triggers containing a pipeline structure, so when writing data to the global buffer, the first buffer can continue to read data, and the shift register can continue to shift. Thereby eliminating the idle time of the hardware unit, reading data, shifting, and writing back data, forming a pipeline process, and improving the utilization rate of the hardware.

[0074] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0075] According to one aspect of an embodiment of the present application, a computing device is provided, including:

[0076] A memory, used for storing matrix transposition instructions to be executed;

[0077] A matrix transposition unit as described above;

[0078] The processing unit is used to load the matrix transposition instruction to be executed and distribute the matrix transposition instruction to be executed to the matrix transposition unit.

[0079] Corresponding to the matrix transposition unit described in the above embodiment, Figure 3 A flowchart of a matrix transposition method provided in an embodiment of the present application is provided. For ease of explanation, only the part related to the embodiment of the present application is shown.

[0080] Reference Figure 3 , the matrix transposition method includes:

[0081] Step 301: Divide the matrix to be transposed into sub-matrices according to the transposition granularity.

[0082] For example, the size of the matrix to be transposed is M*K, where M and K are positive integers, and the matrix to be transposed is divided into submatrices according to the transposition granularity for transposition, and the size of the submatrix that can be transposed each time (transposition granularity) is M0*K0, where M0 and K0 are positive integers and M0 is less than M, and K0 is less than K, where M0 and K0 can be preset, for example, 3, 4, 8, 16, 32, etc. MX, KX represent the number of transposed submatrices that the matrix to be transposed can be split into in the two dimensions of M and K, respectively. For example, in the embodiment of the present application, M=512, K=256, M0=16, K0=16. Then MX=32, KX=16. The embodiment of the present application does not specifically limit the size of the matrix A and the transposed submatrix.

[0083] Step 302: Read the divided sub-matrix data into a first buffer.

[0084] The first buffer may be a first-in-first-out buffer, and the data in the divided sub-matrices are read into the first buffer in order of rows.

[0085] Step 303: read the data passing through the first buffer into the delay unit, and the delay unit performs delays of different periods according to the size of the bytes.

[0086] The maximum number of delay units is M0, and each delay unit is responsible for delaying one byte. The delay operation starts from the lowest byte, and delays by 1 clock cycle to the highest byte by 16 clock cycles (the byte width is 16 for illustration, and the number of clock delay cycles corresponding to the highest byte is the same as its own width). To achieve this delay sequence, each delay unit requires a D flip-flop with the corresponding number of bits.

[0087] Step 304: write the delayed data into the shift register, and the shift register shifts the delayed data.

[0088] Step 305: The second buffer reads the shifted data from the shift register and writes the shifted data into the global buffer.

[0089] The following describes the address and instruction matching method for matrix transposition. Figure 4 , Figure 4 The following is a flowchart of a matrix transposition address and instruction matching method provided in an embodiment of the present application. Figure 4 The methods shown include:

[0090] S401, dividing a matrix into a plurality of sub-matrices, and transposing them in sequence;

[0091] The principle of dividing a matrix into a plurality of sub-matrices is the same as that in the above embodiment and will not be described in detail here.

[0092] S402, obtaining the source address of the matrix row through multiple counters and the base address of the source address;

[0093] After the transposition operation starts, when a row of a divided sub-matrix of the matrix is ​​read from the global buffer to the first buffer without interval, the row source address src_addr_row of the matrix is ​​weighted summed by multiple counters and src_addr in the instruction, and the formula of the source address is shown in formula (1): src_addr_row = src_counter_mx*K*M0+src_counter_m0x*K+src_counter_kx*K0+src_addr(1).

[0094] S403, obtaining a destination address of a matrix row through a plurality of counters and a base address of the destination address;

[0095] After the transposition operation is completed, when writing back to the global buffer, the row destination address dst_addr_row of the matrix is ​​weighted summed by multiple counters and dst_addr in the instruction, where src_addr_row and dst_addr_row are calculated by their own independent counters, and src_counter_kx and dst_counter_kx are independent of each other. The formula of the destination address is shown in formula (2): dst_addr_row = dst_counter_kx*M*K0+dst_counter_ktx*M+dst_counter_mx*M0+dst_addr(2);

[0096] S404, complete matrix calculation.

[0097] When the second buffer reads out the last row of the transposed matrix, the matrix calculation is completed; for a transposition of a [M, K] INT8 type matrix, the calculation time delay is approximately M*K / K0.

[0098] It should be noted that src_addr_row is the global buffer source address, src_addr is the base address of the source address, src_counter_mx (first counter) is the M-dimensional counter, src_counter_kx (second counter) is the K-dimensional counter, and src_counter_m0x is the counter in the M dimension of the sub-matrix; dst_addr_row is the global buffer destination address, dst_addr is the base address of the destination address, dst_counter_mx is the M-dimensional counter, dst_counter_kx is the K-dimensional counter, and dst_counter_k0x is the counter in the K dimension of the sub-matrix.

[0099] The embodiment of the present application uses a combination of a delay unit and a shift register to make the transposition process bubble-free, and only requires a small amount of hardware resources to achieve efficient matrix transposition. In addition, by reading data, shifting, and writing back data to form an efficient pipeline, resource consumption is reduced and the overhead of ping-pong cache is saved.

[0100] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0101] The embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the method described in the above method embodiment is implemented.

[0102] The embodiment of the present application also provides a computer program product, which implements the method described in the above method embodiment when the computer program product is running.

[0103] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable storage medium may at least include: any entity or device that can carry the computer program code to the camera / terminal device, recording medium, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0104] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0105] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0106] In the embodiments provided in the present application, it should be understood that the disclosed devices / equipment and methods can be implemented in other ways. For example, the device / equipment embodiments described above are merely schematic, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0107] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0108] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0109] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0110] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0111] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A matrix transposition unit, characterized in that: The matrix transposition unit comprises: A first buffer is used to read the data of the divided matrix to be transposed from the global buffer; A delay unit, used for delaying the data read from the first buffer by different clock cycles from low to high according to bytes, wherein the different clock cycles are clock cycles that increase from 1 clock cycle to a clock cycle that is the same as the data width, and the data width is the number of bytes of the data; A shift register, used for shifting the delayed data to obtain matrix transposed data; The second buffer is used to read the transposed data from the shift register and write the transposed data into the global buffer.

2. The matrix transposition unit according to claim 1, characterized in that: The divided matrix to be transposed is a plurality of sub-matrices to be transposed into which the entire matrix to be transposed is divided according to a preset transposition granularity.

3. The matrix transposition unit according to claim 1 or 2, characterized in that: The delay unit and the shift register are both implemented by a plurality of D flip-flops with a pipeline structure.

4. The matrix transposition unit according to claim 2, characterized in that: The size of the shift register is the same as the size of the transposition granularity.

5. The matrix transposition unit according to claim 1 or 2, characterized in that: When the second buffer writes the transposed data into the global buffer, the first buffer performs a read operation and the shift register performs a shift operation.

6. A computing device, characterized in that: The computing device comprises: A memory, used for storing matrix transposition instructions to be executed; The matrix transposition unit according to any one of claims 1 to 5; The processing unit is used to load the matrix transposition instruction to be executed and distribute the matrix transposition instruction to be executed to the matrix transposition unit.

7. A matrix transposition method, characterized in that: The matrix transposition method comprises: Divide the matrix to be transposed into sub-matrices according to the transposition granularity; Read the divided sub-matrix data into the first buffer; The data passing through the first buffer is read into the delay unit, and the delay unit sequentially delays the data by different clock cycles from low to high according to the byte, and the different clock cycles are sequentially increased from 1 clock cycle to the clock cycle that is the same as the data width, and the data width is the number of bytes of the data; The delayed data is written into the shift register, and the shift register shifts the delayed data; The second buffer reads the shifted data from the shift register and writes it to the global buffer.

8. The method according to claim 7, characterized in that The step of reading the divided sub-matrix data into the first buffer comprises: when reading a row of a sub-matrix of the matrix from the global buffer to the first buffer without interval, obtaining a row source address of the matrix through a plurality of first counters and a base address of the source address; The second buffer reads the shifted data from the shift register and writes it into the global buffer, comprising: obtaining the row destination address of the matrix through a plurality of second counters and a base address of the destination address; The first counter is independent of the second counter.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 7 to 8 is implemented.

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