Pixel circuit, driving method thereof, display panel and display device

Abstract

Provided are a pixel circuit and a driving method thereof, a display panel, and a display device, and belong to the technical field of display. In the pixel circuit, a first driving circuit is capable of transmitting a light-emitting driving signal to a first node; a second driving circuit is capable of transmitting a light-emitting control signal of a first potential or a second potential to a second node. A light-emitting control circuit is capable of controlling the on-off of the first node and a light-emitting element based on the light-emitting control signal. When the first node and the light-emitting element are turned on, the light-emitting driving signal can be transmitted to the light-emitting element to drive the light-emitting element to emit light. The first potential is a high potential relative to the second potential, that is, the first potential is a high potential and the second potential is a low potential. Therefore, the light-emitting control signal not only has characteristics similar to digital signals, but also can provide a preset gating time for the light-emitting element, that is, control the light-emitting duration of the light-emitting element. Further, the driving of the light-emitting element can be ensured to emit light stably, so that the display stability of the display panel can be better.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel circuit and its driving method, a display panel, and a display device. Background Technology

[0002] A micro light-emitting diode (micro-LED) is a light-emitting element with a size measured in micrometers. It has advantages such as high brightness, small size, and low power consumption, and is commonly used in micro-display scenarios, such as augmented reality (AR) scenarios.

[0003] In related technologies, the pixel circuit for driving micro-LED light emission generally includes an analog circuit consisting of a data writing circuit and a driving circuit. The data writing circuit is coupled to the gate signal terminal, the data signal terminal, and the driving circuit, and is used to control the data signal terminal to transmit data signals to the driving circuit based on the gate driving signal provided by the gate signal terminal. The driving circuit is also coupled to the driving power supply terminal and the micro-LED, and is used to transmit light emission driving signals to the micro-LED based on the data signal and the driving power supply signal provided by the driving power supply terminal, so as to drive the micro-LED to emit light.

[0004] However, due to the small size of micro-LEDs, the driving stability of micro-LEDs using current analog circuits is poor, resulting in poor display quality. Summary of the Invention

[0005] A pixel circuit and its driving method, a display panel, and a display device are provided, which can solve the problem of poor display effect caused by the poor driving stability of current analog circuits used to drive micro-LED light emission. The technical solution is as follows:

[0006] On one hand, a pixel circuit is provided, the pixel circuit comprising:

[0007] The first driving circuit is coupled to the first gate signal terminal, the first data signal terminal, the first power supply terminal and the first node respectively, and is used to transmit the light emission driving signal to the first node based on the first gate driving signal provided by the first gate signal terminal, the first data signal provided by the first data signal terminal and the first power supply signal provided by the first power supply terminal.

[0008] The second driving circuit is coupled to the second gate signal terminal, the second data signal terminal, the third data signal terminal, the driving terminal, and the second node, respectively, and is used to transmit a light emission control signal of the first potential or the second potential to the second node based on the second gate driving signal provided by the second gate signal terminal, the second data signal provided by the second data signal terminal, the third data signal provided by the third data signal terminal, and the driving signal provided by the driving terminal, wherein the first potential is a high potential relative to the second potential;

[0009] The light-emitting control circuit is coupled to the first node, the second node and the light-emitting element respectively, and is used to control the on / off state of the first node and the light-emitting element based on the light-emitting control signal received by the second node.

[0010] Optionally, the second driving circuit includes:

[0011] A switching sub-circuit is coupled to the second gate signal terminal, the second data signal terminal, the third data signal terminal, and the third node, respectively, and is used to control the on / off state of the second data signal terminal and the third node based on the second gate drive signal;

[0012] The output sub-circuit is coupled to the third node, the driving terminal and the second node respectively, and is used to transmit a light emission control signal to the second node based on the potential of the third node and the driving signal.

[0013] Optionally, the driving terminal includes: a first reset terminal; the second gate signal terminal includes: a first sub-gate signal terminal and a second sub-gate signal terminal;

[0014] The switching sub-circuit includes:

[0015] The first switching unit is coupled to the first sub-gate signal terminal, the second data signal terminal and the third node respectively, and is used to control the on / off state of the second data signal terminal and the third node based on the first sub-gate drive signal provided by the first sub-gate signal terminal;

[0016] The second switching unit is coupled to the second sub-gate signal terminal, the third data signal terminal and the third node respectively, and is used to control the on / off state of the third data signal terminal and the third node based on the second sub-gate drive signal provided by the second sub-gate signal terminal;

[0017] The output sub-circuit includes:

[0018] An adjustment unit is coupled to the third node and the fourth node respectively, and is used to adjust the potential of the fourth node based on the potential of the third node;

[0019] An inverting unit is coupled to the fourth node and the second node respectively, and is used to invert the potential of the fourth node and transmit it to the second node as a light emission control signal.

[0020] The third switching unit is coupled to the first reset terminal, the fourth node, and the second node respectively, and is used to control the connection and disconnection of the fourth node and the second node based on the first reset signal provided by the first reset terminal.

[0021] Optionally, the first switching unit includes a first transistor; the second switching unit includes a second transistor; the adjustment unit includes a first capacitor; the inverting unit includes an inverter; and the third switching unit includes a third transistor.

[0022] The gate of the first transistor is coupled to the first sub-gate signal terminal, the first electrode of the first transistor is coupled to the second data signal terminal, and the second electrode of the first transistor is coupled to the third node;

[0023] The gate of the second transistor is coupled to the second sub-gate signal terminal, the first terminal of the second transistor is coupled to the third data signal terminal, and the second terminal of the second transistor is coupled to the third node;

[0024] One end of the first capacitor is coupled to the third node, and the other end of the first capacitor is coupled to the fourth node;

[0025] The input terminal of the inverter is coupled to the fourth node, and the output terminal of the inverter is coupled to the second node;

[0026] The gate of the third transistor is coupled to the first reset terminal, the first terminal of the third transistor is coupled to the fourth node, and the second terminal of the third transistor is coupled to the second node.

[0027] Optionally, the driving end includes: a first power supply end and a second power supply end; the third node includes: a first child node and a second child node;

[0028] The switching sub-circuit includes:

[0029] The first switching unit is coupled to the second gate signal terminal, the second data signal terminal and the first child node respectively, and is used to control the on / off state of the second data signal terminal and the first child node based on the second gate drive signal;

[0030] The second switching unit is coupled to the second gate signal terminal, the third data signal terminal and the second sub-node respectively, and is used to control the on / off state of the third data signal terminal and the second sub-node based on the second gate drive signal;

[0031] The output sub-circuit includes:

[0032] Two output units are provided. One output unit is coupled to the first sub-node, the first power supply terminal, the second power supply terminal, and the second node, respectively. The other output unit is coupled to the second sub-node, the first power supply terminal, the second power supply terminal, and the second node, respectively. The two output units are used to transmit light emission control signals to the second node based on the potential of the first sub-node, the potential of the second sub-node, the first power supply signal, and the second power supply signal provided by the second power supply terminal.

[0033] Optionally, the first switching unit includes a first transistor; the second switching unit includes a second transistor; of the two output units, one output unit includes a third transistor and a fourth transistor of different transistor types; the other output unit includes a fifth transistor and a sixth transistor of different transistor types.

[0034] The gate of the first transistor is coupled to the second gate signal terminal, the first terminal of the first transistor is coupled to the second data signal terminal, and the second terminal of the first transistor is coupled to the first child node;

[0035] The gate of the second transistor is coupled to the second gate signal terminal, the first terminal of the second transistor is coupled to the third data signal terminal, and the second terminal of the second transistor is coupled to the second child node;

[0036] The gate of the third transistor and the gate of the fourth transistor are both coupled to the first sub-node and the second node, the first terminal of the third transistor is coupled to the first power supply terminal, the first terminal of the fourth transistor is coupled to the second power supply terminal, and the second terminals of the third transistor and the fourth transistor are both coupled to the second sub-node.

[0037] The gate of the fifth transistor and the gate of the sixth transistor are both coupled to the second sub-node and the second node. The first terminal of the fifth transistor is coupled to the first power supply terminal. The first terminal of the sixth transistor is coupled to the second power supply terminal. The second terminals of the fifth transistor and the sixth transistor are both coupled to the first sub-node.

[0038] Optionally, the first driving circuit is also coupled to the second reset terminal and the second power supply terminal respectively, and is used to control the connection and disconnection between the second power supply terminal and the first node based on the second reset signal provided by the second reset terminal;

[0039] The first driving circuit includes:

[0040] The data writing sub-circuit is coupled to the first gate signal terminal, the first data signal terminal and the fifth node respectively, and is used to control the on / off state of the first data signal terminal and the fifth node based on the first gate drive signal;

[0041] The driving sub-circuit has an input terminal coupled to the first power supply terminal, a driving terminal coupled to the fifth node, and an output terminal coupled to the first node. It is used to transmit a light-emitting driving signal to the first node based on the potential of the fifth node and the first power supply signal.

[0042] The reset sub-circuit is coupled to the second reset terminal, the second power supply terminal, and the first node, respectively, and is used to control the connection and disconnection between the second power supply terminal and the first node based on the second reset signal.

[0043] Optionally, the data writing sub-circuit includes a seventh transistor; the driving sub-circuit includes an eighth transistor; and the reset sub-circuit includes a ninth transistor.

[0044] The gate of the seventh transistor is coupled to the first gate signal terminal, the first terminal of the seventh transistor is coupled to the first data signal terminal, and the second terminal of the seventh transistor is coupled to the fifth node;

[0045] The gate of the eighth transistor is coupled to the fifth node, the first terminal of the eighth transistor is coupled to the first power supply terminal, and the second terminal of the eighth transistor is coupled to the first node.

[0046] The gate of the ninth transistor is coupled to the second reset terminal, the first terminal of the ninth transistor is coupled to the second power supply terminal, and the second terminal of the ninth transistor is coupled to the first node.

[0047] Optionally, the first driving circuit further includes:

[0048] The first regulating sub-circuit is coupled to the fifth node and the target terminal respectively, and is used to regulate the potential of the fifth node based on the potential of the target terminal;

[0049] The target terminal includes: a reference power supply terminal, the input terminal of the first node or the driving sub-circuit, and if the target terminal is the input terminal of the driving sub-circuit, the first driving circuit further includes:

[0050] The second regulating sub-circuit is coupled to the first power supply terminal and the input terminal of the driving sub-circuit, respectively, and is used to adjust the potential of the input terminal of the driving sub-circuit based on the first power supply signal.

[0051] The light emission control sub-circuit is coupled to the third gate signal terminal, the first power supply terminal, and the input terminal of the driving sub-circuit, respectively, and is used to control the on / off state of the first power supply terminal and the input terminal of the driving sub-circuit based on the third gate driving signal provided by the third gate signal terminal.

[0052] Optionally, the first regulating sub-circuit includes a second capacitor; the second regulating sub-circuit includes a third capacitor; and the light-emitting control sub-circuit includes a tenth transistor.

[0053] One end of the second capacitor is coupled to the target terminal, and the other end of the second capacitor is coupled to the fifth node;

[0054] One end of the third capacitor is coupled to the first power supply terminal, and the other end of the third capacitor is coupled to the input terminal of the driving sub-circuit.

[0055] The gate of the tenth transistor is coupled to the third gate signal terminal, the first terminal of the tenth transistor is coupled to the first power supply terminal, and the second terminal of the tenth transistor is coupled to the input terminal of the driving sub-circuit.

[0056] Optionally, the target terminal is the reference power supply terminal, and the transistor included in the data writing sub-circuit is a transmission gate switch transistor.

[0057] Optionally, the light-emitting control circuit includes: an eleventh transistor;

[0058] The gate of the eleventh transistor is coupled to the second node, the first electrode of the eleventh transistor is coupled to the first node, and the second electrode of the eleventh transistor is coupled to the light-emitting element.

[0059] On the other hand, a driving method for a pixel circuit is provided, the method being applied to a pixel circuit as described in the above aspect; the method includes:

[0060] In the first stage, the first driving circuit transmits the light-emitting driving signal to the first node based on the first gate driving signal provided by the first gate signal terminal, the first data signal provided by the first data signal terminal, and the first power supply signal provided by the first power supply terminal.

[0061] In the second stage, the second driving circuit transmits a light emission control signal of a target potential to the second node based on the second gate driving signal provided by the second gate signal terminal, the second data signal provided by the second data signal terminal, the third data signal provided by the third data signal terminal, and the driving signal provided by the driving terminal. The target potential includes a first potential or a second potential, and the first potential is a higher potential relative to the second potential. Based on the light emission control signal of the target potential received by the second node, the light emission control circuit controls the first node to conduct with the light emission element so as to drive the light emission element to emit light. The conduction duration of the first node and the light emission element is positively correlated with the duration of the target potential.

[0062] In another aspect, a display panel is provided, the display panel comprising: a substrate, and a plurality of pixels located on one side of the substrate;

[0063] The pixel includes a light-emitting element and a pixel circuit as described above, wherein the pixel circuit is coupled to the light-emitting element and is used to drive the light-emitting element to emit light.

[0064] In another aspect, a display device is provided, the display device comprising: a power supply component, and a display panel as described in yet another aspect above;

[0065] The power supply component is coupled to the display panel and is used to supply power to the display panel.

[0066] In summary, the beneficial effects of the technical solutions provided by the embodiments of this disclosure can at least include:

[0067] A pixel circuit and its driving method, a display panel, and a display device are provided. The pixel circuit includes a first driving circuit, a second driving circuit, and a light-emitting control circuit. The first driving circuit transmits a light-emitting driving signal to a first node based on signals provided by each coupled signal terminal. The second driving circuit transmits a light-emitting control signal of a first potential or a second potential to a second node based on signals provided by each coupled signal terminal. The light-emitting control circuit controls the switching between the first node and the light-emitting element based on the light-emitting control signal. When the first node and the light-emitting element are connected, the light-emitting driving signal received by the first node can be further transmitted to the light-emitting element, thereby driving the light-emitting element to emit light. The first potential is higher than the second potential; that is, the first potential is high and the second potential is low. Therefore, the light-emitting control signal not only has characteristics similar to digital signals but also provides a preset selection time for the light-emitting element, i.e., controlling the light-emitting duration of the light-emitting element. This ensures stable light emission from the light-emitting element, resulting in better display stability of the display panel. Attached Figure Description

[0068] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0069] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present disclosure;

[0070] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this disclosure;

[0071] Figure 3 This is a schematic diagram of another pixel circuit provided in an embodiment of the present disclosure;

[0072] Figure 4 This is a schematic diagram of another pixel circuit provided in an embodiment of the present disclosure;

[0073] Figure 5 This is a schematic diagram of another pixel circuit provided in an embodiment of the present disclosure;

[0074] Figure 6 This is a schematic diagram of another pixel circuit provided in an embodiment of the present disclosure;

[0075] Figure 7 This is a schematic diagram of another pixel circuit provided in an embodiment of the present disclosure;

[0076] Figure 8 This is a schematic diagram of another pixel circuit provided in an embodiment of the present disclosure;

[0077] Figure 9 Is Figure 5 A schematic diagram of another pixel circuit structure is shown based on this.

[0078] Figure 10 Is Figure 6 A schematic diagram of another pixel circuit structure is shown based on this.

[0079] Figure 11 Is Figure 7 A schematic diagram of another pixel circuit structure is shown based on this.

[0080] Figure 12 Is Figure 8 A schematic diagram of another pixel circuit structure is shown based on this.

[0081] Figure 13 This is a flowchart of a pixel circuit driving method provided in an embodiment of this disclosure;

[0082] Figure 14 Is Figure 11 The timing diagram of a pixel circuit based on the structure shown is illustrated.

[0083] Figure 15 Is Figure 14 The following is a timing diagram of the operation of a second driving circuit based on the above.

[0084] Figure 16 This is a schematic diagram of the structure of a display panel provided in an embodiment of this disclosure;

[0085] Figure 17 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0086] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0087] It should be noted that the transistors used in all embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of this disclosure are mainly switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of this disclosure, the source is referred to as the first electrode, and the drain as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is designated as the control electrode, also known as the gate; the signal input terminal is the source; and the signal output terminal is the drain. Furthermore, the switching transistors used in the embodiments of this disclosure can include either P-type or N-type switching transistors. A P-type switching transistor conducts when the gate is low and is cut off when the gate is high, while an N-type switching transistor conducts when the gate is high and is cut off when the gate is low. Additionally, multiple signals in various embodiments of this disclosure correspond to a first potential and a second potential. The first potential and the second potential only represent that the signal has two potential states and do not represent that the first potential or the second potential has a specific value throughout the text.

[0088] In recent years, AR display products have developed rapidly. They can use optical waveguide technology to achieve light-emitting displays, making AR display products thinner and lighter. However, optical waveguide technology generally has significant light loss, requiring high device brightness. Therefore, the use of silicon-based organic light-emitting diodes (OLEDs), which are self-emissive and still achieve thinness, is being considered for light-emitting displays. However, due to lifespan limitations, silicon-based OLED AR display products can only operate at lower brightness levels, typically less than 1500 nits, which cannot meet high brightness requirements. Therefore, the use of LEDs for light-emitting displays is being further considered. As inorganic light-emitting devices, LEDs can operate at brightness levels in the millions (or even higher), meeting the needs of more extreme environments. Although micro-LEDs (i.e., micro-LEDs) for AR display products are still in the early stages of commercialization, they are expected to become a major technology for future micro-displays. AR display products typically require 5000 or higher PPI. PPI refers to the number of pixels per inch of a display panel, used to indicate resolution, meaning the spacing between adjacent pixels is at least less than 5 micrometers. Since the display size of microdisplays in AR display products is generally less than 1 inch, silicon-based micro-LEDs are a better candidate for backplanes with smaller pixel sizes and integrated peripheral circuits. Furthermore, the pixel circuits driving micro-LEDs often employ complementary metal-oxide-semiconductor (CMOS) technology.

[0089] AR display products, such as outdoor sports equipment or wearable watches, often require more stable displays and have higher requirements for resistance to external interference, as well as lower grayscale levels. This necessitates a more stable and reliable driving method. This disclosure provides a pixel circuit that combines analog and digital circuits to reliably drive light-emitting devices, such as micro-LEDs, ensuring better display stability.

[0090] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of this disclosure. For example... Figure 1 As shown, the pixel circuit includes: a first driving circuit 01, a second driving circuit 02, and a light emission control circuit 03.

[0091] The first driving circuit 01 is coupled to the first gate signal terminal GateA, the first data signal terminal DataA, the first power supply terminal VDD, and the first node P1. The first driving circuit 01 transmits a light-emitting driving signal to the first node P1 based on the first gate driving signal provided by the first gate signal terminal GateA, the first data signal provided by the first data signal terminal DataA, and the first power supply signal provided by the first power supply terminal VDD. For micro-LEDs, the light-emitting driving signal transmitted here can be a driving current.

[0092] The second driving circuit 02 is coupled to the second gate signal terminal GateB, the second data signal terminal DataB, the third data signal terminal DataC, the driving terminal V1, and the second node P2. The second driving circuit 02 is used to transmit a light emission control signal of the first potential or the second potential to the second node P2 based on the second gate driving signal provided by the second gate signal terminal GateB, the second data signal provided by the second data signal terminal DataB, the third data signal provided by the third data signal terminal DataC, and the driving signal provided by the driving terminal V1.

[0093] Optionally, the first potential can be a high potential relative to the second potential. That is, the first potential can be a high potential and the second potential can be a low potential. The light emission control signal described in the embodiments of this disclosure can have characteristics similar to digital signals, that is, it can realize the switching between high and low potentials in an instantaneous manner, and is either at a high potential or at a low potential within a certain period of time.

[0094] It should be noted that, in the first potential and the second potential, one potential can be considered an effective potential (e.g., a high potential), and the other potential can be considered an ineffective potential (e.g., a low potential). For example, in the embodiments of this disclosure, the effective potential can refer to the first potential, and the ineffective potential can refer to the second potential; that is, the effective potential can be a high potential relative to the ineffective potential. Of course, in some other embodiments, the effective potential can refer to the second potential, and the ineffective potential can refer to the first potential; that is, the effective potential can be a low potential relative to the ineffective potential.

[0095] The light-emitting control circuit 03 is coupled to the first node P1, the second node P2, and the light-emitting element L. The light-emitting control circuit 03 is used to control the on / off state of the first node P1 and the light-emitting element L based on the light-emitting control signal received from the second node P2.

[0096] Optionally, the light-emitting control circuit 03 can be coupled to the first electrode of the light-emitting element L, and the second electrode of the light-emitting element L can also be coupled to the second power supply terminal VSS. The light-emitting element L can emit light under the voltage difference between the light-emitting driving signal received at the first electrode and the second power supply signal provided by the second power supply terminal VSS. Of the first and second electrodes of the light-emitting element L, one electrode can be an anode and the other electrode can be a cathode. Figure 1 The first electrode shown is the anode, and the second electrode is the cathode. Furthermore, the light-emitting element L can be a micro-LED.

[0097] For example, when the potential of the light-emitting control signal received by the second node P2 is an effective potential, the light-emitting control circuit 03 can control the first node P1 to conduct with the light-emitting element L. At this time, the light-emitting driving signal received by the first node P1 can be further transmitted to the light-emitting element L, thereby driving the light-emitting element L to emit light. Conversely, when the potential of the light-emitting control signal received by the second node P2 is an invalid potential, the light-emitting control circuit 03 can control the first node P1 to disconnect from the light-emitting element L.

[0098] Therefore, it can be seen that the grayscale of the light-emitting element L is related to the light-emitting driving signal, and the light-emitting duration of the light-emitting element L is positively correlated with the duration of the light-emitting control signal at the effective potential. That is, the longer the duration of the light-emitting control signal at the effective potential, the longer the light-emitting duration of the light-emitting element L, and thus the brighter the light-emitting element L under the same light-emitting driving signal; conversely, the shorter the duration of the light-emitting control signal at the effective potential, the shorter the light-emitting duration of the light-emitting element L, and thus the weaker the light-emitting brightness of the light-emitting element L under the same light-emitting driving signal. Assuming that, as described in the above embodiment, the first potential (i.e., the high potential) is the effective potential and the second potential (i.e., the low potential) is the ineffective potential, that is, the effective potential is higher than the ineffective potential, then it can be seen that the light-emitting duration of the light-emitting element L is positively correlated with the duration of the light-emitting control signal at the high potential. Therefore, it can be seen that the light-emitting control signal can provide a preset gating time for the light-emitting element, that is, control the light-emitting duration of the light-emitting element.

[0099] Because the potential of the light-emitting control signal generated by the second driving circuit 02 has the abrupt change characteristics of a digital signal, the second driving circuit 02 can be understood as the digital part of the pixel circuit. That is, the term "digital circuit" here does not mean that the second driving circuit 02 is a digital circuit capable of converting analog signals to digital signals, but rather that the signal provided by the second driving circuit 02 has the instantaneous abrupt change characteristics of a digital signal. Since the first driving circuit 01 generates the light-emitting driving signal based on analog signals such as gate driving signals and data signals, and the light-emitting control circuit 03 is used to transmit the light-emitting driving signal to the light-emitting element L, it can be considered that, except for the second driving circuit 02 (i.e., the digital part), the part including the first driving circuit 01 and the light-emitting control circuit 03 can be considered as the analog part of the pixel circuit, belonging to an analog circuit. In other words, the pixel circuit described in this embodiment includes an analog part that generates the light-emitting driving signal and a digital part that generates the light-emitting control signal, which jointly control the light emission of the light-emitting element L. The light-emitting driving signal can be used to determine the light emission grayscale of the light-emitting element L; the light emission control signal can be used to determine the light emission duration of the light-emitting element L, and thus, together with the light-emitting driving signal, determine the light emission brightness of the light-emitting element L. This ensures reliable and stable driving of the light-emitting element L, thereby ensuring better display stability.

[0100] In summary, this disclosure provides a pixel circuit. The pixel circuit includes a first driving circuit, a second driving circuit, and a light-emitting control circuit. The first driving circuit transmits a light-emitting driving signal to a first node based on signals provided by each coupled signal terminal; the second driving circuit transmits a light-emitting control signal of a first potential or a second potential to a second node based on signals provided by each coupled signal terminal. The light-emitting control circuit controls the switching between the first node and the light-emitting element based on the light-emitting control signal. When the first node and the light-emitting element are connected, the light-emitting driving signal received by the first node can be further transmitted to the light-emitting element, thereby driving the light-emitting element to emit light. The first potential is higher than the second potential; that is, the first potential is high and the second potential is low. Therefore, the light-emitting control signal not only has characteristics similar to digital signals but also provides a preset gating time for the light-emitting element, i.e., controls the light-emitting duration of the light-emitting element. This ensures stable light emission from the light-emitting element, resulting in better display stability of the display panel.

[0101] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this disclosure. For example... Figure 2 As shown, the second driving circuit 02 may include a switching sub-circuit 021 and an output sub-circuit 022.

[0102] The switching sub-circuit 021 can be coupled to the second gate signal terminal GateB, the second data signal terminal DataB, the third data signal terminal DataC, and the third node P3, respectively. The switching sub-circuit 021 can be used to control the on / off state of the second data signal terminal DataB and the third node P3, and to control the on / off state of the third data signal terminal DataC and the third node P3, based on the second gate drive signal.

[0103] For example, when the potential of the second gate drive signal is the first potential, the switching sub-circuit 021 can control both the second data signal terminal DataB and the third data signal terminal DataC to be connected to the third node P3. At this time, the second data signal provided by the second data signal terminal DataB and the third data signal provided by the third data signal terminal DataC can both be transmitted to the third node P3. Conversely, when the potential of the second gate drive signal is the second potential, the switching sub-circuit 021 can control both the second data signal terminal DataB and the third data signal terminal DataC to be disconnected from the third node P3.

[0104] The output sub-circuit 022 can be coupled to the third node P3, the driving terminal V1, and the second node P2, respectively. The output sub-circuit 022 can be used to transmit a light-emitting control signal to the second node P2 based on the potential of the third node P3 and the driving signal provided by the driving terminal V1.

[0105] As an optional implementation method: such as Figure 3 Another pixel circuit is shown, in which the driving terminal V1 may include a first reset terminal ResetA. The second gate signal terminal GateB may include a first sub-gate signal terminal GateB1 and a second sub-gate signal terminal GateB2. Based on this, the switching sub-circuit 021 may include a first switching unit 0211 and a second switching unit 0212. The output sub-circuit 022 may include an adjustment unit 0221, an inverting unit 0222, and a third switching unit 0223.

[0106] The first switching unit 0211 can be coupled to the first sub-gate signal terminal GateB1, the second data signal terminal DataB, and the third node P3, respectively. The first switching unit 0211 can be used to control the switching between the second data signal terminal DataB and the third node P3 based on the first sub-gate drive signal provided by the first sub-gate signal terminal GateB1.

[0107] For example, the first switching unit 0211 can control the second data signal terminal DataB to be connected to the third node P3 when the potential of the first sub-gate drive signal provided by the first sub-gate signal terminal GateB1 is at the first potential. At this time, the second data signal provided by the second data signal terminal DataB can be transmitted to the third node P3. Conversely, the first switching unit 0211 can control the second data signal terminal DataB to be disconnected from the third node P3 when the potential of the first sub-gate drive signal provided by the first sub-gate signal terminal GateB1 is at the second potential.

[0108] The second switching unit 0212 can be coupled to the second sub-gate signal terminal GateB2, the third data signal terminal DataC, and the third node P3, respectively. The second switching unit 0212 can be used to control the on / off state of the third data signal terminal DataC and the third node P3 based on the second sub-gate drive signal provided by the second sub-gate signal terminal GateB2.

[0109] For example, the second switching unit 0212 can control the third data signal terminal DataC to be turned on and connected to the third node P3 when the potential of the second sub-gate drive signal provided by the second sub-gate signal terminal GateB2 is at the first potential. At this time, the third data signal provided by the third data signal terminal DataC can be transmitted to the third node P3. Conversely, the second switching unit 0212 can also control the third data signal terminal DataC to be disconnected from the third node P3 when the potential of the second sub-gate drive signal provided by the second sub-gate signal terminal GateB2 is at the second potential.

[0110] The adjustment unit 0221 can be coupled to the third node P3 and the fourth node P4 respectively. The adjustment unit 0221 can be used to adjust the potential of the fourth node P4 based on the potential of the third node P3.

[0111] For example, the adjustment unit 0221 can adjust the potential of the fourth node P4 based on the potential of the third node P3 through coupling.

[0112] The inverting unit 0222 can be coupled to the fourth node P4 and the second node P2 respectively. The inverting unit 0222 can be used to invert the potential of the fourth node P4 and transmit it as a light emission control signal to the second node P2.

[0113] For example, assuming the potential of the fourth node P4 is low, the inverting unit 0222 can invert it to a high potential and transmit it as a light emission control signal to the second node P2. Conversely, assuming the potential of the fourth node P4 is high, the inverting unit 0222 can invert it to a low potential and transmit it as a light emission control signal to the second node P2.

[0114] The third switching unit 0223 can be coupled to the first reset terminal ResetA, the fourth node P4, and the second node P2, respectively. The third switching unit 0223 can be used to control the on / off state of the fourth node P4 and the second node P2 based on the first reset signal provided by the first reset terminal ResetA.

[0115] For example, the third switching unit 0223 can control the fourth node P4 to conduct with the second node P2 when the potential of the first reset signal provided by the first reset terminal ResetA is the first potential. Also, the third switching unit 0223 can control the fourth node P4 to disconnect from the second node P2 when the potential of the first reset signal provided by the first reset terminal ResetA is the second potential.

[0116] As another optional implementation: such as Figure 4 Another pixel circuit is shown, in which the driving terminal V1 may include: a first power supply terminal VDD and a second power supply terminal VSS. Optionally, the second power supply terminal VSS may be ground GND, or it may be shared with the second power supply terminal VSS coupled to the cathode of the light-emitting element L. The third node P3 may include: a first sub-node P31 and a second sub-node P32. Based on this, the switching sub-circuit 021 may include: a first switching unit 0211 and a second switching unit 0212. The output sub-circuit 022 may include: two output units 0221.

[0117] The first switching unit 0211 can be coupled to the second gate signal terminal GateB, the second data signal terminal DataB, and the first sub-node P31, respectively. The first switching unit 0211 can be used to control the on / off state of the second data signal terminal DataB and the first sub-node P31 based on the second gate drive signal.

[0118] For example, the first switching unit 0211 can control the second data signal terminal DataB to be connected to the first child node P31 when the potential of the second gate drive signal is the first potential. At this time, the second data signal provided by the second data signal terminal DataB can be transmitted to the first child node P31. Conversely, the first switching unit 0211 can control the second data signal terminal DataB to be disconnected from the first child node P31 when the potential of the second gate drive signal is the second potential.

[0119] The second switching unit 0212 can be coupled to the second gate signal terminal GateB, the third data signal terminal DataC, and the second sub-node P32, respectively. The second switching unit 0212 can be used to control the on / off state of the third data signal terminal DataC and the second sub-node P32 based on the second gate drive signal.

[0120] For example, the second switching unit 0212 can control the third data signal terminal DataC to be turned on and connected to the second child node P32 when the potential of the second gate drive signal is the first potential. At this time, the third data signal provided by the third data signal terminal DataC can be transmitted to the second child node P32. Conversely, the second switching unit 0212 can control the third data signal terminal DataC to be disconnected from the second child node P32 when the potential of the second gate drive signal is the second potential.

[0121] Of the two output units 0221, one output unit 0221 can be coupled to the first sub-node P31, the first power supply terminal VDD, the second power supply terminal VSS, and the second node P2, respectively. The other output unit 0221 can be coupled to the second sub-node P32, the first power supply terminal VDD, the second power supply terminal VSS, and the second node P2, respectively. The two output units 0221 can be used to transmit a light emission control signal to the second node P2 based on the potential of the first sub-node P31, the potential of the second sub-node P32, the first power supply signal, and the second power supply signal provided by the second power supply terminal VSS.

[0122] Optional, see reference Figures 2 to 4 It can also be seen that the first driving circuit 01 described in this embodiment can be coupled to the second reset terminal ResetB and the second power supply terminal VSS respectively, and can be used to control the connection and disconnection between the second power supply terminal VSS and the first node P1 based on the second reset signal provided by the second reset terminal ResetB. Optionally, the second power supply terminal VSS here can also be ground GND.

[0123] For example, the first driving circuit 01 can control the second power supply terminal VSS to conduct with the first node P1 when the potential of the second reset signal provided by the second reset terminal ResetB is the first potential. At this time, the second power signal provided by the second power supply terminal VSS can be transmitted to the first node P1. Conversely, the first driving circuit 01 can control the second power supply terminal VSS to disconnect from the first node P1 when the potential of the second reset signal provided by the second reset terminal ResetB is the second potential.

[0124] exist Figure 3 Based on the structure shown, continue to refer to Figure 5 As can be seen from another pixel circuit shown, the first driving circuit 01 may include: a data writing sub-circuit 011, a driving sub-circuit 012, and a reset sub-circuit 013.

[0125] The data writing sub-circuit 011 can be coupled to the first gate signal terminal GateA, the first data signal terminal DataA, and the fifth node P5, respectively. The data writing sub-circuit 011 can be used to control the on / off state of the first data signal terminal DataA and the fifth node P5 based on the first gate drive signal.

[0126] For example, the data writing sub-circuit 011 can control the first data signal terminal DataA to be turned on and connected to the fifth node P5 when the potential of the first gate drive signal is at the first potential. At this time, the first data signal provided by the first data signal terminal DataA can be transmitted to the fifth node P5. Furthermore, the data writing sub-circuit 011 can control the first data signal terminal DataA to be disconnected from the fifth node P5 when the potential of the first gate drive signal is at the second potential.

[0127] The input terminal of the driver sub-circuit 012 can be coupled to the first power supply terminal VDD, the driving terminal of the driver sub-circuit 012 can be coupled to the fifth node P5, and the output terminal of the driver sub-circuit 012 can be coupled to the first node P1. The driver sub-circuit 012 can be used to transmit a light-emitting driving signal to the first node P1 based on the potential of the fifth node P5 and the first power supply signal.

[0128] The reset sub-circuit 013 can be coupled to the second reset terminal ResetB, the second power supply terminal VSS, and the first node P1, respectively. The reset sub-circuit 013 can be used to control the on / off state of the second power supply terminal VSS and the first node P1 based on the second reset signal.

[0129] For example, as described in the above embodiments, the reset sub-circuit 013 can control the second power supply terminal VSS to conduct with the first node P1 when the potential of the second reset signal is the first potential. Also, the reset sub-circuit 013 can control the second power supply terminal VSS to disconnect from the first node P1 when the potential of the second reset signal is the second potential.

[0130] Optional, continue to refer to Figure 5 As can be seen from the pixel circuit shown, the first driving circuit 01 described in this embodiment may further include: a first adjustment sub-circuit 014.

[0131] The first regulating sub-circuit 014 can be coupled to the fifth node P5 and the target terminal respectively. The first regulating sub-circuit 014 can be used to adjust the potential of the fifth node P5 based on the potential of the target terminal.

[0132] Optional, as an alternative implementation method: such as Figure 5 As shown, the target terminal may include a reference power supply terminal Vref. Accordingly, the first adjustment sub-circuit 014 can adjust the potential of the fifth node P5 based on the reference power supply signal provided by the reference power supply terminal Vref.

[0133] Optionally, as another alternative implementation: in Figure 3 Based on, and refer to Figure 6Another pixel circuit is shown, in which the target end may include a first node P1. Accordingly, the first adjustment sub-circuit 014 may adjust the potential of the fifth node P5 based on the potential of the first node P1. For example, the potential of the first node P1 may be a second power signal transmitted from the second power supply terminal VSS to the first node P1 when the reset sub-circuit 013 controls the second power supply terminal VSS to be turned on with the first node P1.

[0134] Optionally, as yet another alternative implementation: In Figure 3 and Figure 4 Based on this, refer to the following: Figure 7 and Figure 8 Another pixel circuit shown may include, at its target end, an input terminal of the driving sub-circuit 012 (i.e., the end coupled to the first power supply terminal VDD). Correspondingly, the first adjustment sub-circuit 014 may adjust the potential of the fifth node P5 (i.e., the driving terminal of the driving sub-circuit 012) based on the potential of the input terminal of the driving sub-circuit 012. Furthermore, based on this, the first driving circuit 01 described in this embodiment may further include a second adjustment sub-circuit 015 and a light emission control sub-circuit 016.

[0135] The second regulating sub-circuit 015 can be coupled to both the first power supply terminal VDD and the input terminal of the driving sub-circuit 012. The second regulating sub-circuit 015 can be used to adjust the potential of the input terminal of the driving sub-circuit 012 based on the first power supply signal.

[0136] For example, the second regulating sub-circuit 015 can adjust the potential at the input terminal of the driving sub-circuit 012 through coupling.

[0137] The light-emitting control sub-circuit 016 can be coupled to the third gate signal terminal GateC, the first power supply terminal VDD, and the input terminal of the driver sub-circuit 012, respectively. The light-emitting control sub-circuit 016 can be used to control the on / off state of the first power supply terminal VDD and the input terminal of the driver sub-circuit 012 based on the third gate drive signal provided by the third gate signal terminal GateC.

[0138] For example, the light-emitting control sub-circuit 016 can control the first power supply terminal VDD to conduct with the input terminal of the driving sub-circuit 012 when the potential of the third gate drive signal provided by the third gate signal terminal GateC is at the first potential. At this time, the first power signal provided by the first power supply terminal VDD can be transmitted to the input terminal of the driving sub-circuit 012. Furthermore, the light-emitting control sub-circuit 016 can control the first power supply terminal VDD to decouple from the input terminal of the driving sub-circuit 012 when the potential of the third gate drive signal provided by the third gate signal terminal GateC is at the second potential. That is, the input terminal of the driving sub-circuit 012 and the first power supply terminal VDD can be indirectly coupled.

[0139] Optional, in Figure 5 Based on the structure shown, Figure 9 A schematic diagram of another pixel circuit structure is shown. Figure 6 Based on the structure shown, Figure 10 A schematic diagram of another pixel circuit structure is shown. Figure 7 Based on the structure shown, Figure 11 A schematic diagram of another pixel circuit structure is shown. Figure 8 Based on the structure shown, Figure 12 The diagram below shows another type of pixel circuit.

[0140] Firstly, refer to Figures 9 to 11 It can be seen that, for Figures 5 to 7 Regarding the second driving circuit 02 shown, the first switching unit 0211 may include a first transistor T1. The second switching unit 0212 may include a second transistor T2. The adjustment unit 0221 may include a first capacitor C1. The inverting unit 0222 may include an inverter F1. The third switching unit 0223 may include a third transistor T3.

[0141] The gate of the first transistor T1 can be coupled to the first sub-gate signal terminal GateB1, the first terminal of the first transistor T1 can be coupled to the second data signal terminal DataB, and the second terminal of the first transistor T1 can be coupled to the third node P3.

[0142] The gate of the second transistor T2 can be coupled to the second sub-gate signal terminal GateB2, the first terminal of the second transistor T2 can be coupled to the third data signal terminal DataC, and the second terminal of the second transistor T2 can be coupled to the third node P3.

[0143] One end of the first capacitor C1 can be coupled to the third node P3, and the other end of the first capacitor C1 can be coupled to the fourth node P4.

[0144] The input of inverter F1 can be coupled to the fourth node P4, and the output of inverter F1 can be coupled to the second node P2.

[0145] The gate of the third transistor T3 can be coupled to the first reset terminal ResetA, the first terminal of the third transistor T3 can be coupled to the fourth node P4, and the second terminal of the third transistor T3 can be coupled to the second node P2.

[0146] Secondly, refer to Figure 12 It can be seen that, for Figure 8Regarding the second driving circuit 02 shown, the first switching unit 0211 may include a first transistor T1. The second switching unit 0212 may include a second transistor T2. Of the two output units 0221, one output unit 0221 may include a third transistor T3 and a fourth transistor T4 of different transistor types. The other output unit 0221 may include a fifth transistor T5 and a sixth transistor T6 of different transistor types.

[0147] The gate of the first transistor T1 can be coupled to the second gate signal terminal GateB, the first terminal of the first transistor T1 can be coupled to the second data signal terminal DataB, and the second terminal of the first transistor T1 can be coupled to the first child node P31.

[0148] The gate of the second transistor T2 can be coupled to the second gate signal terminal GateB, the first terminal of the second transistor T2 can be coupled to the third data signal terminal DataC, and the second terminal of the second transistor T2 can be coupled to the second child node P32.

[0149] The gates of the third transistor T3 and the fourth transistor T4 can both be coupled to the first sub-node P31 and the second node P2. The first terminal of the third transistor T3 can be coupled to the first power supply terminal VDD. The first terminal of the fourth transistor T4 can be coupled to the second power supply terminal VSS (e.g., grounded). The second terminals of the third transistor T3 and the fourth transistor T4 can both be coupled to the second sub-node P32.

[0150] The gates of the fifth transistor T5 and the sixth transistor T6 can both be coupled to the second sub-node P32 and the second node P2. The first terminal of the fifth transistor T5 can be coupled to the first power supply terminal VDD, and the first terminal of the sixth transistor T6 can be coupled to the second power supply terminal VSS (e.g., grounded). The second terminals of the fifth transistor T5 and the sixth transistor T6 can both be coupled to the first sub-node P31.

[0151] It should be noted that, for Figure 8 Regarding the structure shown, Figure 12 The two output units 0221 shown, including the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6, can refer to a latch formed by a CMOS circuit.

[0152] Thirdly, refer to Figures 9 to 12 It can be seen that, for Figures 5 to 8 Regarding the first driving circuit 01 shown, the data writing sub-circuit 011 may include: a seventh transistor T7. The driving sub-circuit 012 may include: an eighth transistor T8. The reset sub-circuit 013 may include: a ninth transistor T9. The first adjustment sub-circuit 014 may include: a second capacitor C2.

[0153] The gate of the seventh transistor T7 can be coupled to the first gate signal terminal GateA, the first terminal of the seventh transistor T7 can be coupled to the first data signal terminal DataA, and the second terminal of the seventh transistor T7 can be coupled to the fifth node P5.

[0154] The gate of the eighth transistor T8 can be coupled to the fifth node P5, the first terminal of the eighth transistor T8 can be coupled to the first power supply terminal VDD, and the second terminal of the eighth transistor T8 can be coupled to the first node P1.

[0155] The gate of the ninth transistor T9 can be coupled to the second reset terminal ResetB, the first terminal of the ninth transistor T9 can be coupled to the second power supply terminal VSS (e.g., ground terminal GND), and the second terminal of the ninth transistor T9 can be coupled to the first node P1.

[0156] One end of the second capacitor C2 can be coupled to the target end, and the other end of the second capacitor C2 can be coupled to the fifth node P5.

[0157] As an optional implementation: See reference Figure 9 It can be seen that, for Figure 5 In the pixel circuit shown, one end of the second capacitor C2 can be coupled to the target terminal "reference power supply terminal Vref". Based on this, the transistors included in the data writing sub-circuit 011 can be transmission gate switches. That is, they can be CMOS transistors including N-type transistor T7-1 and P-type transistor T7-2. Correspondingly, the reference... Figure 9 It can also be seen that the first gate signal terminal GateA may include: a first gate signal terminal GateAN coupled to the gate of the N-type transistor T7-1, and a first gate signal terminal GateAP coupled to the gate of the P-type transistor T7-2.

[0158] As an alternative implementation: See reference Figure 10 It can be seen that, for Figure 6 In the pixel circuit shown, one end of the second capacitor C2 can be coupled to the target end "first node P1".

[0159] As another optional implementation: See Figure 11 and Figure 12 It can be seen that, for Figure 7 and Figure 8 In the pixel circuit shown, one end of the second capacitor C2 can be coupled to the input terminal of the target terminal "driver sub-circuit 012 (i.e., the first terminal of the eighth transistor T8)". Furthermore, referring to... Figure 11 and Figure 12It can be seen that the second adjustment sub-circuit 015 in the first driving circuit 01 may include: a third capacitor C3. The light emission control sub-circuit 016 may include: a tenth transistor T10.

[0160] One end of the third capacitor C3 can be coupled to the first power supply terminal VDD, and the other end of the third capacitor C3 can be coupled to the input terminal of the driver sub-circuit 012 (i.e., the first terminal of the eighth transistor T8).

[0161] The gate of the tenth transistor T10 can be coupled to the third gate signal terminal GateC, the first terminal of the tenth transistor T10 can be coupled to the first power supply terminal VDD, and the second terminal of the tenth transistor T10 can be coupled to the input terminal of the driver sub-circuit 012 (i.e., the first terminal of the eighth transistor T8).

[0162] Fourth, refer to Figures 9 to 12 It can be seen that, Figures 5 to 8 The light-emitting control circuit 03 shown may include: the eleventh transistor T11.

[0163] The gate of the eleventh transistor T11 can be coupled to the second node P2, the first terminal of the eleventh transistor T11 can be coupled to the first node P1, and the second terminal of the eleventh transistor T11 can be coupled to the light-emitting element L. Optionally, the second terminal of the eleventh transistor T11 can be coupled to the anode of the light-emitting element L.

[0164] Optional, Figures 9 to 11 In the pixel circuit shown, the first transistor T1, the second transistor T2, and the third transistor T3 in the digital section can all be N-type transistors. Figure 12 In the pixel circuit shown, the first transistor T1, the second transistor T2, the fourth transistor T4 and the sixth transistor T6 in the digital part can all be N-type transistors, while the third transistor T3 and the fifth transistor T5 can both be P-type transistors. Figures 9 to 12 In the pixel circuit shown, the ninth transistor T9 and the eleventh transistor T11 in the analog section can both be N-type transistors, and the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 can all be P-type transistors. Of course, in some embodiments, the types of the above transistors are not limited to these.

[0165] In summary, this disclosure provides a pixel circuit. The pixel circuit includes a first driving circuit, a second driving circuit, and a light-emitting control circuit. The first driving circuit transmits a light-emitting driving signal to a first node based on signals provided by each coupled signal terminal; the second driving circuit transmits a light-emitting control signal of a first potential or a second potential to a second node based on signals provided by each coupled signal terminal. The light-emitting control circuit controls the switching between the first node and the light-emitting element based on the light-emitting control signal. When the first node and the light-emitting element are connected, the light-emitting driving signal received by the first node can be further transmitted to the light-emitting element, thereby driving the light-emitting element to emit light. The first potential is higher than the second potential; that is, the first potential is high and the second potential is low. Therefore, the light-emitting control signal not only has characteristics similar to digital signals but also provides a preset gating time for the light-emitting element, i.e., controls the light-emitting duration of the light-emitting element. This ensures stable light emission from the light-emitting element, resulting in better display stability of the display panel.

[0166] Figure 13 This disclosure provides a pixel circuit driving method, which can be applied to, for example... Figures 1 to 12 In any of the pixel circuits shown. For example... Figure 13 As shown, the method includes:

[0167] Step 1301, First stage: The first driving circuit transmits the light-emitting driving signal to the first node based on the first gate driving signal provided by the first gate signal terminal, the first data signal provided by the first data signal terminal, and the first power supply signal provided by the first power supply terminal.

[0168] Step 1302, Second Stage: The second driving circuit transmits a light emission control signal of the target potential to the second node based on the second gate driving signal provided by the second gate signal terminal, the second data signal provided by the second data signal terminal, the third data signal provided by the third data signal terminal, and the driving signal provided by the driving terminal. The target potential includes a first potential or a second potential, and the first potential is a higher potential relative to the second potential. Based on the light emission control signal of the target potential received by the second node, the light emission control circuit controls the first node to conduct with the light emission element so as to drive the light emission element to emit light.

[0169] Among them, the conduction time of the first node and the light-emitting element are positively correlated with the duration of the target potential.

[0170] Optional, with Figure 11 Taking the structure shown as an example, combined with Figure 14 The timing diagram shown illustrates the working principle of the pixel circuit described in the embodiments of this disclosure as follows:

[0171] First, in phase t1:

[0172] The potentials of the first gate drive signal provided by the first gate signal terminal GateA, the second sub-gate drive signal provided by the second sub-gate signal terminal GateB2 in the second gate signal terminal GateB, and the third gate drive signal provided by the third gate signal terminal GateC are all low. The potentials of the first sub-gate drive signal provided by the first sub-gate signal terminal GateB1 in the second gate signal terminal GateB, the first reset signal provided by the first reset terminal ResetA, and the second reset signal provided by the second reset terminal ResetB are all high. Correspondingly, in the analog section: the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 are all turned on. In the digital section: the first transistor T1 and the third transistor T3 are both turned on, and the second transistor T2 is turned off. Furthermore, in the analog section: the first data signal provided by the first data signal terminal DataA can be transmitted to the fifth node P5 through the turned-on seventh transistor T7, and at this time the potential of the first data signal is low, which correspondingly turns on the eighth transistor T8 in the analog section. The second power signal provided by the second power supply terminal VSS can be transmitted to the first node P1 through the turned-on ninth transistor T9. The first power signal provided by the first power supply terminal VDD can be transmitted to the first terminal of the eighth transistor T8 via the turned-on tenth transistor T10. Digital section: The second data signal provided by the second data signal terminal DataB can be transmitted to the third node P3 via the turned-on first transistor T1, and at this time the potential of the second data signal is low. Under the coupling effect of the first capacitor C1, this low-potential second data signal can be further written to the fourth node P4. The second node P2 and the fourth node P4 are turned on, and the low potential of the fourth node P4 can be further transmitted to the second node P2 via the turned-on third transistor T3. That is, at this time, both the input and output terminals of the inverter F1 can be set low, and correspondingly, the eleventh transistor T11 of the analog section is turned off.

[0173] Next, in stage t2:

[0174] The potential of the second sub-gate drive signal provided by the second sub-gate signal terminal GateB2 in the second gate signal terminal GateB is low. The potential of the first gate drive signal provided by the first gate signal terminal GateA, the potential of the first sub-gate drive signal provided by the first sub-gate signal terminal GateB1 in the second gate signal terminal GateB, the potential of the third gate drive signal provided by the third gate signal terminal GateC, the potential of the first reset signal provided by the first reset terminal ResetA, and the potential of the second reset signal provided by the second reset terminal ResetB are all high. Correspondingly, in the analog section: the ninth transistor T9 is turned on, and the seventh transistor T7 and the tenth transistor T10 are both turned off. In the digital section: the first transistor T1 and the third transistor T3 are both turned on, and the second transistor T2 is turned off. Furthermore, in the analog section: the fifth node P5 is floating. Under the coupling effect of the second capacitor C2 and the third capacitor C3, the threshold voltage Vth of the eighth transistor T8 can be read and written to the fifth node P5 (i.e., the gate of the eighth transistor T8). The second power signal provided by the second power supply terminal VSS can continue to be transmitted to the first node P1 via the activated ninth transistor T9. Digital section: The second data signal provided by the second data signal terminal DataB can continue to be transmitted to the third node P3 via the activated first transistor T1. Under the coupling effect of the first capacitor C1, the potential of the fourth node P4 can change with the potential of the third node P3. The second node P2 and the fourth node P4 are connected, and the signal written to the fourth node P4 can be further transmitted to the second node P2 via the activated third transistor T3.

[0175] Next, in stage t3:

[0176] The potentials of the first gate drive signal provided by the first gate signal terminal GateA, the first sub-gate drive signal provided by the first sub-gate signal terminal GateB1 in the second gate signal terminal GateB, and the first reset signal provided by the first reset terminal ResetA are all low. The potentials of the second sub-gate drive signal provided by the second sub-gate signal terminal GateB2 in the second gate signal terminal GateB, the third gate drive signal provided by the third gate signal terminal GateC, and the second reset signal provided by the second reset terminal ResetB are all high. Correspondingly, in the analog section: the seventh transistor T7 and the ninth transistor T9 are both turned on, and the tenth transistor T10 is turned off. In the digital section: the second transistor T2 is turned on, and the first transistor T1 and the third transistor T3 are both turned off. Furthermore, in the analog section: the first data signal provided by the first data signal terminal DataA can be transmitted to the fifth node P5 through the turned-on seventh transistor T7 to realize the writing of the data signal. The second power signal provided by the second power supply terminal VSS can continue to be transmitted to the first node P1 through the turned-on ninth transistor T9. Digital Section: The third data signal provided by the third data signal terminal DataC can be transmitted to the third node P3 via the activated second transistor T2. Under the coupling effect of the first capacitor C1, the potential of the fourth node P4 can change with the potential of the third node P3. The second node P2 and the fourth node P4 can be disconnected.

[0177] Finally, in stage t4:

[0178] The potentials of the third gate drive signal provided by the third gate signal terminal GateC, the first sub-gate drive signal provided by the first sub-gate signal terminal GateB1 in the second gate signal terminal GateB, the second sub-gate drive signal provided by the second sub-gate signal terminal GateB2 in the second gate signal terminal GateB, the first reset signal provided by the first reset terminal ResetA, and the second reset signal provided by the second reset terminal ResetB are all low potentials, while the potential of the first gate drive signal provided by the first gate signal terminal GateA is high potential. Correspondingly, in the analog section: the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 are all turned off. In the digital section: the second transistor T2 is turned on, and the first transistor T1 and the third transistor T3 are both turned off. Furthermore, under the storage effect of the second capacitor C2, the fifth node P5 can maintain the potential provided in the aforementioned stage, and the eighth transistor T8 is turned on. Furthermore, in the analog section: the first power signal provided by the first power supply terminal VDD can be transmitted to the first terminal of the eighth transistor T8 via the turned-on tenth transistor T10. The eighth transistor T8 can generate a light-emitting drive signal based on the signal at its gate (i.e., the fifth node P5) and the first power supply signal received at the first terminal, and transmit it to the first node P1. Digital section: The third data signal provided by the third data signal terminal DataC can continue to be transmitted to the third node P3 via the turned-on second transistor T2. Under the coupling effect of the first capacitor C1, the potential of the fourth node P4 can change with the potential of the third node P3. The second node P2 and the fourth node P4 can be disconnected.

[0179] Specifically, when the potential of the second node P2 is high, the eleventh transistor T11 in the analog section can be turned on, allowing the light-emitting drive signal transmitted to the first node P1 to be further transmitted to the light-emitting element L via the turned-on eleventh transistor T11, thereby driving the light-emitting element L to emit light. When the potential of the second node P2 is low, the eleventh transistor T11 in the analog section can be turned off, preventing the light-emitting drive signal transmitted to the first node P1 from being further transmitted to the light-emitting element L, thus the light-emitting element L can not emit light. Therefore, it can be seen that the duration for which the potential of the second node P2 (i.e., the potential of the light-emitting control signal) remains high determines the duration for which the light-emitting element L emits light, and the two are positively correlated.

[0180] Based on the above working principles, we will continue to combine Figure 15 The principle of digital control of the potential of the second node P2 is explained:

[0181] Since in stage t2, the first transistor T1 and the third transistor T3 are both turned on and the second transistor T2 is turned off, the second data signal provided by the second data signal terminal DataB can be transmitted to the third node P3, and the second node P2 and the fourth node P4 can be made conductive. The voltage at the input terminal (i.e., the fourth node P4) of the inverter F1 and the potential at the output terminal (i.e., the second node P2) are equal. Assume that the potential of the fourth node P4 is Vp4 = Vc (i.e., the potential of the second node P2 is Vp2 = Vc), and the potential of the second data signal transmitted to the third node P3 is VdataB, that is, the potential of the third node P3 is Vp3 = VdataB. Then it can be known that in this first cycle, the voltage difference across the first capacitor C1 can be: Vp3 - Vp4 = VdataB - Vc.

[0182] In stage t4, since the second transistor T2 is turned on and the first transistor T1 and the third transistor T3 are both turned off, the third data signal provided by the third data signal terminal DataC can be transmitted to the third node P3, and the second node P2 and the fourth node P4 can be decoupled. Under the coupling effect of the first capacitor C1, the potential of the fourth node P4 changes with the potential of the third node P3. Assume that the potential of the third data signal transmitted to the third node P3 is VdataC, that is, the potential of the third node P3 is Vp3 = VdataC. Then it can be known that in this second cycle, the potential Vp4 of the fourth node P4 can satisfy: Vp4 = VdataC - (VdataB - Vc). Thus, it can be seen that on the premise that the amplitude of VdataC changes with time, the potential of the fourth node P4 can also change with time at the same rate.

[0183] Among them, refer to Figure 15 It can be seen that if VdataC < VdataB, then Vp4 < Vc (i.e., Vp2). At this time, in the above stage t4, the output terminal of the inverter F1 can output a high-potential light-emitting control signal, making the eleventh transistor T11 turn on. Then, the light-emitting drive signal transmitted to the first node P1 is transmitted to the light-emitting element L through the turned-on eleventh transistor T11, and the light-emitting element L can be driven by a constant current to emit light. If VdataC > VdataB, then Vp4 > Vc (i.e., Vp2). At this time, in the above stage t4, the output terminal of the inverter F1 can output a low-potential light-emitting control signal, making the eleventh transistor T11 turn off. Then, the light-emitting drive signal transmitted to the first node P1 cannot be transmitted to the light-emitting element L, and the light-emitting element L can be in a non-light-emitting state, that is, in a dark state.

[0184] In some embodiments, given a fixed VdataC waveform, the longer VdataB is greater than VdataC, the longer the duration of the high potential of the light-emitting control signal output from the inverter F1, and consequently, the longer the light-emitting duration Lt of the light-emitting element L; conversely, the shorter the duration of VdataB being greater than VdataC, the shorter the duration of the high potential of the light-emitting control signal output from the inverter F1, and consequently, the shorter the light-emitting duration Lt of the light-emitting element L. (Reference) Figure 15 It can be seen that, in case 1, the amplitude of VdataB is larger than that in case 2. Therefore, in stage t4, VdataB is greater than VdataC for a longer period of time, that is, the time when the P1 potential is high is longer, and Lt02>Lt01.

[0185] As described in the above embodiments, this disclosure provides a pixel circuit comprising a digital section and an analog section. The analog section generates a driving current (i.e., a light-emitting driving signal), while the digital section provides a gating time (i.e., a light-emitting control signal) to control the time and duration of the driving current transmission to the light-emitting element L, thereby achieving different light-emitting brightness and enabling the display panel to display different grayscale levels. This pixel circuit is advantageous for use in scenarios with low grayscale requirements.

[0186] In summary, this disclosure provides a driving method for a pixel circuit. In this method, a first driving circuit transmits a light-emitting driving signal to a first node based on signals provided by each coupled signal terminal; a second driving circuit transmits a light-emitting control signal of a first potential or a second potential to a second node based on signals provided by each coupled signal terminal. The light-emitting control circuit controls the switching between the first node and the light-emitting element based on the light-emitting control signal. When the first node and the light-emitting element are connected, the light-emitting driving signal received by the first node can be further transmitted to the light-emitting element, thereby driving the light-emitting element to emit light. The first potential is higher than the second potential; that is, the first potential is high and the second potential is low. Therefore, the light-emitting control signal not only has characteristics similar to digital signals but also provides a preset gating time for the light-emitting element, i.e., controls the light-emitting duration of the light-emitting element. This ensures stable light emission from the light-emitting element, resulting in better display stability of the display panel.

[0187] Figure 16 This is a schematic diagram of the structure of a display panel provided in an embodiment of this disclosure. Figure 16 As shown, the display panel includes a substrate 100 and a plurality of pixels 000 located on one side of the substrate 100. Optionally, the substrate 100 can be made of any material such as silicon, quartz, glass, plastic or polyimide, and can be used in head-mounted or handheld display products.

[0188] Pixel 000 may include: a light-emitting element L, and such as Figures 1 to 12 Any of the pixel circuits shown is 00, and the pixel circuit 00 is coupled to the light-emitting element L and is used to drive the light-emitting element L to emit light.

[0189] Figure 17 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Figure 17 As shown, the display device includes: a power supply component J1, and as shown in the figure. Figure 16 The display panel M1 shown is shown.

[0190] The power supply component J1 is coupled to the display panel M1 and is used to supply power to the display panel M1.

[0191] Optionally, the display device described in the embodiments of this disclosure can be any product or component with display function, such as a mobile phone, tablet computer, television, and monitor.

[0192] It should be noted that the terminology used in the embodiments of this disclosure is for the purpose of explaining the embodiments of this disclosure and is not intended to limit this disclosure. Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains.

[0193] For example, in embodiments of this disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0194] Similarly, words like "one" or "one" do not indicate a quantity limit, but rather that there is at least one.

[0195] The word “includes” or similar terms means that the elements or objects preceding “includes” or “include” cover the elements or objects listed after “includes” or “include” or their equivalents, and do not exclude other elements or objects.

[0196] "Up," "down," "left," or "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0197] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A pixel circuit, characterized by comprising: The pixel circuit comprises: a first driving circuit coupled with a first gate signal terminal, a first data signal terminal, a first power supply terminal and a first node respectively, and configured to transmit a light-emitting driving signal to the first node based on a first gate driving signal provided by the first gate signal terminal, a first data signal provided by the first data signal terminal and a first power supply signal provided by the first power supply terminal; a second driving circuit coupled with a second gate signal terminal, a second data signal terminal, a third data signal terminal, a driving terminal and a second node respectively, and configured to transmit a light-emitting control signal of a first potential or a second potential to the second node based on a second gate driving signal provided by the second gate signal terminal, a second data signal provided by the second data signal terminal, a third data signal provided by the third data signal terminal and a driving signal provided by the driving terminal, wherein the first potential is a high potential relative to the second potential; a light-emitting control circuit coupled with the first node, the second node and a light-emitting element respectively, and configured to control the on-off of the first node and the light-emitting element based on the light-emitting control signal received by the second node; the second driving circuit comprises: a switch sub-circuit coupled with the second gate signal terminal, the second data signal terminal, the third data signal terminal and a third node respectively, and configured to control the on-off of the second data signal terminal and the third node and the on-off of the third data signal terminal and the third node based on the second gate driving signal; an output sub-circuit coupled with the third node, the driving terminal and the second node respectively, and configured to transmit a light-emitting control signal to the second node based on the potential of the third node and the driving signal; and the driving terminal comprises a first reset terminal; the second gate signal terminal comprises a first sub-gate signal terminal and a second sub-gate signal terminal; the switch sub-circuit comprises: a first switch unit coupled with the first sub-gate signal terminal, the second data signal terminal and the third node respectively, and configured to control the on-off of the second data signal terminal and the third node based on a first sub-gate driving signal provided by the first sub-gate signal terminal; a second switch unit coupled with the second sub-gate signal terminal, the third data signal terminal and the third node respectively, and configured to control the on-off of the third data signal terminal and the third node based on a second sub-gate driving signal provided by the second sub-gate signal terminal; the output sub-circuit comprises: an adjusting unit coupled with the third node and a fourth node respectively, and configured to adjust the potential of the fourth node based on the potential of the third node; an inverting unit coupled with the fourth node and the second node respectively, and configured to transmit the light-emitting control signal to the second node after inverting the potential of the fourth node; a third switch unit coupled with the first reset terminal, the fourth node and the second node respectively, and configured to control the on-off of the fourth node and the second node based on a first reset signal provided by the first reset terminal.

2. The pixel circuit of claim 1, wherein, The first switch unit comprises a first transistor; the second switch unit comprises a second transistor; the adjusting unit comprises a first capacitor; the inverting unit comprises an inverter; and the third switch unit comprises a third transistor. The gate of the first transistor is coupled with the first sub-gate signal terminal, the first pole of the first transistor is coupled with the second data signal terminal, and the second pole of the first transistor is coupled with the third node. The gate of the second transistor is coupled with the second sub-gate signal terminal, the first pole of the second transistor is coupled with the third data signal terminal, and the second pole of the second transistor is coupled with the third node. One end of the first capacitor is coupled with the third node, and the other end of the first capacitor is coupled with the fourth node. The input end of the inverter is coupled with the fourth node, and the output end of the inverter is coupled with the second node. The gate of the third transistor is coupled with the first reset terminal, the first pole of the third transistor is coupled with the fourth node, and the second pole of the third transistor is coupled with the second node.

3. The pixel circuit according to claim 1 or 2, characterized in that, The first driving circuit is further coupled with a second reset terminal and a second power terminal respectively, and is configured to control the second power terminal and the first node based on a second reset signal provided by the second reset terminal. The first driving circuit comprises: a data writing sub-circuit, which is coupled with the first gate signal terminal, the first data signal terminal and a fifth node respectively, and is configured to control the first data signal terminal and the fifth node based on the first gate driving signal; a driving sub-circuit, which is coupled with the first power terminal at the input end, is coupled with the fifth node at the driving end, and is coupled with the first node at the output end, and is configured to transmit a light-emitting driving signal to the first node based on the potential of the fifth node and the first power signal; and a reset sub-circuit, which is coupled with the second reset terminal, the second power terminal and the first node respectively, and is configured to control the second power terminal and the first node based on the second reset signal.

4. The pixel circuit of claim 3, wherein, The data writing sub-circuit comprises a seventh transistor; the driving sub-circuit comprises an eighth transistor; and the reset sub-circuit comprises a ninth transistor. The gate of the seventh transistor is coupled with the first gate signal terminal, the first pole of the seventh transistor is coupled with the first data signal terminal, and the second pole of the seventh transistor is coupled with the fifth node. The gate of the eighth transistor is coupled with the fifth node, the first pole of the eighth transistor is coupled with the first power terminal, and the second pole of the eighth transistor is coupled with the first node. The gate of the ninth transistor is coupled with the second reset terminal, the first pole of the ninth transistor is coupled with the second power terminal, and the second pole of the ninth transistor is coupled with the first node.

5. The pixel circuit of claim 3, wherein, The first driving circuit further comprises: a first adjusting sub-circuit, which is coupled with the fifth node and a target terminal respectively, and is configured to adjust the potential of the fifth node based on the potential of the target terminal. The target end comprises a reference power supply end, the first node or an input end of the driving sub-circuit, and if the target end is the input end of the driving sub-circuit, the first driving circuit further comprises: a second adjusting sub-circuit coupled with the first power supply end and the input end of the driving sub-circuit respectively, and configured to adjust the potential of the input end of the driving sub-circuit based on the first power supply signal; a light-emitting control sub-circuit coupled with the third gate signal end, the first power supply end and the input end of the driving sub-circuit respectively, and configured to control the on-off of the first power supply end and the input end of the driving sub-circuit based on a third gate drive signal provided by the third gate signal end.

6. The pixel circuit of claim 5, wherein, The first adjusting sub-circuit comprises a second capacitor; the second adjusting sub-circuit comprises a third capacitor; and the light-emitting control sub-circuit comprises a tenth transistor. One end of the second capacitor is coupled with the target end, and the other end of the second capacitor is coupled with the fifth node. One end of the third capacitor is coupled with the first power supply end, and the other end of the third capacitor is coupled with the input end of the driving sub-circuit. The gate of the tenth transistor is coupled with the third gate signal end, the first pole of the tenth transistor is coupled with the first power supply end, and the second pole of the tenth transistor is coupled with the input end of the driving sub-circuit.

7. The pixel circuit of claim 5, wherein, The target end is the reference power supply end, and the transistor included in the data writing sub-circuit is a transmission gate switch tube.

8. The pixel circuit according to claim 1 or 2, characterized in that, The light-emitting control circuit comprises an eleventh transistor. The gate of the eleventh transistor is coupled with the second node, the first pole of the eleventh transistor is coupled with the first node, and the second pole of the eleventh transistor is coupled with the light-emitting element.

9. A driving method of a pixel circuit, characterized by, The method is applied to the pixel circuit as claimed in any one of claims 1 to 8; and the method comprises: In a first stage, the first driving circuit transmits a light-emitting drive signal to the first node based on a first gate drive signal provided by the first gate signal end, a first data signal provided by the first data signal end and a first power supply signal provided by the first power supply end; In a second stage, the second driving circuit transmits a light-emitting control signal of a target potential to the second node based on a second gate drive signal provided by the second gate signal end, a second data signal provided by the second data signal end, a third data signal provided by the third data signal end and a drive signal provided by the drive end, the target potential comprising a first potential or a second potential, and the first potential being a high potential relative to the second potential, and the light-emitting control circuit controls the first node and the light-emitting element to be conductive based on the light-emitting control signal of the target potential received by the second node, so as to drive the light-emitting element to emit light; wherein the duration of the conduction of the first node and the light-emitting element is positively correlated with the duration of the target potential.

10. A display panel, characterized by, The display panel comprises a substrate and a plurality of pixels located on one side of the substrate; The pixel comprises a light-emitting element and a pixel circuit as claimed in any one of claims 1 to 8, and the pixel circuit is coupled with the light-emitting element and configured to drive the light-emitting element to emit light.

11. A display device comprising: The display device comprises a power supply component and the display panel as claimed in claim 10. The power supply component is coupled with the display panel and used for supplying power for the display panel.

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