A manufacturing method of a field effect transistor and a field effect transistor

Abstract

The present application provides a method for manufacturing a field effect transistor and a field effect transistor. When forming a first conductivity type semiconductor source region by ion implantation, the manufacturing process and cost of the field effect transistor are not increased, so that the doping concentrations of the first conductivity type semiconductor source regions in different regions are different. Since the channel density of the field effect transistor is reduced, the base voltage drop of the parasitic triode is effectively reduced, the risk of the parasitic triode being turned on is reduced, the thermal instability resistance and the safe operating area of the field effect transistor are enhanced, and compared with the device having a virtual cell, its on-resistance is significantly reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a method for manufacturing a field effect transistor and a field effect transistor. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is widely used in various power systems due to its advantages such as fast switching speed, low power consumption, easy driving of the gate, small driving power, high input impedance, and fast frequency response. In various high electrical stress systems, on the one hand, it is required that the power MOSFET has lower conduction loss, and on the other hand, it is required that the device can work under high voltage and large current for a longer time, that is, the device should have high reliability and a large Safe Operating Area (SOA). Based on the manifestation of the thermal instability of MOSFET, the larger the channel density, the easier the parasitic triode in the body is to turn on, resulting in current concentration, causing the internal temperature of the device to rise, and reducing the Safe Operating Area (SOA). In related technologies, a structure of virtual cells is used to reduce the channel density, but this structure greatly increases the on-resistance and causes waste of chip area.

[0003] Therefore, how to provide a manufacturing method that neither increases the on-resistance nor increases the cost, while expanding the safe operating area of the field effect transistor, is an urgent problem to be solved at present. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the present invention provides a method for manufacturing a field effect transistor and a field effect transistor to solve at least one of the above technical problems.

[0005] To achieve the above and other related purposes, the technical solutions provided in this application are as follows.

[0006] In a first aspect, this application provides a method for manufacturing a field effect transistor, including:

[0007] Providing a substrate, the substrate includes a front surface and a back surface disposed opposite to each other, and generating a first-conductive-type semiconductor drift region on the front surface of the substrate;

[0008] Forming a first trench in the first-conductive-type semiconductor drift region, and forming a first oxide layer in the first trench;

[0009] Performing polysilicon deposition on the first oxide layer to form a shield gate polysilicon electrode;

[0010] Thermal oxidation growth or deposition is carried out on the shield gate polysilicon electrode to form a second oxide layer. Among them, the first oxide layer and the second oxide layer wrap the shield gate polysilicon electrode;

[0011] The first-conductivity-type semiconductor drift region located on the second oxide layer is first subjected to thermal oxidation growth and then etched to form an arc-shaped structure. Thermal oxidation growth is carried out on the arc-shaped structure to form a third oxide layer. Polysilicon deposition is carried out on the second oxide layer to form a gate polysilicon electrode;

[0012] Partitioned ion implantation and junction pushing are carried out on the side of the second-conductivity-type semiconductor region away from the first-conductivity-type semiconductor drift region to form two first-conductivity-type semiconductor source regions with slopes;

[0013] Passivation is carried out on the gate polysilicon electrode, the two first-conductivity-type semiconductor source regions and the third oxide layer to form a gate-source interlayer dielectric;

[0014] Lithography is carried out on the side of the gate-source interlayer dielectric away from the two first-conductivity-type semiconductor source regions to form a second trench. Ion implantation is carried out on the second trench and partially extends into the second-conductivity-type semiconductor region to form a second-conductivity-type semiconductor ohmic contact region;

[0015] Metal deposition is carried out on the gate-source interlayer dielectric and the second-conductivity-type semiconductor ohmic contact region to form a source metal layer;

[0016] Metal deposition is carried out on the back surface of the substrate to form a drain metal layer;

[0017] Among them, the doping concentration of the first of the first-conductivity-type semiconductor source regions is greater than that of the second of the first-conductivity-type semiconductor source regions. The first oxide layer, the second oxide layer and the third oxide layer constitute an insulating dielectric layer.

[0018] In an embodiment of the present invention, forming a first trench in the first-conductivity-type semiconductor drift region and forming a first oxide layer in the first trench includes: masking on the first-conductivity-type semiconductor drift region to generate a mask layer; coating, exposing and developing the mask layer to determine the position of the first trench; etching the mask layer and the first-conductivity-type semiconductor drift region to obtain the first trench; and carrying out thermal oxidation growth on the first trench to form the first oxide layer.

[0019] In an embodiment of the present invention, partitioned ion implantation and junction pushing are performed on the side of the second-conductivity-type semiconductor region away from the first-conductivity-type semiconductor drift region to form two first-conductivity-type semiconductor source regions with a slope, including: opening a window on the second-conductivity-type semiconductor region based on a mask template to obtain an ion implantation window; performing ion implantation on the second-conductivity-type semiconductor region based on the ion implantation window to form an initial-conductivity-type semiconductor source region; and performing junction pushing on the initial-conductivity-type semiconductor source region to form two first-conductivity-type semiconductor source regions.

[0020] In an embodiment of the present invention, a single window is provided on the mask template; or multiple windows are provided on the mask template, and the sizes of the multiple windows increase or decrease from left to right.

[0021] In a second aspect, the present application further provides a field effect transistor, which is manufactured according to the manufacturing method of the field effect transistor described in the first aspect, including:

[0022] A drain metal layer, and a substrate and a first-conductivity-type semiconductor drift region stacked on the drain metal layer in sequence;

[0023] A first trench is provided in the first-conductivity-type semiconductor drift region;

[0024] A gate polysilicon electrode, a shielding gate polysilicon electrode, and an insulating dielectric layer are provided in the first trench. The insulating dielectric layer wraps part of the gate polysilicon electrode and the shielding gate polysilicon electrode. Among them, the gate polysilicon electrode is provided on the shielding gate polysilicon electrode and is isolated by the insulating dielectric layer;

[0025] A second-conductivity-type semiconductor region is provided on the side of the first-conductivity-type semiconductor drift region away from the substrate;

[0026] Two first-conductivity-type semiconductor source regions and a second-conductivity-type semiconductor ohmic contact region are provided on the side of the second-conductivity-type semiconductor region away from the first-conductivity-type semiconductor drift region. Among them, a part of the second-conductivity-type semiconductor ohmic contact region is located between the two first-conductivity-type semiconductor source regions, and a part is located in the second-conductivity-type semiconductor region;

[0027] A gate-source interlayer dielectric is provided on the two first-conductivity-type semiconductor source regions, the gate polysilicon electrode, and part of the insulating dielectric layer;

[0028] A source metal layer is provided on the second-conductivity-type semiconductor ohmic contact region and the gate-source interlayer dielectric.

[0029] In an embodiment of the present invention, the shield gate polysilicon electrode is isolated from the first-conductivity-type semiconductor drift region in the horizontal direction through the insulating dielectric layer; the gate polysilicon electrode is isolated from a part of the first-conductivity-type semiconductor drift region, a part of the second-conductivity-type semiconductor region, and two first-conductivity-type semiconductor source regions through the insulating dielectric layer, where the horizontal direction is parallel to the direction of the drain metal layer.

[0030] In an embodiment of the present invention, on the second-conductivity-type semiconductor ohmic contact region, the source metal layer is, in the horizontal direction, partly between two first-conductivity-type semiconductor source regions and partly between the gate-source dielectric layers.

[0031] In an embodiment of the present invention, the contact surfaces between two first-conductivity-type semiconductor source regions and the second-conductivity-type semiconductor region have slopes, and the doping concentration of the first first-conductivity-type semiconductor source region is greater than that of the second first-conductivity-type semiconductor source region.

[0032] In a third aspect, the present application further provides a manufacturing method of a field effect transistor, including:

[0033] Providing a substrate, where the substrate includes a front surface and a back surface that are oppositely arranged, and generating a first-conductivity-type semiconductor drift region on the front surface of the substrate;

[0034] Forming a third trench with an arc-shaped structure in the first-conductivity-type semiconductor drift region, and forming an insulating dielectric layer in the third trench;

[0035] Performing polysilicon deposition on the insulating dielectric layer to form a gate polysilicon electrode;

[0036] Performing ion implantation and annealing on the side of the first-conductivity-type semiconductor drift region away from the substrate to form a second-conductivity-type semiconductor region;

[0037] Performing partitioned ion implantation and annealing on the side of the second-conductivity-type semiconductor region away from the first-conductivity-type semiconductor drift region to form two first-conductivity-type semiconductor source regions with slopes;

[0038] Performing passivation on the gate polysilicon electrode, two first-conductivity-type semiconductor source regions, and a part of the insulating dielectric layer to form a gate-source dielectric layer;

[0039] Performing photolithography on the side of the gate-source dielectric layer away from two first-conductivity-type semiconductor source regions to form a second trench, performing ion implantation on the second trench, and partly extending into the second-conductivity-type semiconductor region to form a second-conductivity-type semiconductor ohmic contact region;

[0040] Deposit metal on the dielectric layer between the gate and source and the ohmic contact region of the second-conductivity-type semiconductor to form a source metal layer;

[0041] Deposit metal on the back surface of the substrate to form a drain metal layer;

[0042] Wherein, the doping concentration of the first first-conductivity-type semiconductor source region is greater than that of the second first-conductivity-type semiconductor source region.

[0043] Fourthly, the present application further provides a field effect transistor, which is manufactured according to the manufacturing method of the field effect transistor described in the third aspect, and includes:

[0044] A drain metal layer, and a substrate and a first-conductivity-type semiconductor drift region stacked on the drain metal layer in sequence;

[0045] A third trench is provided in the first-conductivity-type semiconductor drift region, and an arc-shaped structure is formed between the bottom and the side wall of the third trench;

[0046] A gate polysilicon electrode and an insulating dielectric layer are provided in the third trench, and the insulating dielectric layer wraps part of the gate polysilicon electrode;

[0047] A second-conductivity-type semiconductor region is provided on a side of the first-conductivity-type semiconductor drift region away from the substrate;

[0048] Two first-conductivity-type semiconductor source regions and a second-conductivity-type semiconductor ohmic contact region are provided on a side of the second-conductivity-type semiconductor region away from the first-conductivity-type semiconductor drift region. Among them, a part of the second-conductivity-type semiconductor ohmic contact region is between the two first-conductivity-type semiconductor source regions, and a part is located in the second-conductivity-type semiconductor region;

[0049] A gate-source interlayer dielectric is provided on the two first-conductivity-type semiconductor source regions, the gate polysilicon electrode and a part of the insulating dielectric layer;

[0050] A source metal layer is provided on the second-conductivity-type semiconductor ohmic contact region and the gate-source interlayer dielectric.

[0051] The present application provides a manufacturing method of a field effect transistor and a field effect transistor. When forming a first-conductivity-type semiconductor source region and a first-conductivity-type semiconductor source region by ion implantation, the manufacturing process and cost of the field effect transistor are not increased, such that the doping concentrations of the first-conductivity-type semiconductor source region and the first-conductivity-type semiconductor source region are different. Due to the reduction of the channel density of the field effect transistor, the base voltage drop of the parasitic triode is effectively reduced, the risk of the parasitic triode turning on is reduced, the thermal instability resistance and the safe operating area of the field effect transistor are enhanced, and compared with the device with a dummy cell, its on-resistance is significantly reduced.

[0052] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The accompanying drawings are incorporated herein and constitute a part of this specification, showing embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts. In the drawings:

[0054] Figure 1 is a flowchart of a manufacturing method of a field effect transistor shown in an exemplary embodiment of the present invention;

[0055] Figures 2 to 14 is a schematic cross-sectional view of a manufacturing method of a field effect transistor shown in an exemplary embodiment of the present invention;

[0056] Figure 15 is a flowchart of a manufacturing method of a field effect transistor shown in another exemplary embodiment of the present invention;

[0057] Figure 16 is a schematic cross-sectional view of a field effect transistor shown in another exemplary embodiment of the present invention.

[0058] Description of the reference numerals: 1 - drain metal layer, 2 - substrate, 3 - first-conductivity-type semiconductor drift region, 4 - second-conductivity-type semiconductor region, 5 - second-conductivity-type semiconductor ohmic contact region, 6a - first first-conductivity-type semiconductor source region, 6b - second first-conductivity-type semiconductor source region, 6z - initial-conductivity-type semiconductor source region, 7 - gate polysilicon electrode, 8 - shield gate polysilicon electrode, 9 - insulating dielectric layer, 9a - first oxide layer, 9b - second oxide layer, 9c - third oxide layer, 10 - gate-source interlayer dielectric, 11 - source metal layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0059] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for explaining the present invention, rather than for limiting the protection scope of the present invention.

[0060] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0061] In the following description, a large number of details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0062] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is widely used in various power systems because of its advantages such as fast switching speed, low power consumption, easy gate driving, small driving power, high input impedance, and fast frequency response. In various high electrical stress systems, on the one hand, it is required that the power MOSFET has lower conduction loss, and on the other hand, it is required that the device can work under high voltage and large current for a longer time, that is, the device should have high reliability and a large Safe Operating Area (SOA). According to the thermal instability of MOSFET, the larger the channel density, the easier the parasitic bipolar transistor in the body is to turn on, which leads to current concentration, causing the internal temperature of the device to rise and the Safe Operating Area (SOA) to shrink. In the related art, a virtual cell structure is used to reduce the channel density, but this structure greatly increases the on-resistance and causes waste of chip area.

[0063] In the first aspect, as Figure 1 shown, the present application provides a manufacturing method of a field-effect transistor, and the manufacturing method at least includes steps S110 to S211,

[0064] S110. Provide a substrate 2, where the substrate 2 includes a front surface and a back surface which are oppositely arranged, and generate a first-conductivity-type semiconductor drift region 3 on the front surface of the substrate 2;

[0065] S120. Form a first trench in the first-conductivity-type semiconductor drift region 3, and form a first oxide layer 9a in the first trench;

[0066] S130. Deposit polysilicon on the first oxide layer 9a to form a shield gate polysilicon electrode 8;

[0067] S140. Perform thermal oxidation growth or deposition on the shield gate polysilicon electrode 8 to form a second oxide layer 9b, wherein the first oxide layer 9a and the second oxide layer 9b wrap the shield gate polysilicon electrode 8;

[0068] S150. First perform thermal oxidation growth on the first-conductivity-type semiconductor drift region 3 located on the second oxide layer 9b and then etch it to form an arc-shaped structure, perform thermal oxidation growth on the arc-shaped structure to form a third oxide layer 9c, deposit polysilicon on the second oxide layer 9b to form a gate polysilicon electrode 7;

[0069] S160. Perform ion implantation and drive-in on the side of the first-conductivity-type semiconductor drift region 3 away from the substrate 2 to form a second-conductivity-type semiconductor region 4;

[0070] S170. Perform partitioned ion implantation and drive-in on the side of the second-conductivity-type semiconductor region 4 away from the first-conductivity-type semiconductor drift region 3 to form two first-conductivity-type semiconductor source regions (6a, 6b) with a slope;

[0071] S180. Perform passivation on the gate polysilicon electrode 7, two first-conductivity-type semiconductor source regions (6a, 6b) and a part of the insulating dielectric layer 9 to form a gate-source interlayer dielectric 10;

[0072] S190. Perform photolithography on the side of the gate-source interlayer dielectric 10 away from the two first-conductivity-type semiconductor source regions (6a, 6b) to form a second trench, perform ion implantation on the second trench, and partially extend it into the second-conductivity-type semiconductor region 4 to form a second-conductivity-type semiconductor ohmic contact region 5;

[0073] S210. Deposit metal on the gate-source interlayer dielectric 10 and the second-conductivity-type semiconductor ohmic contact region 5 to form a source metal layer 11;

[0074] S211. Deposit metal on the back surface of the substrate 2 to form a drain metal layer 1;

[0075] Among them, the doping concentration of the first semiconductor source region 6a of the first conductivity type is greater than that of the second semiconductor source region 6b of the first conductivity type, and the first oxide layer 9a, the second oxide layer 9b, and the third oxide layer 9c form an insulating dielectric layer 9.

[0076] It should be noted that the substrate 2 is a heavily doped semiconductor of the first conductivity type, and the second conductivity type semiconductor ohmic contact region 5 is heavily doped.

[0077] Specifically, as Figure 2 shown, in step S110, a substrate 2 is provided, and a single crystal material is grown on the front surface of the substrate 2 to form a semiconductor drift region 3 of the first conductivity type.

[0078] In detail, in step S120, a first trench is formed in the semiconductor drift region 3 of the first conductivity type, and a first oxide layer 9a is formed in the first trench, including: masking on the semiconductor drift region 3 of the first conductivity type to generate a mask layer; coating, exposing, and developing the mask layer to determine the position of the first trench 9a; etching the mask layer and the semiconductor drift region 3 of the first conductivity type to obtain the first trench, and thermally oxidizing or depositing the first trench to form the first oxide layer 9a. Specifically, as Figure 3 shown, a mask layer is deposited on the semiconductor drift region 3 of the first conductivity type, a photoresist is applied on the mask layer, and then exposed and developed to perform pattern display to determine the position of the first trench. The mask layer and the semiconductor drift region 3 of the first conductivity type are etched to form the first trench. Since semiconductor devices are manufactured by operating on the entire substrate, a substrate includes a plurality of basic units of semiconductor devices. The first trench is located in the semiconductor drift region 3 of the first conductivity type, and then the first trench is thermally oxidized to form the first oxide layer 9a on the sidewall and bottom of the first trench.

[0079] Specifically, as Figure 4 shown, in step S130, polysilicon is deposited on the first oxide layer 9a. If there is excess polysilicon precipitation, the excess polysilicon material inside and outside the first trench is etched to form a shield gate polysilicon electrode 8 on the first oxide layer 9a.

[0080] Specifically, as Figure 5 shown, in step S140, the first oxide layer 9a located on the shield gate polysilicon electrode 8 in the first trench is etched, and thermal oxidation growth or deposition is performed on the shield gate polysilicon electrode 8 to form a second oxide layer 9b, and the shield gate polysilicon electrode 8 is wrapped by the first oxide layer 9a and the second oxide layer 9b. Since two adjacent basic units are in contact with each other, the first oxide layer 9a and the second oxide layer 9b can completely wrap the shield gate polysilicon electrode 8.

[0081] Specifically, as Figure 6 shown, in step S150, the first-conductivity-type semiconductor drift region 3 located on the second oxide layer 9b is first thermally oxidized and grown to form a sacrificial oxide layer, and then the sacrificial oxide layer is etched to form an arc surface structure, so as to etch the side wall of the first trench located on the second oxide layer 9b toward the first-conductivity-type semiconductor drift region 3, so that the side wall of the first trench located on the second oxide layer 9b has an arc surface structure. Thermal oxidation growth is performed on the arc surface structure to form a third oxide layer 9c. Polysilicon is deposited on the second oxide layer 9b, and the deposited excess polysilicon can be etched back to form a gate polysilicon electrode 7. The second oxide layer 9b and the third oxide layer 9c wrap part of the gate polysilicon electrode 7.

[0082] Specifically, as Figure 6 shown, in step S160, on the side of the first-conductivity-type semiconductor drift region 3 facing away from the substrate 2, ion implantation and push-junction are performed on the first-conductivity-type semiconductor drift region 3 between the third oxide layers 9c, and a second-conductivity-type semiconductor region 4 is formed on the first-conductivity-type semiconductor drift region 3.

[0083] In detail, in step S170, partitioned ion implantation and push-junction are performed on the side of the second-conductivity-type semiconductor region 4 facing away from the first-conductivity-type semiconductor drift region 3 to form two first-conductivity-type semiconductor source regions (6a and 6b), including: opening a window on the second-conductivity-type semiconductor region 4 based on a mask to obtain an ion implantation window; performing ion implantation on the second-conductivity-type semiconductor region 4 based on the ion implantation window to form an initial conductivity-type semiconductor source region; and performing push-junction on the initial conductivity-type semiconductor source region to form two first-conductivity-type semiconductor source regions (6a and 6b). Among them, the region formed by ion implantation through the mask is the initial conductivity-type semiconductor source region.

[0084] More specifically, a single window is provided on the mask; or multiple windows are provided on the mask, and the sizes of the multiple windows increase or decrease from left to right.

[0085] Specifically, photoresist is provided above the second-conductivity-type semiconductor region 4, and a mask is formed through the photoresist. As Figure 7 shown, a single window is provided on the mask, covering most of the region above the left side of the second-conductivity-type semiconductor region 4 and covering a small part above the right side of the second-conductivity-type semiconductor region 4. Ions are implanted into the second-conductivity-type semiconductor region 4 through a single ion implantation window to form an initial conductivity-type semiconductor source region 6z in the second-conductivity-type semiconductor region 4, and push-junction is performed on the initial conductivity-type semiconductor source region 6z. As Figure 10 shown, two first-conductivity-type semiconductor source regions (6a and 6b) with slopes are formed in the second-conductivity-type semiconductor region 4.

[0086] As shown Figure 8 in the figure, three windows with different sizes are set on the mask plate to open windows on the second-conductivity-type semiconductor region 4, forming three ion implantation windows. Ions are implanted into the second-conductivity-type semiconductor region 4 through the three ion implantation windows. As shown Figure 9 in the figure, three initial-conductivity-type semiconductor source regions 6z with different sizes are formed in the second-conductivity-type semiconductor region 4, and the three initial-conductivity-type semiconductor source regions 6z with different sizes are pushed to form junctions. As shown Figure 10 in the figure, two first-conductivity-type semiconductor source regions (6a and 6b) with slopes are formed in the second-conductivity-type semiconductor region 4. Among them, the size, dimension and position of the ion implantation window can be adjusted accordingly according to the actual situation.

[0087] Specifically, the doping concentration of the first first-conductivity-type semiconductor source region 6a formed in the region with a large ion implantation window is greater than that of the second first-conductivity-type semiconductor source region 6b formed in the region with a small ion implantation window. As shown Figure 8 in the figure, when the ion implantation window decreases from left to right, as shown Figure 10 in the figure, the first first-conductivity-type semiconductor source region 6a located on the left side is heavily doped, and the second first-conductivity-type semiconductor source region 6b located on the right side is lightly doped; when the ion implantation window increases from left to right, as shown Figure 11 in the figure, the first first-conductivity-type semiconductor source region 6a located on the right side is heavily doped, and the second first-conductivity-type semiconductor source region 6b located on the left side is lightly doped.

[0088] Specifically, as shown Figure 12 in the figure, in step S180, the surfaces of the gate polysilicon electrode 7, the two first-conductivity-type semiconductor source regions (6a, 6b) and the third oxide layer 9c are passivated to form a gate-source dielectric layer 10; in step S190, photolithography is performed on the side of the gate-source dielectric layer 10 facing away from the two first-conductivity-type semiconductor source regions (6a, 6b) to form a second trench between the two first-conductivity-type semiconductor source regions (6a, 6b), and ions are input into the second trench. As shown Figure 13 in the figure, part of it extends into the second-conductivity-type semiconductor region 4 to form a second-conductivity-type semiconductor ohmic contact region 5. Part of the second-conductivity-type semiconductor ohmic contact region 5 is located between the two first-conductivity-type semiconductor source regions (6a, 6b), and part of the second-conductivity-type semiconductor ohmic contact region 5 is located in the second-conductivity-type semiconductor region 4.

[0089] Specifically, as shown Figure 14As shown, in step S210, metal is deposited on the gate-source dielectric layer 10 and the second-conductivity-type semiconductor ohmic contact region 5, and then lithography is performed on the excessively deposited metal layer to form the source metal layer 11; in step S211, the back of the substrate 2 is first thinned, and then metal is deposited on the back of the thinned substrate 2 to form the drain metal layer 1.

[0090] In a second aspect, as Figure 14 shown, the present application also provides a field effect transistor, which is manufactured based on the manufacturing method of the field effect transistor provided in the first aspect, and includes:

[0091] The drain metal layer 1, and the substrate 2 and the first-conductivity-type semiconductor drift region 3 stacked in sequence on the drain metal layer 1;

[0092] A first trench is provided in the first-conductivity-type semiconductor drift region 3;

[0093] A gate polysilicon electrode 7, a shielding gate polysilicon electrode 8, and an insulating dielectric layer 9 are provided in the first trench. The insulating dielectric layer 9 wraps part of the gate polysilicon electrode 7 and the shielding gate polysilicon electrode 8. Among them, the gate polysilicon electrode 7 is provided on the shielding gate polysilicon electrode 8 and is isolated by the insulating dielectric layer 9;

[0094] A second-conductivity-type semiconductor region 4 is provided on the side of the first-conductivity-type semiconductor drift region 3 away from 2;

[0095] Two first-conductivity-type semiconductor source regions (6a, 6b) and a second-conductivity-type semiconductor ohmic contact region 5 are provided on the side of the second-conductivity-type semiconductor region 4 away from the first-conductivity-type semiconductor drift region 3. Among them, a part of the second-conductivity-type semiconductor ohmic contact region 5 is located between the two first-conductivity-type semiconductor source regions (6a, 6b), and a part is located in the second-conductivity-type semiconductor region 4;

[0096] A gate-source dielectric layer 10 is provided on the two first-conductivity-type semiconductor source regions (6a, 6b), the gate polysilicon electrode 7, and a part of the insulating dielectric layer 9;

[0097] A source metal layer 11 is provided on the second-conductivity-type semiconductor ohmic contact region 5 and the gate-source dielectric layer 10.

[0098] Specifically, as Figure 14 shown, the shielding gate polysilicon electrode 8 is isolated from the first-conductivity-type semiconductor drift region 3 by the insulating dielectric layer 9 in the horizontal direction; the gate polysilicon electrode 7 is isolated from a part of the first-conductivity-type semiconductor drift region 3, a part of the second-conductivity-type semiconductor region 4, and the two first-conductivity-type semiconductor source regions by the insulating dielectric layer 9, where the horizontal direction is the direction parallel to the drain metal layer 1.

[0099] More specifically, as Figure 14 shown, on the second-conductive-type semiconductor ohmic contact region 5, a part of the source metal layer 11 is between two first-conductive-type semiconductor source regions (6a, 6b) in the horizontal direction, and a part is between the gate-source dielectric layers 10.

[0100] More specifically, as Figure 14 shown, the contact surfaces of the two first-conductive-type semiconductor source regions (6a, 6b) with the second-conductive-type semiconductor region 4 have slopes. Specifically, as Figure 11 and Figure 12 shown, the doping concentration of the first first-conductive-type semiconductor source region 6a is greater than that of the second first-conductive-type semiconductor source region 6b.

[0101] It should be emphasized that the doping concentration of the heavily doped region of the field-effect transistor provided in this application is greater than 1e18 cm -3 , and the doping concentration of the lightly doped region is less than 1e17 cm -3 . The first-conductive-type semiconductor is an N-type semiconductor, and the second-conductive-type semiconductor is a P-type semiconductor; or the first-conductive-type semiconductor is a P-type semiconductor, and the second-conductive-type semiconductor is an N-type semiconductor. The semiconductor material is silicon or silicon carbide.

[0102] When the field-effect transistor is turned on, on the side of the lightly doped first-conductive-type semiconductor source region 6a, as the dose of the second-conductive-type semiconductor in the source region decreases, the source region gradually shares the voltage and the voltage rises, so that the voltage drops between the second-conductive-type semiconductor region 4 and the first-conductive-type semiconductor source regions (6a, 6b) with different doping concentrations do not exceed 0.7V, thereby effectively suppressing the turn-on of the parasitic triode of the field-effect transistor, enhancing the thermal instability resistance of the field-effect transistor, and obtaining a larger safe operating area. In addition, although the doping concentration decreases, the cell region can be turned on everywhere, overcoming the disadvantage of the large on-resistance of the virtual cell.

[0103] It should be noted that the field-effect transistor may not require the shield gate polysilicon electrode 8, and the trench and planar gate field-effect transistors are also applicable.

[0104] In a third aspect, as Figure 15 shown, this application also provides a manufacturing method of a field-effect transistor, including:

[0105] S1501. Provide a substrate 2. The substrate 2 includes a front surface and a back surface arranged oppositely. Generate a first-conductive-type semiconductor drift region 3 on the front surface of the substrate 2;

[0106] S1502. Form a third trench with an arc-shaped structure in the first-conductive-type semiconductor drift region 3, and form an insulating dielectric layer 9 in the third trench;

[0107] S1503. Deposit polysilicon on the insulating dielectric layer 9 to form a gate polysilicon electrode 7;

[0108] S1504. Perform ion implantation and drive the junction on the side of the first-conductivity-type semiconductor drift region 3 away from the substrate 2 to form a second-conductivity-type semiconductor region 4;

[0109] S1505. Perform partitioned ion implantation and drive the junction on the side of the second-conductivity-type semiconductor region 4 away from the first-conductivity-type semiconductor drift region 3 to form two first-conductivity-type semiconductor source regions (6a, 6b) with a slope;

[0110] S1506. Perform passivation on the gate polysilicon electrode 7, two first-conductivity-type semiconductor source regions (6a, 6b) and a part of the insulating dielectric layer to form a gate-source interlayer dielectric 10;

[0111] S1507. Perform photolithography on the side of the gate-source interlayer dielectric 10 away from the gate-source interlayer dielectric 10 to form a second trench, perform ion implantation on the second trench, and partially extend it into the second-conductivity-type semiconductor region 4 to form a second-conductivity-type semiconductor ohmic contact region 5;

[0112] S1508. Deposit metal on the gate-source interlayer dielectric 10 and the second-conductivity-type semiconductor ohmic contact region 5 to form a source metal layer 11;

[0113] S1509. Deposit metal on the back surface of the substrate 2 to form a drain metal layer 1.

[0114] It should be noted that the position of the third trench is the same as that of the first trench. Since the third trench does not include the shield gate polysilicon electrode 8, the depth of the third trench is less than that of the first trench.

[0115] Fourthly, as Figure 16 shown, the present application also provides a field effect transistor, which is manufactured based on the manufacturing method of the field effect transistor provided in the third aspect, and includes:

[0116] A drain metal layer 1, and a substrate 2 and a first-conductivity-type semiconductor drift region 3 stacked on the drain metal layer 1 in sequence;

[0117] The first-conductivity-type semiconductor drift region 3 is provided with a third trench, and an arc-shaped structure is formed between the bottom and the side wall of the third trench;

[0118] A gate polysilicon electrode 7 and an insulating dielectric layer 9 are arranged in the third trench, and the insulating dielectric layer 9 wraps a part of the gate polysilicon electrode 7;

[0119] On one side of the first conductive type semiconductor drift region 3 facing away from the substrate 2, a second conductive type semiconductor region 4 is provided;

[0120] On one side of the second conductive type semiconductor region 4 facing away from the first conductive type semiconductor drift region 3, two first conductive type semiconductor source regions (6a, 6b) and a second conductive type semiconductor ohmic contact region 5 are provided. Among them, a part of the second conductive type semiconductor ohmic contact region 5 is between the two first conductive type semiconductor source regions (6a, 6b), and a part is located in the second conductive type semiconductor region 4;

[0121] A gate-source interlayer dielectric 10 is provided on the first conductive type semiconductor source region 6, the gate polysilicon electrode 7, and a part of the insulating dielectric layer 9;

[0122] A source metal layer 11 is provided on the second conductive type semiconductor ohmic contact region 5 and the gate-source interlayer dielectric 10.

[0123] The present application provides a manufacturing method and a field effect transistor of a field effect transistor. When forming the first conductive type semiconductor source region by ion implantation, without increasing the manufacturing process and cost of the field effect transistor, only by adjusting the width of the mask template or the position and number of the mask template windows for forming the first conductive type semiconductor source regions in different regions, different doping concentrations can be formed in different regions after pushing the junction. Due to the reduction of the channel density of the field effect transistor, the base voltage drop of the parasitic triode is effectively reduced, the risk of the parasitic triode turning on is reduced, the thermal instability resistance and the safe operating area of the field effect transistor are enhanced, and compared with the device with a virtual cell, its on-resistance is significantly reduced.

[0124] The above embodiments are only used to exemplarily illustrate the principles and effects of the present invention, rather than to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A manufacturing method of a field effect transistor, characterized in that include: Providing a substrate, the substrate comprising a front side and a back side arranged opposite to each other, and generating a first conductive type semiconductor drift region on the front side of the substrate; forming a first trench in the first conductive type semiconductor drift region, and forming a first oxide layer in the first trench; Depositing polysilicon on the first oxide layer to form a shielding gate polysilicon electrode; Performing thermal oxidation growth or deposition on the shielding gate polysilicon electrode to form a second oxide layer, wherein the first oxide layer and the second oxide layer wrap the shielding gate polysilicon electrode; Performing thermal oxidation growth and then etching on the first conductive type semiconductor drift region located on the second oxide layer to form a curved surface structure, performing thermal oxidation growth on the curved surface structure to form a third oxide layer, and performing polysilicon deposition on the second oxide layer to form a gate polysilicon electrode; Performing ion implantation and push-junction on a side of the first conductive type semiconductor drift region away from the substrate to form a second conductive type semiconductor region; Performing partitioned ion implantation and push-junction on a side of the second conductive type semiconductor region away from the first conductive type semiconductor drift region to form two first conductive type semiconductor source regions with the same direction slope; Passivation is performed on the gate polysilicon electrode, the two first conductive type semiconductor source regions and the third oxide layer to form a gate-source dielectric layer; Performing photolithography on a side of the gate-source dielectric layer away from the two first conductive type semiconductor source regions to form a second trench, performing ion implantation on the second trench and partially extending the second trench into the second conductive type semiconductor region to form a second conductive type semiconductor ohmic contact region; Depositing metal on the gate-source dielectric layer and the second conductive type semiconductor ohmic contact region to form a source metal layer; Depositing metal on the back side of the substrate to form a drain metal layer; The doping concentration of the first semiconductor source region of the first conductivity type is greater than the doping concentration of the second semiconductor source region of the first conductivity type, and the first oxide layer, the second oxide layer and the third oxide layer constitute an insulating dielectric layer; Partitioned ion implantation and junction pushing are performed on a side of the second conductive type semiconductor region away from the first conductive type semiconductor drift region to form two first conductive type semiconductor source regions with the same slope, including: Opening a window on the second conductive type semiconductor region based on a mask to obtain an ion implantation window; Performing ion implantation into the second conductive type semiconductor region based on the ion implantation window to form an initial conductive type semiconductor source region; Push-joining the initial conductive type semiconductor source region to form two first conductive type semiconductor source regions; A single window is arranged on the mask; or a plurality of windows are arranged on the mask, and sizes of the plurality of windows increase or decrease from left to right.

2. The manufacturing method of the field effect transistor according to claim 1, characterized in that, Forming a first trench in the first conductive type semiconductor drift region and forming a first oxide layer in the first trench, comprising: Performing masking on the first conductive type semiconductor drift region to generate a mask layer; Coat, expose, and develop the mask layer to determine the position of the first trench; Etch the mask layer and the first-conductivity-type semiconductor drift region to obtain the first trench; Perform thermal oxidation growth on the first trench to form the first oxide layer.

3. A field effect transistor, characterized in that, The field-effect transistor is manufactured by the manufacturing method of the field-effect transistor according to any one of claims 1-2, including: A drain metal layer, and a substrate and a first-conductivity-type semiconductor drift region stacked on the drain metal layer in sequence; A first trench is provided in the first-conductivity-type semiconductor drift region; A gate polysilicon electrode, a shielding gate polysilicon electrode, and an insulating dielectric layer are provided in the first trench. The insulating dielectric layer wraps part of the gate polysilicon electrode and the shielding gate polysilicon electrode. Among them, the gate polysilicon electrode is provided on the shielding gate polysilicon electrode and is isolated by the insulating dielectric layer; A second-conductivity-type semiconductor region is provided on the side of the first-conductivity-type semiconductor drift region away from the substrate; Two first-conductivity-type semiconductor source regions and a second-conductivity-type semiconductor ohmic contact region are provided on the side of the second-conductivity-type semiconductor region away from the first-conductivity-type semiconductor drift region. Among them, part of the second-conductivity-type semiconductor ohmic contact region is between the two first-conductivity-type semiconductor source regions, and part is located in the second-conductivity-type semiconductor region; A gate-source interlayer dielectric is provided on the two first-conductivity-type semiconductor source regions, the gate polysilicon electrode, and part of the insulating dielectric layer; A source metal layer is provided on the second-conductivity-type semiconductor ohmic contact region and the gate-source interlayer dielectric.

4. The field effect transistor according to claim 3, wherein The shielding gate polysilicon electrode is isolated from the first-conductivity-type semiconductor drift region by the insulating dielectric layer in the horizontal direction; the gate polysilicon electrode is isolated from part of the first-conductivity-type semiconductor drift region, part of the second-conductivity-type semiconductor region, and the two first-conductivity-type semiconductor source regions by the insulating dielectric layer, where the horizontal direction is parallel to the direction of the drain metal layer.

5. The field effect transistor according to claim 4, wherein The source metal layer on the second-conductivity-type semiconductor ohmic contact region is, in the horizontal direction, partly between the two first-conductivity-type semiconductor source regions and partly between the gate-source interlayer dielectrics.

6. The field effect transistor according to claim 3, wherein The contact surfaces of the two first-conductivity-type semiconductor source regions and the second-conductivity-type semiconductor region have slopes, and the doping concentration of the first first-conductivity-type semiconductor source region is greater than that of the second first-conductivity-type semiconductor source region.

7. A manufacturing method of a field effect transistor, characterized in that, Including: Provide a substrate. The substrate includes a front surface and a back surface arranged opposite to each other. Generate a first-conductivity-type semiconductor drift region on the front surface of the substrate; Form a third trench with a curved surface structure in the first-conductivity-type semiconductor drift region, and form an insulating dielectric layer in the third trench; Perform polysilicon deposition on the insulating dielectric layer to form a gate polysilicon electrode; Perform ion implantation and annealing on the side of the first-conductivity-type semiconductor drift region away from the substrate to form a second-conductivity-type semiconductor region; Partition ion implantation and junction pushing are performed on the side of the second-conductivity-type semiconductor region facing away from the first-conductivity-type semiconductor drift region to form two first-conductivity-type semiconductor source regions with the same-direction slope; Passivation is performed on the gate polysilicon electrode, the two first-conductivity-type semiconductor source regions, and part of the insulating dielectric layer to form a gate-source interlayer dielectric; Lithography is performed on the side of the gate-source interlayer dielectric facing away from the two first-conductivity-type semiconductor source regions to form a second trench, and ion implantation is performed on the second trench, and part of it extends into the second-conductivity-type semiconductor region to form a second-conductivity-type semiconductor ohmic contact region; Metal is deposited on the gate-source interlayer dielectric and the second-conductivity-type semiconductor ohmic contact region to form a source metal layer; Metal is deposited on the back surface of the substrate to form a drain metal layer; Among them, the doping concentration of the first first-conductivity-type semiconductor source region is greater than that of the second first-conductivity-type semiconductor source region; Among them, partition ion implantation and junction pushing are performed on the side of the second-conductivity-type semiconductor region facing away from the first-conductivity-type semiconductor drift region to form two first-conductivity-type semiconductor source regions with the same slope, including: Based on a mask, openings are made on the second-conductivity-type semiconductor region to obtain ion implantation windows; Based on the ion implantation windows, ion implantation is performed on the second-conductivity-type semiconductor region to form an initial conductivity-type semiconductor source region; Junction pushing is performed on the initial conductivity-type semiconductor source region to form the two first-conductivity-type semiconductor source regions; A single window is provided on the mask; or multiple windows are provided on the mask, and the sizes of the multiple windows increase or decrease from left to right.

8. A field effect transistor manufactured by the manufacturing method of the field effect transistor according to claim 7, characterized in that, Including: A drain metal layer, and a substrate and a first-conductivity-type semiconductor drift region stacked on the drain metal layer in sequence; A third trench is provided in the first-conductivity-type semiconductor drift region, and an arc-shaped structure is formed between the bottom and the side wall of the third trench; A gate polysilicon electrode and an insulating dielectric layer are provided in the third trench, and part of the gate polysilicon electrode is wrapped by the insulating dielectric layer; A second-conductivity-type semiconductor region is provided on the side of the first-conductivity-type semiconductor drift region facing away from the substrate; Two first-conductivity-type semiconductor source regions and a second-conductivity-type semiconductor ohmic contact region are provided on the side of the second-conductivity-type semiconductor region facing away from the first-conductivity-type semiconductor drift region. Among them, part of the second-conductivity-type semiconductor ohmic contact region is between the two first-conductivity-type semiconductor source regions, and part is located in the second-conductivity-type semiconductor region; A gate-source interlayer dielectric is provided on the two first-conductivity-type semiconductor source regions, the gate polysilicon electrode, and part of the insulating dielectric layer; A source metal layer is provided on the second-conductivity-type semiconductor ohmic contact region and the gate-source interlayer dielectric.

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