A metal-oxide-semiconductor field-effect transistor and a power device

Abstract

The application discloses a metal-oxide semiconductor field effect transistor and a power device. The metal-oxide semiconductor field effect transistor comprises a substrate, an epitaxial layer, a drift region, a well region and a first active region arranged on a side of the epitaxial layer away from the substrate, the conductive type of the first active region is opposite to that of the well region, a ballast resistor region, the ballast resistor region is located on a side of the well region away from the drift region, the conductive type of the ballast resistor region is the same as that of the first active region, a low resistance region, the low resistance region is located on a side of the well region away from the drift region, the conductive type of the low resistance region is the same as that of the first active region, the doping concentration of the low resistance region is greater than that of the ballast resistor region, the doping concentration of the low resistance region is less than that of the first active region, and the ballast resistor region and the low resistance region are located on the same side of the first active region. The technical scheme provided by the embodiment of the application improves the ability of the device to bear transient large current and short circuit characteristics.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a metal-oxide semiconductor field-effect transistor and a power device. BACKGROUND

[0002] Silicon carbide or gallium nitride metal-oxide semiconductor field-effect transistors (MOSFETs) have the advantages of high frequency and high efficiency, high voltage resistance, high reliability, etc., and can realize energy saving and consumption reduction, small size, low weight, high power density, etc., and have obvious advantages in the fields of new energy vehicles, photovoltaic power generation, rail transit, smart grid, etc.

[0003] Silicon carbide or gallium nitride MOSFET power devices are being used more and more widely, and the application conditions that follow are becoming more and more complex, and the environment is becoming more and more severe, and overcurrent or even short circuit phenomena often occur. The reasons for short circuit are many, for example, device failure in a certain bridge arm, drive circuit failure or other interference causing misoperation, output line connection error or load insulation damage, output line grounding or load insulation damage causing grounding, which may cause short circuit failure. No matter what causes the short circuit, a large short circuit transient current will be generated, which makes the device in a high power working state and is prone to failure.

[0004] However, the current metal-oxide semiconductor field-effect transistor and power device have poor ability to bear transient large current. SUMMARY

[0005] The present application provides a metal-oxide semiconductor field-effect transistor and a power device to improve its ability to bear transient large current and short circuit characteristics.

[0006] According to one aspect of the present application, a metal-oxide semiconductor field-effect transistor is provided, comprising:

[0007] a substrate;

[0008] an epitaxial layer located on one side of the substrate; the epitaxial layer is provided with a drift region, a well region and an active region away from one side of the substrate; the well region is located away from one side of the drift region, and the active region is located away from one side of the well region, and the active region at least includes a first active region, and the conductivity type of the first active region is opposite to that of the well region;

[0009] a ballast resistance region located away from one side of the well region; the conductivity type of the ballast resistance region is the same as that of the first active region;

[0010] a low-resistance region located on the side of the well region away from the drift region; the low-resistance region has the same conductivity type as the first active region; the doping concentration of the low-resistance region is greater than the doping concentration of the ballast resistance region, and the doping concentration of the low-resistance region is less than the doping concentration of the first active region; the ballast resistance region and the low-resistance region are located on the same side of the first active region;

[0011] under the forward conduction and non-short-circuit working condition, the source-drain current flows through the first active region, the low-resistance region, and the inversion channel of the well region; under the short-circuit working condition, the source-drain current flows through the ballast resistance region and the low-resistance region to the inversion channel of the well region; the ballast resistance region and the low-resistance region are located between the first active region and the inversion channel of the well region;

[0012] a gate structure located on the side of the epitaxial layer away from the substrate, the gate structure comprising a first dielectric layer, a polysilicon gate, and a second dielectric layer, the first dielectric layer being located on the side of the epitaxial layer away from the substrate, the polysilicon gate being located on the side of the first dielectric layer away from the epitaxial layer, and the second dielectric layer being located on the side of the polysilicon gate away from the epitaxial layer;

[0013] a source electrode located on the side of the epitaxial layer away from the substrate;

[0014] a drain electrode located on the side of the substrate away from the epitaxial layer.

[0015] Optionally, the resistance of the ballast resistance region and the threshold current under the short-circuit working condition are negatively correlated; the resistance of the ballast resistance region is related to the doping concentration and volume of the ballast resistance region.

[0016] Optionally, the gate structure comprises a planar structure.

[0017] The ballast resistance region and the low-resistance region are stacked, and both the ballast resistance region and the low-resistance region are in contact with the first active region. Optionally, in the direction of the substrate pointing to the epitaxial layer, the low-resistance region is located between the ballast resistance region and the well region; or the ballast resistance region is located between the low-resistance region and the well region.

[0018] Optionally, the gate structure comprises a trench gate structure.

[0019] The ballast resistance region and the low-resistance region are stacked, and the low-resistance region is located between the ballast resistance region and the first active region, or the ballast resistance region is located between the low-resistance region and the first active region.

[0020] Optionally, the source includes a trench type source structure or the source includes a planar type source structure.

[0021] Optionally, further comprising a JFET region, the JFET region is provided with a doped region, the doped region has a conductive type opposite to a doped type of the drift region.

[0022] Optionally, further comprising a withstand voltage region, the withstand voltage region is located at a side of the trench type gate structure close to the substrate, the withstand voltage region has a conductive type opposite to a conductive type of the drift region, and a doped concentration of the withstand voltage region is greater than a doped concentration of the drift region.

[0023] Optionally, the active region further comprises a second active region, the second active region has a same conductive type as the first active region, and a doped concentration of the second active region is greater than a doped concentration of the well region.

[0024] Optionally, the substrate includes a silicon carbide substrate, and the epitaxial layer includes a silicon carbide epitaxial layer; or the substrate includes a gallium nitride substrate, and the epitaxial layer includes a gallium nitride epitaxial layer.

[0025] Optionally, the source and the first active region are in contact.

[0026] The source and the ballast resistance region do not overlap in the orthographic projection of the substrate.

[0027] The source and the low resistance region do not overlap in the orthographic projection of the substrate.

[0028] According to another aspect of the present application, there is provided a power device comprising the metal-oxide semiconductor field effect transistor of any of the first aspect of the present application.

[0029] The metal-oxide semiconductor field effect transistor and the power device provided by the embodiments of the present application have the following advantages. Since the doped concentration of the low resistance region is greater than the doped concentration of the ballast resistance region and the doped concentration of the low resistance region is less than the doped concentration of the first active region, the on-resistance of the low resistance region is less than the on-resistance of the ballast resistance region. Therefore, in the forward on and non-short circuit working condition, the source-drain current (Ids) is in the linear region, and the source-drain current is relatively small. The small current is selected to flow through the low resistance region with a small on-resistance from the first active region to the inversion channel of the well region, thereby forming a vertical path of the source and the drain. In the short circuit working condition, the high voltage bus voltage between the source and the drain causes the source-drain current to increase significantly, and the low resistance region with a small on-resistance cannot bear all the current. Therefore, the source-drain current flows from the first active region through the ballast resistance region with a large on-resistance and the low resistance region with a small on-resistance to the inversion channel of the well region, thereby limiting the short circuit current, and improving the ability of the device to bear the transient large current and the short circuit characteristics of the device.

[0030] It should be understood that the matters described in this detailed description are intended to be illustrative and are not intended to limit or restrict the scope or applicability of the embodiments of the application. Other features of the embodiments of the application will become apparent to those skilled in the art upon an appreciation of the relevant art of this description and the following description of the embodiments of the application. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0032] Figure 1 is a structural schematic diagram of a metal-oxide semiconductor field effect transistor provided by an embodiment of the present application;

[0033] Figure 2 is a structural schematic diagram of another metal-oxide semiconductor field effect transistor provided by an embodiment of the present application;

[0034] Figure 3 is a structural schematic diagram of still another metal-oxide semiconductor field effect transistor provided by an embodiment of the present application;

[0035] Figure 4 is a structural schematic diagram of still another metal-oxide semiconductor field effect transistor provided by an embodiment of the present application;

[0036] Figure 5 is a flowchart of a preparation method of a metal-oxide semiconductor field effect transistor provided by an embodiment of the present application;

[0037] Figures 6-12 is a structural schematic diagram corresponding to each step of a preparation method of a metal-oxide semiconductor field effect transistor provided by an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the technical personnel in the art better understand the present application scheme, the technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort should belong to the scope of protection of the present application.

[0039] It should be noted that the terms "first", "second", and the like in the description and in the claims of the application and in the above-described drawings are used only for distinguishing between similar objects and do not necessarily have to describe a specific order or sequence. It is to be understood that the data thus designated can be interchanged, where appropriate, so that the embodiments of the application described herein can be carried out in a different order than the one illustrated or described herein. Furthermore, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusions, for example, processes, methods, systems, products, or devices that comprise a list of steps or units are not necessarily limited to those steps or units that are clearly listed, but can include other steps or units that are not clearly listed or inherent to such processes, methods, products, or devices.

[0040] In order to improve the ability of metal-oxide semiconductor field effect transistor to bear transient large current and short circuit characteristics, embodiments of the present application provide the following technical solutions:

[0041] As Figure 1 shown, Figure 1is a structural schematic diagram of a metal-oxide semiconductor field effect transistor provided by an embodiment of the present application. The metal-oxide semiconductor field effect transistor comprises: a substrate 1; an epitaxial layer 101 located on one side of the substrate 1; the epitaxial layer 101 is provided with a drift region 2, a well region 3 and an active region 102 on a side away from the substrate 1; the well region 3 is located on a side of the drift region 2 away from the substrate 1, the active region 102 is located on a side of the well region 3 away from the drift region 2, and the active region 102 at least comprises a first active region 4, the conductivity type of the first active region 4 is opposite to that of the well region 3; a ballast resistor region 6 is located on a side of the well region 3 away from the drift region 2; the conductivity type of the ballast resistor region 6 is the same as that of the first active region 4; a low resistance region 7 is located on a side of the well region 3 away from the drift region 2; the conductivity type of the low resistance region 7 is the same as that of the first active region 4; the doping concentration of the low resistance region 7 is greater than that of the ballast resistor region 6, and the doping concentration of the low resistance region 7 is less than that of the first active region 4; the ballast resistor region 6 and the low resistance region 7 are located on the same side of the first active region 4; in a forward conduction and non-short circuit working condition, the source-drain current flows through the first active region 4, the low resistance region 7 and reaches the inversion channel of the well region 3; in a short circuit working condition, the source-drain current flows through the ballast resistor region 6 and the low resistance region 7 from the first active region 4 and reaches the inversion channel of the well region 3; the ballast resistor region 6 and the low resistance region 7 are located between the first active region 4 and the inversion channel of the well region 3; a gate structure 103 is located on a side of the epitaxial layer 101 away from the substrate 1; the gate structure 103 comprises a first dielectric layer 8, a polysilicon gate 9 and a second dielectric layer 10; the first dielectric layer 8 is located on a side of the epitaxial layer 101 away from the substrate 1, the polysilicon gate 9 is located on a side of the first dielectric layer 8 away from the epitaxial layer 101, and the second dielectric layer 10 is located on a side of the polysilicon gate 9 away from the epitaxial layer 101; a source electrode 11 is located on a side of the epitaxial layer 101 away from the substrate 1; a drain electrode 12 is located on a side of the substrate 1 away from the epitaxial layer 101.

[0042] The metal-oxide semiconductor field effect transistor comprises an N-channel metal-oxide semiconductor field effect transistor or a P-channel metal-oxide semiconductor field effect transistor. Taking the N-channel metal-oxide semiconductor field effect transistor as an example, the substrate 1 is an N+ substrate, the drift region 2 is an N- drift region, the well region 3 is a P-type well region, the active region 102 comprises the first active region 4, and the first active region 4 is an N+ first active region. In other embodiments, the active region 102 can further comprise the first active region 4 and a second active region 5, and the second active region 5 is a P+ active region. The ballast resistor region 6 is an N- ballast resistor region, and the low resistance region 7 is an N-type low resistance region.

[0043] For the P-channel metal-oxide semiconductor field effect transistor, the substrate 1 is a P+ substrate, the drift region 2 is a P- drift region, the well region 3 is an N-type well region, and the active region 102 includes a first active region 4, which is a P+ first active region. In other embodiments, the active region 102 can further include the first active region 4 and a second active region 5, which is an N+ second active region. The ballast resistance region 6 is a P- ballast resistance region, and the low resistance region 7 is a P-type low resistance region.

[0044] Optionally, the first active region 4 has a doping concentration greater than or equal to 1e19 cm -3 and less than or equal to 1e20 cm -3 , the low resistance region 7 has a doping concentration greater than or equal to 1e17 cm -3 and less than or equal to 1e18 cm -3 , the ballast resistance region 6 has a doping concentration greater than or equal to 1e16 cm -3 and less than or equal to 1e17 cm -3 , so as to ensure that the doping concentration of the low resistance region 7 is greater than the doping concentration of the ballast resistance region 6 and the doping concentration of the low resistance region 7 is less than the doping concentration of the first active region 4.

[0045] Specifically, the inversion channel of the well region 3 is a portion of the well region 3 away from the substrate 1 and not covered by the active region 102, the ballast resistance region 6, and the low resistance region 7.

[0046] In this way, in the forward conduction and non-short circuit working condition, the source-drain current flows through the first active region 4, the low resistance region 7, and the inversion channel of the well region 3; and in the short circuit working condition, the source-drain current flows through the first active region 4, the ballast resistance region 6, and the low resistance region 7 to the inversion channel of the well region 3.

[0047] In this way, in the forward conduction and non-short circuit working condition, the source-drain current flows through the first active region 4, the low resistance region 7, and the inversion channel of the well region 3; and in the short circuit working condition, the source-drain current flows through the first active region 4, the ballast resistance region 6, and the low resistance region 7 to the inversion channel of the well region 3.

[0048] The technical scheme provided by the embodiment of the application has the advantages that, since the doping concentration of the low-resistance region 7 is greater than the doping concentration of the ballast resistor region 6 and the doping concentration of the low-resistance region 7 is less than the doping concentration of the first active region 4, the on-resistance of the low-resistance region 7 is less than the on-resistance of the ballast resistor region 6. Then, in the forward conduction and non-short-circuit working condition, the source-drain current (Ids) is in the linear region and is relatively small, and the small current is selected to flow through the first active region 4, the low-resistance region 7 with small on-resistance, and the inversion channel of the well region 3, thereby forming a vertical path of the source electrode 11 and the drain electrode 12. In the short-circuit working condition, the high-voltage bus voltage between the source electrode 11 and the drain electrode 12 causes the source-drain current to instantaneously increase significantly, and the low-resistance region 7 with small on-resistance cannot bear all the current. Therefore, the source-drain current flows from the first active region 4, through the ballast resistor region 6 with large on-resistance and the low-resistance region 7 with small on-resistance, and reaches the inversion channel of the well region 3, thereby playing a role in limiting the short-circuit current, and improving the ability of the device to bear the transient large current and the short-circuit characteristic of the device.

[0049] Optionally, as shown in Figure 1 , the resistance of the ballast resistor region 6 and the threshold current in the short-circuit working condition are negatively correlated; the resistance of the ballast resistor region 6 is related to the doping concentration and the volume of the ballast resistor region 6.

[0050] Specifically, the smaller the doping concentration of the ballast resistor region 6, the greater the resistance of the ballast resistor region 6. In the case of a certain doping concentration, the greater the volume of the ballast resistor region 6, the greater the resistance of the ballast resistor region 6.

[0051] The greater the resistance of the ballast resistor region 6, the smaller the threshold current of the device in the short-circuit working condition. By adjusting the doping concentration and the volume of the ballast resistor region 6, the threshold current in the short-circuit working condition can be adjusted, and thus the short-circuit characteristic of the device can be improved. Optionally, on the basis of the above technical scheme, as shown in Figure 1 , the gate structure 103 includes a planar structure; the ballast resistor region 6 and the low-resistance region 7 are stacked, and the ballast resistor region 6 and the low-resistance region 7 both contact the first active region.

[0052] Specifically, for the metal-oxide semiconductor field effect transistor including the planar structure of the gate structure 103, the inversion channel of the well region 3 is a horizontal channel, the ballast resistor region 6 and the low-resistance region 7 are stacked, and the ballast resistor region 6 and the low-resistance region 7 both contact the first active region 4, so that in the forward conduction and non-short-circuit working condition, the source-drain current (Ids) is facilitated to flow through the first active region 4, the low-resistance region 7 with small on-resistance, and the inversion channel of the well region 3, thereby forming a vertical path of the source electrode 11 and the drain electrode 12. In the short-circuit working condition, the source-drain current is facilitated to flow from the first active region 4, through the ballast resistor region 6 with large on-resistance and the low-resistance region 7 with small on-resistance, and reach the inversion channel of the well region 3.

[0053] Alternatively, as Figure 1 As shown, in the direction from the substrate 1 to the epitaxial layer 2, the low resistance region 7 is located between the ballast resistor region 6 and the well region 3. Alternatively, in other embodiments, in the direction from the substrate 1 to the epitaxial layer 2, the ballast resistor region 6 is located between the low resistance region 7 and the well region 3 (not shown in the figure).

[0054] Optionally, based on the above technical solution, Figure 2 and Figure 3 As shown, Figure 2 is a schematic structural diagram of another metal-oxide semiconductor field-effect transistor provided by an embodiment of the present invention, Figure 3 FIG. 1 is a schematic structural diagram of another metal-oxide semiconductor field-effect transistor according to an embodiment of the present invention. The gate structure 103 includes a trench gate structure. The ballast resistor region 6 and the low-resistance region 7 are stacked, with the low-resistance region 7 located between the ballast resistor region 6 and the first active region 4. Alternatively, in other embodiments, the ballast resistor region 6 is located between the low-resistance region 7 and the first active region 4 (not shown).

[0055] It should be noted that Figure 2 The metal-oxide-semiconductor field-effect transistor shown is a single-trench metal-oxide-semiconductor field-effect transistor, and the source includes a planar source structure. Figure 3 The metal-oxide semiconductor field-effect transistor shown is a dual-trench metal-oxide semiconductor field-effect transistor, whose source comprises a trench source structure. The provision of a trench gate structure eliminates the need for a JFET region in the metal-oxide semiconductor field-effect transistor, thereby reducing the on-resistance of the metal-oxide semiconductor field-effect transistor. The provision of a trench source structure can also reduce the peak voltage of the first dielectric layer 8 on the side of the trench gate structure closest to the substrate 1.

[0056] Specifically, for a metal-oxide semiconductor field-effect transistor including a gate structure 103 having a trench gate structure, the inversion channel of the well region 3 is a vertical channel. The ballast resistor region 6 and the low-resistance region 7 are stacked and both contact the first active region. This allows the source-drain current (Ids) to easily flow through the first active region 4 and the low-resistance region 7, which has a relatively low on-resistance, to the inversion channel of the well region 3 under forward conduction and non-short-circuit conditions, thereby forming a vertical path between the source 11 and the drain 12. Furthermore, under short-circuit conditions, the source-drain current easily flows from the first active region 4 through the ballast resistor region 6, which has a relatively high on-resistance, and the low-resistance region 7, which has a relatively low on-resistance, to the inversion channel of the well region 3.

[0057] Optionally, based on the above technical solution, Figure 4 As shown, Figure 4is a structure schematic diagram of a metal-oxide semiconductor field effect transistor provided by an embodiment of the present application, and the metal-oxide semiconductor field effect transistor with a planar structure of the gate structure 103 further comprises a JFET region, and the JFET region is provided with a doped region 13, and the conductivity type of the doped region 13 is opposite to the doping type of the drift region 2.

[0058] Specifically, the conductivity type of the doped region 13 in the JFET region is opposite to the doping type of the drift region 2, a depletion layer is formed between the conductivity type of the doped region 13 and the drift region 2, and in a short circuit condition, the depletion layer can further limit the short circuit current, thereby further improving the ability of the device to bear transient large current and the short circuit characteristics of the device.

[0059] Optionally, on the basis of the above technical solution, as shown in Figure 2 and Figure 3 for the metal-oxide semiconductor field effect transistor with the gate structure 103 comprising a trench type gate structure, further comprising a voltage withstanding region 14, the voltage withstanding region 14 is located at one side of the trench type gate structure close to the substrate 1, the conductivity type of the voltage withstanding region 14 is opposite to the conductivity type of the drift region 2, and the doping concentration of the voltage withstanding region 14 is greater than the doping concentration of the drift region 2.

[0060] Specifically, a depletion layer is formed between the voltage withstanding region 14 and the drift region 2, and the peak voltage at the first dielectric layer 8 on the one side of the trench type gate structure close to the substrate 1 can be reduced.

[0061] Optionally, on the basis of the above technical solution, as shown in Figures 1-4 the active region 102 further comprises a second active region 5, the conductivity type of the second active region 5 is the same as the conductivity type of the first active region 4, and the doping concentration of the second active region 5 is greater than the doping concentration of the well region 3.

[0062] Specifically, the second active region 5 forms an ohmic contact with the source electrode 11, and simultaneously shorts the well region 3 and the first active region 4, thereby preventing a parasitic bipolar junction transistor (BJT) from being turned on.

[0063] Optionally, on the basis of the above technical solution, as shown in Figures 1-4 the substrate 1 comprises a silicon carbide substrate, and the epitaxial layer 101 comprises a silicon carbide epitaxial layer; or the substrate 1 comprises a gallium nitride substrate, and the epitaxial layer 101 comprises a gallium nitride epitaxial layer, so that the metal-oxide semiconductor field effect transistor is a silicon carbide metal-oxide semiconductor field effect transistor or a gallium nitride metal-oxide semiconductor field effect transistor with advantages of high voltage withstanding, low on-resistance and high frequency.

[0064] Optionally, as shown in Figures 1-4As shown, the source 11 contacts the first active area 4 ; the orthographic projection of the source 11 on the substrate 1 does not overlap with the orthographic projection of the ballast resistor area 6 on the substrate 1 ; the orthographic projection of the source 11 on the substrate 1 does not overlap with the orthographic projection of the low resistance area 7 on the substrate 1 .

[0065] Specifically, the source electrode 11 contacts the first active region 4, but does not contact the ballast resistor region 6 or the low-resistance region 7. Because the doping concentration of the first active region 4 is greater than that of the ballast resistor region 6 and the low-resistance region 7, the above technical solution can ensure that the source electrode 11 forms a good ohmic contact with the first active region 4, thereby improving the electrical performance of the metal-oxide semiconductor field-effect transistor.

[0066] The embodiment of the present invention also provides a method for preparing a metal-oxide semiconductor field effect transistor. Figure 5 As shown, Figure 5 This is a flow chart of a method for preparing a metal-oxide semiconductor field effect transistor provided by an embodiment of the present invention, Figure 1 Taking the metal-oxide semiconductor field effect transistor shown as an example, the preparation method of the metal-oxide semiconductor field effect transistor includes:

[0067] S110 , providing a substrate.

[0068] like Figure 6 As shown, a substrate 1 is provided. Taking an N-channel metal-oxide semiconductor field effect transistor as an example, the substrate 1 is a silicon carbide substrate or a gallium nitride substrate. The substrate 1 is an N+ substrate.

[0069] S120 , forming an epitaxial layer on one side of the substrate.

[0070] like Figure 6 As shown, an epitaxial layer 101 is formed on one side of the substrate 1 by an epitaxial process. Taking an N-channel metal-oxide semiconductor field effect transistor as an example, the epitaxial layer 101 is an N-epitaxial layer, and the drift region 2 is located in the epitaxial layer 101 and is an N-drift region.

[0071] S130 , forming a well region on a side of the epitaxial layer away from the substrate, wherein the well region is located on a side of the drift region away from the substrate.

[0072] like Figure 6 As shown, taking an N-channel metal-oxide semiconductor field-effect transistor as an example, P-type impurities are implanted into the side of the epitaxial layer 101 away from the substrate 1 through a photolithography process and multiple ion implantation processes to form a well region 3. The well region 3 is located on the side of the drift region 2 away from the substrate 1.

[0073] S140 , forming an active region on a side of the well region away from the drift region, wherein the active region includes at least a first active region, and a conductivity type of the first active region is opposite to a conductivity type of the well region.

[0074] As shown in Figure 7 Taking the N-channel metal-oxide semiconductor field effect transistor as an example, the window of the first active region 4 is etched out by growing an oxide layer on the polysilicon mask of the well region 3 through an oxidation process, and then N-type impurities are implanted through a self-alignment process and a plurality of ion implantation processes to form the first active region 4.

[0075] In other embodiments, as shown in Figure 8 Taking the N-channel metal-oxide semiconductor field effect transistor as an example, the second active region 5 is formed by implanting P-type impurities through a photolithography process and a plurality of ion implantation processes, and the second active region 5 is a P+ second active region. It should be noted that during the ion implantation process, the impurity implantation dose corresponding to high implantation energy is small, and the impurity implantation dose corresponding to low implantation energy is large.

[0076] S150, forming a ballast resistance region and a low resistance region in the first active region.

[0077] As shown in Figure 8 Taking the N-channel metal-oxide semiconductor field effect transistor as an example, P-type impurities are implanted through a photolithography process and a plurality of ion implantation processes to neutralize the electrons in the first active region 4, so as to form a ballast resistance region 6 and a low resistance region 7 in the first active region 4.

[0078] The ballast resistance region 6 is located on the side of the well region 3 away from the drift region 2; the conductive type of the ballast resistance region 6 is the same as that of the first active region 4; the low resistance region 7 is located on the side of the well region 3 away from the drift region 2; the conductive type of the low resistance region 7 is the same as that of the first active region 4; the doping concentration of the low resistance region 7 is greater than that of the ballast resistance region 6, and the doping concentration of the low resistance region 7 is less than that of the first active region 4; the ballast resistance region 6 and the low resistance region 7 are located on the same side of the first active region 4.

[0079] S160, forming a gate structure on the side of the epitaxial layer away from the substrate, wherein the gate structure includes a first dielectric layer, a polysilicon gate, and a second dielectric layer, the first dielectric layer is located on the side of the epitaxial layer away from the substrate, the polysilicon gate is located on the side of the first dielectric layer away from the epitaxial layer, and the second dielectric layer is located on the side of the polysilicon gate away from the epitaxial layer.

[0080] The process of forming the gate structure 103 on the side of the epitaxial layer 101 away from the substrate 1 is as follows:

[0081] As shown in Figure 9 Taking the first dielectric layer 8 as silicon oxide as an example, the gate oxide layer is formed as the first dielectric layer 8 through an oxidation process.

[0082] As shown in Figure 10As shown, a polysilicon gate 9 is formed on the side of the first dielectric layer 8 away from the epitaxial layer 101.

[0083] As shown, a portion of the polysilicon gate 9 and the first dielectric layer 8 are etched away by an etching process, and a second dielectric layer 10 is deposited to form a gate structure 103. Figure 11

[0084] S170, a source electrode is formed on the side of the epitaxial layer away from the substrate.

[0085] As shown, a source metal hole is formed in the second dielectric layer 10 by a photolithography process. Figure 11

[0086] As shown, a source electrode 11 is formed on the side of the epitaxial layer 101 away from the substrate 1 by a sputtering process. Figure 12

[0087] S180, a drain electrode is formed on the side of the substrate away from the epitaxial layer.

[0088] As shown, a drain electrode 12 is formed on the side of the substrate 1 away from the epitaxial layer 101. Figure 1

[0089] The technical scheme provided by the embodiment of the present application, since the doping concentration of the low-resistance region 7 is greater than the doping concentration of the ballast resistor region 6, and the doping concentration of the low-resistance region 7 is less than the doping concentration of the first active region 4, the on-resistance of the low-resistance region 7 is less than the on-resistance of the ballast resistor region 6. Then, in the forward conduction and non-short-circuit working condition, the source-drain current (Ids) is in the linear region, and the source-drain current is relatively small. The small current is selected to flow through the first active region 4, the low-resistance region 7 with small on-resistance, and the inversion channel of the well region 3, thereby forming a vertical path of the source electrode 11 and the drain electrode 12. And in the short-circuit working condition, due to the high voltage of the bus between the source electrode 11 and the drain electrode 12, the source-drain electrode instantaneously increases significantly, and the low-resistance region 7 with small on-resistance cannot bear all the current; therefore, the source-drain current flows through the ballast resistor region 6 with large on-resistance and the low-resistance region 7 with small on-resistance from the first active region 4 to the inversion channel of the well region 3, thereby playing a role in limiting the short-circuit current, and improving the ability of the device to bear transient large current and the short-circuit characteristics of the device.

[0090] The embodiment of the present application also provides a power device, which comprises the metal-oxide semiconductor field effect transistor according to any of the embodiments of the present application. Therefore, the power device has the beneficial effects of the metal-oxide semiconductor field effect transistor according to any of the embodiments of the present application, which will not be repeated here.

[0091] ​​​​It should be understood that the various forms of flow shown above can be used to reorder, add, or remove steps. For example, the steps recited in the present application can be performed in parallel, in series, or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, which are not limited herein.

[0092] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A metal-oxide semiconductor field effect transistor, characterized by, The application relates to a semiconductor device, which comprises: a substrate; an epitaxial layer on one side of the substrate; a drift region, a well region and an active region are arranged on the side of the epitaxial layer away from the substrate; the well region is located on the side of the drift region away from the substrate, and the active region is located on the side of the well region away from the drift region, wherein the active region at least comprises a first active region, and the conductive type of the first active region is opposite to that of the well region; a ballast resistance region on the side of the well region away from the drift region; the conductive type of the ballast resistance region is the same as that of the first active region; a low resistance region on the side of the well region away from the drift region; the conductive type of the low resistance region is the same as that of the first active region; the doping concentration of the low resistance region is greater than that of the ballast resistance region, and the doping concentration of the low resistance region is less than that of the first active region; the ballast resistance region and the low resistance region are located on the same side of the first active region; in a forward conduction and non-short circuit working condition, source-drain current flows through the first active region, the low resistance region and reaches the inversion channel of the well region; in a short circuit working condition, the source-drain current flows through the ballast resistance region and the low resistance region and reaches the inversion channel of the well region; the ballast resistance region and the low resistance region are located between the first active region and the inversion channel of the well region; a gate structure on the side of the epitaxial layer away from the substrate, which comprises a first dielectric layer, a polysilicon gate and a second dielectric layer; the first dielectric layer is located on the side of the epitaxial layer away from the substrate; the polysilicon gate is located on the side of the first dielectric layer away from the epitaxial layer; and the second dielectric layer is located on the side of the polysilicon gate away from the epitaxial layer; a source on the side of the epitaxial layer away from the substrate; a drain on the side of the substrate away from the epitaxial layer.

2. The metal-oxide semiconductor field effect transistor of claim 1, wherein, The resistance of the ballast resistance region is negatively correlated with the threshold current in the short circuit working condition; the resistance of the ballast resistance region is related to the doping concentration and volume of the ballast resistance region.

3. The metal-oxide semiconductor field effect transistor of claim 1, wherein, The gate structure comprises a planar structure; The ballast resistance region and the low resistance region are arranged in a stack mode, and both of them are in contact with the first active region.

4. The metal-oxide semiconductor field effect transistor of claim 3, wherein the metal-oxide semiconductor field effect transistor is a metal-oxide-semiconductor field effect transistor (MOSFET). In the direction of the substrate pointing to the epitaxial layer, the low resistance region is located between the ballast resistance region and the well region; or the ballast resistance region is located between the low resistance region and the well region.

5. The metal-oxide semiconductor field effect transistor of claim 1, wherein the metal-oxide semiconductor field effect transistor is a metal-oxide-semiconductor field effect transistor (MOSFET). The gate structure comprises a trench gate structure; The ballast resistance region and the low resistance region are arranged in a stack mode; The low resistance region is located between the ballast resistance region and the first active region, or the ballast resistance region is located between the low resistance region and the first active region.

6. The metal-oxide semiconductor field effect transistor of claim 5, wherein the metal-oxide semiconductor field effect transistor is a metal-oxide-semiconductor field effect transistor (MOSFET). The source comprises a trench source structure or a planar source structure.

7. The metal-oxide semiconductor field effect transistor of claim 3, wherein the metal-oxide semiconductor field effect transistor is a metal-oxide-semiconductor field effect transistor (MOSFET) having a gate electrode comprising a metal gate electrode. The semiconductor device further comprises a JFET region provided with a doped region, and the conductive type of the doped region is opposite to that of the drift region.

8. The metal-oxide semiconductor field effect transistor according to claim 5 or 6, wherein A voltage withstanding region is further included, which is located at one side of the trench gate structure close to the substrate, has opposite conductivity type to the drift region, and has a doping concentration greater than that of the drift region.

9. The metal-oxide semiconductor field effect transistor of claim 1, wherein, The active region further includes a second active region, which has the same conductivity type as the first active region and has a doping concentration greater than that of the well region.

10. The metal-oxide semiconductor field effect transistor of claim 1, wherein, The substrate includes a silicon carbide substrate, and the epitaxial layer includes a silicon carbide epitaxial layer; or the substrate includes a gallium nitride substrate, and the epitaxial layer includes a gallium nitride epitaxial layer.

11. The metal-oxide semiconductor field effect transistor of claim 1, wherein, The source and the first active region are in contact; The source and the ballast resistance region are not overlapped in the projection of the substrate; The source and the low resistance region are not overlapped in the projection of the substrate.

12. A power device, characterized by The metal-oxide-semiconductor field effect transistor of any one of claims 1-11 is included.

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