An ESD-hardened LDMOS device and a method for manufacturing the same

Abstract

The present invention belongs to the field of electronic components, and discloses an ESD reinforced LDMOS device and a preparation method thereof, comprising a substrate and an epitaxial layer arranged on the upper surface of the substrate, and also comprising a body region, a drain contact region, a source contact region, a substrate contact region, a dielectric region, a gate polysilicon, a drain metal, a source metal and a substrate pole metal, wherein the body region and the drain contact region are both located above the inside of the epitaxial layer; the source contact region and the substrate contact region are both located above the inside of the body region; the dielectric region is located above the epitaxial layer; the drain metal, the source metal and the substrate pole metal are all located above the dielectric region, and the drain metal extends through the dielectric region to the drain contact region, the source metal extends through the dielectric region to the source contact region, the substrate pole metal passes through the dielectric region and contacts the upper surface of the substrate contact region; the gate polysilicon is located above the dielectric region. The present invention can eliminate the current concentration region of the LDMOS, thereby improving the ESD resistance of the high-voltage LDMOS and similar lateral devices.

Description

Technical Field

[0001] The present invention belongs to the field of electronic components, and in particular relates to an ESD reinforced LDMOS device and a preparation method thereof. Background Art

[0002] The miniaturization and integration of power electronic systems is one of the important research directions of power semiconductor devices. Smart Power Integrated Circuit (SPIC) or High Voltage Integrated Circuit (HVIC) integrates low-voltage circuits such as protection, control, detection, and drive with high-voltage power devices on the same chip, which not only reduces the system size and improves system reliability, but also significantly reduces the requirements for buffering and protection circuits in higher frequency working environments due to the reduction of system lead inductance.

[0003] Lateral Double Diffused MOSFET (LDMOS) has attracted widespread attention due to its high operating voltage, simple process, and compatibility with low-voltage CMOS (Complementary Metal Oxide Semiconductor) circuits. Figure 1 It is a schematic diagram of the structure of a conventional n-LDMOS device with an N epitaxial layer.

[0004] Electrostatic discharge is a common natural phenomenon in integrated circuits. When ESD transient voltage acts on high-voltage LDMOS, it may cause a transient large current of several amperes or even tens of amperes to flow through the LDMOS device. Due to the carrier conductivity modulation effect inside the LDMOS, under the action of this large current, the resistance distribution in the LDMOS drift region is not uniform, and current concentration is very likely to occur at the edge curvature junction of the N+ source region and the N+ drain region (such as Figure 1 ), which may cause device damage. Summary of the invention

[0005] In order to overcome the above-mentioned shortcomings, the present invention provides an ESD-reinforced LDMOS device and a preparation method thereof, which can eliminate the current concentration area of ​​the LDMOS, thereby improving the ESD resistance of the high-voltage LDMOS and similar lateral devices.

[0006] The main technical solutions adopted in the present invention are:

[0007] An ESD-hardened LDMOS device includes a substrate and an epitaxial layer arranged on the upper surface of the substrate, and also includes a body region, a drain contact region, a source contact region, a substrate contact region, a dielectric region, a gate polysilicon, a drain metal, a source metal and a substrate metal, wherein:

[0008] The body region and the drain contact region are both located above the interior of the epitaxial layer;

[0009] The source contact region and the substrate contact region are both located above the interior of the body region;

[0010] The dielectric region is located above the epitaxial layer;

[0011] The drain metal, source metal and substrate metal are all located above the dielectric region, and the drain metal extends through the dielectric region to the drain contact region, the source metal extends through the dielectric region to the source contact region, and the substrate metal passes through the dielectric region to contact the upper surface of the substrate contact region;

[0012] The gate polysilicon is located above the dielectric region, and a coverage area of ​​the gate polysilicon is located between a source contact region and a drain contact region.

[0013] Preferably, there is a gap between the side of the body region and the drain contact region.

[0014] Preferably, the substrate contact region is located at a side of the source contact region away from the drain contact region, and the substrate contact region is in contact with a side edge of the source contact region.

[0015] Preferably, the drain contact region and the source contact region are both trench-type heavily doped polysilicon thin layers, the drain metal extends into the trench of the drain contact region, and the source metal extends into the trench of the source contact region.

[0016] Preferably, a top region is further provided above the epitaxial layer between the body region and the drain contact region, and the upper surface of the top region is flush with the upper surface of the epitaxial layer, and there are gaps between the drain contact region and the source contact region on both sides of the top region, and the conductivity type of the top region is the same as the conductivity type of the substrate.

[0017] Preferably, a buried layer is further provided inside the epitaxial layer between the body region and the drain contact region, and there is a gap between the upper surface of the buried layer and the upper surface of the epitaxial layer, and there are gaps between the two sides of the buried layer and the drain contact region and the source contact region respectively, and the conductivity type of the buried layer is the same as the conductivity type of the substrate.

[0018] Preferably, when the substrate is a P-type substrate, the conductivity types of the body region and the substrate contact region are both P-type, and the conductivity types of the epitaxial layer, the drain contact region and the source contact region are all N-type.

[0019] Preferably, when the substrate is an N-type substrate, the conductivity types of the body region and the substrate contact region are both N-type, and the conductivity types of the epitaxial layer, the drain contact region and the source contact region are all P-type.

[0020] A method for preparing an ESD-hardened LDMOS device, used for preparing a drain contact region and a source contact region in the LDMOS device according to any one of claims 1 to 8, the specific steps comprising:

[0021] S1: forming a body region on the upper part of the epitaxial layer by sequentially adopting an ion implantation process and a high temperature annealing process;

[0022] S2: etching a source contact region trench and a drain contact region trench at the location of the ohmic contact region on the surface of the epitaxial layer, wherein the source contact region trench is located in the body region;

[0023] S3: directly depositing polysilicon with a high doping concentration on the inner surfaces of the source contact area trench and the drain contact area trench respectively, and etching the deposited polysilicon to form a trench-type heavily doped polysilicon thin layer.

[0024] Preferably, in step S3, the thickness of the trench-shaped heavily doped polysilicon thin layer formed by etching is ≤0.2 μm.

[0025] Beneficial effects: The present invention provides an ESD-hardened LDMOS device and a preparation method thereof, which have the following advantages:

[0026] (1) The present invention designs the source contact region and the drain contact region of the LDMOS as a trench-type heavily doped polysilicon thin layer, and adopts a polysilicon deposition process to prepare the trench-type heavily doped polysilicon thin layer, so that the ion concentration distribution of the source contact region and the drain contact region is more uniform than that of the N+ region formed by the traditional ion implantation-heating activation process, thereby effectively improving the current uniformity of the high-voltage LDMOS under ESD transient large current conditions, and further improving the ESD resistance of the LDMOS.

[0027] (2) The present invention adopts an etching process to etch the polysilicon thin layer in the source contact area and the drain contact area, leaving only a polysilicon thin layer of 0.2 microns or even thinner, which can effectively reduce the resistance increase problem introduced by polysilicon and avoid the deterioration of indicators such as residual voltage and dynamic resistance of ESD devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of the structure of a traditional n-LDMOS device;

[0029] Figure 2 It is a schematic diagram of the structure of the ESD-hardened LDMOS device of Example 1;

[0030] Figure 3It is a schematic diagram of the structure of the ESD-hardened LDMOS device of Example 2;

[0031] Figure 4 This is a schematic diagram of the structure of the ESD-hardened LDMOS device of Example 3.

[0032] In the figure: substrate 01, epitaxial layer 10; body region 20; drain contact region 30, source contact region 31, substrate contact region 32, drain metal 40, source metal 41, substrate metal 42, dielectric region 50, gate polysilicon 60, top region 70, buried layer 71. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application are clearly and completely described below. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application. Example 1

[0034] This embodiment 1 provides an ESD-hardened LDMOS device, such as Figure 2 As shown, including:

[0035] Substrate 01;

[0036] The epitaxial layer 10 is arranged on the upper surface of the substrate 01;

[0037] The body region 20 is located above the epitaxial layer 10;

[0038] A drain contact region 30 is located above the epitaxial layer 10, and there is a gap between the body region 20 and the drain contact region 30;

[0039] A source contact region 31, located above the interior of the body region 20;

[0040] A substrate contact region 32 is located above the body region 20 . The substrate contact region 32 is located on a side of the source contact region 31 away from the drain contact region 30 , and the substrate contact region 32 is in contact with a side edge of the source contact region 30 .

[0041] a dielectric region 50 , located above the epitaxial layer 10 ;

[0042] The drain metal 40 is located above the dielectric region 50, and the drain metal 40 extends through the dielectric region to the drain contact region 30;

[0043] The source metal 41 is located above the dielectric region 50, and the source metal 41 extends through the dielectric region 50 to the second conductivity type source contact 31 region;

[0044] The substrate pole metal 42 is located above the dielectric region 50, and the substrate pole metal 42 passes through the dielectric region 50 and contacts the upper surface of the substrate contact region 32;

[0045] The gate polysilicon 60 is located above the dielectric region 50, and the coverage area of ​​the gate polysilicon 60 is located between the source contact region 31 and the drain contact region 30, as shown in FIG. Figure 2 As shown, the left and right edges of the gate polysilicon 60 do not exceed the drain contact region 30 and the source contact region 31;

[0046] like Figure 2 As shown, the drain contact region 30 and the source contact region 31 are both trench-type polysilicon thin layers, the drain metal 40 extends into the trench of the drain contact region 30, and is coated around the lower part of the drain metal 40 by the drain contact region 30, and the source metal 41 extends into the trench of the source contact region 31, and is coated around the lower part of the source metal 41 by the source contact region 31.

[0047] In this embodiment 1, the conductivity type of the substrate 01, the body region 20 and the substrate contact region 32 are all P-type, and the conductivity type of the epitaxial layer 10, the drain contact region 30 and the source contact region 31 are all N-type. The drain contact region 30 and the source contact region 31 are both heavily doped N-type polysilicon thin layers. In this embodiment 1, the doping concentration of the N-type polysilicon thin layer is preferably 1e20cm -3 .

[0048] In this embodiment 1, Figure 2 As shown, the upper surfaces of the body region 20 , the drain contact region 30 , the source contact region 31 and the substrate contact region 32 are flush with the upper surface of the epitaxial layer 10 .

[0049] In the present embodiment 1, the dielectric region 50 may be, but is not limited to, a silicon dioxide dielectric region, and any existing dielectric material applicable to LDMOS devices may be applicable.

[0050] In this embodiment 1, the specific steps of preparing the drain contact region 30 and the source contact region 31 in the LDMOS device are as follows:

[0051] S1: forming a body region 20 on the inside of the epitaxial layer 10 by sequentially using an ion implantation process and a high temperature annealing process;

[0052] S2: etching the source contact region 31 trench and the drain contact region 30 at the location of the ohmic contact region on the surface of the epitaxial layer, wherein the source contact region 31 trench is located in the body region 20;

[0053] S3: Directly depositing polysilicon with a high doping concentration on the inner surfaces of the trenches of the source contact region 31 and the drain contact region 30 respectively, and etching the deposited polysilicon to form a trench-type heavily doped polysilicon thin layer.

[0054] In this embodiment 1, the preparation of other structures in the LDMOS device is the same as that in the prior art and thus will not be described in detail. Example 2

[0055] This embodiment 2 provides an ESD-hardened Double-RESURF LDMOS device, such as Figure 3 As shown, on the basis of Embodiment 1, a top region 70 is further provided above the epitaxial layer 10 between the body region 20 and the drain contact region 30, and the upper surface of the top region 70 is flush with the upper surface of the epitaxial layer 10, and there are gaps between the drain contact region 30 and the source contact region 31 on both sides of the top region 70. In this Embodiment 2, the conductivity type of the top region 70 is the same as the conductivity type of the substrate 01. Example 3

[0056] This embodiment 3 provides an ESD-hardened Triple-RESURF LDMOS device, such as Figure 4 As shown, on the basis of Embodiment 1, a buried layer 71 is further provided inside the epitaxial layer 10 between the body region 20 and the drain contact region 30, and there is a gap between the upper surface of the buried layer 71 and the upper surface of the epitaxial layer 10, and there are gaps between the two sides of the buried layer 71 and the drain contact region 30 and the source contact region 31. In this Embodiment 3, the conductivity type of the buried layer 71 is the same as the conductivity type of the substrate 01.

[0057] The design principle of the present invention is as follows:

[0058] In the traditional LDMOS structure and its preparation method, Figure 1 As shown, the source contact region 31 and the drain contact region 30 are heavily ion-doped regions (N+ regions), which are generally formed by ion implantation and annealing processes. However, this process will push the original heavily ion-doped region (N+ region) toward the P-type body region 20, thereby forming an N-type transition region at the junction of the heavily ion-doped region (N+ region) and the P-type body region 20. The ion doping concentration of the N-type transition region will be much lower than that of the N+ region. Therefore, under the action of avalanche electron-hole pairs and diffused minority carriers caused by a large amount of ESD transient voltage, carrier electric field modulation will occur in the N-type transition region, resulting in extremely uneven resistance distribution in the N epitaxial layer 10, thereby causing current concentration at the edge curvature junction of the source contact region 31 and the drain contact region 32, causing device damage.

[0059] In order to solve the above problems, the present invention improves the structure of the drain contact region 30 and the source contact region 31. Taking Example 1 as an example, Figure 2As shown, the drain contact region 30 and the source contact region 31 are designed as trench-type heavily doped polysilicon thin layers, which are used to cover the drain metal 40 and the source metal 41 respectively. On the one hand, during the preparation process, the heavily doped polysilicon thin layers forming the drain contact region 30 and the source contact region 31 are deposited in the trenches of the epitaxial layer 10, and are not formed by ion implantation. Since the diffusion of impurity ions in the heavily doped polysilicon thin layer after rapid thermal annealing is much smaller than that of ion implantation, the N-type transition region formed by it is much thinner than the N-type transition region formed by traditional ion implantation, and can be approximately regarded as a sudden junction, and the junction surface maintains extremely high uniformity in the longitudinal direction. In addition, the junction formed by this method has a large side surface area with a deep junction depth, and is not easy to form a current concentration area, thereby improving the ESD resistance of high-voltage LDMOS and similar devices.

[0060] On the other hand, although the resistivity of polysilicon is higher than that of single crystal silicon, heavily doped polysilicon thin layers will also introduce additional resistance, thereby deteriorating the residual voltage, dynamic resistance and other indicators of the ESD device. In order to solve this problem at the same time, the present invention etches the polysilicon thin layer in the process, leaving only a polysilicon thin layer of 0.2 microns or even thinner, thereby greatly reducing the resistance increase problem caused by polysilicon.

[0061] The design principle of the present invention is applicable to various improved structures based on LDMOS, and may be, but not limited to, the Double-RESURF LDMOS structure shown in Embodiment 2 and the Triple-RESURF LDMOS structure shown in Embodiment 3.

[0062] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An ESD-hardened LDMOS device, comprising a substrate (01) and an epitaxial layer (10) arranged on the upper surface of the substrate (01), characterized in that: It also includes a body region (20), a drain contact region (30), a source contact region (31), a substrate contact region (32), a dielectric region (50), a gate polysilicon (60), a drain metal (40), a source metal (41) and a substrate metal (42), wherein: The body region (20) and the drain contact region (30) are both located above the inside of the epitaxial layer (10); The source contact region (31) and the substrate contact region (32) are both located above the interior of the body region (20); The dielectric region (50) is located above the epitaxial layer (10); The drain metal (40), the source metal (41) and the substrate metal (42) are all located above the dielectric region (50), and the drain metal (40) extends through the dielectric region (50) to the drain contact region (30), the source metal (41) extends through the dielectric region (50) to the source contact region (31), and the substrate metal (42) passes through the dielectric region (50) to contact the upper surface of the substrate contact region (32); The gate polysilicon (60) is located above the dielectric region (50), and the coverage area of ​​the gate polysilicon (60) is located between the source contact region (31) and the drain contact region (30); The drain contact region (30) and the source contact region (31) are both trench-type heavily doped polysilicon thin layers.

2. The ESD-hardened LDMOS device according to claim 1, characterized in that: There is a gap between the side of the body region (20) and the drain contact region (30).

3. The ESD-hardened LDMOS device according to claim 1, characterized in that: The substrate contact region (32) is located on a side of the source contact region (31) away from the drain contact region (30), and the substrate contact region (32) is in contact with a side edge of the source contact region (31).

4. The ESD-hardened LDMOS device according to claim 1, wherein: The drain metal (40) extends into the trench of the drain contact region (30), and the source metal (41) extends into the trench of the source contact region (31).

5. The ESD-hardened LDMOS device according to any one of claims 1 to 4, characterized in that: A top region (70) is also provided above the epitaxial layer (10) between the body region (20) and the drain contact region (30), and the upper surface of the top region (70) is flush with the upper surface of the epitaxial layer (10), and there are gaps between the drain contact region (30) and the source contact region (31) on both sides of the top region (70), and the conductivity type of the top region (70) is the same as the conductivity type of the substrate (01).

6. The ESD-hardened LDMOS device according to any one of claims 1 to 4, characterized in that: A buried layer (71) is also provided inside the epitaxial layer (10) between the body region (20) and the drain contact region (30), and there is a gap between the upper surface of the buried layer (71) and the upper surface of the epitaxial layer (10), and there are gaps between the two sides of the buried layer (71) and the drain contact region (30) and the source contact region (31), respectively, and the conductive type of the buried layer (71) is the same as that of the substrate (01).

7. The ESD-hardened LDMOS device according to claim 1, characterized in that: When the substrate (01) is a P-type substrate, the conductivity types of the body region (20) and the substrate contact region (32) are both P-type, and the conductivity types of the epitaxial layer (10), the drain contact region (30) and the source contact region (31) are all N-type.

8. The ESD-hardened LDMOS device according to claim 1, wherein: When the substrate (01) is an N-type substrate, the conductivity types of the body region (20) and the substrate contact region (32) are both N-type, and the conductivity types of the epitaxial layer (10), the drain contact region (30) and the source contact region (31) are all P-type.

9. A method for preparing an ESD-hardened LDMOS device, characterized in that: Used to prepare a drain contact region (30) and a source contact region (31) in an LDMOS device as claimed in any one of claims 1 to 8, the specific steps comprising: S1: sequentially using an ion implantation process and a high temperature annealing process to form a body region (20) above the inside of the epitaxial layer (10); S2: etching a source contact region (31) trench and a drain contact region (30) trench at the location of the ohmic contact region on the surface of the epitaxial layer, wherein the source contact region (31) trench is located in the body region (20); S3: Directly depositing polysilicon with a high doping concentration on the inner surfaces of the source contact region (31) trench and the drain contact region (30) trench respectively, and etching the deposited polysilicon to form a trench-type heavily doped polysilicon thin layer.

10. The method for preparing an ESD-hardened LDMOS device according to claim 9, characterized in that: In the step S3, the thickness of the trench-shaped heavily doped polysilicon thin layer formed by etching is ≤0.2 μm.

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