Maximum value search method in decoder, decoding method, device and equipment

Abstract

The present application relates to the technical field of decoders, and in particular to a maximum value search method, decoding method, device and equipment in a decoder, the method comprising: determining the maximum number of inputs of a tree structure search circuit to be generated according to a base matrix of the decoder, and generating a tree structure search circuit; dividing the multi-level nodes in the tree structure search circuit into L Layer search module, the first level corresponding to the input terminal in the tree structure search circuit is defined as l The last level of the output of the 0-layer search module is defined as l L‑1 Layer search module; settings l Level 0 search module and l L‑1 The processor bit width of the layer search module is W , and from l 1st level search module to l L‑2 The processor bit width corresponding to the layer search module is decreasing; the data to be compared is input into the tree structure search circuit to obtain the minimum value and the second minimum value to solve the existing QC‑LDPC The problem of high complexity of decoder hardware.

Description

Technical Field

[0001] The present application relates to the technical field of decoders, and in particular to an extreme value search method, a decoding method, a device and equipment in a decoder. Background Art

[0002] In digital integrated circuit design, especially in communication, storage and other related fields, forward error correction codes (FEC) are often needed to protect user data. Among them, quasi-cyclic low-density parity check (QC-LDPC) codes have been widely adopted for their excellent error correction performance and easy hardware implementation. How to make the QC-LDPC decoder achieve the peak rate specified by the protocol within an acceptable resource overhead has become a research hotspot in academia and industry. From the algorithm level, the decoding performance of hard decision is too low to give full play to the performance advantages of QC-LDPC codes. The traditional belief propagation (BP) decoding algorithm involves the calculation of complex hyperbolic tangent functions, which is not conducive to hardware implementation. The actual decoders used are basically based on the minimum sum (MS) and its improved algorithms, such as the normalized minimum sum (NMS) algorithm and the offset minimum sum (OMS) algorithm. The key to implementing the minimum sum algorithm is to search for the minimum value, the second minimum value, and the index value of the minimum value of the absolute size of the message transmitted by the variable node to the check node.

[0003] In terms of the parallelism of the implementation architecture, QC-LDPC decoders can be divided into three categories: serial, partial parallel, and full parallel. Serial means that the parallelism of the variable node (VN) and the check node (CN) is one. The parallelism of the fully parallel VN is equal to the code length, and the parallelism of CN is equal to the check bit length. The throughput of the serial structure is too low, and existing research basically focuses on partial parallelism and full parallelism. Partial parallelism can be further divided into row parallelism and block serial. The parallelism of the row parallel VN is equal to the code length, the parallelism of CN is equal to the lifting factor (LF) size, and the parallelism of the block serial VN and CN is LF. Generally speaking, the fully parallel structure has the smallest processing delay, the largest throughput, and the largest resource consumption. Because too many processing units will cause wiring congestion, the actual chip area is much higher than the normal corresponding number of logic gates. The block serial structure has the lowest resource consumption, but the delay and throughput are difficult to meet actual needs. The throughput and processing delay of row parallelism are considerable. If the implementation complexity can be optimized, it can be the best choice for high throughput.

[0004] In a general row-parallel decoder, the Check Node Processing Units (CNPU) occupy more than 30% of the resource area due to its high parallelism. Among them, searching for the minimum and second minimum values ​​of the VN update message accounts for most of the CNPU. Summary of the invention

[0005] In view of this, the embodiments of the present application provide an extremum search method, a decoding method, an apparatus and a device in a decoder, which can effectively solve the problems of high hardware complexity and low throughput of existing QC-LDPC decoders.

[0006] In a first aspect, an embodiment of the present application provides a maximum value search method in a decoder, comprising:

[0007] Determine the maximum number of inputs of the tree structure search circuit to be generated according to the base matrix of the decoder;

[0008] According to the maximum number of inputs, the tree structure search circuit is generated; wherein the tree structure search circuit includes multiple levels of nodes;

[0009] The multi-level nodes in the tree structure search circuit are divided into L Layer search module, L ≥2, wherein the first level corresponding to the input terminal in the tree structure search circuit is defined as l The last level of the output of the 0-layer search module is defined as lL-1 Layer search module;

[0010] Setting the l 0 layer search module and the l L-1 The processor bit width of the layer search module is W , and from l 1st level search module to l L-2 The processor bit width corresponding to the layer search module shows a decreasing trend;

[0011] The data to be compared with the maximum input number is input into the tree structure search circuit to obtain the minimum value and the second minimum value.

[0012] In some embodiments, the step of determining the maximum number of inputs of the tree structure search circuit to be generated according to the base matrix of the decoder includes:

[0013] In the base matrix, the number of non-negative elements in each row is determined respectively, and the largest one among the obtained multiple numbers of non-negative elements is selected as the maximum input number.

[0014] In some embodiments, the last level of the tree structure search circuit is a zero-filling module;

[0015] The zero-filling module l L-2 The processor width of the layer search module is restored to W .

[0016] In some embodiments, the multi-level nodes in the tree structure search circuit are divided into L Layer search module, including:

[0017] In the tree structure search circuit, multiple levels except the first and last levels are divided into search modules according to the hierarchical order and the relationship that the total number of levels included in the next search module is a preset multiple of the total number of levels included in the previous search module.

[0018] In some embodiments, the l 1st level search module to l L-2 The processor bit width corresponding to the layer search module is decreasing, including:

[0019] According to the set decreasing step size, the l 1st level search module to l L-2 The processor bit width corresponding to the layer search module decreases layer by layer, and the decreasing step length z Satisfy: 1≤ z ≤2 and (L -2) z < W .

[0020] In some embodiments, L The value is 4 or 5; the preset multiple y The value range is 1.0 ≤y≤ 3.0.

[0021] In some embodiments, generating the tree structure search circuit according to the maximum number of inputs includes:

[0022] Determine the number of minimum value comparison basic units according to the maximum number of inputs, and generate a minimum value comparison module according to at least one of the determined minimum value comparison basic units;

[0023] Determining the number of next-to-minimum value comparison units according to the number of outputs of the minimum value comparison module to generate a next-to-minimum value comparison module;

[0024] Connecting the output terminals of the minimum value comparison module except the output terminal corresponding to the minimum value to the corresponding input terminals of the second minimum value comparison module;

[0025] The output end of the second minimum value comparison module and the output end corresponding to the minimum value in the minimum value comparison module are connected to the zero filling module to obtain a tree structure search circuit.

[0026] In some embodiments, determining the number of minimum value comparison basic units according to the maximum number of inputs includes:

[0027] Describe the maximum number of inputs as a polynomial arranged in descending powers of 2;

[0028] Generate a minimum value comparison basic unit corresponding to an exponential level for each term in the polynomial;

[0029] Placing the minimum value comparison basic units corresponding to the exponential levels in parallel, and connecting the output ends of the minimum value comparison basic units corresponding to the exponential levels to other layers to continue comparison until the minimum value is obtained;

[0030] The composition of the minimum value comparison basic unit corresponding to the exponential level is expressed by the following formula:

[0031]

[0032] Among them, PRO o The index is o The minimum value of the item corresponding to the basic unit of comparison, PRO o-1 The index is o-1 corresponds to the minimum value comparison basic unit; CM2 represents the second comparator included in the tree structure search circuit, and MUX2 represents the selector included in the tree structure search circuit.

[0033] In a second aspect, an embodiment of the present application provides a decoding method of a decoder, wherein the decoder includes a tree structure search circuit, including:

[0034] The decoder performs decoding based on a minimum sum algorithm; wherein the minimum value and the second minimum value used in the minimum sum algorithm are obtained by using the maximum value search method in the decoder provided in the first aspect of the present application.

[0035] In some embodiments, the method further comprises:

[0036] The following formula is used to correct the message value passed from the check node to the variable node in the minimum sum algorithm to eliminate overestimation:

[0037]

[0038] in, Indicates the first k+ 1) Iteration, i The check node is passed to the j The message value of the variable node, MIN1 represents the minimum value, MIN2 represents the second minimum value, index MIN1 Indicates the minimum index number.

[0039] In a third aspect, an embodiment of the present application provides a maximum value search device in a decoder, comprising:

[0040] A number determination module, used to determine the maximum number of inputs of the tree structure search circuit to be generated according to the base matrix of the decoder;

[0041] A circuit generation module, used to generate a tree structure search circuit according to the maximum input number, the minimum value comparison basic unit and the second minimum value comparison basic unit; wherein the tree structure search circuit includes multiple levels of nodes;

[0042] A hierarchical division module is used to divide the multi-level nodes in the tree structure search circuit into L Layer search module, L ≥2, wherein the first level corresponding to the input terminal in the tree structure search circuit is defined as l The last level of the output of the 0-layer search module is defined as l L-1 Layer search module;

[0043] The bit width setting module is used to set the l Layer 0 search module and thel L-1 The processor bit width of the layer search module is W , and from l 1st level search module to l L-2 The processor bit width corresponding to the layer search module shows a decreasing trend;

[0044] The minimum value and the second minimum value output module is used to input the maximum input number of data to be compared into the tree structure search circuit to obtain the minimum value and the second minimum value.

[0045] In a fourth aspect, an embodiment of the present application provides a terminal device, comprising a processor and a memory, wherein the memory stores a computer program, and the processor is used to execute the computer program to implement a maximum value search method in a decoder provided in the first aspect of the present application.

[0046] The embodiments of the present application have the following beneficial effects:

[0047] The present application divides the multi-level nodes in the tree structure search circuit into L Layer search module, L ≥2, wherein the first level corresponding to the input terminal in the tree structure search circuit is defined as l The last level of the output of the 0-layer search module is defined as l L-1 Layer search module; settings l The processor bit width of the layer 0 search module is W , from l 1st level search module to l L-2 The processor bit width corresponding to the layer search module is decreasing to reduce the occupied resources; l L-1 The layer search module reconstructs the resolution of the processor bit width of the previous layer search module to restore the processor bit width to W , to perform over-estimation optimization. Therefore, the present application can effectively solve the problems of high hardware complexity and low throughput of the existing QC-LDPC decoder. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0049] Figure 1A structural schematic diagram of a basic comparator CM1 of a tree structure search circuit in a maximum value search method in a decoder according to an embodiment of the present application is shown;

[0050] Figure 2 A structural schematic diagram of a basic comparator CM2 of a tree structure search circuit in a maximum value search method in a decoder according to an embodiment of the present application is shown;

[0051] Figure 3 A schematic diagram of the structure of a two-to-one selector MUX2 of a tree structure search circuit in a maximum value search method in a decoder according to an embodiment of the present application is shown;

[0052] Figure 4 A schematic diagram showing a flow chart of a maximum value search method in a decoder according to an embodiment of the present application;

[0053] Figure 5 The maximum value search method in the decoder of the present application embodiment is shown. o Level minimum comparison basic unit PRO o A schematic diagram of

[0054] Figure 6 The maximum value search method in the decoder of the present application embodiment is shown. o Level minimum comparison basic unit PRO o Another schematic diagram of ;

[0055] Figure 7 A schematic diagram of a check matrix base matrix in a maximum value search method in a decoder in an embodiment of the present application is shown;

[0056] Figure 8 A schematic diagram of a tree structure search circuit in a maximum value search method in a decoder according to an embodiment of the present application is shown;

[0057] Fig. 9 A schematic diagram of a row parallel architecture mentioned in the maximum value search method in the decoder of the embodiment of the present application is shown;

[0058] Fig.10 A row parallel timing diagram mentioned in the maximum value search method in the decoder of the embodiment of the present application is shown;

[0059] Fig.11 A structural schematic diagram of a maximum value search device in a decoder according to an embodiment of the present application is shown.

[0060] Description of main component symbols:

[0061] 1010 - number determination module; 1020 - circuit generation module; 1030 - level division module; 1040 - bit width setting module; 1050 - minimum value and second minimum value output module. DETAILED DESCRIPTION

[0062] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0063] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0064] Hereinafter, the terms "including", "having" and their cognates that can be used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or a combination of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or a combination of the foregoing items or increasing the possibility of one or more features, numbers, steps, operations, elements, components or a combination of the foregoing items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.

[0065] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.

[0066] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0067] In the prior art, the Check Node Processing Units (CNPU) in the decoder with a parallel structure occupy a large resource area due to its high parallelism, among which the search for the minimum and second minimum values ​​of the VN update message accounts for most of the CNPU. Therefore, the present application proposes a maximum value search method, decoding method, device and equipment in the decoder, which can effectively solve the problems of high hardware complexity, low throughput and large resource occupation of the search for the minimum and second minimum values ​​of the VN update message in the existing QC-LDPC decoder.

[0068] The present application is based on a tree structure search circuit to calculate the minimum value and the second minimum value. The tree structure search circuit is a tree comparison network, which can achieve the optimal hardware complexity. However, in order to ensure the error correction performance of the decoder, the tree structure search circuit needs to ensure a certain resolution, which naturally limits the reduction of hardware complexity. Based on this, the present application proposes a minimum and second minimum value search method for a mixed resolution of a row parallel QC-LDPC decoder, that is, the maximum value search method in the decoder of the present application. The method includes:

[0069] 1) First, determine the maximum number of inputs of the search circuit based on the maximum row weight of the check matrix.

[0070] 2) Build a tree structure search circuit. The tree structure search circuit includes two basic comparators CM1 (first comparator), CM2 (second comparator), a zero padding module (Zeros Padding, ZP) and a two-choice selector MUX2. Figure 1 As shown, CM2 Figure 2 As shown, MUX2, such as Figure 3 As shown. For CM1 and CM2, if A>B, C =1, otherwise, if A≤B, then C =0. For MUX2: If C =0, then output A, otherwise, if C = 1, output B. The tree structure search circuit can reuse the intermediate comparison result obtained by calculating the minimum value, and use the comparison result as a candidate object for calculating the next minimum value, thereby reducing the number of comparators. Specifically, the tree structure search circuit first uses the search unit composed of CM2 and MUX2 to search for the minimum value among the input multiple data to be compared, and obtains several candidate objects at the same time, and then uses the search unit composed of CM1 to search for the next minimum value among the several candidate objects.

[0071] 3) Apply mixed resolution based on the tree structure search circuit to reduce resource overhead and shorten the critical path.

[0072] The maximum value search method in the decoder is described below in conjunction with some specific embodiments.

[0073] Figure 4 A flow chart of a method for searching an extreme value in a decoder according to an embodiment of the present application is shown. Exemplarily, the method for searching an extreme value in a decoder includes the following steps:

[0074] S10, determining the maximum number of inputs of the tree structure search circuit to be generated according to the base matrix of the decoder.

[0075] The size of the basis matrix H of the QC-LDPC code is defined as M × N , the quantization bit width of the information transmitted from the variable node VN to the check node CN is W .

[0076] Determine the maximum number of inputs to the search circuit K : The number of columns of the basis matrix N It can be seen that each verification node CN can be connected to at most N variable node VN.

[0077] Furthermore, considering resource minimization, the step S10 of determining the maximum number of inputs of the tree structure search circuit to be generated according to the base matrix of the decoder includes:

[0078] In the base matrix, the number of non-negative elements in each row is determined, and the largest number of non-negative elements is selected from the obtained multiple numbers of non-negative elements as the maximum input number. K . Count the number of non-negative elements in each row, get a corresponding number of non-negative elements for each row, and select the largest number from them. The specific calculation formula is as follows:

[0079]

[0080] in, h m,n is the basis matrix H m OK n The value of the column.

[0081] S20, generating the tree structure search circuit according to the maximum number of inputs, wherein the tree structure search circuit includes multiple levels of nodes.

[0082] The step S20 of generating the tree structure search circuit according to the maximum number of inputs includes:

[0083] S21, determining the number of minimum value comparison basic units according to the maximum number of inputs, and generating the minimum value comparison module according to at least one of the determined minimum value comparison basic units;

[0084] S22, determining the number of next-to-minimum value comparison units according to the number of outputs of the minimum value comparison module to generate a next-to-minimum value comparison module;

[0085] S23, connecting the output terminals of the minimum value comparison module except the output terminal corresponding to the minimum value to the corresponding input terminals of the second minimum value comparison module;

[0086] S24, connecting the output end of the second minimum value comparison module and the output end corresponding to the minimum value in the minimum value comparison module to the zero filling module. The tree structure search circuit also includes a zero filling module to obtain a tree structure search circuit.

[0087] Determining the number of minimum value comparison basic units according to the maximum number of inputs in step S21 includes:

[0088] S211, describing the maximum input number as a polynomial arranged in descending powers of data 2.

[0089] The specific steps are as follows: K It is expressed in the form of accumulation of exponential powers of 2 (that is, the maximum input number is written as a polynomial of descending powers of 2), as shown in the following formula:

[0090]

[0091] in, K is the maximum number of inputs, t is the maximum power value. Figure 5 As shown, for each power value o You can use the corresponding PRO o Basic unit find 2 o The minimum value MIN1 in the input data and the candidate second minimum values ​​are compared and finally at least one CM1 is used to compare and select the second minimum value MIN2 from the candidate values ​​of the second minimum value.

[0092] S212, generating an exponentially corresponding minimum value comparison basic unit PRO for each term in the polynomial o , o The exponent representing the power.

[0093] S213, compare the minimum values ​​corresponding to the exponential levels of each item with the basic unit PRO o Placed in parallel, and compare the minimum values ​​corresponding to each of the index levels to the basic unit PRO o The output of is then connected to other layers to continue the comparison until the minimum value is obtained.

[0094] S214, the minimum value comparison basic unit PRO corresponding to the exponential levelo The composition of is expressed by the following formula:

[0095]

[0096] Among them, the minimum comparison basic unit PRO o Included o Comparison level; PRO o The index is o The minimum value of the item corresponding to the basic unit of comparison, PRO o-1 The index is o -1 corresponding to the minimum value comparison basic unit; CM2 represents the second comparator included in the tree structure search circuit, and MUX2 represents the two-to-one selector included in the tree structure search circuit. Specifically, Figure 6 As shown:

[0097] The 1-level minimum comparison basic unit PRO1 includes 1·CM2 (1 second comparator);

[0098] 2-level minimum comparison basic unit PRO2 includes 2·PRO1+1·CM2+( t -1) MUX2;

[0099] 3-level minimum comparison basic unit PRO3 includes 2·PRO2+1·CM2+( t -1)·MUX2.

[0100] For example o is 3, then the specific tree structure search circuit is as follows Figure 6 As shown. At the same time, the comparison results generated by CM2 C 00 , C 01 , C 02 , C 03 , C 10 , C 11 and C 20 Get the position index of the minimum value through MUX2 index (MIN1).

[0101] The o-level minimum value comparison basic unit PRO corresponding to each term in the polynomial o Together they form a minimum value comparison module.

[0102] S30, dividing the multi-level nodes in the tree structure search circuit into L Layer search module, L≥2, wherein the first level corresponding to the input terminal in the tree structure search circuit is defined as l The last level of the output of the 0-layer search module is defined as l L-1 Layer search module.

[0103] S40, setting the l Layer 0 search module and the l L-1 The processor bit width of the layer search module is W , and from l 1st level search module to l L-2 The processor bit width corresponding to the layer search module is decreasing; that is to say, l L-1 The layer search module reconstructs the resolution of the processor bit width of the previous layer search module to restore the processor bit width to W .

[0104] The last level of the tree structure search circuit is a zero-filling module. l L-2 The processor width of the layer search module is restored to W That is to say, l L-2 The layer search module uses the zero filling module to reconstruct the resolution of the processor bit width of the previous layer search module to restore the processor bit width to W . The output bit width of the second-to-last layer is restored to W .

[0105] In one embodiment, in step S30, the multi-level nodes in the tree structure search circuit are divided into L Layer search module, including:

[0106] In the tree structure search circuit, multiple intermediate levels except the first level and the last level are divided into search modules according to the hierarchical order and the relationship that the total number of levels included in the next search module is a preset multiple of the total number of levels included in the previous search module. Preferably, the preset multiple y The value range is 1.0≤ y ≤3.0. That is, the total number of levels contained in the next-level search module is about twice the total number of levels contained in the previous-level search module.

[0107] In step S40, the l 1st level search module to l L-2 The processor bit width corresponding to the layer search module is decreasing, including:

[0108] According to the set decreasing step size, the l 1st level search module to l L-2 The processor bit width corresponding to the layer search module decreases layer by layer, and the decreasing step length z Satisfy: 1≤ z ≤2 and ( L -2) z < W。 That is to say, each layer decreases by 1 or 2 bits.

[0109] Further, according to performance requirements, preferably, L The value is 4 or 5. If it is too large, the minimum value will be overcorrected, which will have a significant impact on the decoding performance.

[0110] First floor l 0 and the last layer l L-1 Only one level of comparator is covered, and the processing bit width is W . l The processing bit width of the 0-layer comparator is W This is to ensure the accuracy of the search results as much as possible and avoid the position of the minimum value deviating from the position due to changes in resolution. l L-1 The layer uses ZP to convert the bit width of the previous stage ( W - L +2) Reconstruct the resolution and restore it to W , ensuring that the decoding performance will not be significantly degraded, and at the same time completing the correction of the overestimation of the minimum sum algorithm, as shown in the following formula:

[0111]

[0112] in, Indicates the first k+ 1) Iteration, i The check node is passed to the j The message value of the variable node, CN i Pass to VN j message value, MIN1 represents the minimum value, MIN2 represents the second minimum value, index MIN1 Indicates the minimum index number. l 1st floor to l L-2 The resolution is reduced by gradually reducing the processing bit width by 1 bit to save hardware resources.

[0113] S50, inputting the maximum number of input data to be compared into the tree structure search circuit to obtain the minimum value and the second minimum value.

[0114] The following is a specific example to illustrate the maximum value search method in the decoder of the present application:

[0115] like Figure 7 As shown, taking the base matrix with a code length of 1296 bits and a code rate of 5 / 6 in the IEEE 802.11 series protocols as an example, there are 4 rows and 24 columns, and the corresponding LF size is 54.

[0116] S110, determining the maximum number of inputs of the tree structure search circuit K .Depend on Figure 7 From the basis matrix shown in FIG, it can be seen that the number of VNs connected to the CNs of the 0th to 3rd layers (each check block CNs contains a total of 54 CNs) are 21, 21, 22, and 21 respectively, so the maximum number of inputs of the tree structure search circuit is 22.

[0117] S120, generating a tree structure of a search circuit. The maximum number of inputs ("22") is expressed as the sum of polynomials of powers of 2, as shown in the following formula:

[0118]

[0119] Among them, the power value o They are 4, 2 and 1 respectively. l Level 0 search module and l The unit combination of the 1-layer search module is PRO4, PRO2 and PRO1, such as Figure 8 As shown. The combination of PRO2 and PRO1 can refer to the combination of PRO3, and the output x 16 arrive x 21 The minimum value and 3 candidate next minimum values, this step consumes 5 CM2 and 2 MUX2. x 0 to x 15 The minimum value and 4 candidate next minimum values ​​are obtained. This step consumes the standard 15 CM2s and 11 MUX2s. Further, the results of PRO4, PRO2 and PRO1 are compared to obtain x 0 to x 21 This step consumes 1 CM2, 4 CM1s and 3 MUX2s.

[0120] S130, applying a mixed resolution solution. Figure 8 As shown, assuming that the input bit width of the tree structure search circuit is w=7, that is, the quantization bit width of the message transmitted by VN to CN is 8 (the absolute value needs to remove the sign bit), then the CM2 of the first level of the tree structure search circuit is l The 0-layer search module maintains the quantization bit width of 7 to ensure the accuracy of the search results. The second and third levels of CM2 l 1-layer search module, the quantization bit width is 6, that is, l The high 6 bits of the output are 0 as l Input of the search module at level 1. CM2 at level 4 and level 5 and all CM1s l 2, the quantization bit width is 5, and the same l The high 5 bits of the output of the layer 1 search module are used as input. l The 3-layer search module will start from l MIN1 of the 2nd layer search module input w-2 and MIN2 w-2 The tail of is padded with 2 bits of zero to re-form a 7-bit output, completing the reconstruction of the resolution and correcting the overestimation of the minimum sum algorithm. x 0~ x 15 are 40, 8, 34, 47, 64, 46, 47, 42, 17, 22, 13, 17, 55, 21, 24, 26, 23, 11, 45, 60, 31, 10, then the output MIN1 is 8, MIN2 is 8, index MIN1 is 1.

[0121] The position of this application in the QC-LDPC row parallel decoder is as follows Fig. 9 As shown in Figure 1, each check node block CNs connects 22 variable node blocks VNs through a configurable routing network. The number of nodes in CNs depends on the size of LF. Figure 7 Taking the basis matrix shown in the figure as an example, LF = 54. Memory Q Store the posterior probability value of the codeword, memory R Stores the message value passed by CN to VN. Message t 0~ t 21 The message value passed to the VN connected to the first CN in this check node block. t 0~ t 21 After passing through the absolute value module ABS, it is sent to the mixed resolution search circuit (a tree structure search circuit after dividing the levels and setting the processor bit width), and the minimum value MIN1 is given by the tree structure search circuit w , the corresponding index value index MIN1 w and the next minimum value MIN2 wThe subsequent modules combine the results of the search module with the message t Completion Message r And the posterior probability q The update is written into the corresponding memory R and Q In order to overcome the data dependency problem of row-parallel decoders, multiple codewords are usually used in an alternating pipeline, such as Fig.10 As shown. VNP (Variable Node Processing) represents variable node processing, which completes VN message update and codeword posterior probability update, SMP (Search Module Processing) represents search processing, and the hybrid resolution search circuit completes the search and over-estimation correction, and CNP (Check Node Processing) represents check node processing, which completes CN message update. In short, this application has extremely low hardware complexity, comes with a minimum sum algorithm correction process, shortens the critical path length, and is particularly suitable for high operating frequency and high throughput application scenarios; in addition, the minimum value position can also be given at the same time.

[0122] An embodiment of the present application provides a decoding method of a decoder. Exemplarily, the decoder includes a tree structure search circuit, and the decoder performs decoding based on a minimum sum algorithm; wherein the minimum value and the second minimum value used in the minimum sum algorithm are obtained by using an extreme value search method in the decoder of the embodiment of the present application.

[0123] In some embodiments, the decoding method further includes:

[0124] The following formula is used to correct the message value passed from the check node to the variable node in the minimum sum algorithm to eliminate overestimation:

[0125]

[0126] in, It represents the message value passed by the i-th check node to the j-th variable node in the (k+1)th iteration. MIN1 represents the minimum value, MIN2 represents the second minimum value, and indexMIN1 represents the minimum value index number.

[0127] It can be understood that the device of this embodiment corresponds to the maximum value searching method in the decoder of the above embodiment, and the options in the above embodiment are also applicable to this embodiment, so they will not be described repeatedly here.

[0128] The present application also provides a maximum value search device in a decoder. For example, Fig.11As shown, the maximum value searching device in the decoder includes: a number determining module 1010, a circuit generating module 1020, a hierarchy dividing module 1030, a bit width setting module 1040 and a minimum value and a second minimum value output module 1050.

[0129] The number determination module 1010 is used to determine the maximum number of inputs of the tree structure search circuit to be generated according to the base matrix of the decoder;

[0130] The circuit generation module 1020 is used to generate a tree structure search circuit according to the maximum input number, the minimum value comparison basic unit and the second minimum value comparison basic unit; wherein the tree structure search circuit includes multiple levels of nodes;

[0131] The hierarchical division module 1030 is used to divide the multi-level nodes in the tree structure search circuit into L Layer search module, L ≥2, wherein the first level corresponding to the input terminal in the tree structure search circuit is defined as l The last level of the output of the 0-layer search module is defined as l L-1 Layer search module;

[0132] The bit width setting module 1040 is used to set the l Layer 0 search module and the l L-1 The processor bit width of the layer search module is W , and from l 1st level search module to l L-2 The processor bit width corresponding to the layer search module shows a decreasing trend;

[0133] The minimum value and the second minimum value output module 1050 is used to input the maximum number of input data to be compared into the tree structure search circuit to obtain the minimum value and the second minimum value.

[0134] It can be understood that the device of this embodiment corresponds to the maximum value searching method in the decoder of the above embodiment, and the options in the above embodiment are also applicable to this embodiment, so they will not be described repeatedly here.

[0135] The present application also provides a terminal device. Exemplarily, the terminal device includes a processor and a memory, wherein the memory stores a computer program, and the processor runs the computer program to enable the terminal device to execute the functions of the various modules in the above-mentioned maximum value search method in the decoder or the above-mentioned maximum value search device in the decoder.

[0136] Among them, the processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including a central processing unit (CPU), a graphics processing unit (GPU), a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or at least one of other programmable logic devices, discrete gates or transistor logic devices, and discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc., which can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present application.

[0137] The memory may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electric erasable programmable read-only memory (EEPROM), etc. The memory is used to store a computer program, and the processor may execute the computer program accordingly after receiving an execution instruction.

[0138] The present application also provides a readable storage medium for storing the computer program used in the above-mentioned terminal device.

[0139] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or the flow diagram, and the combination of boxes in the structure diagram and / or the flow diagram, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0140] In addition, the functional modules or units in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0141] If the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program code.

[0142] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A method for searching for an extreme value in a decoder, characterized in that: include: Determine the maximum number of inputs of the tree structure search circuit to be generated according to the base matrix of the decoder; According to the maximum number of inputs, the tree structure search circuit is generated; wherein the tree structure search circuit includes multiple levels of nodes; The multi-level nodes in the tree structure search circuit are divided into L Layer search module, L ≥2, wherein the first level corresponding to the input terminal in the tree structure search circuit is defined as l The last level of the output of the 0-layer search module is defined as l L-1 Layer search module; Setting the l 0 layer search module and the l L-1 The processor bit width of the layer search module is W , and from l 1st level search module to l L-2 The processor bit width corresponding to the layer search module shows a decreasing trend; The data to be compared with the maximum input number is input into the tree structure search circuit to obtain the minimum value and the second minimum value.

2. The method for searching the maximum value in a decoder according to claim 1, characterized in that: The step of determining the maximum number of inputs of the tree structure search circuit to be generated according to the base matrix of the decoder comprises: In the base matrix, the number of non-negative elements in each row is determined respectively, and the largest one among the obtained multiple numbers of non-negative elements is selected as the maximum input number.

3. The method for searching the maximum value in a decoder according to claim 1, characterized in that: The last level of the tree structure search circuit is a zero-filling module; The zero-filling module l L-2 The processor width of the layer search module is restored to W .

4. The method for searching the maximum value in a decoder according to claim 3, characterized in that: The multi-level nodes in the tree structure search circuit are divided into L Layer search module, include: In the tree structure search circuit, multiple intermediate levels except the first and last levels are divided into search modules according to the hierarchical order and the relationship that the total number of levels included in the next search module is a preset multiple of the total number of levels included in the previous search module.

5. The method for searching the maximum value in a decoder according to claim 1, characterized in that: Said from l 1st level search module to l L-2 The processor bit width corresponding to the layer search module is decreasing, including: According to the set decreasing step size, the l 1st level search module to l L-2 The processor bit width corresponding to the layer search module decreases layer by layer, and the decreasing step length z satisfies: 1≤ z ≤2 and ( L -2) z < W .

6. The method for searching the maximum value in a decoder according to claim 4, characterized in that: L The value is 4 or 5; the preset multiple y The value range is 1.0≤ y ≤3.

0.

7. The method for searching the maximum value in a decoder according to claim 3, characterized in that: The step of generating the tree structure search circuit according to the maximum number of inputs comprises: Determine the number of minimum value comparison basic units according to the maximum number of inputs, and generate a minimum value comparison module according to at least one of the determined minimum value comparison basic units; Determining the number of next-to-minimum value comparison units according to the number of outputs of the minimum value comparison module to generate a next-to-minimum value comparison module; Connecting the output terminals of the minimum value comparison module except the output terminal corresponding to the minimum value to the corresponding input terminals of the second minimum value comparison module; The output end of the second minimum value comparison module and the output end corresponding to the minimum value in the minimum value comparison module are connected to the zero filling module to obtain a tree structure search circuit.

8. The method for searching for an extreme value in a decoder according to claim 7, wherein: The step of determining the number of minimum value comparison basic units according to the maximum number of inputs includes: Describing the maximum number of inputs by a polynomial arranged in descending powers of 2; Generate a minimum value comparison basic unit corresponding to an exponential level for each term in the polynomial; Placing the minimum value comparison basic units corresponding to the exponential levels in parallel, and connecting the output ends of the minimum value comparison basic units corresponding to the exponential levels to other layers to continue comparison until the minimum value is obtained; The composition of the minimum value comparison basic unit corresponding to the exponential level is expressed by the following formula: Among them, PRO o The index is o The minimum value of the item corresponding to the basic unit of comparison, PRO o-1 The index is o- 1 corresponds to the minimum value comparison basic unit; CM2 represents the second comparator included in the tree structure search circuit, and MUX2 represents the selector included in the tree structure search circuit.

9. A decoding method of a decoder, wherein the decoder comprises a tree structure search circuit, characterized in that: The decoder performs decoding based on a minimum sum algorithm; wherein the minimum value and the second minimum value used in the minimum sum algorithm are obtained by using the maximum value search method in the decoder as described in any one of claims 1 to 8.

10. The decoding method according to claim 9, characterized in that: The method further comprises: The following formula is used to correct the message value transmitted by the check node to the variable node in the minimum sum algorithm: in, Indicates the first k+ 1) Iteration, i The check node is passed to the j The message value of the variable node, MIN1 represents the minimum value, MIN2 represents the second minimum value, index MIN1 Indicates the minimum index number.

11. An extremum search device in a decoder, characterized in that: include: A number determination module, used to determine the maximum number of inputs of the tree structure search circuit to be generated according to the base matrix of the decoder; A circuit generation module, used to generate a tree structure search circuit according to the maximum input number, the minimum value comparison basic unit and the second minimum value comparison basic unit; wherein the tree structure search circuit includes multiple levels of nodes; A hierarchical division module is used to divide the multi-level nodes in the tree structure search circuit into L Layer search module, L ≥2, wherein the first level corresponding to the input terminal in the tree structure search circuit is defined as l The last level of the output of the 0-layer search module is defined as l L-1 Layer search module; The bit width setting module is used to set the l 0 layer search module and the l L-1 The processor bit width of the layer search module is W , and from l 1st level search module to l L-2 The processor bit width corresponding to the layer search module shows a decreasing trend; The minimum value and the second minimum value output module is used to input the maximum input number of data to be compared into the tree structure search circuit to obtain the minimum value and the second minimum value.

12. A terminal device, characterized in that: The terminal device comprises a processor and a memory, wherein the memory stores a computer program, and the processor is used to execute the computer program to implement the maximum value search method in the decoder according to any one of claims 1 to 8.

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