Method of stripping and cleaning a semiconductor structure

Abstract

Methods for removing oxide films and for cleaning silicon-on-insulator structures are disclosed. The methods can involve immersing the silicon-on-insulator structure in a stripping bath to strip an oxide film from a surface of the silicon-on-insulator structure. The stripped silicon-on-insulator structure is immersed in an ozone bath comprising ozone. The ozone-treated silicon-on-insulator structure can be immersed in an SC-1 bath comprising ammonium hydroxide and hydrogen peroxide to clean the structure.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to U.S. nonprovisional patent application No. 17 / 670,167, filed February 11, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to methods for removing oxides from silicon-on-insulator (SOI) structures and for cleaning such structures. Background Technology

[0004] For example, a semiconductor structure of silicon-on-insulator (“SOI” structure) may undergo annealing before downstream processing. This annealing can result in the formation of oxide (SiO2) on the surface of the SOI structure. This oxide is typically removed from the top surface of the structure. During the cleaning of the structure after the oxide is removed, some areas on the surface of the SOI structure form protrusions or “bumps” on the wafer surface. Previous attempts to remove these bumps, for example, by increasing the stripping process time, have not successfully eliminated their formation.

[0005] There is a need for methods for reducing or eliminating protrusions from the surface of an SOI structure, for removing oxides from the top surface of the SOI structure, and for cleaning the structure.

[0006] This section aims to introduce the reader to various technical aspects that may relate to the various aspects of this disclosure described and / or claimed below. This discussion is intended to help provide the reader with background information to facilitate a better understanding of the various aspects of this disclosure. Accordingly, it should be understood that these statements should be interpreted in this light and not as an admission of prior art. Summary of the Invention

[0007] One aspect of this disclosure relates to a method for stripping and cleaning the surface of a silicon-on-insulator (SOS) structure. The SOS structure includes a treatment structure, a silicon top layer, and a dielectric layer disposed between the treatment structure and the silicon top layer. The SOS structure has an oxide film on its top surface. The SOS structure is immersed in a stripping bath to remove the oxide film from the surface of the SOS structure and prepare a stripped SOS structure. The stripping bath contains hydrofluoric acid and a surfactant. The stripped SOS structure is immersed in an ozone bath containing ozone to prepare an ozone-treated SOS structure. The ozone-treated SOS structure is immersed in an SC-1 bath containing ammonium hydroxide and hydrogen peroxide to prepare an SC-1-treated SOS structure.

[0008] Various modifications exist to the features described in the foregoing aspects of this disclosure. Further features may also be incorporated into the foregoing aspects of this disclosure. These modifications and additional features may exist individually or in any combination. For example, various features discussed below with respect to any of the illustrated embodiments of this disclosure may be incorporated individually or in any combination into any of the foregoing aspects of this disclosure. Attached Figure Description

[0009] Figure 1 It is a cross-sectional view of a donor structure having a donor wafer and a dielectric layer thereon;

[0010] Figure 2 This is a cross-sectional view of the donor structure during ion implantation;

[0011] Figure 3 It is a cross-sectional view of the donor structure joined to the treatment structure;

[0012] Figure 4 This is a cross-sectional view of the bonded wafer structure when the donor structure is split at the splitting plane.

[0013] Figure 5 It is a method used to remove oxides and clean silicon structures on insulators;

[0014] Figure 6 This is another embodiment of a method for removing oxides and cleaning silicon structures on insulators;

[0015] Figure 7 This is another embodiment of a method for removing oxides and cleaning silicon structures on insulators;

[0016] Figure 8 This is a reproduction of AFM images of nanoscale defects formed in conventional methods used to remove oxides and clean silicon structures on insulators; and

[0017] Figure 9 It is a display Figure 8 The chart shows the height of the defects.

[0018] The diagram runs through the entire structure, with corresponding component symbols indicating the relevant parts. Detailed Implementation

[0019] This disclosure provides a method for stripping and cleaning the surface of a semiconductor structure. In some embodiments, oxides (e.g., SiO2) are removed from the surface of the semiconductor structure by immersing it in a stripping bath comprising hydrofluoric acid and a surfactant. After stripping, the semiconductor structure is immersed in a bath comprising ozone before subsequent cleaning operations to remove defects (e.g., nanoscale defects) to prevent these defects from acting as etching masks, thereby forming protrusions on the surface of the semiconductor structure.

[0020] The method is generally applicable to removing oxide from any semiconductor structure (e.g., a single layer or a bonded structure), such as any bonded wafer structure in which it is desirable to remove an oxide film. The cleaned semiconductor structure according to embodiments of this disclosure has a front surface, a back surface, circumferential edges, and a central axis. The semiconductor structure can be of any diameter suitable for use by those skilled in the art, including substrates with diameters of, for example, about 200 mm, about 300 mm, greater than about 300 mm, or even about 450 mm.

[0021] In some embodiments, the structure being processed may be a silicon-on-insulator (SBI) structure. Such a structure may include a disposal wafer, a silicon layer (sometimes referred to as a “silicon device layer” or “silicon top layer”), and a dielectric layer disposed between the disposal wafer and the silicon layer. The following is merely one example of a method for fabricating a SBI structure, and other methods may be used unless otherwise stated.

[0022] Figure 1 An example of a donor structure 30 that can be bonded to a disposal structure to form a bonded wafer structure is shown. The donor structure 30 may be formed with a dielectric layer 15 deposited on the front surface of the donor wafer 12. It should be understood that, alternatively, the dielectric layer 15 may be grown or deposited on the disposal wafer or on both the donor wafer and the disposal wafer, and these structures can be bonded in any of a variety of arrangements without limitation. A suitable donor wafer 12 may be composed of silicon, germanium, silicon-germanium, gallium nitride, aluminum nitride, gallium arsenide, indium gallium arsenide, and any combination thereof. In some embodiments, the donor wafer is composed of single-crystal silicon.

[0023] The dielectric layer 15 can be any electrically insulating material suitable for use in an SOI structure, such as materials including SiO2, Si3N4, aluminum oxide, or magnesium oxide. In some embodiments, the dielectric layer 15 is SiO2 (i.e., the dielectric layer is essentially composed of SiO2). In embodiments where the dielectric layer is silicon dioxide (SiO2), the dielectric layer is sometimes referred to as a “buried oxide” or “BOX” layer 15. The dielectric layer 15 can be applied according to any technique known in the art, such as thermal oxidation, wet oxidation, thermal nitriding, or a combination of these techniques.

[0024] For example Figure 2As shown, ions (e.g., hydrogen atoms, helium atoms, or combinations of hydrogen and helium atoms) can be implanted at a generally uniform, designated depth below the front surface 22 of the donor structure to define a cleaving plane 17. It should be noted that when helium and hydrogen ions are co-implanted into the structure to form the cleaving plane 17, the helium and hydrogen ions can be implanted simultaneously or sequentially. In some embodiments, the ions are implanted prior to the deposition of the dielectric layer 15. When implantation is performed prior to the deposition of the dielectric layer 15, subsequent growth or deposition of the dielectric layer on the donor wafer 12 is appropriately performed at a sufficiently low temperature to prevent premature separation or cleavage along the plane 17 in the donor layer (i.e., prior to the wafer bonding process step).

[0025] Disposal Structure 10 ( Figure 3 The treatment structure 10 may include a treatment wafer obtained from any suitable material used for fabricating multilayer structures, such as silicon, silicon carbide, sapphire, germanium, silicon-germanium, gallium nitride, aluminum nitride, gallium arsenide, indium gallium arsenide, quartz, and combinations thereof. The treatment structure 10 may include a dielectric layer deposited on the treatment wafer, or, as in other embodiments, may consist solely of the treatment wafer (i.e., without a dielectric layer). The treatment wafer and donor wafer may be single-crystal silicon wafers and may be single-crystal silicon wafers diced from a single-crystal ingot grown according to the conventional Chuklaski crystal growth method.

[0026] like Figure 3 As shown, the front surface of the dielectric layer 15 of the donor structure is suitably bonded to the front surface of the disposal structure 10 to form a bonded wafer structure 20 by a bonding process. The dielectric layer 15 and the disposal structure 10 can be bonded together while surface activation is performed by exposing the surfaces of the structures to a plasma containing, for example, oxygen or nitrogen. The wafers are then pressed together and a bond is formed therebetween at the bonding interface 18. Generally, wafer bonding can be achieved essentially using any technique known in the art, provided that the energy used to achieve the formation of the bonding interface is sufficient to ensure the integrity of the bonding interface is maintained during subsequent processing (i.e., layer transfer by separation along the cleaving or separating plane 17 in the donor wafer).

[0027] Once prepared, the bonded wafer structure 20 is placed in a cleaving apparatus to separate (i.e., cleave) a portion of the donor wafer along a cleaving plane to form a layered semiconductor structure (e.g., an SOI structure). Generally, the cleaving apparatus can use techniques known in the art, such as thermal and / or mechanically induced cleaving techniques, to induce this fracture.

[0028] refer to Figure 4 During separation, two structures 30 and 31 are formed. This is because the separation of the bonded wafer structure 20 occurs along the cleaving plane 17 in the donor structure 12. Figure 3Therefore, a portion of the donor structure retains a portion of both structures (i.e., a portion of the donor wafer is transferred together with dielectric layer 15). Structure 30 includes a portion of the donor wafer. Structure 31 is an SOI structure and includes disposal structure 10, dielectric layer 15, and a silicon top layer 25 disposed on top of dielectric layer 15 (the portion of the donor wafer retained after cleaving). In embodiments where both the donor structure and disposal structure include dielectric layers, the dielectric layers are combined to form dielectric layer 15 of the SOI structure.

[0029] A splitting device used to separate bonded wafer structures along a splitting plane can be a mechanical splitting device in which separation is induced or achieved solely by mechanical force or as a supplement to annealing. For example, the bonded structure can be placed in a jig, in which a mechanical force is applied perpendicular to the opposite side of the bonded structure to pull a portion of the donor structure away from the bonded structure.

[0030] The example cleaving device includes a chuck that applies mechanical force near the front cleaving edge of the bonded wafer structure 20. Separation of the portion of the donor wafer can be initiated by applying a mechanical wedge or blade at the edge of the bonded wafer at the cleaving plane 17 to initiate the propagation of a crack along the cleaving plane 17. The mechanical force applied by the chuck then pulls the portion of the donor structure from the bonded structure, thus forming an SOI structure. The mechanical cleaving device is commercially available, such as Debond & Cleave Tools from Silicon Genesis Corporation (San Jose, California).

[0031] In an alternative embodiment, the splitting device is a thermal splitting device, wherein splitting is achieved by annealing the bonded structure. For example, thermal splitting can be performed for a period of at least about 10 seconds, at least about 1 minute, at least about 15 minutes, at least about 1 hour, or even at least about 3 hours under an inert (e.g., argon or nitrogen) atmosphere or ambient conditions at temperatures from about 200°C to about 800°C or from about 250°C to about 650°C (the higher the temperature, the shorter the annealing time required, and vice versa). The thermal splitting device can be a strip furnace, wherein the propagation of splitting is achieved at the leading edge of the bonded structure (i.e., the leading edge in the direction of travel of the structure through the furnace) and continues toward the trailing edge of the bonded wafer structure. Other types of splitting devices may also be used.

[0032] The layers of SOI structure 31 (disposal structure 10, dielectric layer 15, and silicon top layer 25) may typically have any thickness that allows the layers to function as described herein. In some embodiments, the silicon top layer 25 is relatively thin (e.g., about 0.1 μm to about 0.3 μm thick), and the dielectric layer 15 is relatively thick (about 1.0 μm or more).

[0033] The methods for generating SOI structures described herein are instance methods, and other methods may be used without departing from the scope of this disclosure.

[0034] For reference Figure 5 This illustrates method 100 of the present disclosure. While the methods of the present disclosure may be described herein with reference to silicon-on-insulator structures, other semiconductor structures may be processed by the disclosed methods in some embodiments. In a first step 110, silicon-on-insulator structure 101 is immersed in a stripping bath to remove oxides (e.g., SiO2) from the top surface of silicon-on-insulator structure 101 and to prepare a stripped silicon-on-insulator structure 112. The stripping bath comprises hydrofluoric acid and a surfactant. In some embodiments, the surfactant is a nonionic surfactant. In some embodiments, the nonionic surfactant comprises an ether group. In some embodiments, the ether surfactant is a polyoxyethylene alkyl ether. Commercially available ether surfactants include the TRITON X series (Dow Chemical Company (Midland, MI)) and NCW1001 and NCW1002 (Wako Chemicals USA (Richmond, VA)).

[0035] In some embodiments, a mega-frequency ultrasonic field may be applied to the various cleaning baths described herein during the stripping or cleaning of the semiconductor substrate. Typical frequencies for mega-frequency ultrasonic cleaning range from 750 kHz to about 1.5 MHz. Mega-frequency ultrasonic cleaning causes cavitation, which facilitates the removal of particles from the surface of the substrate. In other embodiments, no mega-frequency ultrasonic field is applied during the various stripping and cleaning steps described herein.

[0036] The amount of surfactant in the stripping bath can be any effective amount that allows the stripping bath to function as described herein. In some embodiments, the amount of surfactant is at least 0.01 wt%, or as in other embodiments at least about 0.025 wt% or at least 0.05 wt%, or from 0.01 wt% to about 0.1 wt%, or from 0.025 wt% to 0.075 wt%. The ratio (v:v) of deionized water to hydrofluoric acid (HF) can be less than 100:1, less than 50:1, less than 25:1, at least 1:1, at least 5:1, from 1:1 to 100:1, or from 1:1 to 25:1. The immersion time of the silicon-on-insulator structure in the stripping bath can be at least 5 minutes, at least 10 minutes, or from 5 minutes to about 60 minutes, or from about 5 minutes to about 30 minutes. In some embodiments, the stripping bath does not contain acetic acid.

[0037] The stripping bath (and any additional baths mentioned below) can be held in any suitable container, such as a container that is part of the wet immersion station equipment. An example of this system is the GAMA automated wetting station, available from Naura-Akrion (Allentown, PA), which may contain multiple containers for immersing structures in different baths. Multiple semiconductor structures (e.g., at least 5, 10, 25, or 50 or more) can be loaded onto wafer carriers (or “cassettes” or “crystal boats”), and one or more of these carriers can be immersed in the bath held within the container. The components used to hold the structures in the bath are typically high-purity parts, such as PTFE, quartz, or coated aluminum or stainless steel. Commercially available cleaning equipment can be purchased from Echo Giken Co., Ltd. (Tokyo, Japan) and Akrion Systems LLC (Allentown, Pennsylvania). In other embodiments, the structure can be immersed in a bath within a "cassette-less" system.

[0038] According to embodiments of this disclosure, “immersing” a silicon-on-insulator (SBI) structure in a stripping bath or other baths described below involves completely immersing the SBI structure in the bath. Typically, and according to embodiments of this disclosure, the substrate is not rotated during cleaning in such immersion processes.

[0039] In the second step 120 of the method, the stripped silicon-on-insulator structure 111 is immersed in an ozone bath to prepare an ozone-treated silicon-on-insulator structure 121. The ozone bath comprises ozone (O3). In some embodiments, the concentration of ozone in the ozone bath is at least 5 ppm, or at least 10 ppm, at least 20 ppm, or from 5 ppm to 40 ppm. The stripped silicon-on-insulator structure 111 may be immersed in the ozone bath for at least 1 minute, at least 5 minutes, or at least 10 minutes (e.g., from 1 minute to 30 minutes or from 5 minutes to about 20 minutes).

[0040] In the third step 130, the ozone-treated silicon-on-insulator structure 121 is immersed in an SC-1 bath to prepare an SC-1 treated silicon-on-insulator structure 131. The “SC-1” bath is an aqueous cleaning bath known to those skilled in the art and may also be referred to as “Standard Clean-1” or “RCA-1” bath.

[0041] The SC-1 bath comprises ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2). The amount of ammonium hydroxide in the SC-1 bath may be at least 0.1 wt%, at least 0.5 wt%, or at least 1.0 wt% (e.g., from 0.1 wt% to 5 wt% or from 1 wt% to 3 wt%). The amount of hydrogen peroxide in the SC-1 bath may be at least 0.5 wt%, at least 1 wt%, at least 2 wt%, from 0.5 wt% to 10 wt%, or from 2 wt% to about 5 wt%.

[0042] In another embodiment of the method, and as Figure 6 As shown, after immersion in an SC-1 bath, the SC-1 treated silicon-on-insulator structure 131 is immersed in an SC-2 bath to form an SC-2 treated silicon-on-insulator structure 141. The “SC-2” bath is an aqueous cleaning bath known to those skilled in the art and may also be referred to as a “Standard Clean-2” or “RCA-2” bath. The SC-2 bath includes hydrochloric acid (HCl). In some embodiments, the SC-2 bath includes at least 0.01 wt% hydrochloric acid, at least 0.1 wt% hydrochloric acid, at least 0.25 wt% hydrochloric acid, from 0.01 wt% to 5 wt% hydrochloric acid, or from 0.1 wt% to 5 wt% hydrochloric acid. The silicon-on-insulator structure may be immersed in the SC-2 bath for at least 5 minutes, at least 7.5 minutes, or from 5 minutes to 20 minutes.

[0043] Figure 7Another embodiment of a method for stripping and cleaning the surface of a silicon-on-insulator (SOS) structure is shown. In a rinsing step 115, the stripped SOS structure 111 (i.e., the structure after immersion in the stripping bath in step 110) is rinsed, in which the structure is contacted with deionized water (DIW), for example, by immersion. In a second rinsing step 135, the SOS structure 131 treated with SC-1 is rinsed with DIW water. The SC-2 treated structure 141 may undergo a third rinsing step 150, for example, by contacting the structure 141 with DIW (e.g., immersion). The rinsed SOS structure may be dried in a drying step 160. For example, the structure may be dried in an isopropyl alcohol vapor (IPA) dryer (Marangoni drying).

[0044] The various baths described herein may be at room temperature (approximately 25°C). In other embodiments, heated baths are used (e.g., at least 30°C, at least 40°C, at least 60°C, from 30°C to 95°C, or from 30°C to 80°C).

[0045] The above description and Figures 5 to 7 The method shown in the document for stripping and cleaning the surface of silicon structures on insulators is exemplary and may include additional steps, or the steps may be reordered or one or more steps may be eliminated.

[0046] The method disclosed herein offers several advantages over conventional methods for removing oxides from silicon-on-insulator (SOI) structures. Unbound by any particular theory, it is believed that the surfactants used during oxide stripping cause the formation of nanoscale defects on the surface of the SOI structure. These nanoscale defects can be surfactants or surfactant-bound contaminants. These defects are nanoscale and cannot be detected by conventional wafer inspection tools, such as the KLA-Tencor Surfscan SPx wafer surface analysis system. These defects are considered to act as an etching mask during subsequent cleaning steps (SC-1 cleaning). Ozone treatment has been found to remove these defects prior to the cleaning process, reducing or eliminating protrusions from the surface of the SOI structure.

[0047] Example

[0048] The process disclosed herein is further illustrated by the following examples. These examples should not be considered limiting.

[0049] Example 1: Protrusions on the SOI surface under conventional methods

[0050] A 200 mm SOI structure was fabricated using the method described herein. The SOI structure was annealed to form oxide (SiO2) on the top surface of the silicon device layer of the SOI structure. The structure was then immersed in an HF bath containing a surfactant, subjected to DIW rinsing, and then immersed in an SC-1 bath. Figure 8 It is a reproduction of the AFM image of the SOI structure, which shows the nanoscale protrusions on the surface of the structure. Figure 9 This is an AFM chart showing the height of the protrusion. When a 200mm SOI structure with oxide (SiO2) on the top surface of the silicon device layer of the SOI structure is immersed in an ozone bath before SC-1 cleaning, the AFM image shows that defects are eliminated.

[0051] As used herein, the terms “about,” “generally,” “essentially,” and “approximately” are intended, when used in conjunction with ranges of size, concentration, temperature, or other physical or chemical properties or characteristics, to cover variations that may exist within the upper and / or lower limits of the range of said property or characteristic, including variations caused, for example, by rounding, measurement methods, or other statistical variations.

[0052] When describing elements of this disclosure or embodiments thereof, the articles “(a / an)” and “the / said” are intended to mean the presence of one or more of the elements. The terms “comprising,” “including,” “containing,” and “having” are intended to be inclusive and mean that additional elements besides those listed may also be present. The use of terms indicating a particular orientation (e.g., “top,” “bottom,” “side,” etc.) is for ease of description and does not require any particular orientation of the described items.

[0053] Since various changes can be made to the above construction and methods without departing from the scope of this disclosure, all matters contained in the above description and shown in the accompanying drawings should be interpreted as illustrative rather than limiting.

Claims

1. A method for stripping and cleaning the surface of a silicon-on-insulator structure, the silicon-on-insulator structure comprising a treatment structure, a silicon top layer, and a dielectric layer disposed between the treatment structure and the silicon top layer, the silicon-on-insulator structure having an oxide film on its top surface, the method comprising: The silicon-on-insulator structure is immersed in a stripping bath to remove the oxide film from the surface of the silicon-on-insulator structure and to prepare a stripped silicon-on-insulator structure, wherein the stripping bath includes hydrofluoric acid and a surfactant. The stripped silicon-on-insulator structure is immersed in an ozone bath containing ozone to prepare an ozone-treated silicon-on-insulator structure. and The ozone-treated silicon-on-insulator structure was immersed in an SC-1 bath containing ammonium hydroxide and hydrogen peroxide to prepare an SC-1-treated silicon-on-insulator structure.

2. The method of claim 1, further comprising immersing the SC-1 treated silicon-on-insulator structure in an SC-2 bath comprising hydrochloric acid to form an SC-2 treated silicon-on-insulator structure.

3. The method of claim 2, further comprising rinsing the SC-1 treated silicon-on-insulator structure with water before immersing the SC-1 treated silicon-on-insulator structure into the SC-2 bath.

4. The method of claim 2, further comprising drying the SC-2 treated silicon-on-insulator structure by contacting the SC-2 treated silicon-on-insulator structure with isopropanol vapor.

5. The method of claim 4, further comprising rinsing the SC-2 treated silicon-on-insulator structure with water before drying the SC-2 treated silicon-on-insulator structure.

6. The method of claim 1, wherein the stripping bath comprises at least 0.01 wt% of a surfactant.

7. The method according to claim 1, wherein the surfactant is a nonionic surfactant.

8. The method of claim 7, wherein the nonionic surfactant is an ether surfactant comprising an ether group.

9. The method according to claim 8, wherein the ether surfactant is a polyoxyethylene alkyl ether.

10. The method of claim 1, wherein the ozone bath comprises at least 20 ppm of ozone.

11. The method of claim 1, wherein the stripped silicon-on-insulator structure is immersed in the ozone bath for at least 5 minutes.

12. The method of claim 1, wherein the stripped silicon-on-insulator structure is immersed in the ozone bath for between 5 and 20 minutes.

13. The method of claim 1, wherein the silicon-on-insulator structure is immersed in the stripping bath for at least 5 minutes.

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