A method for characterizing the full-area degradation of IGBTs

Abstract

The present invention discloses a method for characterizing the degradation of the entire region of an IGBT. A negative voltage gradually increasing from 0V is applied between the collector and emitter of the IGBT. ce The gate voltage of the IGBT is scanned and a small signal is superimposed. The gate voltage scanning range is V g1 ~V g2 . In each V ce Next, test V g1 ~V g2 The gate capacitance C g , draw C g ‑V g The degraded device is tested again using the same voltage application method. g1 ~V g2 The gate capacitance C g Value, plot C g ‑V g The curve is then partitioned in the same manner. By comparing the drift of different regions of the curve before and after degradation, the degradation and damage level of the entire IGBT power device region can be characterized. This method can quickly and easily extract the degradation of the gate oxide and epitaxial layers of IGBT power devices, providing a rapid basis for determining the reliability of IGBT power devices.

Description

Technical Field

[0001] The present invention relates to the field of power device reliability testing, and in particular to a full-area degradation characterization method for IGBTs. Background Art

[0002] As an important power semiconductor device, IGBT transistors offer higher power density, higher power output capability, and faster switching speeds, making them widely used in high-voltage, high-power density applications such as power systems, industrial automation, and new energy vehicles. However, due to the long-term high-temperature, high-pressure, and radiation exposure of IGBTs, defects can develop in their gate oxide and drift regions. This is particularly true for silicon carbide-based IGBTs, where poor gate oxide quality leads to the propagation of dislocations in the drift region, leading to more severe degradation.

[0003] Currently, the most widely used methods for testing gate oxide defects in power semiconductor devices are the capacitance (CV) method and the charge pump method. However, neither method can characterize defects in the IGBT epitaxial layer. The present invention provides a testing method that can characterize both gate oxide interface state defect charge and epitaxial layer defect charge. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for characterizing the full-area degradation of IGBTs, which can characterize the types and charge density of gate oxide interface state defects and the types and locations of epitaxial layer defects in IGBT power devices.

[0005] To achieve the above functions, the present invention designs a method for characterizing the degradation of the entire region of an IGBT, performing the following steps S1 to S6 to characterize the degradation and damage degree of the entire region of the IGBT device to be tested:

[0006] Step S1: Build a test circuit. For the IGBT device under test, use a voltage source to apply a bias voltage gradually increasing from 0V between the collector and emitter of the IGBT device under test, perform a voltage sweep on the gate of the IGBT device under test, and superimpose a small AC signal.

[0007] Step S2: Extract each gate voltage V during the gate voltage scanning process of the IGBT device to be tested g The gate capacitance C g , draw the curve of gate capacitance changing with gate voltage C g -V g ;

[0008] Step S3: gradually increasing the bias voltage applied between the collector and emitter of the IGBT device to be tested from 0V to a negative voltage direction, performing a gate voltage scan in the same voltage application manner as step S1 and superimposing a small AC signal;

[0009] Step S4: repeat step S2;

[0010] Step S5: After the IGBT device under test has been degraded due to stress, repeat steps S1 to S4 and draw the gate capacitance versus gate voltage curve C again. g -V g ;

[0011] Step S6: According to the gate capacitance C g The gate capacitance changes with the gate voltage curve C g -V g Partitions represent the degradation of each area of ​​the IGBT device under test, and compare the gate capacitance versus gate voltage curve C before and after degradation of the IGBT device under test. g -V g The lateral and longitudinal drift of the g -V g The drift amplitude is used to analyze the damage degree of each area of ​​the IGBT device under test.

[0012] As a preferred technical solution of the present invention: the AC small signal voltage amplitude range in step S1 is between 1mV and 1V, and the frequency is between 1KHz and 100MHz.

[0013] As a preferred technical solution of the present invention: the absolute value of the bias voltage applied between the collector and the emitter in step S1 is not greater than the reverse breakdown voltage of the device, and the typical value range of the absolute value of the bias voltage is between -10000V and 0V.

[0014] As a preferred technical solution of the present invention: the voltage application method in step S1 is: connecting a DC voltage source and an AC small signal to the gate of the IGBT device to be tested, the AC small signal is superimposed on the DC power supply, and the gate voltage is scanned. The gate voltage scanning range is required to make the junction field effect region under the gate oxide undergo three states of accumulation, depletion, and inversion, and to make the channel region under the gate oxide undergo three states of accumulation, depletion, and inversion, and keep the bias voltage between the collector and the emitter constant during the gate voltage scanning.

[0015] As a preferred technical solution of the present invention: in step S5, the stress characterized by the IGBT device to be tested includes one or more of short-circuit switching stress, unclamped inductive switching stress, high-temperature gate voltage bias, on-state high current impact stress, hot carrier injection, and radiation stress.

[0016] As a preferred technical solution of the present invention, in step S6, the gate capacitance versus gate voltage curve C g -V g It is divided into zones I, II, III, IV, V and VI in sequence;

[0017] When the bias voltage applied to the gate of the IGBT device to be tested is negative and the absolute value of the negative voltage is greater than the preset threshold, the gate capacitance C g At a stable high value, this part of the curve C g -V g Divided into Zone I;

[0018] When the absolute value of the bias voltage applied to the gate of the IGBT device under test decreases, the gate capacitance C g Reduce to the lowest value, this part of the curve C g -V g Divided into Zone II;

[0019] When the bias voltage applied to the gate of the IGBT device under test changes from negative to positive, the gate capacitance C g Increase this part of the curve C g -V g Divided into Zone III;

[0020] When the bias voltage applied to the gate of the IGBT device to be tested continues to increase from negative to positive, the gate capacitance C g A platform area appears, and this part of the curve C g -V g It is divided into Zone IV;

[0021] When the bias voltage applied to the gate of the IGBT device under test gradually increases from a low voltage, the gate capacitance C g Increase this part of the curve C g -V g Divided into V zones;

[0022] When the bias voltage applied to the gate of the IGBT device under test continues to increase, the gate capacitance C g At a stable high value, this part of the curve C g -V g Divided into Zone VI.

[0023] As a preferred technical solution of the present invention: in step S6, curve C g -V g The lateral drift of region II characterizes the degradation of the gate oxide interface above the junction field effect region of the IGBT device under test;

[0024] When there is a positive charge on the gate oxide interface above the junction field effect region, the junction field effect region switches from the depletion state to the inversion state under a negative gate voltage with a larger absolute value compared to the case where there is no defect in the gate oxide interface. g -V g Zone II along V gAxis negative drift; when there is a negative charge on the gate oxide interface above the junction field effect region, the junction field effect region switches from the depletion state to the inversion state under a smaller absolute value of negative gate voltage compared to the case where there is no defect in the gate oxide. Curve C g -V g Zone II will follow V g Axis drift in positive direction.

[0025] As a preferred technical solution of the present invention: in step S6, curve C g -V g The lateral drift of the IV region characterizes the degradation of the gate oxide interface above the channel region of the IGBT device under test;

[0026] When there is a positive charge on the gate oxide interface above the channel region, the channel region switches from the depletion state to the inversion state at a smaller positive gate voltage than when there is no defect in the gate oxide interface. g -V g Zone IV to V g Axis negative drift; when there is a negative charge on the gate oxide interface above the channel region, the channel region switches from the depletion state to the inversion state under a larger positive gate voltage compared to the case where there is no defect in the gate oxide. Curve C g -V g Zone IV to V g Axis drift in positive direction.

[0027] As a preferred technical solution of the present invention: in step S6, curve C g -V g Zone III in C g The drift on the axis characterizes the defects of the epitaxial layer of the device;

[0028] When the defects in the epitaxial layer are positively charged, curve C g -V g Zone III to C g Axis positive drift; when the defects in the epitaxial layer are negatively charged, curve C g -V g Zone III to C g Axis drift in negative direction.

[0029] As a preferred technical solution of the present invention, in step S6, the stress curve C is extracted. g -V g Zones II and IV along V g In the case of axis drift, the gate oxide interface defect charge density ΔD caused by stress is calculated according to the following formula ot , to characterize the degree of damage:

[0030]

[0031] Among them, Cox is the gate oxide capacitance per unit area, ΔV g Curve C g -V g The voltage drift on the horizontal axis is q, and the electron charge is q.

[0032] Beneficial effects: Compared with the prior art, the advantages of the present invention include:

[0033] 1. The method of the present invention can characterize the degradation of the entire area of ​​the IGBT device by C g -V g The drift of each region of the curve can be used to extract the defect polarity and defect density of the gate oxide above the device junction field effect region and above the channel region, as well as the defect position and defect polarity in the epitaxial layer.

[0034] 2. This test method will C g -V g The curve is divided into 6 regions, among which region II, region III, and region IV can respectively represent the gate oxide defects above the junction field effect region, the epitaxial layer defects, and the gate oxide defects above the channel region.

[0035] 3. By analyzing C g -V g The drift of curves in regions II and IV can be used to extract the polarity and density of gate oxide interface defects above the junction field effect region and above the channel region, respectively. g -V g The drift of curve III can be used to extract the location and type of epitaxial layer defects.

[0036] 4. The test circuit conditions of the method of the present invention are relatively low; it is also more intuitive and convenient to extract the defect location and polarity, and only C g -V g The drift direction of curve II, III, and IV regions; this test method only needs to extract C g -V g Curve II and IV areas are at V g The drift of the axis can be used to calculate the defect density in the gate oxide according to the formula. Compared with the traditional calculation method of extracting gate oxide defects, it is relatively simple.

[0037] From the above advantages, it can be seen that the testing method provided by the present invention can simply and quickly extract the degradation of the gate oxide layer and epitaxial layer of the IGBT power device, and can provide a rapid judgment basis for the analysis of the reliability of the IGBT power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 1. It is a diagram of an IGBT device structure and a capacitor composition according to an embodiment of the present invention;

[0039] Figure 2 This is a flow chart of a method for characterizing full-area degradation of an IGBT according to an embodiment of the present invention;

[0040] Figure 3 is a test circuit diagram provided according to an embodiment of the present invention;

[0041] Figure 4 is the initial state C provided according to an embodiment of the present invention g -V g curve chart;

[0042] Figure 5 The device is provided according to an embodiment of the present invention, wherein the gate oxide above the channel region has defects after device degradation. g -V g curve chart;

[0043] Figure 6 The device is provided according to an embodiment of the present invention, wherein the gate oxide above the junction field effect region has defects after device degradation. g -V g curve chart;

[0044] Figure 7 The device provided in the embodiment of the present invention has a defective epitaxial layer after degradation. g -V g curve chart. DETAILED DESCRIPTION

[0045] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention.

[0046] The insulated-gate bipolar-transistor (IGBT) is a high-power electronic device that combines the characteristics of MOSFET (metal-oxide-semiconductor field-effect transistor) and BJT (bipolar transistor), achieving low switching loss while having high current density.

[0047] The structure of IGBT transistor and the capacitor composition are as follows Figure 1 As shown, the gate capacitance mainly consists of the capacitance C between the gate and the collector. gc , the capacitance C between the gate and emitter ge Two parts. Capacitor C gc It is composed of four types of capacitors connected in series and in parallel, namely the surface MOS capacitor C oc , the surface MOS capacitance C of the junction field effect region oj , PN junction capacitance C j , substrate capacitance C sub, where the surface MOS capacitance C of the junction field effect region is oj and substrate capacitance C sub The series capacitor dominates. Capacitor C ge It is composed of three types of capacitors connected in series and in parallel, namely the channel surface MOS capacitor C oc , the surface MOS capacitance C of the junction field effect region oj , PN junction capacitance C j , where C ge Mainly affected by C oc When the emitter and collector are short-circuited, the PN junction capacitance C j The effect is shielded, the gate capacitance C g By capacitor C gc and capacitor C ge Parallel formation.

[0048] When the bias voltage applied to the gate of the IGBT continues to increase, the channel region below the gate electrode undergoes a transition from depletion to inversion, and carrier accumulation occurs in the junction field effect region, forming an inversion layer channel connecting the N+ emitter region and the N-base region. When a positive voltage is applied to the collector, the electron current flows from the N+ emitter region to the N-base region, at which point a voltage drop is formed in the N-base region. The electron current acts as the base drive current of the PNP transistor, promoting the injection of holes from the P+ collector region into the N-type base region. The PNP transistor is turned on, and the current density increases sharply.

[0049] The semiconductor surface inversion refers to the fact that when the gate applies a voltage, electrons or holes on the semiconductor surface are attracted to the semiconductor surface, causing the semiconductor surface to convert from the original n-type to p-type or from the original p-type to n-type; the semiconductor surface depletion refers to the fact that when the gate applies a voltage, electrons or holes are repelled, the original donor atoms or acceptor atoms lose electrons or holes, and a space charge region is formed on the semiconductor surface; the semiconductor surface accumulation refers to the fact that when the gate applies a voltage, electrons or holes accumulate on the semiconductor surface, making the electron concentration in the n-type region or the hole concentration in the p-type region on the semiconductor surface higher than the electron concentration in the n-type region or the hole concentration in the p-type region inside the semiconductor.

[0050] Since the working scenarios of IGBT involve factors such as high temperature, large current, and radiation, this will cause defects to be introduced in the gate oxide and epitaxial layer of the IGBT. The introduction of defect charges in the gate oxide will seriously affect the gate control capability of the device. Defects in the substrate will seriously affect the current capability of the device.

[0051] An embodiment of the present invention provides a method for characterizing the degradation of an IGBT in the entire region, referring to Figure 2 , perform the following steps S1 to S6 to characterize the degradation and damage degree of the entire area of ​​the IGBT device to be tested:

[0052] Step S1: Build a test circuit as shown in the following example: Figure 3 For the IGBT device under test, a bias voltage V is applied between the collector and emitter of the IGBT device under test, which is gradually increased from 0V. ce The bias voltage applied between the collector and emitter is determined by the withstand voltage capability of the device itself; the gate voltage of the IGBT device to be tested is scanned and a small AC signal is superimposed; the gate voltage scanning range is V g1 ~V g2 ;

[0053] In actual applications, the number and interval of bias voltages can be determined based on the test rate and test accuracy requirements. Generally, the fewer bias voltages, the faster the test rate, and the smaller the interval between bias voltages, the higher the test accuracy.

[0054] The AC small signal voltage amplitude ranges from 1mV to 1V, and the frequency ranges from 1KHz to 1MHz.

[0055] The absolute value of the bias voltage applied between the collector and the emitter is not greater than the reverse breakdown voltage of the device. A typical absolute value range of the bias voltage is between -10000V and 0V.

[0056] The voltage application method in step S1 is: connecting a DC voltage source and an AC small signal to the gate of the IGBT device to be tested, superimposing the AC small signal on the DC power supply, and performing a voltage scan on the gate. The gate voltage scanning range is required to make the junction field effect region under the gate oxide experience the three states of accumulation, depletion, and inversion, and to make the channel region under the gate oxide experience the three states of accumulation, depletion, and inversion. The bias voltage between the collector and the emitter is kept constant during the gate voltage scanning.

[0057] Step S2: Extract each gate voltage V during the gate voltage scanning process of the IGBT device to be tested g The gate capacitance C g , draw the curve of gate capacitance changing with gate voltage C g -V g ;

[0058] At each bias voltage V ce Under the test gate voltage scanning range V g1 ~V g2 The gate capacitance C g , gate voltage scanning range V g1 ~V g2 (or V g2 ~V g1 ), V g1 A typical value range is -50V-0V; the corresponding V g2 A typical value range is 0V-50V.

[0059] Step S3: gradually increasing the bias voltage applied between the collector and emitter of the IGBT device to be tested from 0V to a negative voltage direction, performing a gate voltage scan in the same voltage application manner as step S1 and superimposing a small AC signal;

[0060] Step S4: repeat step S2;

[0061] Step S5: After the IGBT device to be tested has been degraded by stress, repeat steps S1 to S4. The gate voltage scanning range and the value interval step length are the same before and after stress. The amplitude and frequency of the AC small signal are the same before and after stress. The bias voltage V ce The value remains the same before and after stress, and the gate capacitance vs. gate voltage curve C is plotted again. g -V g ;

[0062] The stress characterized by the IGBT device under test includes but is not limited to high-temperature gate bias stress, such as one or more of short-circuit switching stress, unclamped inductive switching stress, on-state high current impact stress, hot carrier injection, and radiation stress.

[0063] High-temperature gate bias stress: When a voltage bias is applied to the gate at high temperature, charge traps at the gate-oxide interface capture or release electrons, causing the device threshold voltage to drift. Under positive high-temperature gate bias stress, the gate is forward biased for a long time, causing traps at the gate-oxide interface to capture electrons and increase the threshold voltage. Under negative high-temperature gate bias stress, the gate is forward biased for a long time, causing traps at the gate-oxide interface to capture holes and increase the threshold voltage.

[0064] Step S6: According to the gate capacitance C g The gate capacitance changes with the gate voltage curve C g -V g Partitions represent the degradation of each area of ​​the IGBT device under test, and compare the gate capacitance versus gate voltage curve C before and after degradation of the IGBT device under test. g -V g The lateral and longitudinal drift of the g -V g The drift amplitude is used to analyze the damage degree of each area of ​​the IGBT device under test.

[0065] The gate capacitance versus gate voltage curve C g -V g It is divided into zones I, II, III, IV, V and VI in sequence;

[0066] Gate capacitance C after the emitter and collector are shorted before device degradation gWith gate voltage V g The change curve is as follows Figure 4 As shown. When a negative voltage with a large absolute value is applied to the gate, the channel region under the gate oxide is in an accumulation state and the junction field effect region is in an inversion state. At this time, the surface MOS capacitance C oc and the surface MOS capacitance C of the junction field effect region oj Approximately gate oxide capacitance, when the voltage between collector and emitter is constant, substrate capacitance C sub Constant, at this time the gate capacitance C g is at a stable high value; Figure 4 As shown in area I in the middle. When the absolute value of the negative voltage applied by the gate decreases to the point where the junction field effect region switches from the inversion state to the depletion state, the width of the depletion layer on the semiconductor surface increases, and C oj starts to decrease, and causes C gc Since the channel region is still in the accumulation state, C oc Still approximately the gate oxide capacitance, the capacitance C ge unchanged, which eventually leads to the gate capacitance C g like Figure 4 As shown in the middle II area. When the gate bias voltage continues to increase from negative to positive, the channel region begins to switch from the accumulation state to the depletion state, and the capacitor C oc It is formed by the gate oxide capacitance and the space charge region capacitance in series, C oc At the same time, the junction field effect region gradually changes from a completely depleted state to an accumulated state, the width of the depletion layer on the semiconductor surface decreases, and the capacitance C oj Since the area of ​​the junction field effect region under the gate oxide is much larger than the channel area, the capacitance C oj The increase of the overall capacitance C g Increase as Figure 4 As shown in the III area. As the gate voltage increases, due to the capacitance C oj and substrate capacitance C sub Series and substrate capacitance C sub Smaller, C gc The capacitor C sub Clamping. As the gate voltage increases from negative to positive, the channel region is further depleted, and the capacitor C oc Further reduce, the capacitance C g By C gc Dominant, a platform area appears Figure 4 As shown in the IV region in the middle. When the gate voltage gradually increases from low voltage, the channel region begins to gradually switch from the depletion state to the inversion state, and the capacitor C oc Starts to increase, the overall capacitance C g Increase as Figure 4 As shown in the V region in the middle. When the gate voltage increases to the point where the channel region is strongly inverted, the capacitance C oc With MOS capacitors close to Coj At the same time, it is the gate oxide capacitance, then the capacitance C g At a stable high value Figure 4 As shown in Zone VI.

[0067] When defect charges are introduced into the gate oxide interface due to stress, the surface potential of the semiconductor below the gate oxide will be changed, thereby promoting or hindering the inversion or depletion of the region below the gate oxide and changing the semiconductor surface capacitance device; when defects are introduced into the epitaxial layer due to stress, the presence of defect charges will change the effective doping concentration of the epitaxial layer, thereby affecting the conduction performance of the device. Based on the above analysis, Figure 4 Middle C g -V g Region II of the curve is mainly affected by the surface capacitance C of the junction field effect region. oj Affected by the surface capacitance C of the channel region, the V region is mainly affected by the surface capacitance C of the channel region. oc Influence, so C can be used g -V g The II and V areas of the curve are along V g The drift of the axis indicates the degradation of the gate oxide interface. Figure 5 As shown in the figure, when positive charge is introduced into the gate oxide above the channel region, electrons are attracted to the channel region below the gate oxide, and the device will be inverted under a smaller positive voltage. The curve V region is along V g Axis negative drift; when negative charge is introduced into the gate oxide above the channel region, the device will be inverted under a larger positive voltage, and the curve V region will drift along the V g The axis drifts in the positive direction. Figure 6 As shown in the figure, when positive charge is introduced into the gate oxide above the junction field effect region, electrons are attracted to the junction field effect region below the gate oxide, and the device will be inverted under a negative voltage with a larger absolute value. The curve II area is along V g Axis negative drift; when negative charge is introduced into the gate oxide above the junction field effect region, the device will be inverted under a negative voltage with a smaller absolute value, and the curve II area along V g The axis drifts in the positive direction. Figure 7 As shown, when defects are introduced into the epitaxial layer due to stress, the V ce The depletion layer of the substrate PN junction widens to the area containing the defect, the substrate capacitance is affected, and the platform curve drifts. If the defect is an acceptor-type defect, the effective doping concentration of the epitaxial layer decreases, the depletion layer width increases compared to the theoretical value, and the substrate capacitance decreases compared to before device degradation. The platform region along C g Axis drifts negatively; if the defect is a donor defect, the effective doping concentration of the epitaxial layer increases, the depletion layer width decreases compared to the theoretical value, and the substrate capacitance increases compared to the device degradation. The platform region along C g Axis drift in positive direction.

[0068] Extract the capacitance curve along V gThe axis drift and gate oxide capacitance value can be used to calculate the defect density of the gate oxide interface according to the formula.

[0069] Based on this, we can g -V g The drift of the II and IV regions of the curve are used to calculate the types and densities of gate oxide defect charges above the junction field effect region and above the channel region of the device respectively; according to C g -V g The drift of curve III can be used to extract the location and polarity of the defect charges in the device epitaxial layer.

[0070] When there is a positive charge on the gate oxide interface above the junction field effect region, the junction field effect region switches from the depletion state to the inversion state under a negative gate voltage with a larger absolute value compared to the case where there is no defect in the gate oxide interface. g -V g Zone II along V g Axis negative drift; when there is a negative charge on the gate oxide interface above the junction field effect region, the junction field effect region switches from the depletion state to the inversion state under a smaller absolute value of negative gate voltage compared to the case where there is no defect in the gate oxide. Curve C g -V g Zone II will follow V g Axis drift in positive direction.

[0071] Curve C g -V g Zone III in C g The drift on the axis characterizes the defects of the epitaxial layer of the device;

[0072] When the defects in the epitaxial layer are positively charged, curve C g -V g Zone III to C g Axis negative drift; when the defects in the epitaxial layer are negatively charged, curve C g -V g Zone III to C g Axis drift in positive direction.

[0073] Curve C g -V g The lateral drift of the IV region characterizes the degradation of the gate oxide interface above the channel region of the IGBT device under test;

[0074] When there is a positive charge on the gate oxide interface above the channel region, the channel region switches from the depletion state to the inversion state at a smaller positive gate voltage than when there is no defect in the gate oxide interface. g -V g Zone IV to V gAxis negative drift; when there is a negative charge on the gate oxide interface above the channel region, the channel region switches from the depletion state to the inversion state under a larger positive gate voltage compared to the case where there is no defect in the gate oxide. Curve C g -V g Zone IV to V g Axis drift in positive direction.

[0075] Step S6 extracts the stress curve C before and after g -V g Zones II and IV along V g In the case of axis drift, the gate oxide interface defect charge density ΔD caused by stress is calculated according to the following formula ot , to characterize the degree of damage:

[0076]

[0077] Among them, C ox is the gate oxide capacitance per unit area, ΔV g Curve C g -V g The voltage drift on the horizontal axis is q, and the electron charge is q.

[0078] The embodiments of the present invention are described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Various changes can be made within the scope of knowledge possessed by ordinary technicians in this field without departing from the scope of the present invention.

Claims

1. A method for characterizing the full-area degradation of an IGBT, characterized in that: Perform the following steps S1 to S6 to characterize the degradation and damage level of the entire region of the IGBT device under test: Step S1: Build a test circuit. For the IGBT device under test, use a voltage source to apply a bias voltage gradually increasing from 0V between the collector and emitter of the IGBT device under test, perform a voltage sweep on the gate of the IGBT device under test, and superimpose a small AC signal. The voltage application method is as follows: a DC voltage source and a small AC signal are connected to the gate of the IGBT device under test. The small AC signal is superimposed on the DC power supply, and the gate voltage is scanned. The gate voltage scanning range is such that the junction field effect region under the gate oxide undergoes three states: accumulation, depletion, and inversion, and the channel region under the gate oxide undergoes three states: accumulation, depletion, and inversion. The bias voltage between the collector and emitter is kept constant during the gate voltage scanning. Step S2: Extract each gate voltage V during the gate voltage scanning process of the IGBT device to be tested g The gate capacitance C g , draw the curve of gate capacitance changing with gate voltage C g -V g ; Step S3: gradually increasing the bias voltage applied between the collector and emitter of the IGBT device to be tested from 0V to a negative voltage direction, performing a gate voltage scan in the same voltage application manner as step S1 and superimposing a small AC signal; Step S4: repeat step S2; Step S5: After the IGBT device under test has been degraded due to stress, repeat steps S1 to S4 and draw the gate capacitance versus gate voltage curve C again. g -V g ; Step S6: According to the gate capacitance C g The gate capacitance changes with the gate voltage curve C g -V g Partitions represent the degradation of each area of ​​the IGBT device under test, and compare the gate capacitance versus gate voltage curve C before and after degradation of the IGBT device under test. g -V g The lateral and longitudinal drift of the g -V g The drift amplitude is used to analyze the damage degree of each area of ​​the IGBT device under test.

2. The method for characterizing the full-area degradation of an IGBT according to claim 1, wherein: The AC small signal voltage amplitude in step S1 is in the range of 1 mV to 1 V, and the frequency is in the range of 1 KHz to 100 MHz.

3. The method for characterizing the full-area degradation of an IGBT according to claim 1, wherein: The absolute value of the bias voltage applied between the collector and the emitter in step S1 is not greater than the reverse breakdown voltage of the device, and the typical value range of the absolute value of the bias voltage is between -10000V and 0V.

4. The method for characterizing the full-area degradation of an IGBT according to claim 1, wherein: The degenerative stresses that may be introduced into the IGBT device under test in step S5 include one or more of short-circuit switching stress, unclamped inductive switching stress, high-temperature gate voltage bias, on-state high current impact stress, hot carrier injection, and radiation stress.

5. The method for characterizing the full-area degradation of an IGBT according to claim 1, wherein: In step S6, the gate capacitance versus gate voltage curve C g -V g It is divided into zones I, II, III, IV, V and VI in sequence; When the bias voltage applied to the gate of the IGBT device to be tested is negative and the absolute value of the negative voltage is greater than the preset threshold, the gate capacitance C g At a stable high value, this part of the curve C g -V g Divided into Zone I; When the absolute value of the bias voltage applied to the gate of the IGBT device under test decreases, the gate capacitance C g Reduce to the lowest value, this part of the curve C g -V g Divided into Zone II; When the bias voltage applied to the gate of the IGBT device under test changes from negative to positive, the gate capacitance C g Increase this part of the curve C g -V g Divided into Zone III; When the bias voltage applied to the gate of the IGBT device to be tested continues to increase from negative to positive, the gate capacitance C g A platform area appears, and this part of the curve C g -V g It is divided into Zone IV; When the bias voltage applied to the gate of the IGBT device under test gradually increases from a low voltage, the gate capacitance C g Increase this part of the curve C g -V g Divided into V zones; When the bias voltage applied to the gate of the IGBT device under test continues to increase, the gate capacitance C g At a stable high value, this part of the curve C g -V g Divided into Zone VI.

6. The method for characterizing the full-area degradation of an IGBT according to claim 5, wherein: Curve C in step S6 g -V g The lateral drift of region II characterizes the degradation of the gate oxide interface above the junction field effect region of the IGBT device under test; When there is a positive charge on the gate oxide interface above the junction field effect region, the junction field effect region switches from the depletion state to the inversion state under a negative gate voltage with a larger absolute value compared to the case where there is no defect in the gate oxide interface. g -V g Zone II along V g Axis negative drift; when there is a negative charge on the gate oxide interface above the junction field effect region, the junction field effect region switches from the depletion state to the inversion state under a smaller absolute value of negative gate voltage compared to the case where there is no defect in the gate oxide. Curve C g -V g Zone II will follow V g Axis drift in positive direction.

7. The method for characterizing the full-area degradation of an IGBT according to claim 5, wherein: Curve C in step S6 g -V g The lateral drift of the IV region characterizes the degradation of the gate oxide interface above the channel region of the IGBT device under test; When there is a positive charge on the gate oxide interface above the channel region, the channel region switches from the depletion state to the inversion state at a smaller positive gate voltage than when there is no defect in the gate oxide interface. g -V g Zone IV to V g Axis negative drift; when there is a negative charge on the gate oxide interface above the channel region, the channel region switches from the depletion state to the inversion state under a larger positive gate voltage compared to the case where there is no defect in the gate oxide. Curve C g -V g Zone IV to V g Axis drift in positive direction.

8. The method for characterizing the full-area degradation of an IGBT according to claim 5, wherein: Curve C in step S6 g -V g Zone III in C g The drift on the axis characterizes the defects of the epitaxial layer of the device; When the defects in the epitaxial layer are positively charged, curve C g -V g Zone III to C g Axis positive drift; when the defects in the epitaxial layer are negatively charged, curve C g -V g Zone III to C g Axis drift in negative direction.

9. The method for characterizing the full-area degradation of an IGBT according to claim 5, wherein: Step S6 extracts the stress curve C before and after g -V g Zones II and IV along V g In the case of axis drift, the gate oxide interface defect charge density ΔD caused by stress is calculated according to the following formula ot , to characterize the degree of damage: Among them, C ox is the gate oxide capacitance per unit area, ΔV g Curve C g -V g The voltage drift on the horizontal axis is q, and the electron charge is q.

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