Chip signal testing method, device, equipment and storage medium

Abstract

The present invention relates to the field of chip testing technology, and discloses a chip signal testing method, device, equipment and storage medium, the method comprising: obtaining a signal to be tested and a typical value of the signal to be tested; determining the relationship between the typical value of the signal to be tested and each gear of the signal analyzer; if the reference level intervals of two adjacent gears in the signal analyzer both include the typical value, obtaining the critical value of the reference level intervals of the two adjacent gears; according to the critical value and the typical value, determining a target gear in the two adjacent gears, so as to measure the signal to be tested through the target gear. The above scheme can make the selection of the test gear more accurate and improve the accuracy of the chip measurement results.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a chip signal testing method, device, equipment and storage medium. Background Art

[0002] The principle of chip testing is to simulate various actual working scenarios and perform input and output operations on the chip to check whether the chip's functions and performance are normal. During the test, special testing equipment and methods are required to apply stimulus signals to the chip and monitor its response signals to determine whether the chip's functions and performance meet the standards.

[0003] When testing the chip, it is necessary to set a reasonable reference level. Simply selecting the test gear according to the power range of the typical power value may lead to errors. For example, the typical power value of the chip under test is 0dBm, so the reference level is usually set to 3dBm during testing. If the normal calibration is 10dBm, such as 0-10dBm calibration once and 10dBm~20dBm calibration once, if the typical power value of the chip under test is 9dBm at this time, then the gear is selected as 0-10dBm. Normally, 3dBm should be added as the reference level selection range. Then the reference level is 12dBm, that is, the reference level exceeds the selected gear, resulting in inaccurate measurement results. Summary of the invention

[0004] In view of this, the present application provides a chip signal testing method, device, equipment and storage medium to improve the accuracy of chip measurement results. The technical solution is as follows.

[0005] In a first aspect, a chip signal testing method is provided, which is applied to a signal analyzer; the signal analyzer includes several gears; there is an overlapping interval between any two adjacent gears among the several gears, and the method includes: obtaining a signal to be tested and a typical value of the signal to be tested; determining the relationship between the typical value of the signal to be tested and each gear of the signal analyzer; if the reference level intervals of two adjacent gears in the signal analyzer both include typical values, obtaining a critical value of the reference level intervals of the two adjacent gears; the critical value is the median of the overlapping interval of the reference level intervals of the two adjacent gears; and determining a target gear between the two adjacent gears according to the critical value and the typical value, so as to measure the signal to be tested through the target gear.

[0006] In one possible implementation, two adjacent gears include a first gear and a second gear; the median of a reference horizontal interval of the first gear is smaller than the median of a reference horizontal interval of the second gear; and a target gear is determined between the two adjacent gears based on a critical value and a typical value, including: when the typical value is smaller than the critical value, the first gear is used as the target gear; when the typical value is greater than or equal to the critical value, the second gear is used as the target gear.

[0007] In a possible implementation, measuring a signal to be tested through a target gear position includes: receiving a signal to be tested sent by a chip to be tested; measuring the signal to be tested through the target gear position to obtain a first result; processing the first result through a mapping relationship corresponding to the target gear position to obtain a test result of the chip to be tested.

[0008] In a possible implementation, the signal to be tested is generated after the chip under test receives a trigger signal sent by a signal generator.

[0009] In a possible implementation, the method further includes: obtaining each target signal value preset by the signal generator in the target gear; measuring each target signal value through the target gear to obtain each result to be calibrated; and determining the mapping relationship of the target gear according to each result to be calibrated and each target signal value.

[0010] In a second aspect, a chip signal testing device is provided, which is applied to a signal analyzer; the signal analyzer includes a plurality of gears; there is an overlapping interval between any two adjacent gears among the plurality of gears, and the method includes: a signal acquisition module, used to obtain a signal to be tested and a typical value of the signal to be tested; a gear determination module, used to determine the relationship between the typical value of the signal to be tested and each gear of the signal analyzer; a critical value judgment module, used to obtain a critical value of the reference level interval of two adjacent gears if the reference level intervals of two adjacent gears in the signal analyzer both include typical values; the critical value is the median of the overlapping interval of the reference level intervals of the two adjacent gears; a measurement module, used to determine a target gear between two adjacent gears according to the critical value and the typical value, so as to measure the signal to be tested through the target gear.

[0011] In one possible implementation, two adjacent gears include a first gear and a second gear; the median of a reference horizontal interval of the first gear is smaller than the median of a reference horizontal interval of the second gear; and a gear determination module is used to: when a typical value is smaller than a critical value, use the first gear as a target gear; when a typical value is greater than or equal to a critical value, use the second gear as a target gear.

[0012] In a possible implementation, the measurement module is further used to: receive a test signal sent by the chip under test; measure the test signal through a target gear to obtain a first result; and process the first result through a mapping relationship corresponding to the target gear to obtain a test result of the chip under test.

[0013] In a possible implementation, the signal to be tested is generated after the chip under test receives a trigger signal sent by a signal generator.

[0014] In one possible implementation, the device also includes: a preset signal acquisition module, used to obtain each target signal value preset by the signal generator in the target gear; a pre-measurement module, used to measure each target signal value through the target gear to obtain each result to be calibrated; and a mapping relationship acquisition module, used to determine the mapping relationship of the target gear according to each result to be calibrated and each target signal value.

[0015] In a third aspect, a computer device is provided, comprising a processor and a memory, wherein at least one instruction is stored in the memory, and the at least one instruction is loaded and executed by the processor to implement the above-mentioned chip signal testing method.

[0016] In a fourth aspect, a computer-readable storage medium is provided, wherein at least one instruction is stored in the storage medium, and the at least one instruction is loaded and executed by a processor to implement the above-mentioned chip signal testing method.

[0017] In a fifth aspect, a computer program product or a computer program is provided, the computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the chip signal testing method.

[0018] The technical solution provided by this application may have the following beneficial effects:

[0019] The chip signal testing method of the present application first obtains the signal to be tested and the typical value of the signal to be tested, which is the data basis for subsequent test analysis. Then, through comparative analysis, the relationship between the typical value of the signal to be tested and the various gears of the signal analyzer is determined. If the reference level intervals of two adjacent gears in the signal analyzer both include typical values, the critical value of the reference level interval of the two adjacent gears is obtained. Finally, the typical value and the critical value are compared, and the target gear is determined in the two adjacent gears through the comparison results, so as to measure the signal to be tested through the target gear. In the above scheme, the overlapping design between adjacent gears enables the method to cope with signals to be tested in different power ranges, and a critical value can be set in the overlapping interval of adjacent gears, so that when the typical value falls in the overlapping interval, a gear that is more suitable for measuring the chip to be tested can be selected in the adjacent gears, which can make the selection of the test gear more accurate and improve the accuracy of the chip measurement results. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 The figure is a schematic diagram showing the structure of a chip testing system according to an exemplary embodiment.

[0022] Figure 2 The figure is a flowchart of a chip signal testing method according to an exemplary embodiment.

[0023] Figure 3 A method application flowchart of a chip signal testing method is shown according to an exemplary embodiment.

[0024] Figure 4 It is a structural schematic diagram of a chip signal testing device provided in an embodiment of the present application.

[0025] Figure 5 It is a structural schematic diagram of a computer device provided by an optional embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0027] In the description of the embodiments of the present application, the term "corresponding" may indicate a direct or indirect correspondence between two items, or an association relationship between the two items, or a relationship between indication and being indicated, configuration and being configured, and the like.

[0028] Figure 1 FIG. 1 is a schematic diagram showing the structure of a chip testing system according to an exemplary embodiment. Figure 1 As shown, the chip testing system includes a signal generator 101, a chip under test 102 and a signal analyzer 103;

[0029] Among them, the signal generator is used to generate test signals to simulate various input conditions that the chip may encounter when working. By generating signals of different frequencies, powers, modulation methods, etc., the performance of the chip in different working environments can be simulated. The chip under test is the test object, which responds to the signal generated by the signal generator. By monitoring the output signal of the chip under test, it is possible to detect whether the chip works as expected, check its functions, performance, and whether it meets the design specifications.

[0030] The signal analyzer is used to monitor and analyze the output signal of the chip under test. By analyzing the frequency, amplitude, phase and other characteristics of the output signal, it can be determined whether the chip works normally when processing the signal.

[0031] In an embodiment of the present application, the signal analyzer includes several gears; any two adjacent gears in the several gears have overlapping intervals. For example, the maximum range of the signal analyzer test is -174dBm~30dBm. The test range of the signal analyzer is divided into different gears with 15dBm as a gear, and these gears have 5dBm overlap, for example, -15dBm~0dBm is a gear, -5dBm~10dBm is a gear, 5dBm~20dBm is a gear, and so on.

[0032] Figure 2 is a method flow chart of a chip signal testing method according to an exemplary embodiment. The method is executed by a computer device, which may be as follows Figure 1 The signal analyzer 103 in the chip test system shown in FIG. Figure 2 As shown, the chip signal testing method may include the following steps:

[0033] Step 201: Acquire a signal to be tested and a typical value of the signal to be tested.

[0034] When testing a chip, you first need to obtain the specific parameters of the signal to be tested, especially the typical power value of the signal. This can be achieved through pre-set test conditions or input signals simulated by a signal generator. The typical value is a characteristic value of the signal to be tested, which usually represents the normal power or frequency of the signal in actual work. The typical value is usually derived from the specifications, design parameters or historical data of the equipment. The acquisition of the signal to be tested and the typical value provides basic data for subsequent analysis.

[0035] Step 202, determining the relationship between the typical value of the signal to be measured and each gear position of the signal analyzer.

[0036] After obtaining the typical value of the signal to be tested, compare the typical value with the reference level interval of each gear of the signal analyzer. The gear design of the signal analyzer is usually based on different measurement range requirements, and each gear corresponds to a specific reference level interval. By comparison, it can be determined that the typical value of the signal to be tested is located in the reference level interval, or falls in the overlapping interval of two adjacent gears. For example, a signal analyzer may have different gear intervals (such as -15dBm~0dBm as one gear, -5dBm~10dBm as one gear, etc.), and it is necessary to determine in which intervals the typical value (such as -2dBm) falls.

[0037] Step 203: If there are two adjacent reference level intervals in the signal analyzer that both include the typical value, a critical value of the reference level interval of the two adjacent gears is obtained.

[0038] When it is found that the typical value of the signal to be tested is located in the overlapping interval of two adjacent gears, in order to ensure the accuracy of the test results, it is necessary to select a gear closer to the typical value of the signal to be tested for measurement, which requires further determination of the critical value between the two gears.

[0039] In the signal analyzer in the embodiment of the present application, there is an overlapping interval between the reference level intervals of two adjacent gears, for example, the gear of -15dBm~0dBm and the gear of -5dBm~10dBm are two adjacent gears, and the overlapping interval between the two is -5dBm~0dBm. However, if the typical power value of the chip under test is -1dBm at this time, considering the error between the typical power value and the actual power, when the gear of -15dBm~0dBm is selected to measure the chip under test, the actual power is likely to exceed 0dBm, that is, the reference level exceeds the selected gear, which may cause inaccurate measurement results.

[0040] Therefore, when the typical value falls in the overlapping interval of two adjacent gears, theoretically both adjacent gears can be used to detect the signal to be tested. At this time, in order to select a gear that is more suitable for the signal to be tested, the critical value of the two adjacent gears can be calculated and used as a reference for gear selection. For example, the critical value can be the midpoint of the overlapping interval of the two adjacent gears. By obtaining the critical value, it can help testers further narrow the selection range and ensure that the gear selection is more accurate. Since there is overlap in gears, the introduction of the critical value avoids the problem of ambiguity in gear selection and helps to improve the accuracy of the measurement.

[0041] Step 204 , determining a target gear position between the two adjacent gear positions according to the critical value and the typical value, so as to measure the signal to be measured through the target gear position.

[0042] For example, in an embodiment of the present application, the typical value can be compared with the critical value. The critical value can divide the overlapping interval of adjacent gears into two parts according to the size of the reference level. If the typical value is greater than or equal to the critical value, the typical value falls in the larger part of the reference level. At this time, the signal to be tested is more likely to fall in the reference level interval of the larger gear among the adjacent gears; similarly, if the typical value is less than the critical value, the typical value falls in the smaller part of the reference level. At this time, the signal to be tested is more likely to fall in the reference level interval of the smaller gear among the adjacent gears.

[0043] In summary, the overlapping design between adjacent gears of the present method enables the method to cope with test signals of different power ranges, and a critical value can be set in the overlapping interval of adjacent gears, so that when the typical value falls in the overlapping interval, a gear that is more suitable for measuring the chip to be tested can be selected from the adjacent gears, which can make the selection of the test gear more accurate and improve the accuracy of the chip measurement results.

[0044] Figure 3 is a method application flow chart of a chip signal testing method according to an exemplary embodiment. The method is executed by a computer device, which may be as follows Figure 1 The signal analyzer 103 in the chip test system shown in FIG. Figure 3 As shown, the application of the chip signal testing method may include the following steps:

[0045] Step 301: Acquire a signal to be tested and a typical value of the signal to be tested.

[0046] Optionally, the signal to be tested is generated after the chip under test receives a trigger signal sent by a signal generator.

[0047] Step 302, determining the relationship between the typical value of the signal to be measured and each gear position of the signal analyzer.

[0048] Step 303: If there are two adjacent reference level intervals of the signal analyzer that both include the typical value, a critical value of the reference level interval of the two adjacent gears is obtained.

[0049] The above steps 301 to 303 are similar to steps 201 to 203 and will not be repeated here.

[0050] Step 304 : determining a target gear position between the two adjacent gear positions according to the critical value and the typical value.

[0051] Optionally, the two adjacent gears include a first gear and a second gear; a median value of a reference horizontal interval of the first gear is smaller than a median value of a reference horizontal interval of the second gear;

[0052] When the typical value is less than the critical value, the signal analyzer takes the first gear as the target gear; when the typical value is greater than or equal to the critical value, the signal analyzer takes the second gear as the target gear.

[0053] The first gear and the second gear are two consecutive gears in the signal analyzer, which are used to measure signals of different ranges. For each gear, there is a corresponding reference level interval. The signal value in this interval is the range that can be measured by this gear, and the median is a specific point in the middle of this interval. The median of the reference level interval of the first gear is usually smaller than the median of the reference level interval of the second gear. The median of the overlapping interval of these two gears can be selected as the critical value, which is used to determine which gear the typical value of the signal to be tested should be classified into for testing.

[0054] When the typical value is less than the critical value, it means that the power of the signal to be tested is relatively low, so the first gear is selected as the target gear for testing because it covers a lower signal range. When the typical value is greater than or equal to the critical value, it means that the power of the signal to be tested is relatively high, so the second gear is selected as the target gear for testing because it can more accurately measure signals within this range.

[0055] That is, the signal analyzer can determine the target gear according to the comparison between the typical value and the critical value. If the typical value is less than the critical value, the gear with a smaller reference level is selected as the target gear (such as the first gear -15dBm~0dBm); if the typical value is greater than or equal to the critical value, the gear with a larger reference level is selected as the target gear (such as the second gear -5dBm~10dBm).

[0056] This step ensures that the typical value falls within the most appropriate range, avoiding measurement errors caused by selecting an inappropriate range. The logic of critical value and range selection further improves the adaptability and measurement accuracy of the signal analyzer.

[0057] Optionally, the critical value is the median of the overlapping interval between the first gear and the second gear.

[0058] The median refers to a specific value in the overlapping interval of two adjacent gears, which is located in the middle of the overlapping interval. Specifically, if the overlapping interval of the first gear and the second gear is from A to B (that is, A is the starting value of the overlapping interval and B is the ending value), then the median of the overlapping interval of the two gears is (A+B) / 2. For example, the overlapping part of the -15dBm~0dBm gear and the -5dBm~10dBm gear is -5dBm~0dBm, and the median value is -2.5dBm, so the critical value is set to -2.5dBm, and the signal greater than or equal to -2.5dBm selects the -5dBm~10dBm gear, and the signal less than -2.5dBm selects the -15dBm~0dBm gear. By using the median as the critical value, the signal to be tested can be more clearly assigned to one of the gears for testing, thereby avoiding measurement errors caused by incorrect gear selection.

[0059] Step 305: receiving a signal to be tested sent by the chip under test.

[0060] After the gear position is determined, the signal analyzer starts to receive the signal to be tested sent by the chip. At this time, the signal to be tested has been reasonably selected according to the typical value and the target gear position, and the signal received by the signal analyzer will be more accurate.

[0061] Step 306: measure the signal to be measured through the target gear position to obtain a first result.

[0062] The target gear is used to measure the signal to be measured, and the measurement result is the first result. The target gear collects signals through the hardware and software of the signal analyzer to obtain measurement data of power, frequency or other key indicators.

[0063] Step 307: Process the first result through the mapping relationship corresponding to the target gear position to obtain the test result of the chip under test.

[0064] After obtaining the first result, the signal analyzer further processes the measured data through the mapping relationship of the target gear, and finally obtains the true test result of the chip under test. The mapping relationship is implemented by a built-in table or algorithm in the signal analyzer, which is usually based on the standard value pre-calibrated with the typical value of the target gear and the signal.

[0065] The measurement results are converted into the actual performance values ​​of the chip through mapping relationships, further improving the accuracy of the results and ensuring that the measurement data can truly reflect the actual working status of the chip.

[0066] Optionally, before executing the above steps in the embodiment of the present application, the signal analyzer may further execute the following steps to obtain the mapping relationship of the target gear:

[0067] Obtaining each target signal value preset by the signal generator in the target gear position;

[0068] The target signal values ​​are measured through the target gear position to obtain the calibration results;

[0069] The mapping relationship of the target gear is determined according to the various calibration results and the various target signal values.

[0070] Before the above steps, the signal analyzer can be calibrated. A series of target signal values ​​(such as power values) are sent to the signal analyzer through the signal generator. The signal analyzer measures these signal values ​​and compares them with the target values ​​to obtain the calibration results. Based on the difference between the measurement results and the target signal values, a mapping relationship of the target gear is generated.

[0071] Specifically, the signal generator is set to emit a series of preset target signal values ​​within the target gear. The target signal value is a known value used to verify the accuracy of the signal analyzer during the calibration process, covering the entire measurement range of the target gear, especially the value located in the gear overlap interval, to ensure the comprehensiveness and accuracy of the calibration. Next, the signal analyzer receives and measures these target signal values ​​emitted by the signal generator at the target gear. During the measurement process, the signal analyzer records the readings corresponding to each target signal value, which constitute the results to be calibrated. The results to be calibrated include deviations caused by equipment performance, environmental factors or measurement errors. The calibrator compares each target signal value and its corresponding result to be calibrated, identifies the deviations in the measurement process, and determines a mapping relationship. The mapping relationship describes the conversion relationship from the signal analyzer reading to the actual target signal value, which is used to correct the measurement results in subsequent tests.

[0072] For example, calibrate each gear position separately. Take the gear position of 5dBm~20dBm as an example, set the interval of 0.1dBm, and the signal generator sends out target signal values ​​such as 5dBm, 5.1dBm, 5.2dBm~19.8dBm, 19.9dBm, and 20dBm in turn. The signal analyzer receives these signals respectively and records the corresponding relationship between the signal sent and the received signal under this gear position. The purpose of calibration is to avoid errors in the test process. After knowing the corresponding relationship, when actually testing an unknown signal value, the real input signal value can be calculated based on the read signal and the corresponding relationship. For the countless signal values ​​in 5dBm~5.1dBm, it can be assumed that their changes are linear, and the specific corresponding relationship can be calculated by interpolation.

[0073] Then, if you want to measure a target signal with a typical value of 5dBm, you should first select the range of -5dBm~10dBm. The signal analyzer receives a signal of, for example, 5.3dBm, and then according to the corresponding relationship, you can get the actual value of the target signal to be 5.1dBm.

[0074] Combining the above steps, if you want to measure a target signal with a typical value of -2dBm, there are two gears containing -2dBm, namely -15dBm~0dBm and -5dBm~10dBm. Then, it is judged that -2 is greater than -2.5, so the -5dBm~10dBm gear is selected. The signal analyzer receives a signal of, for example, -2.5dBm, and then the actual value of the target signal can be obtained according to the corresponding relationship.

[0075] In summary, the chip signal testing method of the present application first obtains the signal to be tested and the typical value of the signal to be tested, which is the data basis for subsequent test analysis. Then, through comparative analysis, the relationship between the typical value of the signal to be tested and the various gears of the signal analyzer is determined. If the reference level intervals of two adjacent gears in the signal analyzer both include typical values, the critical value of the reference level interval of the two adjacent gears is obtained. Finally, the typical value and the critical value are compared, and the target gear is determined in the two adjacent gears through the comparison result to measure the signal to be tested through the target gear. In the above scheme, the overlapping design between adjacent gears enables the method to cope with signals to be tested in different power ranges, and a critical value can be set in the overlapping interval of adjacent gears, so that when the typical value falls in the overlapping interval, a gear that is more suitable for measuring the chip to be tested can be selected from the adjacent gears, which can make the selection of the test gear more accurate and improve the accuracy of the chip measurement results;

[0076] Furthermore, in the embodiment of the present application, by obtaining the difference between the measurement result and the target signal value and forming a mapping relationship for the difference, the mapping relationship corresponding to each range in the signal analyzer can be obtained. At this time, when the test result needs to be measured, the test result can be corrected based on the mapping relationship, and the test reference level can be set more effectively, thereby improving the accuracy of the test result.

[0077] In the embodiments of the present application, a chip signal testing device is also provided, which is used to implement the above embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware for a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0078] The present application embodiment provides a chip signal testing device, Figure 4 : is a schematic diagram of a chip signal testing device provided in an embodiment of the present application, the device comprising:

[0079] The signal acquisition module 401 is used to acquire the signal to be tested and the typical value of the signal to be tested;

[0080] The gear determination module 402 determines the relationship between the typical value of the signal to be measured and each gear of the signal analyzer;

[0081] The critical value judgment module 403 is used to obtain the critical value of the reference level interval of the two adjacent gears if the reference level intervals of the two adjacent gears in the signal analyzer both include typical values; the critical value is the median of the overlapping interval of the reference level intervals of the two adjacent gears;

[0082] The measuring module 404 is used to determine a target gear position between two adjacent gear positions according to the critical value and the typical value, so as to measure the signal to be measured through the target gear position.

[0083] In a possible implementation, the two adjacent gears include a first gear and a second gear; a median value of a reference horizontal interval of the first gear is smaller than a median value of a reference horizontal interval of the second gear;

[0084] The gear determination module is used to:

[0085] When the typical value is less than the critical value, the first gear is used as the target gear;

[0086] When the typical value is greater than or equal to the critical value, the second gear is used as the target gear.

[0087] In a possible implementation, the measuring module is further configured to:

[0088] Receive the signal to be tested sent by the chip under test;

[0089] The signal to be measured is measured by the target gear position to obtain a first result;

[0090] The first result is processed according to the mapping relationship corresponding to the target gear position to obtain the test result of the chip under test.

[0091] In a possible implementation, the signal to be tested is generated after the chip under test receives a trigger signal sent by a signal generator.

[0092] In a possible implementation, the device further includes:

[0093] A preset signal acquisition module is used to obtain each target signal value preset by the signal generator in the target gear position;

[0094] A pre-measurement module is used to measure each target signal value through the target gear position to obtain each calibration result;

[0095] The mapping relationship acquisition module is used to determine the mapping relationship of the target gear according to each calibration result and each target signal value.

[0096] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0097] The terminal authentication device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0098] The embodiment of the present invention also provides a computer device having the above Figure 4 A chip signal testing device is shown.

[0099] See also Figure 5 , Figure 5 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 5 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process instructions executed in the computer device, including instructions stored in or on the memory to display graphic information in a graphical user interface on an external input / output device (such as a display device coupled to an interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 5 A processor 10 is taken as an example.

[0100] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0101] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0102] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0103] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0104] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0105] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0106] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0107] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A chip signal testing method, characterized in that: The method is applied to a signal analyzer; the signal analyzer includes a plurality of gears; any two adjacent gears among the plurality of gears have overlapping intervals, and the method includes: Acquire a signal to be tested and a typical value of the signal to be tested; Determine the relationship between the typical value of the signal to be measured and each gear position of the signal analyzer; If there are two adjacent gear positions in the signal analyzer, both of which have reference level intervals including the typical value, then a critical value of the reference level intervals of the two adjacent gear positions is obtained; the critical value is the median value of the overlapping intervals of the reference level intervals of the two adjacent gear positions; the two adjacent gear positions include a first gear position and a second gear position; the median value of the reference level interval of the first gear position is smaller than the median value of the reference level interval of the second gear position; When the typical value is less than the critical value, taking the first gear as the target gear; When the typical value is greater than or equal to the critical value, taking the second gear as the target gear; The signal to be measured is measured through the target gear position.

2. The method according to claim 1, characterized in that: The measuring the signal to be measured through the target gear position includes: Receive the signal to be tested sent by the chip under test; Measuring the signal to be measured through the target gear position to obtain a first result; The first result is processed according to the mapping relationship corresponding to the target gear position to obtain the test result of the chip under test.

3. The method according to claim 2, characterized in that The signal to be tested is generated after the chip under test receives a trigger signal sent by a signal generator.

4. The method according to claim 2, characterized in that: The method further comprises: Acquiring each target signal value preset by the signal generator in the target gear position; Measuring each target signal value through the target gear position to obtain each calibration result; The mapping relationship of the target gear is determined according to the various calibration results and the various target signal values.

5. A chip signal testing device, characterized in that: The device is applied to a signal analyzer; the signal analyzer includes a plurality of gears; any two adjacent gears among the plurality of gears have overlapping intervals, and the device includes: A signal acquisition module, used to acquire a signal to be tested and a typical value of the signal to be tested; A gear determination module, which determines the relationship between the typical value of the signal to be measured and each gear of the signal analyzer; A critical value judgment module, used for obtaining the critical value of the reference level interval of the two adjacent gears if the reference level intervals of the two adjacent gears in the signal analyzer both include the typical value; the critical value is the median value of the overlapping interval of the reference level intervals of the two adjacent gears; the two adjacent gears include a first gear and a second gear; the median value of the reference level interval of the first gear is smaller than the median value of the reference level interval of the second gear; a measuring module, configured to use the first gear as a target gear when the typical value is less than the critical value; When the typical value is greater than or equal to the critical value, taking the second gear as the target gear; The signal to be measured is measured through the target gear position.

6. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the chip signal testing method according to any one of claims 1 to 4 by executing the computer instructions.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the chip signal testing method according to any one of claims 1 to 4.

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