A regulating circuit, regulating module and data acquisition system

Abstract

This application provides an adjustment circuit, an adjustment module, and a data acquisition system. The input terminal of the adjustment circuit is connected to a signal transmitting unit, and the output terminal is connected to a signal processing unit. The adjustment circuit includes a first branch and a second branch, which are connected in parallel between the input and output terminals. The first branch includes a resistor unit, and the second branch includes a first capacitor unit and a first voltage conversion unit connected in series with the first capacitor unit. The first voltage conversion unit is used to convert the amplitude of a first signal output by the signal transmitting unit to obtain a second signal, thereby adjusting the capacitance between the output terminal of the adjustment circuit and a reference ground. Implementing this application can improve adjustment accuracy and reduce adjustment error.

Description

Technical Field

[0001] This application relates to the field of signal processing, and more particularly to a modulation circuit, modulation module, and data acquisition system. Background Technology

[0002] The signal output from the signal transmitting unit needs to be transmitted to the signal processing unit via a transmission circuit. Due to circuit parameters such as trace length and resistor / capacitor values, the signal transmitted through the transmission circuit experiences a delay, meaning it arrives at the signal processing unit later than the signal output from the signal transmitting unit. Furthermore, the amount of this delay is uncontrollable and depends primarily on the circuit parameters.

[0003] To control the delay of the signal after it passes through the transmission circuit, the current method is... Figure 1 The delay adjustment circuit shown in the diagram is used for adjustment. Specifically, this delay adjustment circuit adjusts the delay amount after the signal passes through the transmission circuit by changing the resistance value of the digital potentiometer R1. In this case, the adjustment error of the delay adjustment circuit is related to the accuracy of the resistance value of the digital potentiometer R1. Because the current digital potentiometer R1 has relatively low resistance accuracy, the adjustment error of the delay adjustment circuit is large. Summary of the Invention

[0004] This application provides an adjustment circuit, an adjustment module, and a data acquisition system, which can improve adjustment accuracy and reduce adjustment error.

[0005] In a first aspect, embodiments of this application provide an adjustment circuit, the input terminal of which is connected to a signal transmitting unit, and the output terminal of which is connected to a signal processing unit. The adjustment circuit includes a first branch and a second branch, which are connected in parallel between the input terminal and the output terminal of the adjustment circuit.

[0006] In a specific implementation, the first branch includes a resistor unit, and the second branch includes a first capacitor unit and a first voltage conversion unit connected in series with the first capacitor unit. The first voltage conversion unit converts the amplitude of the first signal output by the signal transmitting unit to obtain a second signal, so as to adjust the capacitance between the output terminal of the adjustment circuit and the reference ground.

[0007] This application provides a novel circuit structure for an adjustment circuit. Unlike existing technologies that rely on digital potentiometers to adjust signals, this application adjusts the capacitance between the output terminal of the adjustment circuit and the reference ground by changing the coefficient of the first voltage conversion unit that transforms the amplitude of the first signal. Implementing this application improves adjustment accuracy, reduces adjustment error, and, in addition to achieving signal delay, also achieves signal lead, offering good flexibility and wide applicability.

[0008] In conjunction with the first aspect, in a first possible implementation, the phase difference between the first signal and the signal received by the signal processing unit is determined based on the resistance value of the resistor unit and the capacitance between the output terminal of the adjustment circuit and the reference ground. That is, the adjustment circuit can change the phase adjustment amount of the first signal by controlling the capacitance between the output terminal of the adjustment current and the reference ground.

[0009] In a second possible implementation, in conjunction with the first aspect or the first possible implementation of the first aspect, when the amplitude of the second signal is less than the amplitude of the first signal, the phase of the signal received by the signal processing unit lags behind the phase of the first signal.

[0010] In a third possible implementation, in conjunction with the first aspect or the first possible implementation of the first aspect, when the amplitude of the second signal is greater than the amplitude of the first signal, the phase of the signal received by the signal processing unit leads the phase of the first signal.

[0011] In a fourth possible implementation, in conjunction with the first aspect or any of the above possible implementations of the first aspect, the adjustment circuit further includes a third branch connected in parallel with the second branch, the third branch including a second capacitor unit and a second voltage conversion unit connected in series with the second capacitor unit.

[0012] In a specific implementation, the second voltage conversion unit transforms the amplitude of the first signal output by the signal transmission unit to obtain a third signal, which is used to adjust the capacitance between the output of the adjustment circuit and the reference ground. Compared to setting a first branch and a second branch in the adjustment circuit, this embodiment adds a third branch connected in parallel with the second branch, which expands the adjustment range of the capacitance between the output of the adjustment circuit and the reference ground, thereby increasing the range of phase adjustment of the adjustment circuit.

[0013] In conjunction with the fourth possible implementation of the first aspect, in the fifth possible implementation, the difference between the capacitance value of the first capacitor unit and the capacitance value of the second capacitor unit is greater than a preset threshold. In this embodiment, by widening the gap between the capacitance values ​​of the first capacitor unit in the second branch and the second capacitor unit in the third branch, it can be ensured that one branch of the second and third branches can achieve coarse phase adjustment, while the other branch achieves fine phase adjustment. By increasing the range of phase adjustment in the adjustment circuit, a combination of coarse and fine adjustment can be achieved, improving the resolution of the phase adjustment in the adjustment circuit.

[0014] In a sixth possible implementation, in conjunction with the first aspect or any of the above possible implementations of the first aspect, the adjustment circuit further includes a buffer unit.

[0015] The aforementioned buffer unit is located between the parallel connection point and the output terminal of the regulating circuit, wherein the parallel connection point is the connection point after the first branch and the second branch are connected in parallel. In this embodiment, by setting a buffer unit between the connection point after the first branch and the second branch are connected in parallel and the output terminal of the regulating circuit, the buffer unit can isolate the interference between the output terminal of the regulating circuit and the signal processing unit, ensuring the stability of the regulating circuit and the signal processing unit.

[0016] In a seventh possible implementation, in conjunction with the first aspect or any of the above possible implementations of the first aspect, the regulating circuit further includes a third branch connected in parallel with the second branch, the third branch including a second voltage conversion unit and a second capacitor unit connected in series with the second voltage conversion unit.

[0017] The aforementioned first voltage conversion unit may include a programmable gain amplifier, a proportional amplifier, or a voltage-controlled gain amplifier. Similarly, the second voltage conversion unit in the third branch may include a programmable gain amplifier, a proportional amplifier, a voltage-controlled gain amplifier, or a multiplicative DAC. It should be explained that because programmable gain amplifiers, proportional amplifiers, or voltage-controlled gain amplifiers have high adjustment resolution, including a programmable gain amplifier, a proportional amplifier, or a voltage-controlled gain amplifier in the first voltage conversion unit ensures that the first voltage conversion unit has high adjustment resolution. Likewise, including a programmable gain amplifier, a proportional amplifier, or a voltage-controlled gain amplifier in the second voltage conversion unit ensures that the second voltage conversion unit has high adjustment resolution, thereby guaranteeing the adjustment accuracy of the adjustment circuit.

[0018] Secondly, embodiments of this application also provide an adjustment module, which includes at least two adjustment circuits. The input terminals of each adjustment circuit are respectively connected to a signal transmitting unit corresponding to each adjustment circuit to receive the first signal output by their respective signal transmitting units. Meanwhile, the output terminals of each adjustment circuit are connected to a signal processing unit.

[0019] Each of the aforementioned adjustment circuits includes a first branch and a second branch, which are connected in parallel between the input and output terminals of their respective adjustment circuits. The first branch includes a resistor unit, and the second branch includes a first capacitor unit and a first voltage conversion unit connected in series with the first capacitor unit. In a specific implementation, each of the aforementioned adjustment circuits may include a first adjustment circuit. The first voltage conversion unit of the first adjustment circuit transforms the amplitude of the first signal corresponding to the first adjustment circuit based on the phase difference between the first target signal and the first signal corresponding to the first adjustment circuit, thereby obtaining a second signal corresponding to the first adjustment circuit. This second signal is used to adjust the capacitance between the output terminal of the first adjustment circuit and the reference ground to the first target capacitance value corresponding to the first target signal.

[0020] In this embodiment, the first voltage conversion unit transforms the amplitude of the first signal based on the first target signal to adjust the capacitance between the output terminal of the first adjustment circuit and the reference ground to the first target capacitance value. Furthermore, the first adjustment circuit can adjust the phase of the first signal based on the resistance value of the resistor unit and the first target capacitance value to output a signal to the signal processing unit whose phase is consistent with the phase of the first target signal; that is, the signal phase received by the signal processing unit is consistent with the phase of the first target signal.

[0021] In conjunction with the second aspect, in the first possible implementation, each adjustment circuit includes a second adjustment circuit. The first target signal is the signal output by the second adjustment circuit to the signal processing unit. In this embodiment, the second adjustment circuit in the adjustment module is used as a reference adjustment circuit, so that the second adjustment circuit does not need to perform phase adjustment, thus saving adjustment resources in the adjustment module while ensuring that the signal processing unit can synchronously acquire signals.

[0022] In conjunction with the second aspect, in the second possible implementation, each adjustment circuit of the adjustment module includes a second adjustment circuit.

[0023] The first voltage conversion unit of the second adjustment circuit transforms the amplitude of the first signal corresponding to the second adjustment circuit according to the phase difference between the first target signal and the first signal corresponding to the second adjustment circuit to obtain the second signal corresponding to the second adjustment circuit, so as to adjust the capacitance between the output terminal of the second adjustment circuit and the reference ground to the second target capacitance value corresponding to the first target signal. The first target signal is determined according to the first signal corresponding to the first adjustment circuit and the first signal corresponding to the second adjustment circuit.

[0024] In a third possible implementation, combining the second aspect and the second possible implementation, when the phase of the first target signal leads the phase of both the first signal corresponding to the first adjustment circuit and the first signal corresponding to the second adjustment circuit, the first voltage conversion unit of the second adjustment circuit increases the amplitude of the first signal corresponding to the second adjustment circuit based on the phase difference between the first target signal and the first signal corresponding to the second adjustment circuit, thereby adjusting the capacitance between the output terminal of the second adjustment circuit and the reference ground to the second target capacitance value corresponding to the first target signal. Similarly, the first adjustment circuit increases the amplitude of the first signal corresponding to the first adjustment circuit based on the phase difference between the first target signal and the first signal corresponding to the first adjustment circuit, so that the first adjustment circuit leads the phase of the corresponding first signal, i.e., the phase of the signal output by the first adjustment circuit received by the signal processing unit leads the phase of the first signal corresponding to the first adjustment circuit. At this time, the phases of the signal output by the first adjustment circuit and the signal output by the second adjustment circuit are the same. In this embodiment, each adjustment circuit in the adjustment module adjusts the first signal it receives in advance, which improves the acquisition efficiency of the signal processing unit while ensuring that the signal processing unit can acquire signals synchronously.

[0025] In conjunction with the second possible implementation of the second aspect, in the fourth possible implementation, when the phase of the first target signal lags behind the phase of both the first signal corresponding to the first adjustment circuit and the first signal corresponding to the second adjustment circuit, the first voltage conversion unit of the second adjustment circuit reduces the amplitude of the first signal corresponding to the second adjustment circuit based on the phase difference between the first target signal and the first signal corresponding to the second adjustment circuit, thereby adjusting the capacitance between the output terminal of the second adjustment circuit and the reference ground to the second target capacitance value corresponding to the first target signal. Similarly, the first adjustment circuit reduces the amplitude of the first signal corresponding to the first adjustment circuit based on the phase difference between the first target signal and the first signal corresponding to the first adjustment circuit, so that the first adjustment circuit lags behind the phase of the corresponding first signal, i.e., the phase of the signal output by the first adjustment circuit received by the signal processing unit lags behind the phase of the first signal corresponding to the first adjustment circuit. At this time, the phase of the signal output by the first adjustment circuit received by the signal processing unit is the same as the phase of the signal output by the second adjustment circuit. In the embodiments of this application, the lag adjustment of each adjustment circuit in the adjustment module on its respective received first signal can ensure that the signal processing unit synchronously acquires signals.

[0026] In conjunction with the second possible implementation of the second aspect, in the fifth possible implementation, when the phase of the first target signal leads the phase of the first signal corresponding to the first adjustment circuit but lags behind the phase of the first signal corresponding to the second adjustment circuit, the first voltage conversion unit of the second adjustment circuit reduces the amplitude of the first signal corresponding to the second adjustment circuit based on the phase difference between the first target signal and the first signal corresponding to the second adjustment circuit, thereby adjusting the capacitance between the output terminal of the second adjustment circuit and the reference ground to the second target capacitance value corresponding to the first target signal. Furthermore, the first adjustment circuit increases the amplitude of the first signal corresponding to the first adjustment circuit based on the phase difference between the first target signal and the first signal corresponding to the first adjustment circuit, so that the first adjustment circuit leads the phase of the corresponding first signal. At this time, the signal received by the signal processing unit has the same phase as the signal output by the first adjustment circuit and the signal output by the second adjustment circuit. In this embodiment, different adjustment circuits in the adjustment module can respectively perform lag adjustment or lead adjustment on their respective received first signals, providing multiple phase adjustment methods while ensuring synchronous signal acquisition by the signal processing unit.

[0027] Thirdly, embodiments of this application also provide a data acquisition system, which includes a signal transmitting unit, a signal processing unit, and an adjustment circuit as described in the first aspect or any of the possible implementations of the first aspect; or, the data acquisition system includes a signal transmitting unit, a signal processing unit, and an adjustment module as described in the second aspect or any of the possible implementations of the second aspect.

[0028] It should be understood that the implementations and beneficial effects of the above-mentioned aspects of this application can be referenced from each other. Attached Figure Description

[0029] Figure 1 A delay adjustment circuit provided for the prior art;

[0030] Figure 2 A structural block diagram of a data acquisition system provided in an embodiment of this application;

[0031] Figure 3 Another structural block diagram of the data acquisition system provided in the embodiments of this application;

[0032] Figure 4 A structural block diagram of a data acquisition system provided for the present technology;

[0033] Figure 5 A structural block diagram of the adjustment circuit provided in an embodiment of this application;

[0034] Figure 6 A waveform diagram of a signal provided in an embodiment of this application;

[0035] Figure 7 Another structural block diagram of the adjustment circuit provided in the embodiments of this application;

[0036] Figure 8 Another structural block diagram of the adjustment circuit provided in the embodiments of this application;

[0037] Figure 9 Another structural block diagram of the adjustment circuit provided in the embodiments of this application;

[0038] Figure 10 This is a structural block diagram of the adjustment module provided in an embodiment of this application. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0040] The implementation of the technical solution of this application will be further described in detail below with reference to the accompanying drawings.

[0041] In some feasible implementations, see Figure 2 , Figure 2 This is a schematic diagram of the structure of a data acquisition system provided in an embodiment of this application. Figure 2 As shown, the data acquisition system 20 includes a signal transmission unit 201, an adjustment circuit 202, and a signal processing unit 203, wherein the signal transmission unit 201 is connected to the signal processing unit 203 through the adjustment circuit 202.

[0042] For example, the signal transmitting unit 201 may have the functions of signal generation and signal output. The signal transmitting unit 201 may be specifically implemented as an analog signal source, such as a signal generator, which directly outputs a first signal to the adjustment circuit 202. Alternatively, the signal transmitting unit 201 may be implemented as an analog signal source and at least one transmission circuit, where the signal output by the analog signal source is transmitted through the transmission circuit to obtain the first signal.

[0043] The adjustment circuit 202 can adjust the phase of the first signal output by the signal transmitting unit 201. For example, after the adjustment circuit 202 adjusts the phase of the first signal, the resulting signal lags behind the phase of the first signal, i.e., the signal is delayed. Alternatively, after the adjustment circuit 202 adjusts the phase of the first signal, the resulting signal leads the phase of the first signal, i.e., the signal is ahead.

[0044] The signal processing unit 203 receives the signal obtained after the adjustment circuit 202 adjusts the phase of the first signal. For example, the signal processing unit 203 can be specifically implemented as a micro control unit (MCU), a central processing unit (CPU), other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0045] It is understood that the signal obtained after the adjustment circuit 202 adjusts the phase of the first signal is an analog signal. For example, the signal processing unit 203 can be specifically implemented as an integrated circuit chip with an analog-to-digital converter (ADC) function, which can convert the analog signal into a digital signal for acquisition. Optionally, the signal processing unit 203 can also be specifically implemented as an ADC and a processor, in which case the signal processing unit 203 can be specifically implemented as two integrated circuit chips, with the processor acquiring the digital signal converted by the ADC. That is, this application embodiment does not limit the number of integrated circuit chips included in the signal processing unit 203.

[0046] In this embodiment, the data acquisition system adjusts the first signal without relying on a digital potentiometer by changing the circuit structure of the adjustment circuit. Implementing this embodiment improves the adjustment accuracy of the signal delay by the adjustment circuit, reduces adjustment errors, and in addition to achieving signal delay, the data acquisition system provided by this embodiment can also achieve signal lead, offering good flexibility and strong applicability.

[0047] Optionally, in some feasible implementations, see [link to relevant documentation]. Figure 3 , Figure 3 This is another structural schematic diagram of the data acquisition system provided in an embodiment of this application. For example... Figure 3 As shown, the data acquisition system 30 includes an adjustment module 302, which comprises at least two adjustment circuits relative to... Figure 2 The data acquisition system 20 shown in the figure, and the data acquisition system 30 provided in the embodiments of this application, include at least two adjustment circuits, such as adjustment circuit 3021, adjustment circuit 3022, and adjustment circuit 302n, wherein n is greater than or equal to 3.

[0048] In the data acquisition system 30, the input terminals of each adjustment circuit are connected to their respective signal transmission units. For example... Figure 3 As shown, the input terminal of the adjustment circuit 3021 is connected to the signal transmitting unit 3011 to receive the first signal output by the signal transmitting unit 3011; the input terminal of the adjustment circuit 3022 is connected to the signal transmitting unit 3012 to receive the first signal output by the signal transmitting unit 3012; and the input terminal of the adjustment circuit 302n is connected to the signal transmitting unit 301n to receive the first signal output by the signal transmitting unit 301n.

[0049] It should be noted that, Figure 3 The statement that one regulation circuit corresponds to one signal transmission unit should be understood as an example. In some feasible implementations, two or more regulation circuits may share one signal transmission unit.

[0050] The output of each adjustment circuit is connected to the signal processing unit 303. For example, a specific implementation of the signal processing unit 303 can be found in [reference needed]. Figure 2 The signal processing unit 203 shown in the figure will not be described in detail here.

[0051] The signal processing unit 303 can receive signals after adjustment by each adjustment circuit, that is, the signal processing unit 303 can collect signals after adjustment by multiple adjustment circuits.

[0052] It is understandable that each signal transmitting unit may contain analog circuits. The different circuit parameters of these analog circuits result in different times when the first signal is output by each signal transmitting unit, meaning that the times at which the first signal is received by each regulating circuit are different. Furthermore, during the transmission of the first signal output by each signal transmitting unit to its corresponding regulating circuit, the circuit parameters of the transmission circuit for each signal transmitting unit are also different. Even if each signal transmitting unit can output its first signal simultaneously, the times at which the first signal is received by each regulating circuit will still differ.

[0053] Since the signal processing unit needs to synchronously acquire signals in the data acquisition system, in this embodiment, each adjustment circuit can perform phase adjustment on its received first signal, so that the phase of the signal output by each adjustment circuit to the signal processing unit is the same, ensuring that the signal processing unit can synchronously acquire the signals output by different adjustment circuits. That is, each adjustment circuit performs phase adjustment on its received first signal, so that the time elapsed from the output of the first signal by each signal transmitting unit to the reception of the signal output by the adjustment circuit corresponding to each signal transmitting unit by the signal processing unit is the same.

[0054] In specific implementation, the various adjustment circuits in this application embodiment adjust the phase of the received first signal by adjusting the capacitance between their respective output terminals and the reference ground. Unlike existing technologies that use software control to enable the signal processing unit to synchronously acquire the first signals output by different signal transmitting units, this application embodiment uses a change in the circuit structure of the adjustment circuits to enable the signal processing unit to synchronously acquire signals output by different adjustment circuits.

[0055] To better understand the differences between the embodiments of this application and existing data acquisition systems in achieving synchronous signal acquisition, the following will be combined with... Figure 4 Introduce existing technologies. For example... Figure 4 As shown, signal transmitting units 4011, 4012, and 401m can output a first signal to the corresponding ADC. The ADC acquires each first signal and transmits it to the processor 403 for processing. There is a time difference between the first signals output by each signal transmitting unit. The processor adjusts the trigger time of the ADC's sampling pulse signal (Sample) to achieve synchronous acquisition of the first signals output by different signal transmitting units. Specifically, existing technology measures the time difference between the first signals output by every two signal transmitting units and compensates this time difference into the ADC's sampling pulse signal. For example, if the time difference between the first signals output by signal transmitting units 4011 and 4012 is dt, and assuming the trigger time for ADC 4021 to acquire the sampling pulse signal of signal transmitting unit 4011 is at time t0, then the trigger time for ADC 4021 to acquire the sampling pulse signal of signal transmitting unit 4011 is at time t0+dt. Therefore, the processor 403 can simultaneously (i.e. synchronously) acquire the first signal output by the signal transmitting unit 4011 and the signal transmitting unit 4012 at time t0+dt.

[0056] Existing technologies using this software control method can only achieve signal delay adjustment, and the adjustment accuracy depends on the processor's clock frequency. Even with a processor with a clock frequency of 100MHz, the adjustment accuracy of the signal delay can only reach 10ns, meaning that the adjustment accuracy of existing technologies is low.

[0057] Implementing the embodiments of this application provides a different data acquisition system. This system modifies the circuit structure of each adjustment circuit in the adjustment module, allowing for the adjustment of the phase of each received first signal. The adjusted signals are then transmitted to the signal processing unit, enabling the signal processing unit to synchronously acquire the signals output by different adjustment circuits. Implementing the embodiments of this application reduces adjustment errors and improves adjustment accuracy while achieving synchronous acquisition of signals output by multiple signal transmitting units.

[0058] In some feasible implementations, the data acquisition system 20 or data acquisition system 30 can be applied in scenarios such as base stations, terminal devices, radar, and wireless Fidelity (WIFI). The terminal devices can be, for example, smart wearable devices, smartphones, tablets, laptops, in-vehicle computers, servers, and smart cars. This application does not limit the specific implementation of the terminal devices.

[0059] The circuit structure of the adjustment circuit provided in this application will be described in detail below with reference to the accompanying drawings.

[0060] In some feasible implementations, see Figure 5 , Figure 5 This is a circuit structure block diagram of the adjustment circuit provided in an embodiment of this application. Figure 5 As shown, the input terminal of the adjustment circuit 50 is connected to the signal transmitting unit 51, and the output terminal of the adjustment circuit 50 is connected to the signal processing unit 52. The adjustment circuit 50 includes a first branch 501 and a second branch 502, which are connected in parallel between the input terminal and the output terminal of the adjustment circuit 50; that is, the first branch 501 and the second branch 502 are connected in parallel between the signal transmitting unit 51 and the signal processing unit 52.

[0061] The first branch 501 includes a resistor unit. Among them, Figure 5 Taking a resistor unit specifically including a resistor R51 as an example, in some feasible implementations, the resistor unit involved in this application may include two or more resistors. These two or more resistors may be connected in series, in parallel, or in a series-parallel connection. That is, the embodiments of this application do not limit the number of resistors included in the resistor unit, nor do they limit the connection relationship between the multiple resistors included in the resistor unit.

[0062] One end of resistor R51 is connected to signal transmitting unit 51, and the other end of resistor R51 is connected to signal processing unit 52.

[0063] The second branch 502 includes a first capacitor unit and a first voltage conversion unit 5021 connected in series with the first capacitor unit. Figure 5 Taking the first capacitor unit as specifically including a capacitor C51 as an example, in some feasible embodiments, the capacitor unit involved in this application may include two or more capacitors. The two or more capacitors may be connected in series, in parallel, or in a series-parallel connection. That is, the embodiments of this application do not limit the number of capacitors in the first capacitor unit, nor do they limit the connection relationship between the multiple capacitors included in the first capacitor unit.

[0064] For example, one end of the first voltage conversion unit 5021 is connected to the signal transmitting unit 51, and the other end of the first voltage conversion unit 5021 can be connected to the signal processing unit 52 through the capacitor C51. Alternatively, one end of the capacitor is connected to the input terminal of the adjustment circuit, and the other end of the capacitor is connected to the output terminal of the adjustment circuit through the first voltage conversion unit. That is, the relative positions of the first voltage conversion unit and the capacitor can be interchanged. Figure 5 The relative positional relationship between capacitor C51 and the first voltage conversion unit 5021 shown is only an example.

[0065] The second branch 502 can be specifically equivalent to a capacitive branch, and forms an RC parallel circuit with the first branch 501. The capacitance value of the capacitive branch can be understood as the capacitance between the output terminal of the adjustment circuit 50 and the reference ground.

[0066] In a specific implementation, the signal transmitting unit 51 outputs a first signal, which is transmitted to the adjustment circuit 50. The first voltage conversion unit 5021 converts the amplitude of the first signal to obtain a second signal, thereby changing the capacitance between the output terminal of the adjustment circuit 50 and the reference ground.

[0067] The capacitance between the output terminal of the adjustment circuit 50 and the reference ground, as well as the resistor R51, determine the phase adjustment amount of the adjustment circuit 50, that is, the phase difference between the first signal and the signal received by the signal processing unit 52. The system function H(s) of the adjustment circuit 50 can be expressed as:

[0068]

[0069] Where s = 2πfi, f is the frequency of the first signal, i is the imaginary unit; R1 is the resistance value of resistor R51; C1 is the capacitance value of capacitor C51; D1 represents the coefficient by which the first voltage conversion unit 5021 converts the amplitude of the first signal, that is, the ratio between the amplitude of the second signal and the amplitude of the first signal.

[0070] According to Formula 1, the phase adjustment amount Δθ of the adjustment circuit 50 can be expressed as:

[0071] Δθ=tan -1 (2πfR1C4D1)-tan -1 (2πfR1C1) Formula 2

[0072] Based on the relationship between phase and time, the time adjustment amount Δt of the regulating circuit 50 can be expressed as follows using Formula 2:

[0073]

[0074] When the frequency f of the first signal is much smaller than At that time, that is When formula 3 is simplified, we can obtain formula 4 as follows:

[0075] Δt≈R1C1(D1-1) Formula 4

[0076] C1(D1-1) can be understood as the capacitance between the output terminal of the adjustment circuit 50 and the reference ground. The capacitance between the output terminal of the adjustment circuit 50 and the reference ground changes with the ratio D1 between the amplitude of the second signal and the amplitude of the first signal.

[0077] Therefore, in this embodiment of the application, the capacitance between the output terminal of the adjustment circuit and the reference ground can be changed by adjusting the ratio between the amplitude of the second signal and the amplitude of the first signal, thereby controlling the time adjustment amount of the adjustment circuit, that is, controlling the phase adjustment amount of the adjustment circuit.

[0078] For example, the coefficient D1 of the first voltage conversion unit 5021 for converting the amplitude of the first signal is less than 1. That is, the first voltage conversion unit 5021 reduces the amplitude of the first signal to obtain the second signal, and the amplitude of the second signal is less than the amplitude of the first signal. At this time, according to Formula 4, the time adjustment amount Δt of the adjustment circuit 50 is less than 0, and therefore the phase adjustment amount Δθ of the adjustment circuit 50 is also less than 0. Therefore, the phase of the signal received by the signal processing unit 52 lags behind the phase of the first signal.

[0079] For example, with Figure 6 The waveform of the signal shown is used to illustrate signal hysteresis as an example. For example... Figure 6 As shown, the first signal output by the signal transmitting unit 51 is represented as signal V1. When the amplitude of the second signal is less than the amplitude of the first signal, the signal received by the signal processing unit 52 is represented as signal V. a It can be seen that signal V a To the right of signal V1, signal V a Lags behind signal V1, and signal V a The phase difference θ1 between the signal and the signal V1 can be obtained according to Formula 2. That is, the phase of the signal received by the signal processing unit 52 lags behind the phase of the first signal.

[0080] For example, if the coefficient D1 of the first voltage conversion unit 5021 for converting the amplitude of the first signal is greater than 1, then the first voltage conversion unit 5021 amplifies the amplitude of the first signal to obtain the second signal. The amplitude of the second signal is greater than the amplitude of the first signal. According to formula 4, the time adjustment amount Δt of the adjustment circuit 50 is greater than 0, therefore the phase adjustment amount Δθ of the adjustment circuit 50 is also greater than 0. Thus, the phase of the signal received by the signal processing unit 52 leads the phase of the first signal. At this time, the signal received by the signal processing unit 52 is represented as signal V. bIt can be seen that signal V b To the left of signal V1, signal V b Leading signal V1, and signal V b The phase difference θ2 between the signal V1 and the signal V1 can be obtained from Equation 2.

[0081] For example, if the coefficient D1 of the first voltage conversion unit 5021 for converting the amplitude of the first signal is equal to 1, the first voltage conversion unit 5021 does not amplify or reduce the amplitude of the first signal, and the amplitude of the second signal is equal to the amplitude of the first signal, then according to formula 4, the time adjustment amount Δt of the adjustment circuit 50 is 0, that is, the adjustment circuit 50 does not adjust the phase of the first signal, that is, the phase of the signal received by the signal processing unit 52 is consistent with the phase of the first signal.

[0082] This application provides a novel circuit structure for an adjustment circuit. Unlike existing technologies that rely on digital potentiometers to adjust signals, this application adjusts the capacitance between the output terminal of the adjustment circuit and the reference ground by changing the coefficient of the first voltage conversion unit that transforms the amplitude of the first signal. Implementing this application improves adjustment accuracy, reduces adjustment error, and, in addition to achieving signal delay, also achieves signal lead, offering good flexibility and wide applicability.

[0083] Furthermore, in some feasible implementations, the regulating circuit also includes a buffer unit, in which case the specific implementation of the regulating circuit is as follows: Figure 7 As shown. The regulating circuit 70 includes a first branch 701, a second branch 702, and a buffer unit 703. The buffer unit 703 is located between the parallel connection point A and the output terminal of the regulating circuit 70. The parallel connection point A is the connection point where the first branch 701 and the second branch 702 are connected in parallel.

[0084] The first branch 701 includes a resistor R71, and the second branch 702 includes a first voltage conversion unit 7021 and a capacitor C71. The specific implementations of the first branch 701 and the second branch 702 can be found in the preceding text. Figure 5 The first branch road 501 and the second branch road 502 described herein will not be elaborated upon here.

[0085] In this embodiment of the application, a buffer unit is provided between the connection point of the first branch and the second branch in parallel and the output terminal of the adjustment circuit. The buffer unit can isolate the interference between the output terminal of the adjustment circuit and the signal processing unit, and ensure the stability of the adjustment circuit and the signal processing unit.

[0086] Optionally, in some feasible implementations, the regulating circuit further includes a third branch connected in parallel with the second branch. In this case, the regulating circuit can be as follows: Figure 8As shown, in addition to the first branch 801 and the second branch 802, the adjustment circuit 80 also includes a third branch 803. In this case, the third branch 803 is connected in parallel with the first branch 801 and the second branch 802 between the input terminal and the output terminal of the adjustment circuit 80. That is, the third branch 803 is connected in parallel with the first branch 801 and the second branch 802 between the signal transmitting unit 81 and the signal processing unit 82.

[0087] The first branch 801 includes a resistor R81, the second branch 802 includes a first voltage conversion unit 8021 and a capacitor C81, and the third branch 803 includes a second capacitor unit and a second voltage conversion unit 8022 connected in series with the second capacitor unit. Figure 8 Taking the second capacitor unit as an example, specifically implemented as capacitor C82.

[0088] For example, one end of the second voltage conversion unit 8022 is connected to the signal transmission unit 81, and the other end of the second voltage conversion unit 8022 can be connected to the signal processing unit 82 through the capacitor C82. Similarly, the relative positions of the second voltage conversion unit and the capacitor can be interchanged. Figure 8 The relative positional relationship between capacitor C82 and the second voltage conversion unit 8022 shown is only an example.

[0089] In this embodiment, the third branch 803 and the second branch 802 can be specifically equivalent to two capacitive branches. These two capacitive branches are connected to ground in parallel at the output of the regulating circuit 80 and form an RC parallel circuit with the first branch 801. The capacitance of these two capacitive branches can be understood as the capacitance between the output of the regulating circuit 80 and the reference ground.

[0090] In specific implementation, signal transmitting unit 81 outputs a first signal, which is transmitted to regulating circuit 80. Specifically, first voltage conversion unit 8021 converts the amplitude of the first signal to obtain a second signal, changing the capacitance between the output terminal of regulating circuit 80 and reference ground; and second voltage conversion unit 8022 converts the amplitude of the first signal to obtain a third signal, also changing the capacitance between the output terminal of regulating circuit 80 and reference ground. That is, both first voltage conversion unit 8021 and second voltage conversion unit 8022 can change the capacitance between the output terminal of regulating circuit 80 and reference ground.

[0091] The capacitance between the output terminal of the adjustment circuit 80 and the reference ground, as well as the resistor R81, determine the phase adjustment amount of the adjustment circuit 80, that is, the phase difference between the first signal and the signal received by the signal processing unit 82. The system function H(s1) of the adjustment circuit 80 can be expressed as:

[0092]

[0093] Where s = 2πfi, f is the frequency of the first signal, and i is the imaginary unit; R 81 The resistance value of resistor R81; C 81 Here is the capacitance value of capacitor C81, C 82 Where C82 is the capacitance value; D 81 The coefficients characterizing the transformation of the amplitude of the first signal by the first voltage conversion unit 8021 are, in other words, the ratio between the amplitude of the second signal and the amplitude of the first signal; D 82 The coefficients characterizing the transformation of the amplitude of the first signal by the second voltage conversion unit 8022 are the ratio between the amplitude of the third signal and the amplitude of the first signal.

[0094] According to Formula 5, the phase adjustment amount Δθ3 of the adjustment circuit 80 can be expressed as:

[0095] Δθ3=tan -1 (2πfR 81 .(C 81 D 81 +C 82 D 82 ))-tan -1 (2πfR 81 .(C 81 +C 82 )) Formula 6

[0096] Based on the relationship between phase and time, the time adjustment amount Δt3 of the regulating circuit 80 can be expressed as follows using Formula 6:

[0097]

[0098] When the frequency f of the first signal is much smaller than At that time, that is When formula 7 is simplified, we can obtain formula 8 as follows:

[0099] Δt3≈R 81 .C 81 (D 81 -1)+R 81 .C 82 (D 82 -1) Formula 8

[0100] Among them, C 81 (D 81 -1)+C 82 (D 82 -1) This can be understood as adjusting the capacitance between the output terminal of the adjustment circuit 80 and the reference ground. The capacitance between the output terminal of the adjustment circuit 80 and the reference ground changes with the ratio D between the amplitude of the second signal and the amplitude of the first signal.81 And the ratio D between the amplitude of the second signal and the amplitude of the first signal. 82 change.

[0101] Therefore, in the embodiments of this application, the ratio D between the amplitude of the second signal and the amplitude of the first signal can be adjusted. 81 And the ratio D between the amplitude of the third signal and the amplitude of the first signal. 82 By changing the capacitance between the output of the regulating circuit and the reference ground, the time regulation amount of the regulating circuit is controlled, that is, the phase regulation amount of the regulating circuit is controlled.

[0102] For example, the coefficient D of the first voltage conversion unit 8021 for converting the amplitude of the first signal 81 The value is less than 1, meaning that the first voltage conversion unit 8021 reduces the amplitude of the first signal to obtain the second signal, and the amplitude of the second signal is less than the amplitude of the first signal; and the coefficient D of the second voltage conversion unit 8022 transforming the amplitude of the first signal. 82 The amplitude is less than 1, meaning the second voltage conversion unit 8022 reduces the amplitude of the first signal to obtain the third signal, and the amplitude of the third signal is less than the amplitude of the first signal. At this time, according to formula 8, the time adjustment amount Δt3 of the adjustment circuit 80 is less than 0, therefore the phase adjustment amount Δθ3 of the adjustment circuit 80 is also less than 0. Thus, the phase of the signal received by the signal processing unit 82 lags behind the phase of the first signal.

[0103] For example, the coefficient D of the first voltage conversion unit 8021 for converting the amplitude of the first signal. 81 The amplitude is greater than 1, meaning that the first voltage conversion unit 8021 amplifies the amplitude of the first signal to obtain the second signal, and the amplitude of the second signal is greater than the amplitude of the first signal; and the coefficient D of the second voltage conversion unit 8022 transforming the amplitude of the first signal. 82 The amplitude is greater than 1, meaning the second voltage conversion unit 8022 amplifies the amplitude of the first signal to obtain the third signal, and the amplitude of the third signal is greater than the amplitude of the first signal. At this point, according to formula 8, the time adjustment amount Δt3 of the adjustment circuit 80 is greater than 0, therefore the phase adjustment amount Δθ3 of the adjustment circuit 80 is also greater than 0. Thus, the phase of the signal received by the signal processing unit 82 leads the phase of the first signal.

[0104] For example, the coefficient D of the first voltage conversion unit 8021 for converting the amplitude of the first signal. 81 The value equals 1, meaning the first voltage conversion unit 8021 did not amplify or reduce the amplitude of the first signal, and the amplitude of the second signal is equal to the amplitude of the first signal; and the coefficient D of the second voltage conversion unit 8022 that converts the amplitude of the first signal. 82The value equals 1, meaning the second voltage conversion unit 8022 did not amplify or reduce the amplitude of the first signal, and the amplitude of the third signal is equal to the amplitude of the first signal. At this point, according to formula 8, the time adjustment amount Δt3 of the adjustment circuit 80 is 0, therefore the adjustment circuit 80 did not adjust the phase of the first signal, meaning the phase of the signal received by the signal processing unit 82 is consistent with the phase of the first signal.

[0105] relatively Figure 5 The adjustment circuit shown in the figure can expand the adjustment range of the capacitance between the output terminal of the adjustment circuit and the reference ground by adding a third branch connected in parallel with the second branch in the adjustment circuit, thereby increasing the range of the phase adjustment amount of the adjustment circuit.

[0106] Furthermore, in some feasible implementations, the difference between the capacitance value of the first capacitor unit and the capacitance value of the second capacitor unit in the adjustment circuit is greater than a preset threshold. Figure 8 Taking the adjustment circuit 80 shown as an example, the difference between the capacitance values ​​of capacitor C81 and C82 is greater than a preset threshold. At this time, the adjustment circuit 80 can construct a phase adjustment that combines coarse and fine adjustments.

[0107] In specific implementation, the adjustment resolution Δ1 of the capacitance value between the output terminal of the adjustment circuit and the reference ground in the second branch can be expressed as:

[0108]

[0109] Where N1 represents the number of bits in the first voltage conversion unit 8021. Therefore, it can be seen that the adjustment resolution Δ1 of the capacitance between the output of the second branch and the reference ground is related to the capacitance value of capacitor C81.

[0110] Similarly, the adjustment resolution Δ2 of the capacitance between the output of the third branch and the reference ground can be expressed as:

[0111]

[0112] Where N2 represents the number of bits in the second voltage conversion unit 8022. Therefore, it can be seen that the adjustment resolution Δ2 of the capacitance between the output of the third branch and the reference ground is related to the capacitance of capacitor C82.

[0113] For example, if the capacitance value of capacitor C81 is large, the adjustment resolution Δ1 of the capacitance between the output terminal of the adjustment circuit and the reference ground in the second branch is larger. That is, by adjusting the ratio D between the amplitude of the second signal and the amplitude of the first signal... 81Coarse adjustment can be achieved; if the capacitance value of capacitor C82 is small, the adjustment resolution Δ2 of the capacitance between the output terminal of the adjustment circuit and the reference ground by the third branch will be small, that is, the ratio D between the amplitude of the third signal and the amplitude of the first signal will be smaller. 82 Fine-tuning is possible. It can be seen that the greater the difference between the capacitance values ​​of capacitor C81 and C82, the more pronounced the effects of coarse and fine-tuning.

[0114] by Figure 8 The resistance value R of resistor R81 shown in the figure is R 81 Taking a resistance of 7.5kΩ and N1=N2=16 as an example, let C 81 =470pF, C 82 =47pF. At this time, the time adjustment range of the regulating circuit is from 0ns to 3878ns, Δ1 = 54ps, Δ2 = 5.4ps. Therefore, the adjustment resolution of the regulating circuit 80 depends on the third branch, that is, on the coefficient D of the second voltage conversion unit 8022 that converts the amplitude of the first signal. 82 .

[0115] Optionally, the capacitance value of the first capacitor unit can be a smaller value, and the capacitance value of the second capacitor unit can be a larger value. Then, by adjusting the ratio D between the amplitude of the second signal and the amplitude of the first signal... 81 Fine-tuning can be achieved by using the ratio D between the amplitude of the third signal and the amplitude of the first signal. 82 Coarse adjustment can be achieved.

[0116] In this embodiment, by widening the gap between the capacitance value of the first capacitor unit in the second branch and the capacitance value of the second capacitor unit in the third branch, it can be ensured that one of the second and third branches can achieve coarse phase adjustment, while the other branch can achieve fine phase adjustment. Based on the increased range of phase adjustment amount of the adjustment circuit, coarse and fine adjustment can be combined to improve the phase adjustment resolution of the adjustment circuit.

[0117] Furthermore, in some feasible embodiments, the regulating circuit 80 may also include a buffer unit 803, which is disposed between the parallel connection point B and the output terminal of the regulating circuit 80. The parallel connection point B is the connection point after the second branch 802 and the third branch 803 are connected in parallel.

[0118] Optionally, in some feasible implementations, the regulating circuit may further include j branches connected in parallel with the second branch, where j is greater than or equal to 3. In this case, the regulating circuit can be as follows: Figure 9As shown, the adjustment circuit 90 includes a first branch 901, a second branch 902, a third branch 903, and a j-th branch 90j. Each branch is connected in parallel between the input terminal and the output terminal of the adjustment circuit 90, that is, each branch is connected in parallel between the signal transmitting unit 91 and the signal processing unit 92.

[0119] The specific implementation of the second branch 902 and the third branch 903 can be found in the previous text. Figure 8 The second branch 802 and the third branch 803 in the described embodiment. The specific implementation of the j-th branch 90j can also be found in the preceding text. Figure 8 The second branch 802 or the third branch 803 in the described embodiments will not be elaborated here.

[0120] At this time, the phase adjustment amount Δθ of the adjustment circuit 90 j It can be represented as:

[0121] Δθ j =tan -1 (2πfR 91 .C 91 D 91 +C 92 D 92 +…+C 9j D 9j ))-tan -1 (2πfR 91 .C 91 +C 92 +...+C 9j )) Formula 11

[0122] Among them, R 91 The resistance value of resistor R91; C 91 Where C91 is the capacitance value, C 92 The capacitance value of capacitor C92; D 91 The coefficients characterizing the transformation of the amplitude of the first signal by the first voltage conversion unit 9021 are, in other words, the ratio between the amplitude of the second signal and the amplitude of the first signal; D 92 The coefficients characterizing the transformation of the amplitude of the first signal by the second voltage conversion unit 9022 are, i.e., the ratio between the amplitude of the third signal and the amplitude of the first signal; D 9j The coefficient characterizing the amplitude of the first signal by the j-th voltage transformation unit 902j is the ratio between the amplitude of the j-th signal and the amplitude of the first signal.

[0123] The time adjustment amount Δt of the regulating circuit 90 can be obtained from formula 11. j It can be represented as:

[0124]

[0125] When the frequency f of the first signal is much smaller than At that time, that is Then, formula 12 can be simplified to formula 13 as follows:

[0126] Δt j ≈R 91 C 91 (D 91 -1)+R 91 C 92 (D 92 -1)+…+R 91 C 9j (D 9j -1) Formula 13

[0127] Among them, C 91 (D 91 -1)+C 92 (D 92 -1)+…+C 9j (D 9j -1) This can be understood as the capacitance between the output terminal of the adjustment circuit 90 and the reference ground. The capacitance between the output terminal of the adjustment circuit 90 and the reference ground can be adjusted by the coefficient D of the first voltage conversion unit 9021 to change the amplitude of the first signal. 91 The second voltage conversion unit 9022 converts the amplitude of the first signal by the coefficient D. 92 And the coefficient D of the voltage transformation unit 902j that transforms the amplitude of the first signal. 9j change.

[0128] This application embodiment expands the phase adjustment range of the adjustment circuit by adding multiple branches in parallel with the first branch to the adjustment circuit, and the capacitor unit of each branch can be selected with different capacitance values.

[0129] Furthermore, in some feasible embodiments, the regulating circuit 90 may also include a buffer unit 903, which is disposed between the parallel connection point and the output terminal of the regulating circuit 90. The parallel connection point is the connection point after the second branch 902 and the third branch 903 are connected in parallel.

[0130] In some feasible implementations, the first voltage conversion unit included in each of the above branches may include a programmable gain amplifier (PGA), a proportional amplifier, a voltage-controlled gain amplifier, or a multiplicative DAC.

[0131] The programmable gain amplifier can adjust the amplitude of the first signal using a program, and the amplification factor can be understood as the coefficient by which the voltage conversion unit transforms the amplitude of the first signal.

[0132] Optionally, in some feasible implementations, see [link to relevant documentation]. Figure 10 , Figure 10 This is a structural block diagram of the adjustment module provided in an embodiment of this application. Figure 10 As shown, the adjustment module 1002 includes at least two adjustment circuits, such as adjustment circuit 10021 and adjustment circuit 10022.

[0133] Each adjustment circuit has its input terminal connected to its corresponding signal transmitting unit. Specifically, adjustment circuit 10021 is connected to signal transmitting unit 10011 to receive the first signal output by signal transmitting unit 10011; adjustment circuit 10022 is connected to signal transmitting unit 10012 to receive the first signal output by signal transmitting unit 10012. The output terminals of adjustment circuits 10021 and 10022 are connected to signal processing unit 1003.

[0134] The specific implementation of regulating circuit 10021 or regulating circuit 10022 can be combined with the above. Figures 5 to 9 Any one of the regulating circuits described will not be elaborated here.

[0135] In the adjustment module 1002 provided in this application embodiment, the signals output by the adjustment circuit 10021 and the adjustment circuit 10022 to the signal processing unit 1003 are in phase. That is, the first signal output by the signal transmitting unit 10011 is transmitted to the signal processing unit 1003 through the adjustment circuit 10021, and the time taken for the first signal output by the signal transmitting unit 10012 to be transmitted to the signal processing unit 1003 through the adjustment circuit 10022 is the same.

[0136] In some feasible implementations, any one of the adjustment circuits in the adjustment module 1002 can be used as a reference adjustment circuit, and the signal output by the reference adjustment circuit to the signal processing unit 1003 can be used as the first target signal. In this case, the reference adjustment circuit does not perform phase adjustment, that is, the time adjustment amount of the reference adjustment circuit is 0.

[0137] For example, if adjustment circuit 10022 serves as a reference adjustment circuit, then the target phase adjustment amount of adjustment circuit 10021 is the phase difference between the signal output by adjustment module 1002 to signal processing unit 1003 and the first signal received by adjustment circuit 10021. Specifically, the first voltage conversion unit in adjustment circuit 10021, based on the phase difference between the first target signal and the first signal received by adjustment circuit 10021, transforms the amplitude of the first signal received by adjustment circuit 10021 to obtain the second signal corresponding to adjustment circuit 10021. This adjusts the capacitance between the output terminal of adjustment circuit 10021 and reference ground to the capacitance corresponding to the first target signal, thereby controlling the time adjustment amount of adjustment circuit 10021. At this time, the signal output by adjustment circuit 10021 to signal processing unit 1003 has the same phase as the signal output by adjustment circuit 10022 to signal processing unit 1003. That is, signal processing unit 1003 can synchronously acquire the signals output by adjustment circuit 10021 and adjustment circuit 10022. In this embodiment, any one of the adjustment circuits in the adjustment module is used as a reference adjustment circuit, so that the reference adjustment circuit does not need to perform phase adjustment. This saves adjustment resources in the adjustment module while ensuring that the signal processing unit can synchronously acquire signals.

[0138] For example, the first signal received by the adjustment circuit 10022 has a 4-second delay, and the first signal received by the adjustment circuit 10021 has a 3-second delay. In this case, the time adjustment amount of the adjustment circuit 10021 can be +1 second. Alternatively, the first signal received by the adjustment circuit 10022 has a 4-second delay, and the first signal received by the adjustment circuit 10021 has a 5-second delay. In this case, the time adjustment amount of the adjustment circuit 10021 can be -1 second.

[0139] In a specific implementation, the adjustment module in this application embodiment adjusts the capacitance between the output terminal of the first adjustment circuit and the reference ground to the first target capacitance corresponding to the first target signal, thereby making the first adjustment circuit and the second adjustment circuit have the same delay time.

[0140] Optionally, in some feasible implementations, each adjustment circuit in the adjustment module performs phase adjustment. Specifically, the first voltage conversion unit in adjustment circuit 10021 transforms the amplitude of the first signal received by adjustment circuit 10021 based on the phase difference between the first target signal and the first signal received by adjustment circuit 10021 to obtain a second signal corresponding to adjustment circuit 10021. This adjusts the capacitance between the output terminal of adjustment circuit 10021 and the reference ground to the capacitance corresponding to the first target signal, thereby controlling the time adjustment amount of adjustment circuit 10021. Furthermore, the first voltage conversion unit in adjustment circuit 10022 transforms the amplitude of the first signal received by adjustment circuit 10022 based on the phase difference between the first target signal and the first signal received by adjustment circuit 10022 to obtain a second signal corresponding to adjustment circuit 10022. This adjusts the capacitance between the output terminal of adjustment circuit 10022 and the reference ground to the capacitance corresponding to the first target signal, thereby controlling the time adjustment amount of adjustment circuit 10022. The first target signal is determined based on the first signal received by the adjustment circuit 10021 and the first signal received by the adjustment circuit 10022.

[0141] In specific implementation, when the phase of the first target signal leads the phase of the first signal received by the adjustment circuit 10021 and the phase of the corresponding first signal of the adjustment circuit 10022, the first voltage conversion unit of the adjustment circuit 10021 increases the amplitude of the first signal received by the adjustment circuit 10021 according to the phase difference between the first target signal and the first signal received by the adjustment circuit 10021. Furthermore, the first voltage conversion unit of the adjustment circuit 10022 increases the amplitude of the first signal received by the adjustment circuit 10022 according to the phase difference between the first target signal and the first signal received by the adjustment circuit 10022. At this time, the signals output by the adjustment circuits 10021 and 10022 to the signal processing unit 1003 have the same phase as the first target signal. That is, the signal processing unit 1003 can synchronously acquire the signals output by the adjustment circuits 10021 and 10022. In this embodiment, each adjustment circuit in the adjustment module performs advance adjustment on its respective received first signal, which improves the acquisition efficiency of the signal processing unit while ensuring that the signal processing unit can synchronously acquire signals.

[0142] For example, the first signal received by the adjustment circuit 10021 has a 4-second delay, and the first signal received by the adjustment circuit 10022 has a 3-second delay. Taking a first target signal with a 2-second delay as an example, the time adjustment amount of the adjustment circuit 10021 is -2 seconds, and the time adjustment amount of the adjustment circuit 10022 is -1 second.

[0143] Alternatively, when the phase of the first target signal lags behind the phase of the first signal received by the adjustment circuit 10021 and the phase of the corresponding first signal of the adjustment circuit 10022, the first voltage conversion unit of the adjustment circuit 10021 reduces the amplitude of the first signal received by the adjustment circuit 10021 based on the phase difference between the first target signal and the first signal received by the adjustment circuit 10021. Furthermore, the first voltage conversion unit of the adjustment circuit 10022 reduces the amplitude of the first signal received by the adjustment circuit 10022 based on the phase difference between the first target signal and the first signal received by the adjustment circuit 10022. Similarly, the signals output by the adjustment circuits 10021 and 10022 to the signal processing unit 1003 have the same phase as the first target signal. That is, the signal processing unit 1003 can synchronously acquire the signals output by the adjustment circuits 10021 and 10022. In this embodiment, the lag adjustment of each adjustment circuit in the adjustment module on its respective received first signal ensures that the signal processing unit acquires the signal synchronously.

[0144] For example, the first signal received by the adjustment circuit 10021 has a 4-second delay, and the first signal received by the adjustment circuit 10022 has a 3-second delay. Taking a first target signal with a 6-second delay as an example, the time adjustment amount of the adjustment circuit 10021 is -2 seconds, and the time adjustment amount of the adjustment circuit 10022 is -3 seconds.

[0145] Alternatively, when the phase of the first target signal leads the phase of the first signal received by the adjustment circuit 10021 but lags behind the phase of the first signal corresponding to the adjustment circuit 10022, the first voltage conversion unit of the adjustment circuit 10021 amplifies the amplitude of the first signal received by the adjustment circuit 10021 based on the phase difference between the first target signal and the first signal received by the adjustment circuit 10021. Furthermore, the first voltage conversion unit of the adjustment circuit 10022 reduces the amplitude of the first signal received by the adjustment circuit 10022 based on the phase difference between the first target signal and the first signal received by the adjustment circuit 10022. Similarly, the signals output by the adjustment circuits 10021 and 10022 to the signal processing unit 1003 have the same phase as the first target signal. That is, the signal processing unit 1003 can synchronously acquire the signals output by the adjustment circuits 10021 and 10022. In this embodiment, different adjustment circuits in the adjustment module can respectively perform hysteresis adjustment or lead adjustment on the first signal they receive, which can provide multiple phase adjustment methods while ensuring that the signal processing unit synchronously acquires signals.

[0146] For example, the first signal received by the adjustment circuit 10021 has a 2-second delay, and the first signal received by the adjustment circuit 10022 has a 4-second delay. Taking the first target signal having a 3-second delay as an example, the time adjustment amount of the adjustment circuit 10021 is -1 second, and the time adjustment amount of the adjustment circuit 10022 is +1 second.

[0147] Understandably, a negative time adjustment value represents phase lag adjustment, while a positive value represents phase lead adjustment.

[0148] It should be explained that the specific implementation of the first and second adjustment circuits adjusting the corresponding first signals, including the specific implementation of the first voltage conversion unit in the first adjustment circuit converting the first signal into a second signal, and the specific implementation of the second voltage conversion unit in the second adjustment circuit converting the first signal into a third signal, can be referred to the specific implementation of the adjustment circuits in the above content, and will not be repeated here.

[0149] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0150] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A regulating circuit, characterized by An input terminal of the adjusting circuit is configured to be connected to a signal transmitting unit, and an output terminal of the adjusting circuit is configured to be connected to a signal processing unit. The adjusting circuit comprises a first branch and a second branch, and the first branch and the second branch are connected in parallel between the input terminal of the adjusting circuit and the output terminal of the adjusting circuit. In the adjusting circuit, The first branch comprises a resistance unit. The second branch comprises a first capacitance unit and a first voltage conversion unit connected in series with the first capacitance unit. The first voltage conversion unit is configured to convert an amplitude of a first signal output by the signal transmitting unit to obtain a second signal, so as to adjust a capacitance value between the output terminal of the adjusting circuit and a reference ground. The adjusting circuit further comprises a third branch connected in parallel with the second branch. In the adjusting circuit, The third branch comprises a second capacitance unit and a second voltage conversion unit connected in series with the second capacitance unit. The second voltage conversion unit is configured to convert the amplitude of the first signal output by the signal transmitting unit to obtain a third signal, so as to adjust the capacitance value between the output terminal of the adjusting circuit and the reference ground.

2. The regulation circuit of claim 1, wherein, A phase difference between the first signal and a signal received by the signal processing unit is determined according to a resistance value of the resistance unit and the capacitance value between the output terminal of the adjusting circuit and the reference ground.

3. The regulation circuit according to any of claims 1-2, characterized in that, In a case where the amplitude of the second signal is smaller than the amplitude of the first signal, a phase of the signal received by the signal processing unit lags behind a phase of the first signal.

4. The regulation circuit according to any of claims 1-2, characterized in that, In a case where the amplitude of the second signal is greater than the amplitude of the first signal, the phase of the signal received by the signal processing unit leads the phase of the first signal.

5. The regulation circuit of claim 1, wherein, A difference between the capacitance value of the first capacitance unit and the capacitance value of the second capacitance unit is greater than a preset threshold value.

6. The regulation circuit according to any one of claims 1 to 5, characterized in that The adjusting circuit further comprises a buffer unit arranged between a parallel connection point and the output terminal of the adjusting circuit. The parallel connection point is a connection point after the first branch and the second branch are connected in parallel.

7. The adjusting circuit of any one of claims 1-6, wherein The first voltage conversion unit and the second voltage conversion unit in the third branch comprise a programmable gain amplifier, a proportional amplifier, a voltage-controlled gain amplifier, or a multiplication type DAC.

8. A regulating module, characterized by The adjusting module comprises at least two adjusting circuits. An input terminal of each adjusting circuit of the at least two adjusting circuits is configured to be connected to a corresponding signal transmitting unit of each adjusting circuit, so as to receive a first signal output by the corresponding signal transmitting unit of each adjusting circuit, respectively. An output terminal of each adjusting circuit is configured to be connected to a signal processing unit. Each adjusting circuit comprises a first adjusting circuit, and the first adjusting circuit comprises a first branch, a second branch, and a third branch. The first branch, the second branch, and the third branch of the first adjusting circuit are connected in parallel between an input terminal of the first adjusting circuit and an output terminal of the first adjusting circuit. The first branch comprises a resistance unit, the second branch comprises a first capacitance unit and a first voltage conversion unit connected in series with the first capacitance unit; and the third branch comprises a second capacitance unit and a second voltage conversion unit connected in series with the second capacitance unit. The first voltage conversion unit is configured to transform the amplitude of the first signal received by the first adjusting circuit to obtain a second signal corresponding to the first adjusting circuit according to the phase difference between the first target signal and the first signal received by the first adjusting circuit, and the second voltage conversion unit is configured to transform the amplitude of the first signal received by the first adjusting circuit to obtain a third signal corresponding to the first adjusting circuit according to the phase difference between the first target signal and the first signal received by the first adjusting circuit, so as to adjust the capacitance value between the output end of the first adjusting circuit and the reference ground to the first target capacitance value corresponding to the first target signal.

9. The adjustment module of claim 8, wherein, The adjusting circuit comprises a second adjusting circuit. The first target signal is a signal output by the second adjusting circuit to the signal processing unit.

10. The adjustment module of claim 9, wherein, The phase of the first target signal is ahead of the phase of the first signal corresponding to the first adjusting circuit. The first voltage conversion unit is configured to increase the amplitude of the first signal corresponding to the first adjusting circuit according to the phase difference between the first target signal and the first signal corresponding to the first adjusting circuit.

11. The conditioning module of claim 9, wherein, The phase of the first target signal is behind the phase of the first signal corresponding to the first adjusting circuit. The first voltage conversion unit is configured to decrease the amplitude of the first signal corresponding to the first adjusting circuit according to the phase difference between the first target signal and the first signal corresponding to the first adjusting circuit.

12. A data acquisition system characterized by, The data acquisition system comprises a signal sending unit, a signal processing unit and the adjusting circuit according to any one of claims 1-7, or the data acquisition system comprises a signal sending unit, a signal processing unit and the adjusting module according to any one of claims 8-11.

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