Low voltage drop linear regulator circuit and RF module

Abstract

The present application relates to a low voltage difference linear voltage regulator circuit and a radio frequency module. The low voltage difference linear voltage regulator circuit of the embodiment of the present application includes an operational amplifier, a transmission transistor, a feedback circuit and a feedforward power supply ripple cancellation module; wherein, at least a third path is formed from the power supply end to the voltage regulation output end based on the feedforward power supply ripple cancellation module, which is used to transmit the power supply noise to the control end of the transmission transistor at medium and high frequencies, so as to generate a ripple cancellation current at the output of the low voltage difference linear voltage regulator circuit, thereby improving the power supply ripple suppression capability of the low voltage difference linear voltage regulator circuit at medium and high frequencies.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a low voltage difference linear voltage regulator circuit and a radio frequency module. Background Art

[0002] Nowadays, CMOS technology has developed to deep sub-micron gate length. Therefore, various functional modules, such as analog, digital, RF and other circuit modules, can be integrated into one chip as a system. In this case, the system performance may be deteriorated due to the influence of noise from the power supply. Noise-sensitive circuit modules such as analog-to-digital converters, phase-locked loops and switching audio amplifiers will have their performance seriously affected.

[0003] Therefore, engineers often use LDO (low dropout regulator) to directly connect to various functional modules, so that the noise from the power supply can be suppressed by the power supply rejection (PSR) capability of LDO, so as not to cause the performance of noise-sensitive circuit modules to decline. However, in the mid-to-high frequency band, due to the reduction of LDO loop gain, its PSR capability will be reduced, so it is crucial to improve the PSR capability of LDO in the mid-to-high frequency band. Summary of the invention

[0004] In view of this, the embodiments of the present application provide a low voltage difference linear voltage regulator circuit and a radio frequency module to solve at least one problem existing in the background technology.

[0005] In a first aspect, an embodiment of the present application provides a low voltage difference linear voltage regulator circuit, wherein the low voltage difference linear voltage regulator circuit includes an operational amplifier, a transmission transistor, a feedback circuit and a feedforward power supply ripple cancellation module;

[0006] The inverting input terminal of the operational amplifier is configured to receive a reference voltage signal, the non-inverting input terminal of the operational amplifier is connected to the output terminal of the feedback circuit, and the output terminal of the operational amplifier is connected to the control terminal of the transmission transistor; the first terminal of the transmission transistor is connected to the power supply terminal, the second terminal of the transmission transistor is respectively connected to the input terminal of the feedback circuit and the voltage stabilization output terminal of the low voltage difference linear voltage stabilization circuit, and the voltage stabilization output terminal is used to provide an output signal;

[0007] Wherein, a first path is formed from the power supply end to the regulated output end based at least on the transconductance of the transmission transistor, and is used to generate a first ripple current at the output of the low voltage difference linear voltage regulator circuit through the first path under the influence of power supply noise; a second path is formed from the power supply end to the regulated output end based at least on the conductance of the transmission transistor, and is used to generate a second ripple current at the output of the low voltage difference linear voltage regulator circuit through the second path under the influence of power supply noise;

[0008] The input end of the feed-forward power supply ripple cancellation module is connected to the power supply end, and the output end of the feed-forward power supply ripple cancellation module is connected to the control end of the transmission transistor;

[0009] Wherein, at least based on the feed-forward power supply ripple cancellation module, a third path is formed from the power supply end to the voltage regulated output end, which is used to transmit the power supply noise to the control end of the transmission transistor at medium and high frequencies to generate a ripple cancellation current at the output of the low voltage difference linear voltage regulator circuit;

[0010] The ripple compensation current is used to reduce or offset the first ripple current and the second ripple current, so as to improve the power supply suppression capability of the low voltage difference linear voltage regulator circuit at medium and high frequencies.

[0011] In combination with the first aspect, in an optional implementation manner, the feedforward power supply ripple cancellation module includes:

[0012] High-pass filter, used to select power supply ripple with medium and high ripple frequencies;

[0013] A proportional amplification module, used for adjusting the amplitude of the power supply ripple of the medium and high frequency ripple frequency selected by the high-pass filter; and

[0014] The current mirror module is used to feed forward the output of the proportional amplification module to the control end of the transmission transistor through the transmission of the current mirror.

[0015] In combination with the first aspect, in an optional implementation manner, the high-pass filter includes a filter capacitor and a filter resistor;

[0016] The same-proportional amplification module includes a same-proportional amplifier, the filter resistor, a first feedback resistor and a second feedback resistor;

[0017] The first end of the filter capacitor is connected to the power supply end, and the second end of the filter capacitor is respectively connected to the second end of the filter resistor and the non-inverting input end of the proportional amplifier; the first end of the filter resistor and the first end of the first feedback resistor are respectively configured to receive a reference voltage signal, the second end of the first feedback resistor is respectively connected to the inverting input end of the proportional amplifier and the first end of the second feedback resistor, and the output end of the proportional amplifier is respectively connected to the second end of the second feedback resistor and the input end of the current mirror module.

[0018] In combination with the first aspect, in an optional implementation manner, the current mirror module includes a twenty-sixth PMOS transistor, a twenty-seventh PMOS transistor, a twenty-eighth NMOS transistor, a twenty-ninth NMOS transistor, a thirtieth PMOS transistor, and a thirty-first PMOS transistor;

[0019] The gate of the twenty-seventh PMOS transistor is configured as the input end of the current mirror module, and the drain of the thirty-first PMOS transistor is configured as the output end of the current mirror module;

[0020] The drain of the twenty-seventh PMOS transistor is respectively connected to the drain of the twenty-eighth NMOS transistor, the gate of the twenty-eighth NMOS transistor and the gate of the twenty-ninth NMOS transistor; the drain of the twenty-ninth NMOS transistor is respectively connected to the drain of the thirtieth PMOS transistor, the gate of the thirtieth PMOS transistor and the gate of the thirty-first PMOS transistor; the source of the twenty-eighth NMOS transistor and the source of the twenty-ninth NMOS transistor are respectively connected to the ground terminal; the source of the thirtieth PMOS transistor and the source of the thirty-first PMOS transistor are respectively connected to the power supply terminal; the source of the twenty-seventh PMOS transistor is connected to the drain of the twenty-sixth PMOS transistor, the source of the twenty-sixth PMOS transistor is connected to the power supply terminal, and the gate of the twenty-sixth PMOS transistor is configured to receive a second high-bit bias signal.

[0021] In combination with the first aspect, in an optional implementation manner, the proportional amplifier includes a first amplifier and a second amplifier connected in cascade;

[0022] The non-inverting input terminal of the first amplifier is configured as the non-inverting input terminal of the proportional amplifier, the inverting input terminal of the first amplifier is configured as the inverting input terminal of the proportional amplifier, the output terminal of the first amplifier is connected to the input terminal of the second amplifier, and the output terminal of the second amplifier is configured as the output terminal of the proportional amplifier;

[0023] Wherein, the first amplifier comprises a high-gain amplifier, which is used to adjust the amplitude of the power supply ripple of the medium and high frequency ripple frequency selected to pass through by the high-pass filter;

[0024] The second amplifier comprises a low output impedance amplifier for eliminating a low frequency pole.

[0025] In combination with the first aspect, in an optional implementation manner, the first amplifier includes a telescopic cascode amplifier;

[0026] and / or, the first amplifier includes a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, and a twentieth NMOS transistor;

[0027] The gate of the twelfth NMOS transistor is configured as a non-inverting input terminal of the first amplifier, the gate of the thirteenth NMOS transistor is configured as an inverting input terminal of the first amplifier, and the drain of the nineteenth NMOS transistor is configured as an output terminal of the first amplifier;

[0028] The drain of the twelfth NMOS transistor is connected to the source of the eighteenth NMOS transistor, and the drain of the thirteenth NMOS transistor is connected to the source of the nineteenth NMOS transistor; the drain of the eighteenth NMOS transistor is respectively connected to the drain of the sixteenth PMOS transistor, the gate of the sixteenth PMOS transistor and the gate of the seventeenth PMOS transistor, and the drain of the nineteenth NMOS transistor is connected to the drain of the seventeenth PMOS transistor; the source of the sixteenth PMOS transistor is respectively connected to the drain of the fourteenth PMOS transistor, the gate of the fourteenth PMOS transistor and the gate of the fifteenth PMOS transistor, and the source of the seventeenth PMOS transistor is connected to the drain of the fifteenth PMOS transistor; the source of the fourteenth PMOS transistor and the source of the fifteenth PMOS transistor are respectively connected to the power supply terminal; the source of the twelfth NMOS transistor and the source of the thirteenth NMOS transistor are respectively connected to the drain of the twentieth NMOS transistor, and the source of the twentieth NMOS transistor is connected to the ground terminal;

[0029] The gate of the twentieth NMOS transistor is configured to receive a first low bias signal, and the gate of the eighteenth NMOS transistor and the gate of the nineteenth NMOS transistor are respectively configured to receive a second low bias signal.

[0030] In combination with the first aspect, in an optional implementation, the second amplifier includes an inverted source follower;

[0031] and / or, the second amplifier includes a twenty-first NMOS transistor, a twenty-second PMOS transistor and a twenty-third PMOS transistor;

[0032] A gate of the twenty-second PMOS transistor is configured as an input terminal of the second amplifier, and a source of the twenty-second PMOS transistor is configured as an output terminal of the second amplifier;

[0033] The gate of the twenty-second PMOS transistor is connected to the drain of the nineteenth NMOS transistor, the drain of the twenty-second PMOS transistor is respectively connected to the gate of the twenty-third PMOS transistor and the drain of the twenty-first NMOS transistor, the source of the twenty-second PMOS transistor is connected to the drain of the twenty-third PMOS transistor, the source of the twenty-third PMOS transistor is connected to the power supply terminal, and the source of the twenty-first NMOS transistor is connected to the ground terminal;

[0034] The gate of the twenty-first NMOS transistor is configured to receive the first low bias signal.

[0035] In combination with the first aspect, in an optional implementation manner, the operational amplifier includes a first PMOS transistor, a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twenty-fourth NMOS transistor, a twenty-fifth PMOS transistor, a first compensation capacitor, and a second compensation capacitor;

[0036] The gate of the first PMOS transistor is configured as the inverting input terminal of the operational amplifier, the gate of the second PMOS transistor is configured as the non-inverting input terminal of the operational amplifier; the drain of the eleventh PMOS transistor is configured as the output terminal of the operational amplifier;

[0037] The gate of the twenty-fifth PMOS transistor is configured to receive the first high-bit bias signal, the source of the twenty-fifth PMOS transistor is connected to the power supply terminal, the drain of the twenty-fifth PMOS transistor is respectively connected to the source of the first PMOS transistor and the source of the second PMOS transistor, the drain of the first PMOS transistor is respectively connected to the drain of the fifth NMOS transistor and the source of the ninth NMOS transistor, the drain of the second PMOS transistor is respectively connected to the drain of the fourth NMOS transistor and the source of the eighth NMOS transistor; the drain of the eighth NMOS transistor is respectively connected to the drain of the sixth PMOS transistor, the gate of the sixth PMOS transistor and the gate of the seventh PMOS transistor, and the source of the sixth PMOS transistor and the source of the seventh PMOS transistor are respectively connected to the power supply terminal; the source of the fourth NMOS transistor and the source of the fifth NMOS transistor are respectively connected to the ground terminal; the gate of the fourth NMOS transistor and the gate of the fifth NMOS transistor are respectively configured to receive the first low-bit bias signal, and the gate of the eighth NMOS transistor and the gate of the ninth NMOS transistor are respectively configured to receive the second low-bit bias signal;

[0038] The drain of the ninth NMOS transistor is respectively connected to the drain of the seventh PMOS transistor and the gate of the third NMOS transistor, the source of the third NMOS transistor is connected to the ground terminal, the drain of the third NMOS transistor is respectively connected to the drain of the tenth PMOS transistor, the gate of the tenth PMOS transistor, the gate of the eleventh PMOS transistor and the output terminal of the current mirror module; the source of the tenth PMOS transistor and the source of the eleventh PMOS transistor are respectively connected to the power supply terminal; the drain of the eleventh PMOS transistor is connected to the drain of the twenty-fourth NMOS transistor, the source of the twenty-fourth NMOS transistor is connected to the ground terminal, and the gate of the twenty-fourth NMOS transistor is configured to receive the first low-bit bias signal;

[0039] The first end of the first compensation capacitor is connected to the drain of the ninth NMOS transistor and the drain of the seventh PMOS transistor respectively, and the second end of the first compensation capacitor is connected to the voltage stabilization output terminal;

[0040] A first end of the second compensation capacitor is connected to the drain of the twenty-fourth NMOS transistor and the drain of the eleventh PMOS transistor respectively, and a second end of the second compensation capacitor is connected to the voltage stabilization output terminal.

[0041] In combination with the first aspect, in an optional implementation manner, the transfer transistor is a PMOS transistor, and its gate, source, and drain correspond to the control terminal, the first terminal, and the second terminal of the transfer transistor, respectively;

[0042] And / or, the feedback circuit includes a first resistor and a second resistor;

[0043] The non-inverting input terminal of the operational amplifier is respectively connected to the second end of the first resistor and the first end of the second resistor, the second end of the transmission transistor is respectively connected to the first end of the first resistor and the voltage stabilization output terminal of the low voltage difference linear voltage stabilization circuit; the second end of the second resistor is connected to the ground.

[0044] In a second aspect, an embodiment of the present application provides a radio frequency module, wherein the radio frequency module includes the low voltage difference linear voltage regulator circuit as described in the first aspect.

[0045] The beneficial effects brought about by the technical solution provided by the embodiment of the present application include: through the feedforward power supply ripple cancellation technology, the power supply ripple can be fed forward to the control end of the transmission transistor at medium and high frequencies, and the first ripple current and the second ripple current can be cancelled at medium and high frequencies, thereby improving the PSR capability of the circuit. Therefore, not only at low frequencies, due to the high loop gain, the circuit has a good PSR characteristic; but also at medium and high frequencies, due to the cancellation of the ripple current in the output of the low voltage difference linear voltage regulator circuit, the PSR capability of the circuit can be improved. And because the feedforward power supply ripple cancellation module does not participate in the main loop of the circuit, the loop stability is guaranteed.

[0046] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below and in part will become apparent from the description below or will be learned through the practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0048] Figure 1 A circuit diagram of a specific example of an LDO circuit in the related art;

[0049] Figure 2 for Figure 1 A curve diagram of a specific example of how the PSR of the LDO circuit varies with frequency;

[0050] Figure 3 A circuit diagram of a specific example of a low voltage difference linear voltage regulator circuit in an embodiment of the present application;

[0051] Figure 4 A circuit diagram of another specific example of a low voltage difference linear voltage regulator circuit in an embodiment of the present application;

[0052] Figure 5 A circuit diagram of a specific example of a proportional amplifier in an embodiment of the present application;

[0053] Figure 6 Schematic diagram of another specific example of a proportional amplifier in an embodiment of the present application. DETAILED DESCRIPTION

[0054] In order to make the technical solutions and beneficial effects of the present invention more clearly understandable, the following is a detailed description by listing specific embodiments. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application belongs.

[0055] The embodiments of the present application are not exhaustive, but are only illustrative of some embodiments, and are not intended to be a specific limitation on the scope of protection of the present application. In the absence of contradiction, each step in a certain embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, in a certain embodiment, the solution after removing some steps can also be implemented as an independent embodiment, and the order of the steps in a certain embodiment can be arbitrarily exchanged. In addition, the optional implementations in a certain embodiment can be arbitrarily combined; in addition, the embodiments can be arbitrarily combined, for example, some or all of the steps of different embodiments can be arbitrarily combined, and a certain embodiment can be arbitrarily combined with the optional implementations of other embodiments.

[0056] In each embodiment of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between the embodiments are consistent and can be referenced to each other. The technical features in different embodiments can be combined to form a new embodiment based on their internal logical relationships.

[0057] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0058] In the embodiments of the present application, unless otherwise specified, elements expressed in the singular form, such as "a", "an", "the", "above", "said", "aforementioned", "this", etc., may mean "one and only one", or "one or more", "at least one", etc. For example, when using articles such as "a", "an", "the" in English in translation, the noun after the article may be understood as a singular expression or a plural expression.

[0059] In the embodiments of the present application, "plurality" refers to two or more.

[0060] In some embodiments, the terms “at least one”, “one or more”, “a plurality of”, “multiple”, etc. can be used interchangeably.

[0061] The prefixes such as "first" and "second" in the embodiments of the present application are only used to distinguish different description objects, and do not constitute restrictions on the position, order, priority, value or content of the description objects. The statement of the description object refers to the description in the context of the claims or embodiments, and should not constitute unnecessary restrictions due to the use of prefixes. For example, the numerical value of the description object is not limited by the ordinal number, and can be one or more. Take "first device" as an example, where the numerical value of "device" can be one or more. In addition, the objects modified by different prefixes can be the same or different. For example, if the description object is "device", the "first device" and the "second device" can be the same device or different devices, and their types can be the same or different.

[0062] In some embodiments, the term "connection" may indicate that an electrical signal or data is transmitted between a connected end and a connected end, and may be understood as "electrical connection", "communication connection", etc. "Connection" may be a direct connection between two components, an indirect connection established through other components, internal communication between two components, or any other possible connection form.

[0063] In the process of implementing this application, the inventor found that the related technology has the following problems:

[0064] Figure 1 A circuit diagram of a specific example of an LDO circuit in the related art is shown. As shown in the figure, the LDO circuit may include a first 001 operational amplifier U1001, a first 001 transistor M1001, a first 001 resistor R1001 and a first 002 resistor R1002. The first 001 operational amplifier U1001 may be an error amplifier GEA. The first 001 transistor M1001 may be a transmission transistor MP, which may be a PMOS transistor.

[0065] The inverting input terminal of the first one thousand one operational amplifier U1001 is configured to receive a reference voltage vref, the output terminal of the first one thousand one operational amplifier U1001 is connected to the control terminal of the first one thousand one transistor M1001, the first terminal of the first one thousand one transistor M1001 is configured to receive an input power supply vin, and the second terminal of the first one thousand one transistor M1001 is configured to provide an output voltage vout and is connected to the non-inverting input terminal of the first one thousand one operational amplifier U1001 via a resistor feedback network. The resistor feedback network may include a first one thousand one resistor R1001 and a first one thousand two resistor R1002 connected in series between the second terminal of the first one thousand one transistor M1001 and the ground terminal, and a connection node A between the first one thousand one resistor R1001 and the first one thousand two resistor R1002 is connected to the non-inverting input terminal of the first one thousand one operational amplifier U1001.

[0066] like Figure 1 As shown, assuming that the ripple voltage amplitude of the input power supply noise is V R , the power supply noise can include ripple, and the power supply noise can be coupled to the output voltage vout mainly through two paths (path 1 and path 2), causing the output voltage of the LDO circuit to fluctuate. The capacitor CL is the load capacitance, and the resistor RL is the load resistance.

[0067] Path 1 may be mainly formed based on the transconductance gm of the pass transistor MP. The power ripple is coupled to the gate of the pass transistor MP in a certain ratio through path 1, generating a ripple voltage at the gate, thereby generating a first ripple current Δi1 at the output of the LDO circuit through the transconductance gm.

[0068] The calculation formula of the ripple voltage can be:

[0069]

[0070] Among them, V R is the ripple voltage amplitude, Cgs is the gate-source capacitance value of the transmission transistor MP, and Cgd is the gate-drain capacitance value of the transmission transistor MP.

[0071] Then, the calculation formula of the first ripple current Δi1 can be:

[0072]

[0073] Wherein, gm is the transconductance of the transfer transistor MP.

[0074] The certain ratio can be determined according to the gate-source capacitance Cgs and the gate-drain capacitance Cgd of the transfer transistor MP, and the amplitude of the first ripple current Δi1 depends on the ratio between the gate-source capacitance Cgs and the gate-drain capacitance Cgd.

[0075] Path 2 may be mainly formed based on the conductance gds of the transmission transistor MP. The power ripple is transmitted to the output end through path 2, through the conductance gds of the source and drain of the transmission transistor MP, thereby generating a second ripple current Δi2 at the output of the LDO circuit.

[0076] The calculation formula of the second ripple current Δi2 can be:

[0077]

[0078] Among them, V R is the ripple voltage amplitude, gds is the conductance of the transfer transistor MP.

[0079] It can be seen that the output voltage of the LDO circuit will fluctuate due to the first ripple current Δi1 and the second ripple current Δi2 generated at least through path 1 and path 2. Since the LDO main loop formed by the error amplifier GEA, the transmission transistor MP, the first 001 resistor R1001 and the first 002 resistor R1002 has a high loop gain at low frequency, the LDO circuit has a good PSR characteristic at low frequency, so that the fluctuation can be well suppressed.

[0080] but, Figure 2 Shows Figure 1 A specific example of a curve diagram of the PSR of an LDO circuit changing with frequency. As shown in the figure, the smaller the PSR (negative value), the better the power supply rejection capability. At low frequencies, the LDO circuit has a very small PSR because the LDO main loop gain is very high. However, at medium and high frequencies (such as Figure 2 In the frequency range indicated by the red dotted circle in the middle), the LDO main loop gain will gradually decrease with the increase of frequency, making the PSR performance of the LDO circuit gradually worse; and as the LDO main loop gain continues to increase, the loop effect may disappear, making the LDO main loop gain may be 0dB, and the PSR capability of the LDO circuit is also lost. Therefore, the power supply rejection capability of the LDO circuit in the medium and high frequency bands is poor, or even lost.

[0081] To this end, an embodiment of the present application provides a low voltage difference linear voltage regulator circuit, which can improve the power supply rejection (PSR) capability of the circuit in the medium and high frequency bands. Figure 3 A circuit diagram of a specific example of a low voltage difference linear voltage regulator circuit in an embodiment of the present application is shown. As shown in the figure, the low voltage difference linear voltage regulator circuit includes an operational amplifier GEA, a transmission transistor MP, a feedback circuit 10 and a feedforward power supply ripple cancellation module FFRC;

[0082] The inverting input terminal of the operational amplifier GEA is configured to receive a reference voltage signal Vref, the non-inverting input terminal of the operational amplifier GEA is connected to the output terminal of the feedback circuit 10, and the output terminal of the operational amplifier GEA is connected to the control terminal of the transmission transistor MP; the first terminal of the transmission transistor MP is connected to the power supply terminal vdda, and the second terminal of the transmission transistor MP is respectively connected to the input terminal of the feedback circuit 10 and the regulated output terminal of the low voltage difference linear voltage regulator circuit, and the regulated output terminal is used to provide an output signal VLDO;

[0083] Wherein, a first path (path 1) is formed from the power supply terminal vdda to the regulated output terminal based at least on the transconductance gm of the transmission transistor MP, and is used to generate a first ripple current Δi1 at the output of the low voltage difference linear voltage regulator circuit through the first path under the influence of power supply noise; a second path (path 2) is formed from the power supply terminal vdda to the regulated output terminal based at least on the conductance gds of the transmission transistor MP, and is used to generate a second ripple current Δi2 at the output of the low voltage difference linear voltage regulator circuit through the second path under the influence of power supply noise;

[0084] The input end of the feed-forward power supply ripple cancellation module FFRC is connected to the power supply terminal vdda, and the output end of the feed-forward power supply ripple cancellation module FFRC is connected to the control end of the transmission transistor MP;

[0085] Wherein, at least based on the feed-forward power supply ripple cancellation module FFRC, a third path (path 3) is formed from the power supply terminal vdda to the voltage regulated output terminal, which is used to transmit the power supply noise to the control terminal of the transmission transistor MP at medium and high frequencies to generate a ripple cancellation current at the output of the low voltage difference linear voltage regulator circuit;

[0086] The ripple compensation current is used to reduce or offset the first ripple current Δi1 and the second ripple current Δi2, so as to improve the power supply suppression capability of the low voltage difference linear voltage regulator circuit at medium and high frequencies.

[0087] In the embodiment of the present application, the low voltage difference linear voltage regulator circuit can be named differently, such as low voltage difference voltage regulator circuit, low voltage difference regulator, LDO circuit, etc., and the name is not limited here. The low frequency, medium high frequency and high frequency arranged sequentially in the frequency interval can be relative values, not limited to absolute values. The power supply terminal vdda can provide the input power supply vin, which may include power supply noise, such as power supply ripple; the ground terminal vsa can be grounded.

[0088] In the embodiment of the present application, the transmission transistor MP may include at least one of a PMOS transistor (P-type metal oxide semiconductor field effect transistor, referred to as a PMOS transistor), an NMOS transistor (N-type metal oxide semiconductor field effect transistor, referred to as an NMOS transistor), a BJT transistor (bipolar junction transistor, commonly known as a triode), etc., which has a control terminal, a first terminal and a second terminal, and its working principle is that under the control of a control signal input to the control terminal, the path between the first terminal and the second terminal is turned on or off to connect or block the signal transmission between the first terminal and the second terminal. For example, the first terminal may be a source or an emitter, and correspondingly, the second terminal may be a drain or a collector; or conversely, the first terminal may be a drain or a collector, and correspondingly, the second terminal may be a source or an emitter. Exemplarily, the transmission transistor MP may also include at least one of the following: IGBT (insulated gate bipolar transistor), GTO (gate turn-off thyristor), SCR (silicon controlled thyristor), MCT (MOS controlled thyristor), IGCT (integrated gate commutated thyristor), IEGT (electron injection enhanced gate transistor).

[0089] Exemplarily, the operational amplifier GEA may be an error amplifier, and the transfer transistor MP may be a PMOS transistor.

[0090] The low voltage difference linear voltage regulator circuit of the embodiment of the present application is Figure 1 Like the LDO circuit in, it has path 1 and path 2 as well as path 3. Through the feedforward power supply ripple cancellation module FFRC, the power supply ripple can be fed forward to the control end of the transmission transistor MP at medium and high frequencies, so that only at medium and high frequencies, a ripple voltage is generated at the control end of the transmission transistor MP, thereby generating a ripple cancellation current in the output of the low-voltage difference linear voltage regulator circuit to reduce or cancel the first ripple current Δi1 and the second ripple current Δi2, thereby improving the PSR capability of the low-voltage difference linear voltage regulator circuit at medium and high frequencies, and overcoming the reduction in PSR capability caused by the reduction in the main loop gain of the low-voltage difference linear voltage regulator circuit at medium and high frequencies. And the ripple cancellation current generated at the output of the low-voltage difference linear voltage regulator circuit at medium and high frequencies can be equal in magnitude and opposite in direction to the current generated by path 1 and path 2, so as to achieve the cancellation of the first ripple current Δi1 and the second ripple current Δi2.

[0091] Exemplarily, when the output current of the low voltage difference linear voltage regulator circuit caused by the input power ripple is 0, the following formula may exist:

[0092]

[0093] Among them, V Rc It is the ripple voltage generated at the control terminal of the transmission transistor MP by the power ripple through the third path (path 3).

[0094] Then, according to formula (4), we can solve V Rc The optimal solution is:

[0095]

[0096] Combination Figure 3 It can be seen that the feed-forward power supply ripple cancellation module FFRC does not participate in the main loop of the low voltage difference linear voltage regulator circuit, so theoretically it will not affect the loop stability of the circuit.

[0097] In some possible implementations, the feed-forward power supply ripple cancellation module FFRC may be a signal amplification circuit using an operational amplifier or the like, which may adjust the amplitude of the small AC signal of the power supply ripple and may be set according to actual needs.

[0098] The embodiment of the present application uses the feedforward power supply ripple cancellation technology to transmit the power supply ripple feedforward to the control end of the transmission transistor at medium and high frequencies, and can achieve the cancellation of the first ripple current and the second ripple current at medium and high frequencies, thereby improving the PSR capability of the circuit. Therefore, not only at low frequencies, due to the high loop gain, the circuit has a good PSR characteristic; but also at medium and high frequencies, due to the cancellation of the ripple current in the output of the low-voltage difference linear voltage regulator circuit, the PSR capability of the circuit can be improved. And because the feedforward power supply ripple cancellation module does not participate in the main loop of the circuit, the loop stability is guaranteed.

[0099] In an optional implementation, the feed-forward power supply ripple cancellation module FFRC includes:

[0100] A high pass filter 20 for selecting power ripples of medium and high frequency ripple frequencies;

[0101] A proportional amplification module 30, for adjusting the amplitude of the power ripple of the medium and high frequency ripple frequency selected by the high-pass filter 20; and

[0102] The current mirror module 40 is used to feed forward the output of the proportional amplification module 30 to the control terminal of the transmission transistor MP through the transmission of the current mirror.

[0103] In this way, through the frequency selection of the high-pass filter 20, the medium and high frequency bands of the power supply ripple are selected to be fed forward to the control end of the transmission transistor, so as to realize the cancellation of the ripple current in the output of the low-voltage difference linear voltage regulator circuit at medium and high frequencies; and through the amplitude adjustment performed by the proportional amplification module 30, the ripple cancellation current generated at the output of the low-voltage difference linear voltage regulator circuit can completely cancel the first ripple current and the second ripple current, or can reduce the first ripple current and the second ripple current; and the power supply ripple is transmitted through the current mirror of the current mirror module 40 without passing through the frequency selection of other high-pass filters, so that the full-band power supply ripple can be suppressed, thereby improving the PSR capability of the circuit at medium and high frequencies, and also avoiding the destruction of the PSR at low frequencies.

[0104] In some possible implementations, the high-pass filter 20 may include at least one of an RC high-pass filter, an RLC high-pass filter, an RL high-pass filter and other high-pass filters, and may be configured according to actual needs.

[0105] In some possible implementations, the proportional amplification module 30 can use an operational amplifier to convert the input power supply ripple (AC small signal) voltage amplitude V R Enlarge the same proportion.

[0106] Figure 4 A circuit diagram of another specific example of a low voltage difference linear voltage regulator circuit in an embodiment of the present application is shown. Among them, the specific circuit structure of the high-pass filter 20, the proportional amplification module 30 and the current mirror module 40 can be set according to actual needs and is not limited thereto. As shown in the figure, in an optional embodiment, the high-pass filter 20 includes a filter capacitor Cm and a filter resistor Rm;

[0107] The same-proportional amplification module 30 includes a same-proportional amplifier AMP, a filter resistor Rm, a first feedback resistor RB1 and a second feedback resistor RB2;

[0108] The first end of the filter capacitor Cm is connected to the power supply terminal vdda, and the second end of the filter capacitor Cm is respectively connected to the second end of the filter resistor Rm and the non-inverting input terminal of the proportional amplifier AMP; the first end of the filter resistor Rm and the first end of the first feedback resistor RB1 are respectively configured to receive a reference voltage signal Vref, the second end of the first feedback resistor RB1 is respectively connected to the inverting input terminal of the proportional amplifier AMP and the first end of the second feedback resistor RB2, and the output terminal of the proportional amplifier AMP is respectively connected to the second end of the second feedback resistor RB2 and the input terminal of the current mirror module 40.

[0109] In the embodiment of the present application, the output end of the current mirror module 40 may be connected to the control end of the transfer transistor MP. For example, the output end of the current mirror module 40 may be further connected to the control end of the transfer transistor MP through a current mirror.

[0110] The first feedback resistor RB1 and the second feedback resistor RB2 form a feedback resistor network. The first feedback resistor RB1 and the second feedback resistor RB2 can be a single resistor, or a plurality of resistors connected in series and / or in parallel, or a passive resistor network or an active resistor network including resistors, capacitors, inductors, etc. Moreover, the filter capacitor and filter resistor in the high-pass filter 20 are not limited to a single resistor or capacitor, but can also be a modified structure using series and / or parallel connections.

[0111] In an optional implementation, the current mirror module 40 includes a twenty-sixth PMOS transistor M26, a twenty-seventh PMOS transistor M27, a twenty-eighth NMOS transistor M28, a twenty-ninth NMOS transistor M29, a thirtieth PMOS transistor M30, and a thirty-first PMOS transistor M31;

[0112] The gate of the twenty-seventh PMOS transistor M27 is configured as the input end of the current mirror module 40, and the drain of the thirty-first PMOS transistor M31 is configured as the output end of the current mirror module 40;

[0113] The drain of the twenty-seventh PMOS transistor M27 is connected to the drain of the twenty-eighth NMOS transistor M28, the gate of the twenty-eighth NMOS transistor M28 and the gate of the twenty-ninth NMOS transistor M29 respectively; the drain of the twenty-ninth NMOS transistor M29 is connected to the drain of the thirtieth PMOS transistor M30, the gate of the thirtieth PMOS transistor M30 and the gate of the thirty-first PMOS transistor M31 respectively; the source of the twenty-eighth NMOS transistor M28 and the source of the twenty-ninth NMOS transistor M29 are connected to the ground terminal vssa respectively; the source of the thirtieth PMOS transistor M30 and the source of the thirty-first PMOS transistor M31 are connected to the power supply terminal vdda respectively; the source of the twenty-seventh PMOS transistor M27 is connected to the drain of the twenty-sixth PMOS transistor M26, the source of the twenty-sixth PMOS transistor M26 is connected to the power supply terminal vdda, and the gate of the twenty-sixth PMOS transistor M26 is configured to receive the second high-bit bias signal vbp2.

[0114] In the embodiment of the present application, the twenty-seventh PMOS transistor M27 can constitute a source follower, and can pass the power supply ripple voltage after the amplitude adjustment by the proportional amplification module 30 to the subsequent current mirror. The twenty-eighth NMOS transistor M28 and the twenty-ninth NMOS transistor M29 can constitute a current mirror, and the thirtieth PMOS transistor M30 and the thirty-first PMOS transistor M31 can constitute a current mirror, so that the power supply ripple voltage after the amplitude adjustment is transmitted through the current mirror and output from the drain of the thirty-first PMOS transistor M31, that is, the output end of the current mirror module 40.

[0115] In this way, the embodiment of the present application constitutes a FFRC structure based on the feedforward power supply ripple cancellation (FFRC) technology, and the FFRC structure is mainly composed of a proportional amplifier AMP, a high-pass filter 20 (Rm and Cm), and feedback networks RB1 and RB2. The medium and high frequency ripple frequency (AC small signal) of the power supply ripple is obtained through the filter resistor Rm and the filter capacitor Cm, and the AC small signal is input to the positive input end of the proportional amplifier AMP, and the coupled AC small signal is amplified by 1+ RB2 / RB1, and then transmitted through the current mirror, and finally injected into the gate end of the transmission transistor MP. Therefore, the ripple in the output of the low voltage difference linear voltage regulator circuit can be eliminated at medium and high frequencies, and the PSR capability of the low voltage difference linear voltage regulator circuit in the medium and high frequency bands is improved.

[0116] Figure 5 The circuit diagram of a specific example of a proportional amplifier in the embodiment of the present application is shown. The specific circuit structure of the proportional amplifier AMP can be set according to actual needs, but is not limited thereto. For example, it is not limited to the cascade of two-stage sampling amplifiers, but can also be a cascade of multiple amplifiers or other circuit structures. As shown in the figure, the proportional amplifier AMP includes a cascaded first amplifier Stage1 and a second amplifier Stage2;

[0117] The non-inverting input terminal of the first amplifier Stage1 is configured as the non-inverting input terminal Ain+ of the proportional amplifier AMP, the inverting input terminal of the first amplifier Stage1 is configured as the inverting input terminal Ain- of the proportional amplifier AMP, the output terminal of the first amplifier Stage1 is connected to the input terminal of the second amplifier Stage2, and the output terminal of the second amplifier Stage2 is configured as the output terminal Aout of the proportional amplifier AMP;

[0118] Wherein, the first amplifier Stage1 comprises a high-gain amplifier, which is used to adjust the amplitude of the power supply ripple of the medium and high frequency ripple frequency selected by the high-pass filter;

[0119] The second amplifier Stage2 comprises a low output impedance amplifier for eliminating low frequency poles.

[0120] In the embodiment of the present application, the high-gain amplifier may be an amplifier that can provide a high gain. The low-output impedance amplifier may be an amplifier with low output impedance. The high-gain amplifier and the low-output impedance amplifier may have different names, which are not limited here, and both may be configured with specific circuit structures according to actual needs.

[0121] In this way, the embodiment of the present application obtains a high gain through a high gain amplifier to achieve amplitude adjustment, and the output impedance of the operational amplifier can be reduced through a low output impedance amplifier, thereby avoiding the generation of a low-frequency pole.

[0122] Figure 6 A circuit diagram of another specific example of a proportional amplifier in an embodiment of the present application is shown. As shown in the figure, in an optional implementation, the first amplifier Stage1 includes a telescopic common source and common gate amplifier;

[0123] and / or, the first amplifier Stage1 includes a twelfth NMOS transistor M12, a thirteenth NMOS transistor M13, a fourteenth PMOS transistor M14, a fifteenth PMOS transistor M15, a sixteenth PMOS transistor M16, a seventeenth PMOS transistor M17, an eighteenth NMOS transistor M18, a nineteenth NMOS transistor M19, and a twentieth NMOS transistor M20;

[0124] The gate of the twelfth NMOS transistor M12 is configured as the non-inverting input terminal of the first amplifier Stage1, the gate of the thirteenth NMOS transistor M13 is configured as the inverting input terminal of the first amplifier Stage1, and the drain of the nineteenth NMOS transistor M19 is configured as the output terminal of the first amplifier Stage1;

[0125] The drain of the twelfth NMOS transistor M12 is connected to the source of the eighteenth NMOS transistor M18, the drain of the thirteenth NMOS transistor M13 is connected to the source of the nineteenth NMOS transistor M19; the drain of the eighteenth NMOS transistor M18 is respectively connected to the drain of the sixteenth PMOS transistor M16, the gate of the sixteenth PMOS transistor M16 and the gate of the seventeenth PMOS transistor M17, the drain of the nineteenth NMOS transistor M19 is connected to the drain of the seventeenth PMOS transistor M17; the source of the sixteenth PMOS transistor M16 is respectively connected to the drain of the fourteenth PMOS transistor M18, and the gate of the seventeenth PMOS transistor M17. The drain of the body transistor M14, the gate of the fourteenth PMOS transistor M14 and the gate of the fifteenth PMOS transistor M15 are connected, and the source of the seventeenth PMOS transistor M17 is connected to the drain of the fifteenth PMOS transistor M15; the source of the fourteenth PMOS transistor M14 and the source of the fifteenth PMOS transistor M15 are respectively connected to the power supply terminal vdda; the source of the twelfth NMOS transistor M12 and the source of the thirteenth NMOS transistor M13 are respectively connected to the drain of the twentieth NMOS transistor M20, and the source of the twentieth NMOS transistor M20 is connected to the ground terminal vssa;

[0126] The gate of the twentieth NMOS transistor M20 is configured to receive the first low bias signal vbn1 , and the gates of the eighteenth NMOS transistor M18 and the nineteenth NMOS transistor M19 are respectively configured to receive the second low bias signal vbn2 .

[0127] In this way, the first amplifier Stage1 can form a telescopic cascode amplifier, thereby improving the output gain.

[0128] In an optional implementation, the second amplifier Stage2 comprises an inverted source follower (FVF);

[0129] and / or, the second amplifier Stage2 includes a twenty-first NMOS transistor M21, a twenty-second PMOS transistor M22 and a twenty-third PMOS transistor M23;

[0130] A gate of the twenty-second PMOS transistor M22 is configured as an input terminal of the second amplifier Stage2, and a source of the twenty-second PMOS transistor M22 is configured as an output terminal of the second amplifier Stage2;

[0131] The gate of the twenty-second PMOS transistor M22 is connected to the drain of the nineteenth NMOS transistor M19, the drain of the twenty-second PMOS transistor M22 is respectively connected to the gate of the twenty-third PMOS transistor M23 and the drain of the twenty-first NMOS transistor M21, the source of the twenty-second PMOS transistor M22 is connected to the drain of the twenty-third PMOS transistor M23, the source of the twenty-third PMOS transistor M23 is connected to the power supply terminal vdda, and the source of the twenty-first NMOS transistor M21 is connected to the ground terminal vssa;

[0132] A gate of the twenty-first NMOS transistor M21 is configured to receive the first low bit bias signal vbn1 .

[0133] In this way, the twenty-second PMOS transistor M22 and the twenty-third PMOS transistor M23 can form an inverted source follower (FVF), which reduces the output impedance of the operational amplifier, thereby avoiding the generation of a low-frequency pole.

[0134] In the embodiment of the present application, the specific circuit structure of the operational amplifier GEA can be set according to actual needs and is not limited to Figure 4 In an optional implementation, the operational amplifier GEA includes a first PMOS transistor M1, a second PMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, a sixth PMOS transistor M6, a seventh PMOS transistor M7, an eighth NMOS transistor M8, a ninth NMOS transistor M9, a tenth PMOS transistor M10, an eleventh PMOS transistor M11, a twenty-fourth NMOS transistor M24, a twenty-fifth PMOS transistor M25, a first compensation capacitor Cm1, and a second compensation capacitor Cm2;

[0135] The gate of the first PMOS transistor M1 is configured as the inverting input terminal of the operational amplifier GEA, and the gate of the second PMOS transistor M2 is configured as the non-inverting input terminal of the operational amplifier GEA; the drain of the eleventh PMOS transistor M11 is configured as the output terminal of the operational amplifier GEA;

[0136] The gate of the twenty-fifth PMOS transistor M25 is configured to receive the first high-bit bias signal vbp1, the source of the twenty-fifth PMOS transistor M25 is connected to the power supply terminal vdda, the drain of the twenty-fifth PMOS transistor M25 is respectively connected to the source of the first PMOS transistor M1 and the source of the second PMOS transistor M2, the drain of the first PMOS transistor M1 is respectively connected to the drain of the fifth NMOS transistor M5 and the source of the ninth NMOS transistor M9, the drain of the second PMOS transistor M2 is respectively connected to the drain of the fourth NMOS transistor M4 and the source of the eighth NMOS transistor M8; the drain of the eighth NMOS transistor M8 is respectively connected to the drain of the fifth NMOS transistor M5 and the source of the ninth NMOS transistor M9. connected to the drain of the sixth PMOS transistor M6, the gate of the sixth PMOS transistor M6 and the gate of the seventh PMOS transistor M7, the source of the sixth PMOS transistor M6 and the source of the seventh PMOS transistor M7 are respectively connected to the power supply terminal vdda; the source of the fourth NMOS transistor M4 and the source of the fifth NMOS transistor M5 are respectively connected to the ground terminal vssa; the gate of the fourth NMOS transistor M4 and the gate of the fifth NMOS transistor M5 are respectively configured to receive the first low-bit bias signal vbn1, and the gate of the eighth NMOS transistor M8 and the gate of the ninth NMOS transistor M9 are respectively configured to receive the second low-bit bias signal vbn2;

[0137] The drain of the ninth NMOS transistor M9 is respectively connected to the drain of the seventh PMOS transistor M7 and the gate of the third NMOS transistor M3, the source of the third NMOS transistor M3 is connected to the ground terminal vssa, the drain of the third NMOS transistor M3 is respectively connected to the drain of the tenth PMOS transistor M10, the gate of the tenth PMOS transistor M10, the gate of the eleventh PMOS transistor M11 and the output terminal of the current mirror module 40; the source of the tenth PMOS transistor M10 and the source of the eleventh PMOS transistor M11 are respectively connected to the power supply terminal vdda; the drain of the eleventh PMOS transistor M11 is connected to the drain of the twenty-fourth NMOS transistor M24, the source of the twenty-fourth NMOS transistor M24 is connected to the ground terminal vssa, and the gate of the twenty-fourth NMOS transistor M24 is configured to receive the first low-bit bias signal vbn1;

[0138] The first end of the first compensation capacitor Cm1 is connected to the drain of the ninth NMOS transistor M9 and the drain of the seventh PMOS transistor M7 respectively, and the second end of the first compensation capacitor Cm1 is connected to the voltage stabilization output terminal;

[0139] A first end of the second compensation capacitor Cm2 is connected to the drain of the twenty-fourth NMOS transistor M24 and the drain of the eleventh PMOS transistor M11 respectively, and a second end of the second compensation capacitor Cm2 is connected to the voltage stabilization output terminal.

[0140] In some possible implementations, the gate of the first PMOS transistor M1 can be configured to receive a reference voltage signal Vref. The gate of the second PMOS transistor M2 can obtain a feedback signal vfb and can be connected to a connection node between the first resistor R1 and the second resistor R2. The gate of the transmission transistor MP can be connected to the drain of the eleventh PMOS transistor M11. The drain of the thirty-first PMOS transistor M31 can be connected to the gate of the eleventh PMOS transistor M11, the gate of the tenth PMOS transistor M10, the drain of the tenth PMOS transistor M10, and the drain of the third NMOS transistor M3, respectively, that is, the output end of the current mirror module 40 is connected to the current mirror load of the third NMOS transistor M3, and the output of the current mirror module 40 is finally transmitted to the gate of the transmission transistor MP through the current mirror load of the third NMOS transistor M3.

[0141] In the embodiment of the present application, the first compensation capacitor Cm1 and the second compensation capacitor Cm2 may be a single capacitor, or a plurality of capacitors connected in series and / or in parallel, and may also include a passive capacitor network or an active capacitor network of resistors, capacitors, inductors, etc. The first compensation capacitor Cm1 and the second compensation capacitor Cm2 provide the function of Miller compensation capacitors, which can improve the stability of the output signal VLDO at the voltage regulated output terminal.

[0142] Combination Figure 4 and Figure 6 It can be seen that the low voltage difference linear voltage regulator circuit includes a first-stage amplifier, a second-stage amplifier and a third-stage amplifier. Among them, the first PMOS transistor M1 and the second PMOS transistor M2 are the input pair of the first-stage amplifier. The third NMOS transistor M3 and its corresponding current mirror load (the tenth PMOS transistor M10 and the eleventh PMOS transistor M11) constitute the second-stage amplifier. The transmission transistor MP is the third-stage amplifier.

[0143] In the embodiment of the present application, the specific circuit structure of the feedback circuit 10 can be set according to actual needs and is not limited to Figure 4 In an optional embodiment, the transfer transistor MP is a PMOS transistor, whose gate, source and drain correspond to the control terminal, the first terminal and the second terminal of the transfer transistor MP respectively;

[0144] The feedback circuit 10 includes a first resistor R1 and a second resistor R2;

[0145] The non-inverting input terminal of the operational amplifier GEA is respectively connected to the second end of the first resistor R1 and the first end of the second resistor R2, the second end of the transmission transistor MP is respectively connected to the first end of the first resistor R1 and the voltage stabilization output terminal of the low voltage difference linear voltage regulator circuit; the second end of the second resistor R2 is connected to the ground terminal vsa.

[0146] In the embodiment of the present application, the first resistor R1 and the second resistor R2 can be a single resistor, or a plurality of resistors connected in series and / or in parallel, or a passive resistor network or an active resistor network including resistors, capacitors, inductors, etc.

[0147] In the embodiment of the present application, the first low voltage bias signal vbn1, the second low bias signal vbn2, the first high bias signal vbp1 and the second high bias signal vbp2 can all be provided by external bias circuits, and these bias circuits can be controlled by logic control circuits. These are not the inventive points of the invention, and the bias circuits and logic control circuits are both prior art, and the present invention will not be described in detail.

[0148] The transistor in the embodiment of the present application may be a single transistor or a plurality of transistors may be connected in series and / or in parallel.

[0149] An embodiment of the present application also provides a radio frequency module, which includes a low voltage difference linear voltage regulator circuit as described in the above embodiment, thereby improving the PSR capability of the module at medium and high frequencies.

[0150] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations included in the claims. Various modifications and changes may be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may be arbitrarily combined to form other embodiments of the present application that may not be explicitly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A low voltage drop linear voltage regulator circuit, characterized in that: The low voltage difference linear voltage stabilization circuit comprises an operational amplifier, a transmission transistor, a feedback circuit and a feedforward power supply ripple cancellation module; The inverting input terminal of the operational amplifier is configured to receive a reference voltage signal, the non-inverting input terminal of the operational amplifier is connected to the output terminal of the feedback circuit, and the output terminal of the operational amplifier is connected to the control terminal of the transmission transistor; the first terminal of the transmission transistor is connected to the power supply terminal, the second terminal of the transmission transistor is respectively connected to the input terminal of the feedback circuit and the voltage stabilization output terminal of the low voltage difference linear voltage stabilization circuit, and the voltage stabilization output terminal is used to provide an output signal; Wherein, a first path is formed from the power supply end to the regulated output end based at least on the transconductance of the transmission transistor, and is used to generate a first ripple current at the output of the low voltage difference linear voltage regulator circuit through the first path under the influence of power supply noise; a second path is formed from the power supply end to the regulated output end based at least on the conductance of the transmission transistor, and is used to generate a second ripple current at the output of the low voltage difference linear voltage regulator circuit through the second path under the influence of power supply noise; The input end of the feed-forward power supply ripple cancellation module is connected to the power supply end, and the output end of the feed-forward power supply ripple cancellation module is connected to the control end of the transmission transistor; Wherein, at least based on the feed-forward power supply ripple cancellation module, a third path is formed from the power supply end to the voltage regulated output end, which is used to transmit the power supply noise to the control end of the transmission transistor at medium and high frequencies to generate a ripple cancellation current at the output of the low voltage difference linear voltage regulator circuit; The ripple compensation current is used to reduce or offset the first ripple current and the second ripple current, so as to improve the power supply suppression capability of the low voltage difference linear voltage regulator circuit at medium and high frequencies; The feed-forward power supply ripple cancellation module comprises: High-pass filter, used to select power supply ripple with medium and high ripple frequencies; A proportional amplification module, used for adjusting the amplitude of the power supply ripple of the medium and high frequency ripple frequency selected by the high-pass filter; and A current mirror module, used for feeding forward the output of the same-proportional amplification module to the control terminal of the transmission transistor through the transmission of the current mirror; The current mirror module includes a twenty-sixth PMOS transistor, a twenty-seventh PMOS transistor, a twenty-eighth NMOS transistor, a twenty-ninth NMOS transistor, a thirtieth PMOS transistor and a thirty-first PMOS transistor; The gate of the twenty-seventh PMOS transistor is configured as the input end of the current mirror module, and the drain of the thirty-first PMOS transistor is configured as the output end of the current mirror module; The drain of the twenty-seventh PMOS transistor is respectively connected to the drain of the twenty-eighth NMOS transistor, the gate of the twenty-eighth NMOS transistor and the gate of the twenty-ninth NMOS transistor; the drain of the twenty-ninth NMOS transistor is respectively connected to the drain of the thirtieth PMOS transistor, the gate of the thirtieth PMOS transistor and the gate of the thirty-first PMOS transistor; the source of the twenty-eighth NMOS transistor and the source of the twenty-ninth NMOS transistor are respectively connected to the ground terminal; the source of the thirtieth PMOS transistor and the source of the thirty-first PMOS transistor are respectively connected to the power supply terminal; the source of the twenty-seventh PMOS transistor is connected to the drain of the twenty-sixth PMOS transistor, the source of the twenty-sixth PMOS transistor is connected to the power supply terminal, and the gate of the twenty-sixth PMOS transistor is configured to receive a second high-bit bias signal.

2. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The high-pass filter includes a filter capacitor and a filter resistor; The same-proportional amplification module includes a same-proportional amplifier, the filter resistor, a first feedback resistor and a second feedback resistor; The first end of the filter capacitor is connected to the power supply end, and the second end of the filter capacitor is respectively connected to the second end of the filter resistor and the non-inverting input end of the proportional amplifier; the first end of the filter resistor and the first end of the first feedback resistor are respectively configured to receive a reference voltage signal, the second end of the first feedback resistor is respectively connected to the inverting input end of the proportional amplifier and the first end of the second feedback resistor, and the output end of the proportional amplifier is respectively connected to the second end of the second feedback resistor and the input end of the current mirror module.

3. The low voltage difference linear voltage regulator circuit according to claim 2, characterized in that: The proportional amplifier comprises a first amplifier and a second amplifier connected in cascade; The non-inverting input terminal of the first amplifier is configured as the non-inverting input terminal of the proportional amplifier, the inverting input terminal of the first amplifier is configured as the inverting input terminal of the proportional amplifier, the output terminal of the first amplifier is connected to the input terminal of the second amplifier, and the output terminal of the second amplifier is configured as the output terminal of the proportional amplifier; Wherein, the first amplifier comprises a high-gain amplifier, which is used to adjust the amplitude of the power supply ripple of the medium and high frequency ripple frequency selected to pass through by the high-pass filter; The second amplifier comprises a low output impedance amplifier for eliminating a low frequency pole.

4. The low voltage difference linear voltage regulator circuit according to claim 3, characterized in that: The first amplifier comprises a telescopic cascode amplifier; and / or, the first amplifier includes a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, and a twentieth NMOS transistor; The gate of the twelfth NMOS transistor is configured as a non-inverting input terminal of the first amplifier, the gate of the thirteenth NMOS transistor is configured as an inverting input terminal of the first amplifier, and the drain of the nineteenth NMOS transistor is configured as an output terminal of the first amplifier; The drain of the twelfth NMOS transistor is connected to the source of the eighteenth NMOS transistor, and the drain of the thirteenth NMOS transistor is connected to the source of the nineteenth NMOS transistor; the drain of the eighteenth NMOS transistor is respectively connected to the drain of the sixteenth PMOS transistor, the gate of the sixteenth PMOS transistor and the gate of the seventeenth PMOS transistor, and the drain of the nineteenth NMOS transistor is connected to the drain of the seventeenth PMOS transistor; the source of the sixteenth PMOS transistor is respectively connected to the drain of the fourteenth PMOS transistor, the gate of the fourteenth PMOS transistor and the gate of the fifteenth PMOS transistor, and the source of the seventeenth PMOS transistor is connected to the drain of the fifteenth PMOS transistor; the source of the fourteenth PMOS transistor and the source of the fifteenth PMOS transistor are respectively connected to the power supply terminal; the source of the twelfth NMOS transistor and the source of the thirteenth NMOS transistor are respectively connected to the drain of the twentieth NMOS transistor, and the source of the twentieth NMOS transistor is connected to the ground terminal; The gate of the twentieth NMOS transistor is configured to receive a first low bias signal, and the gate of the eighteenth NMOS transistor and the gate of the nineteenth NMOS transistor are respectively configured to receive a second low bias signal.

5. The low voltage difference linear voltage regulator circuit according to claim 4, characterized in that: The second amplifier comprises an inverted source follower; and / or, the second amplifier includes a twenty-first NMOS transistor, a twenty-second PMOS transistor and a twenty-third PMOS transistor; A gate of the twenty-second PMOS transistor is configured as an input terminal of the second amplifier, and a source of the twenty-second PMOS transistor is configured as an output terminal of the second amplifier; The gate of the twenty-second PMOS transistor is connected to the drain of the nineteenth NMOS transistor, the drain of the twenty-second PMOS transistor is respectively connected to the gate of the twenty-third PMOS transistor and the drain of the twenty-first NMOS transistor, the source of the twenty-second PMOS transistor is connected to the drain of the twenty-third PMOS transistor, the source of the twenty-third PMOS transistor is connected to the power supply terminal, and the source of the twenty-first NMOS transistor is connected to the ground terminal; The gate of the twenty-first NMOS transistor is configured to receive the first low bias signal.

6. The low voltage difference linear voltage regulator circuit according to claim 5, characterized in that: The operational amplifier includes a first PMOS transistor, a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twenty-fourth NMOS transistor, a twenty-fifth PMOS transistor, a first compensation capacitor and a second compensation capacitor; The gate of the first PMOS transistor is configured as the inverting input terminal of the operational amplifier, the gate of the second PMOS transistor is configured as the non-inverting input terminal of the operational amplifier; the drain of the eleventh PMOS transistor is configured as the output terminal of the operational amplifier; The gate of the twenty-fifth PMOS transistor is configured to receive the first high-bit bias signal, the source of the twenty-fifth PMOS transistor is connected to the power supply terminal, the drain of the twenty-fifth PMOS transistor is respectively connected to the source of the first PMOS transistor and the source of the second PMOS transistor, the drain of the first PMOS transistor is respectively connected to the drain of the fifth NMOS transistor and the source of the ninth NMOS transistor, the drain of the second PMOS transistor is respectively connected to the drain of the fourth NMOS transistor and the source of the eighth NMOS transistor; the drain of the eighth NMOS transistor is respectively connected to the drain of the sixth PMOS transistor, the gate of the sixth PMOS transistor and the gate of the seventh PMOS transistor, and the source of the sixth PMOS transistor and the source of the seventh PMOS transistor are respectively connected to the power supply terminal; the source of the fourth NMOS transistor and the source of the fifth NMOS transistor are respectively connected to the ground terminal; the gate of the fourth NMOS transistor and the gate of the fifth NMOS transistor are respectively configured to receive the first low-bit bias signal, and the gate of the eighth NMOS transistor and the gate of the ninth NMOS transistor are respectively configured to receive the second low-bit bias signal; The drain of the ninth NMOS transistor is respectively connected to the drain of the seventh PMOS transistor and the gate of the third NMOS transistor, the source of the third NMOS transistor is connected to the ground terminal, the drain of the third NMOS transistor is respectively connected to the drain of the tenth PMOS transistor, the gate of the tenth PMOS transistor, the gate of the eleventh PMOS transistor and the output terminal of the current mirror module; the source of the tenth PMOS transistor and the source of the eleventh PMOS transistor are respectively connected to the power supply terminal; the drain of the eleventh PMOS transistor is connected to the drain of the twenty-fourth NMOS transistor, the source of the twenty-fourth NMOS transistor is connected to the ground terminal, and the gate of the twenty-fourth NMOS transistor is configured to receive the first low-bit bias signal; The first end of the first compensation capacitor is connected to the drain of the ninth NMOS transistor and the drain of the seventh PMOS transistor respectively, and the second end of the first compensation capacitor is connected to the voltage stabilization output terminal; A first end of the second compensation capacitor is connected to the drain of the twenty-fourth NMOS transistor and the drain of the eleventh PMOS transistor respectively, and a second end of the second compensation capacitor is connected to the voltage stabilization output terminal.

7. The low voltage difference linear voltage regulator circuit according to any one of claims 1 to 6, characterized in that: The transmission transistor is a PMOS transistor, and its gate, source and drain correspond to the control terminal, the first terminal and the second terminal of the transmission transistor respectively; And / or, the feedback circuit includes a first resistor and a second resistor; The non-inverting input terminal of the operational amplifier is respectively connected to the second end of the first resistor and the first end of the second resistor, the second end of the transmission transistor is respectively connected to the first end of the first resistor and the voltage stabilization output terminal of the low voltage difference linear voltage stabilization circuit; the second end of the second resistor is connected to the ground.

8. A radio frequency module, characterized in that: The radio frequency module includes the low voltage drop linear voltage regulator circuit as described in any one of claims 1-7.

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