CNFET-based high-speed digital low dropout linear regulator power supply chip

Abstract

The invention discloses a CNFET-based high-speed digital low dropout regulator power supply chip, which comprises a silicon-based SOC and a CNFET power supply management chip layer grown above the silicon-based SOC, a plurality of digital LDOs are arranged on the CNFET power supply management chip layer, the input end of the CNFET power supply management chip layer is connected to an external power supply end, and the output end of the CNFET power supply management chip layer is connected with the silicon-based SOC to supply power to the silicon-based SOC. The digital LDO comprises a comparator, a coarse adjustment unit, a fine adjustment unit and a voltage output unit which are connected in sequence. The input end of the comparator is respectively connected with a reference voltage end and the voltage output unit, and the output end is respectively connected to the coarse adjustment unit and the fine adjustment unit; the coarse adjustment unit comprises an adjustment controller and a coarse adjustment power transistor array which are connected with each other; the fine adjustment unit comprises a shift register and a fine adjustment power transistor array which are connected with each other. According to the invention, high-efficiency and stable voltage regulation can be realized under the condition of considering the response speed and the regulation precision.

Description

Technical Field

[0001] The present invention relates to the technical field of chip research and development, and in particular to a high-speed digital low-voltage dropout linear regulator power supply chip based on CNFET. Background Art

[0002] Carbon nanotube field effect transistor (CNFET) is a transistor with carbon nanotubes as channel material, which has high electron mobility, low power consumption and excellent electrical performance. Due to the large-scale system on chip (SOC) with large working current, it has high requirements for the output current of the power management module. Compared with silicon-based MOSFET, CNFET has a higher current density, because the use of CNFET process can design a low-dropout linear regulator (LDO) with a large output current, which can increase the output current of LDO. At present, LDO can be mainly divided into analog LDO and digital LDO. Among them, the core functional unit of analog LDO is the error amplifier. This structure is more sensitive to process changes and is difficult to implement under the current immature CNFET process. Digital LDO technology benefits from digital control methods, with larger output current, more stable performance and stronger robustness in the face of process changes. These characteristics make digital LDO more suitable for implementation using CNFET technology and effectively utilize the advantages of CNFET's high current density.

[0003] However, the current CNFET and SOC chips are mostly interconnected by wirebond and then sealed together, which leads to signal delay and increased power consumption between the two. The reliability of the package also makes the overall chip yield low, further increasing the production cost. In addition, there is currently no analog LDO or digital LDO based on CNFET, and the response speed and regulation accuracy of the current digital LDO are not high. It is difficult to respond quickly and accurately when the load current changes greatly, and it is impossible to effectively maintain the stability of the output voltage. It is urgent to develop a high-speed digital LDO structure based on CNFET. Summary of the invention

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: A high-speed digital low-dropout linear regulator power chip based on CNFET, comprising a CNFET power management chip layer and a silicon-based SOC, wherein the CNFET power management chip layer is grown on the silicon-based SOC, and more than one digital LDO is arranged on the CNFET power management chip layer, wherein the input end of each digital LDO is connected to an external power supply end, and the output end of each digital LDO is connected to the silicon-based SOC to supply power to the silicon-based SOC, and the digital LDO comprises: a comparator, a coarse adjustment unit, a fine adjustment unit, and a voltage output unit connected in sequence; The input end of the comparator is connected to the reference voltage end and the voltage output unit respectively, and the output end of the comparator is connected to the coarse adjustment unit and the fine adjustment unit respectively; the comparator is used to compare the reference voltage with the output voltage fed back by the voltage output unit and output a comparison signal; The coarse adjustment unit includes an adjustment controller and a coarse adjustment power transistor array which are connected to each other, and the adjustment controller controls the switching state of each transistor in the coarse adjustment power transistor array according to a comparison signal output by a comparator so as to match the current load current; The fine adjustment unit includes a shift register and a fine adjustment power transistor array connected to each other. The shift register performs a shift operation after the coarse adjustment unit is adjusted to control the switching state of each transistor in the fine adjustment power transistor array until the output voltage is adjusted to the reference voltage.

[0005] Furthermore, the input end of the coarse adjustment unit also includes a multi-phase comparator array, which is used to further compare the reference voltage with the output voltage fed back by the voltage output unit and output a corresponding comparison signal. The input end of the multi-phase comparator array is respectively connected to the reference voltage end and the voltage output unit, and the output end is respectively connected to the coarse adjustment unit and the fine adjustment unit; the multi-phase comparator array is also provided with a trigger end for controlling whether it works or not, and the trigger end is connected to the output end of the comparator.

[0006] Further, the regulation controller includes a first-stage regulation controller, a second-stage regulation controller, a stage conversion judgment module and a coarse adjustment control register; The first stage adjustment controller is used to preliminarily adjust the coarse adjustment control register according to the comparison signal, the input end of the first stage adjustment controller is connected to the output end of the comparator, and the output end of the first stage adjustment controller is respectively connected to the stage conversion judgment module and the coarse adjustment control register; The second stage regulation controller is used to perform secondary regulation on the coarse adjustment control register according to a comparison signal between a reference voltage and an output voltage fed back by a voltage output unit, the input end of the second stage regulation controller is respectively connected to the output end of the phase conversion judgment module and the multi-phase comparator array, and the output end of the second stage regulation controller is respectively connected to the coarse adjustment control register and the shift register of the fine adjustment unit; The coarse adjustment control register is connected to the coarse adjustment power transistor array and is used to control the switch state of the corresponding transistor in the coarse adjustment power transistor array; The phase conversion judgment module is used to control whether the second-stage regulating controller is started according to the output signal of the first-stage regulating controller.

[0007] Furthermore, the first stage regulation controller includes: A first judgment module, used for judging the value of the received comparison signal and outputting a judgment result; The first adjustment module is used to set the value of the coarse adjustment control register according to the judgment result of the judgment unit. If the judgment result is that the output voltage is higher than the reference voltage and the difference between the two is greater than a preset threshold, the values ​​of the coarse adjustment control register are all set to the first value so that all transistors in the coarse adjustment power transistor array are turned on; if the judgment result is that the output voltage is lower than the reference voltage and the difference between the two is greater than the preset threshold, all values ​​of the coarse adjustment control register are set to the second value so that all transistors in the coarse adjustment power transistor array are turned off.

[0008] Furthermore, the second stage regulation controller includes: A second judgment module is used to judge the value of the coarse adjustment control register; The second adjustment module is used to adjust the value of the coarse adjustment control register according to the judgment result of the second judgment module. If the judgment result is that the values ​​of the coarse adjustment control register have all been set to the first value, the value in the coarse adjustment control register is adjusted to adjust so that part of the transistors in the coarse adjustment power transistor array are turned off, and the number of transistors currently turned on matches the current load current; if the judgment result is that the values ​​of the coarse adjustment control register have all been set to the second value, the value in the coarse adjustment control register is adjusted to adjust so that part of the transistors in the coarse adjustment power transistor array are turned on, and the number of transistors currently turned on matches the current load current.

[0009] Furthermore, the first-stage regulation controller also includes a fine-tuning locking module and a fine-tuning unlocking module, wherein the fine-tuning locking module is used to output a fine-tuning locking signal so that the shift register of the fine-tuning unit is locked when the first-stage regulation controller performs preliminary adjustment on the coarse-tuning control register according to the comparison signal; and the fine-tuning unlocking module is used to output a fine-tuning unlocking signal so that the shift register of the fine-tuning unit is unlocked after the second-stage regulation controller completes adjusting the value of the coarse-tuning control register according to the received comparison signal.

[0010] Furthermore, the coarse adjustment unit also includes a coarse adjustment code temporary storage unit and a coarse adjustment pulse generator, the input end of the coarse adjustment code temporary storage unit is connected to the coarse adjustment control register, the output end of the coarse adjustment code temporary storage unit is respectively connected to the second stage adjustment controller and the fine adjustment unit, and the coarse adjustment code temporary storage unit is used to save the value in the coarse adjustment control register; the input end of the coarse adjustment pulse generator is respectively connected to the output end of the first stage adjustment controller and the second stage adjustment controller, the output end of the coarse adjustment pulse generator is connected to the input end of the coarse adjustment control register, and the coarse adjustment pulse generator is used to perform pulse conversion on the signals output by the first stage adjustment controller and the second stage adjustment controller.

[0011] Furthermore, the fine adjustment unit also includes a clock frequency adjustment module and an adjustment end judgment module. The clock frequency adjustment module is connected to the output end of the comparator, the output end of the multi-phase comparator array of the coarse adjustment unit, the shift register, the adjustment end judgment module and the coarse adjustment code temporary storage unit of the coarse adjustment unit. The clock frequency adjustment module is used to divide the clock signal using different division ratios according to the output signals of the coarse adjustment code temporary storage unit and the comparator. The adjustment end judgment module is used to judge whether the output signal of the shift register changes, and if it no longer changes, outputs an adjustment end signal.

[0012] Furthermore, the digital LDO also includes a reset end, which is respectively connected to the first stage adjustment controller of the coarse adjustment unit, the second stage adjustment controller of the coarse adjustment unit, the multi-phase comparator array of the coarse adjustment unit, and the input end of the coarse adjustment code temporary storage unit of the coarse adjustment unit. The reset end signal is generated by the adjustment end judgment module of the fine adjustment unit, and is used to enable the corresponding module that receives the reset end signal to reset the output signal.

[0013] Furthermore, the high-speed digital low-voltage difference linear regulator power chip also includes an upper oxide layer and a lower oxide layer respectively arranged on the upper and lower sides of the CNFET power management chip layer, the silicon-based SOC and the CNFET power management chip layer are isolated by the lower oxide layer, and the lower oxide layer is provided with a conductive member passing through the lower oxide layer at the power supply end position corresponding to the silicon-based SOC so that the power supply end is electrically connected to the LDO power chip, and the upper oxide layer is provided with a plurality of metal areas distributed around the edge, and the signal end of the silicon-based SOC is electrically connected to the metal area through the conductive member penetrating the upper oxide layer, the CNFET power management chip layer and the lower oxide layer.

[0014] Compared with the prior art, the advantages of the present invention are: By growing the CNFET power management chip layer above the silicon-based SOC, the present invention can effectively utilize the vertical space, reduce the total physical path for connecting the two, reduce the overall area of ​​the chip, and achieve higher integration; at the same time, by adopting a combination of a coarse adjustment unit and a fine adjustment unit to achieve output voltage control and regulation, the coarse adjustment unit first controls the coarse adjustment power transistor array, which can achieve rapid response to load mutations, significantly improve transient response speed, and avoid large voltage fluctuations, and then the fine adjustment unit controls the fine adjustment power transistor array to fine-tune the output voltage, which can reduce output voltage ripple and achieve higher output voltage accuracy. While taking into account both response speed and regulation accuracy, it can still respond and adjust quickly and accurately when the load current changes greatly, effectively maintaining the stability of the output voltage, thereby achieving efficient and stable voltage regulation within a wide load range, better meeting application scenarios with high requirements for voltage stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Schematic diagram of the three-dimensional integration of the CNFET-based high-speed digital low-voltage dropout linear regulator power chip and the silicon-based SOC chip of this embodiment.

[0016] Figure 2 It is a cross-sectional view of the three-dimensional integration of the CNFET-based high-speed digital low-voltage dropout linear regulator power chip and the silicon-based SOC chip of this embodiment.

[0017] Figure 3 Schematic diagram of the structure of a single digital LDO in the CNFET-based high-speed digital low-dropout linear regulator power supply chip of this embodiment. DETAILED DESCRIPTION

[0018] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0019] like Figure 1~Figure 3 As shown, the CNFET-based high-speed digital low-dropout linear regulator power chip of this embodiment includes a CNFET power management chip layer and a silicon-based SOC, the CNFET power management chip layer is grown on the silicon-based SOC, and more than one digital LDO is arranged on the CNFET power management chip layer, the input end of each digital LDO is connected to the external power supply end, and the output end of each digital LDO is connected to the silicon-based SOC to power the silicon-based SOC, wherein the digital LDO includes: a comparator, a coarse adjustment unit, a fine adjustment unit, and a voltage output unit connected in sequence; The input end of the comparator is connected to the reference voltage end and the voltage output unit respectively, and the output end of the comparator is connected to the coarse adjustment unit and the fine adjustment unit respectively; the comparator is used to compare the reference voltage with the output voltage fed back by the voltage output unit and output a comparison signal; The coarse adjustment unit includes an adjustment controller and a coarse adjustment power transistor array which are connected to each other. The adjustment controller controls the switching state of each transistor in the coarse adjustment power transistor array according to the comparison signal output by the comparator so as to match the current load current. The fine adjustment unit includes a shift register and a fine adjustment power transistor array connected to each other. After the coarse adjustment unit is adjusted, the shift register performs a shift operation to control the switching state of each transistor in the fine adjustment power transistor array until the output voltage is adjusted to the reference voltage.

[0020] In this embodiment, by growing the CNFET power management chip layer above the silicon-based SOC, the vertical space can be effectively utilized, the total physical path for connecting the two can be reduced, the overall area of ​​the chip can be reduced, and a higher degree of integration can be achieved; at the same time, the output voltage control and adjustment is achieved by adopting a combination of a coarse adjustment unit and a fine adjustment unit. The coarse adjustment unit first controls the coarse adjustment power transistor array, which can achieve a rapid response to sudden load changes, significantly improve the transient response speed, and avoid large voltage fluctuations. The fine adjustment unit then controls the fine adjustment power transistor array to fine-tune the output voltage, which can reduce the output voltage ripple and achieve higher output voltage accuracy. It can take into account both the response speed and the adjustment accuracy, so that it can still respond and adjust quickly and accurately when the load current changes greatly, and effectively maintain the stability of the output voltage, thereby achieving efficient and stable voltage regulation within a wide load range.

[0021] In this embodiment, the input end of the coarse adjustment unit also includes a multi-phase comparator array, which is used to further compare the reference voltage with the output voltage fed back by the voltage output unit and output a corresponding comparison signal. The input end of the multi-phase comparator array is respectively connected to the reference voltage end and the voltage output unit, and the output end is respectively connected to the coarse adjustment unit and the fine adjustment unit; the multi-phase comparator array is also provided with a trigger end for controlling whether it works or not, and the trigger end is connected to the output end of the comparator.

[0022] It can be understood that all digital LDOs in the power chip based on CNFET in this embodiment can preferably be implemented by a high-speed digital LDO structure based on a multi-phase comparator array. Since the high-speed digital LDO structure based on the multi-phase comparator array is mainly implemented by asynchronous and synchronous hybrid control, all digital LDOs will carry out regulation work at the same time, avoiding the situation where a single digital LDO works while other digital LDOs are idle, giving full play to the advantages of simultaneous regulation of multiple digital LDOs, and being able to solve the problem of local overheating when the current of a single digital LDO is too large, and improving the output current and regulation speed of the digital LDO power chip. In addition, the multi-phase comparator array compares the input voltage one by one according to the delay sequence through multiple comparators, and its output can more accurately reflect the change of the output voltage relative to the reference voltage. And the multi-phase comparator array is controlled by a trigger signal, there is no dynamic power consumption caused by the clock signal, and its operating frequency is not limited by the operating frequency of the comparator itself. Compared with the comparator controlled by the clock signal, it has a higher operating speed and lower power consumption.

[0023] In this embodiment, the regulation controller includes a first-stage regulation controller, a second-stage regulation controller, a stage conversion judgment module, and a coarse adjustment control register, wherein: The first stage adjustment controller is used to perform preliminary adjustment on the coarse adjustment control register according to the comparison signal, the input end of the first stage adjustment controller is connected to the output end of the comparator, and the output end of the first stage adjustment controller is respectively connected to the stage conversion judgment module and the coarse adjustment control register; The second stage regulation controller is used to perform secondary regulation on the coarse adjustment control register according to a comparison signal between the reference voltage and the output voltage fed back by the voltage output unit, the input end of the second stage regulation controller is respectively connected to the output end of the phase conversion judgment module and the multi-phase comparator array, and the output end of the second stage regulation controller is respectively connected to the coarse adjustment control register and the shift register of the fine adjustment unit; The coarse adjustment control register is connected to the coarse adjustment power transistor array and is used to control the switch state of the corresponding transistor in the coarse adjustment power transistor array; The phase conversion judgment module is used to control whether the second-stage regulating controller is started according to the output signal of the first-stage regulating controller.

[0024] In this embodiment, the first stage regulation controller includes: A first judgment module, used for judging the value of the received comparison signal and outputting a judgment result; The first adjustment module is used to set the value of the coarse adjustment control register according to the judgment result of the judgment unit. If the judgment result is that the output voltage is higher than the reference voltage and the difference between the two is greater than a preset threshold, the values ​​of the coarse adjustment control register are all set to the first value (for example, specifically set to 0) so that all transistors in the coarse adjustment power transistor array are turned on; if the judgment result is that the output voltage is lower than the reference voltage and the difference between the two is greater than the preset threshold, all values ​​of the coarse adjustment control register are set to the second value (for example, specifically set to 1) so that all transistors in the coarse adjustment power transistor array are turned off.

[0025] In this embodiment, the second stage regulation controller includes: A second judgment module is used to judge the value of the coarse adjustment control register; The second adjustment module is used to adjust the value of the coarse adjustment control register according to the judgment result of the second judgment module. If the judgment result is that the values ​​of the coarse adjustment control register have all been set to the first value, the value in the coarse adjustment control register is adjusted to adjust so that part of the transistors in the coarse adjustment power transistor array are turned off, and the number of transistors currently turned on matches the current load current; if the judgment result is that the values ​​of the coarse adjustment control register have all been set to the second value, the value in the coarse adjustment control register is adjusted to adjust so that part of the transistors in the coarse adjustment power transistor array are turned on, and the number of transistors currently turned on matches the current load current.

[0026] It can be understood that the first-stage regulation controller sets the value of the coarse adjustment control register by comparing the signal, so that the coarse adjustment power transistor array is in a fully on or fully off state, and can quickly adjust the output current to reduce the voltage deviation when the output voltage has a significant overshoot or undershoot; the second-stage regulation controller determines the upper and lower deviations between the adjusted voltage and the reference voltage based on the multi-phase comparator array, and can correct the value of the coarse adjustment control register, so that the number of coarse adjustment power transistors controlled by the coarse adjustment control register that are turned on matches the current load current, thereby reducing circuit oscillation or instability caused by voltage fluctuations.

[0027] In this embodiment, the first-stage adjustment controller also includes a fine adjustment locking module and a fine adjustment unlocking module. The fine adjustment locking module is used to output a fine adjustment locking signal to lock the shift register of the fine adjustment unit when the first-stage adjustment controller performs preliminary adjustment on the coarse adjustment control register according to the comparison signal; the fine adjustment unlocking module is used to output a fine adjustment unlocking signal to unlock the shift register of the fine adjustment unit after the second-stage adjustment controller completes adjusting the value of the coarse adjustment control register according to the received comparison signal.

[0028] It can be understood that locking the shift register of the fine-tuning unit when the coarse-tuning unit starts the coarse-tuning stage can avoid control logic competition (such as overshoot oscillation) caused by the simultaneous operation of the coarse-tuning unit and the fine-tuning unit, and prevent additional losses caused by redundant adjustments when the coarse-tuning is not completed; the fine-tuning unit only starts adjustment after the coarse-tuning unit is completed, ensuring strict timing of the two-stage adjustment, reducing multi-loop coupling interference, and improving adjustment efficiency.

[0029] In this embodiment, the coarse adjustment unit also includes a coarse adjustment code temporary storage unit and a coarse adjustment pulse generator. The input end of the coarse adjustment code temporary storage unit is connected to the coarse adjustment control register, and the output end of the coarse adjustment code temporary storage unit is respectively connected to the second stage adjustment controller and the fine adjustment unit. The coarse adjustment code temporary storage unit is used to save the value in the coarse adjustment control register; the input end of the coarse adjustment pulse generator is respectively connected to the output end of the first stage adjustment controller and the second stage adjustment controller, and the output end of the coarse adjustment pulse generator is connected to the input end of the coarse adjustment control register. The coarse adjustment pulse generator is used to convert the signals output by the first stage adjustment controller and the second stage adjustment controller into pulses. Specifically, Figure 3 As shown, the st1 and st2 signals received by the input end of the coarse adjustment pulse generator are formally a rising edge, specifically, the signal changes from 0 to 1, and the function of the coarse adjustment pulse generator is to convert the rising edge into a short pulse, specifically, the signal changes from 0 to 1, and then changes from 1 to 0 after a short period of time, and then performs the corresponding output.

[0030] In this embodiment, the fine adjustment unit also includes a clock frequency adjustment module and an adjustment end judgment module. The clock frequency adjustment module is connected to the output end of the comparator, the output end of the multi-phase comparator array of the coarse adjustment unit, the shift register, the adjustment end judgment module and the coarse adjustment code temporary storage unit of the coarse adjustment unit. The clock frequency adjustment module is used to divide the clock signal using different division ratios according to the output signals of the coarse adjustment code temporary storage unit and the comparator. The adjustment end judgment module is used to judge whether the output signal of the shift register changes, and if it no longer changes, it outputs an adjustment end signal.

[0031] Specifically, the function of the clock frequency adjustment module is to ensure that the system is in a stable state under different load conditions. In order to ensure system stability, the digital LDO needs to work at different operating frequencies under different load conditions. The clock frequency adjustment module will divide the clock signal using different frequency division ratios according to the output of the coarse tuning code temporary storage unit and the comparator, so that the digital LDO can work at a clock frequency that can ensure system stability. The function of the adjustment end judgment module is to output the tune_end signal according to the output of the shift register. The specific working principle is that when the output of the shift register no longer changes, the tune_end signal is set to a high level.

[0032] In this embodiment, the digital LDO also includes a reset end, which is respectively connected to the first stage adjustment controller of the coarse adjustment unit, the second stage adjustment controller of the coarse adjustment unit, the multi-phase comparator array of the coarse adjustment unit, and the input end of the coarse adjustment code temporary storage unit of the coarse adjustment unit. The reset end signal is generated by the adjustment end judgment module of the fine adjustment unit, and is used to enable the corresponding module that receives the reset end signal to reset the output signal.

[0033] Specifically, Figure 3 As shown, the reset output signal is a tune_end signal, indicating that the entire system has completed a round of adjustment. The tune_end signal is used to reset the controller and memory in the system. For example, the first-stage adjustment controller and the second-stage adjustment controller complete the reset of the output signal under the control of the tune_end signal; the coarse adjustment code temporary storage unit completes the reset of the output signal under the control of the tune_end signal; and the multi-phase comparator array completes the reset of the output signal under the control of the tune_end signal.

[0034] In this embodiment, Figure 1 and Figure 2As shown, the high-speed digital low-voltage difference linear regulator power chip also includes an upper oxide layer and a lower oxide layer respectively arranged on the upper and lower sides of the CNFET power management chip layer, the silicon-based SOC and the CNFET power management chip layer are isolated by the lower oxide layer, and the lower oxide layer is provided with a conductive member passing through the lower oxide layer at the power supply end position corresponding to the silicon-based SOC so that the power supply end is electrically connected to the LDO power chip, and a plurality of metal areas distributed around the edge are provided on the upper oxide layer, and the signal end of the silicon-based SOC is electrically connected to the metal area through the conductive member penetrating the upper oxide layer, the CNFET power management chip layer and the lower oxide layer.

[0035] In a specific application embodiment, the CNFET power management chip can be grown on top of the silicon-based SOC, and the two are connected by SiO 2 The power input of the CNFET power management chip is at the top of the entire three-dimensional integrated circuit structure. Figure 2 The power supply of silicon-based SOC ( Figure 2 The power supply of the silicon-based SOC is electrically connected to the PAD on the oxide layer through the above-mentioned multi-layer metal connection. The input end of each digital LDO in the CNFET grown on the silicon-based SOC is connected to the external power PAD (that is, the metal area), and the output end can be directly connected to the power pin of the silicon-based SOC through a metal through-hole to power the SOC. The signal line in the SOC ( Figure 2 The signal in the circuit directly passes through the CNFET layer through the through hole and is directly connected to the PAD. This avoids the problem of separate packaging of the power management chip and the silicon-based SOC, reduces the IR drop (voltage drop) between the two chips, and is conducive to improving the efficiency of the power management chip. The CNFET power management chip is integrated with a large-scale SOC through three-dimensional integration technology, which can reduce the SOC area and improve the yield of the SOC. The high-speed adjustment capability and high current density of the CNFET power management chip are used to provide the SOC with efficient power management functions, thereby improving the power-on speed and power stability of the SOC.

[0036] In a specific application embodiment, Figure 3 Take the following as an example to illustrate the working process of the high-speed digital low-voltage dropout linear regulator power supply chip based on CNFET in this embodiment ( Figure 3 The “\” on the arrow line indicates that the bit width of the signal line is greater than 1, that is, multiple signals are transmitted on this line at the same time): When the circuit is working normally, the output voltage V out With reference voltage V ref are equal in size. When the load changes, V out The voltage at the input terminal will also change, thus deviating from the reference voltage. At this time, the comparator will adjust the reference voltage V ref and the voltage output unit feedback V fb , and when the difference between the two exceeds the preset threshold, an os or us signal is output. These two signals represent that the output voltage has fluctuated upward (os) or downward (us).

[0037] When the coarse adjustment unit detects that the comparator generates an os or us signal, the first-stage adjustment controller will set the value of the coarse adjustment control register to all 0s or all 1s, thereby turning off or on all transistors of the coarse adjustment power transistor array (for example, after the coarse adjustment unit receives the os signal, the coarse adjustment power transistor array will be completely turned off, and when it receives the us signal, the coarse adjustment power transistor array will be completely turned on).

[0038] The first-stage regulation controller generates a fine-tuning lock signal while controlling the change of the coarse-tuning control register, locking the shift register (specifically a 64-bit shift register) in the fine-tuning unit, making it impossible to perform shift operations. In addition, after the coarse-tuning unit detects that the comparator generates an os or us signal, the multi-phase comparator array will also start working at the same time, comparing the reference voltage with the output voltage, and outputting a series of comparison results to the second-stage regulation controller. When all comparators in the comparator array have completed the comparison, it will output a comparison end signal AE. When both the st1 and AE signals are valid, the second-stage regulation controller will start working. Among them, the st1 signal indicates that the first-stage regulation controller has completed the output of the control signal, and the second-stage regulation controller can start working.

[0039] The second-stage regulation controller corrects the value of the coarse adjustment control register again according to the comparison result of the multi-phase comparator array to ensure that the number of coarse adjustment power transistors controlled by the coarse adjustment control register matches the current load current. The specific process of the second-stage regulation controller is as follows: the first step is to receive the output result of the multi-phase comparator array, and the output result of the multi-phase comparator array will increase or decrease accordingly with the change of the load current; the second step is to call back the value of the coarse adjustment control register according to the content stored in the coarse adjustment code temporary storage unit (that is, the value in the coarse adjustment control register) and the output result of the multi-phase comparator array. For example, if the first-stage regulation controller previously sets the value of the coarse adjustment control register to all 0, the second-stage regulation controller will increase the value of the coarse adjustment control register from 0 to a part, and if the first-stage regulation controller previously sets the value of the coarse adjustment control register to all 1, the second-stage regulation controller will reduce the value of the coarse adjustment control register from all 1 to a part, so that the number of coarse adjustment power transistors turned on roughly matches the current load current.

[0040] After the second stage regulation controller is finished, the st2 signal will become high level, indicating that the second stage regulation controller is finished. At this time, the second stage regulation controller outputs the fine adjustment unlock signal, so that the shift register in the fine adjustment unit can start working. The shift register will shift according to the output of the comparator. When the comparator detects that the digital LDO output voltage is lower than the reference voltage, the value of the shift register will increase by 1 at the rising edge of each clock signal; when the comparator detects that the digital LDO output voltage is higher than the reference voltage, the value of the shift register will decrease by 1 at the rising edge of each clock signal. Through the above adjustment method, the output voltage can be accurately and quickly restored to the value before the load current changes, thereby improving the power supply stability of the SOC.

[0041] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A high-speed digital low-dropout linear regulator power supply chip based on CNFET, characterized in that: It includes a CNFET power management chip layer and a silicon-based SOC, wherein the CNFET power management chip layer is grown on the silicon-based SOC, and more than one digital LDO is arranged on the CNFET power management chip layer, wherein the input end of each digital LDO is connected to an external power supply end, and the output end of each digital LDO is connected to the silicon-based SOC to power the silicon-based SOC, and the digital LDO includes: a comparator, a coarse adjustment unit, a fine adjustment unit, and a voltage output unit connected in sequence; The input end of the comparator is connected to the reference voltage end and the voltage output unit respectively, and the output end of the comparator is connected to the coarse adjustment unit and the fine adjustment unit respectively; the comparator is used to compare the reference voltage with the output voltage fed back by the voltage output unit and output a comparison signal; The coarse adjustment unit includes an adjustment controller and a coarse adjustment power transistor array which are connected to each other, and the adjustment controller controls the switching state of each transistor in the coarse adjustment power transistor array according to a comparison signal output by a comparator so as to match the current load current; The fine adjustment unit includes a shift register and a fine adjustment power transistor array connected to each other. The shift register performs a shift operation after the coarse adjustment unit is adjusted to control the switching state of each transistor in the fine adjustment power transistor array until the output voltage is adjusted to the reference voltage.

2. The CNFET-based high-speed digital low-dropout linear regulator power supply chip according to claim 1, characterized in that: The input end of the coarse adjustment unit also includes a multi-phase comparator array, which is used to further compare the reference voltage with the output voltage fed back by the voltage output unit and output a corresponding comparison signal. The input end of the multi-phase comparator array is respectively connected to the reference voltage end and the voltage output unit, and the output end is respectively connected to the coarse adjustment unit and the fine adjustment unit; the multi-phase comparator array is also provided with a trigger end for controlling whether it works or not, and the trigger end is connected to the output end of the comparator.

3. The CNFET-based high-speed digital low-dropout linear regulator power supply chip according to claim 2, characterized in that: The regulation controller includes a first-stage regulation controller, a second-stage regulation controller, a stage conversion judgment module and a coarse adjustment control register; The first stage adjustment controller is used to preliminarily adjust the coarse adjustment control register according to the comparison signal, the input end of the first stage adjustment controller is connected to the output end of the comparator, and the output end of the first stage adjustment controller is respectively connected to the stage conversion judgment module and the coarse adjustment control register; The second stage regulation controller is used to perform secondary regulation on the coarse adjustment control register according to a comparison signal between a reference voltage and an output voltage fed back by a voltage output unit, the input end of the second stage regulation controller is respectively connected to the output end of the phase conversion judgment module and the multi-phase comparator array, and the output end of the second stage regulation controller is respectively connected to the coarse adjustment control register and the shift register of the fine adjustment unit; The coarse adjustment control register is connected to the coarse adjustment power transistor array and is used to control the switch state of the corresponding transistor in the coarse adjustment power transistor array; The phase conversion judgment module is used to control whether the second-stage regulating controller is started according to the output signal of the first-stage regulating controller.

4. The CNFET-based high-speed digital low-dropout linear regulator power supply chip according to claim 3, characterized in that: The first stage regulation controller comprises: A first judgment module, used for judging the value of the received comparison signal and outputting a judgment result; The first adjustment module is used to set the value of the coarse adjustment control register according to the judgment result of the judgment unit. If the judgment result is that the output voltage is higher than the reference voltage and the difference between the two is greater than a preset threshold, the values ​​of the coarse adjustment control register are all set to the first value so that all transistors in the coarse adjustment power transistor array are turned on; if the judgment result is that the output voltage is lower than the reference voltage and the difference between the two is greater than the preset threshold, all values ​​of the coarse adjustment control register are set to the second value so that all transistors in the coarse adjustment power transistor array are turned off.

5. The CNFET-based high-speed digital low-dropout linear regulator power supply chip according to claim 3, characterized in that: The second stage regulation controller comprises: A second judgment module is used to judge the value of the coarse adjustment control register; The second adjustment module is used to adjust the value of the coarse adjustment control register according to the judgment result of the second judgment module. If the judgment result is that the values ​​of the coarse adjustment control register have all been set to the first value, the value in the coarse adjustment control register is adjusted to adjust so that part of the transistors in the coarse adjustment power transistor array are turned off, and the number of transistors currently turned on matches the current load current; if the judgment result is that the values ​​of the coarse adjustment control register have all been set to the second value, the value in the coarse adjustment control register is adjusted to adjust so that part of the transistors in the coarse adjustment power transistor array are turned on, and the number of transistors currently turned on matches the current load current.

6. The CNFET-based high-speed digital low-dropout linear regulator power supply chip according to claim 3, characterized in that: The first-stage regulation controller also includes a fine-tuning locking module and a fine-tuning unlocking module. The fine-tuning locking module is used to output a fine-tuning locking signal to lock the shift register of the fine-tuning unit when the first-stage regulation controller performs preliminary adjustment on the coarse-tuning control register according to the comparison signal; the fine-tuning unlocking module is used to output a fine-tuning unlocking signal to unlock the shift register of the fine-tuning unit after the second-stage regulation controller completes adjusting the value of the coarse-tuning control register according to the received comparison signal.

7. The CNFET-based high-speed digital low-dropout linear regulator power supply chip according to claim 3, characterized in that: The coarse adjustment unit also includes a coarse adjustment code temporary storage unit and a coarse adjustment pulse generator. The input end of the coarse adjustment code temporary storage unit is connected to the coarse adjustment control register, and the output end of the coarse adjustment code temporary storage unit is respectively connected to the second stage adjustment controller and the fine adjustment unit, and the coarse adjustment code temporary storage unit is used to save the value in the coarse adjustment control register; the input end of the coarse adjustment pulse generator is respectively connected to the output end of the first stage adjustment controller and the second stage adjustment controller, and the output end of the coarse adjustment pulse generator is connected to the input end of the coarse adjustment control register, and the coarse adjustment pulse generator is used to perform pulse conversion on the signals output by the first stage adjustment controller and the second stage adjustment controller.

8. The CNFET-based high-speed digital low-dropout linear regulator power supply chip according to any one of claims 1 to 7, characterized in that: The fine adjustment unit also includes a clock frequency adjustment module and an adjustment end judgment module. The clock frequency adjustment module is respectively connected to the output end of the comparator, the output end of the multi-phase comparator array of the coarse adjustment unit, the shift register, the adjustment end judgment module and the coarse adjustment code temporary storage unit of the coarse adjustment unit. The clock frequency adjustment module is used to divide the clock signal using different division ratios according to the output signals of the coarse adjustment code temporary storage unit and the comparator. The adjustment end judgment module is used to judge whether the output signal of the shift register changes, and output an adjustment end signal if it no longer changes.

9. The CNFET-based high-speed digital low-dropout linear regulator power supply chip according to any one of claims 1 to 7, characterized in that: The digital LDO also includes a reset end, which is respectively connected to the first stage adjustment controller of the coarse adjustment unit, the second stage adjustment controller of the coarse adjustment unit, the multi-phase comparator array of the coarse adjustment unit, and the input end of the coarse adjustment code temporary storage unit of the coarse adjustment unit. The reset end signal is generated by the adjustment end judgment module of the fine adjustment unit, and is used to enable the corresponding module that receives the reset end signal to reset the output signal.

10. The CNFET-based high-speed digital low-dropout linear regulator power supply chip according to claim 1, characterized in that: The high-speed digital low-voltage difference linear regulator power chip also includes an upper oxide layer and a lower oxide layer respectively arranged on the upper and lower sides of the CNFET power management chip layer; the silicon-based SOC and the CNFET power management chip layer are isolated by the lower oxide layer, and the lower oxide layer is provided with a conductive member passing through the lower oxide layer at the power supply end position corresponding to the silicon-based SOC so that the power supply end is electrically connected to the LDO power chip, and the upper oxide layer is provided with a plurality of metal areas distributed around the edge, and the signal end of the silicon-based SOC is connected to the metal area through a conductive member penetrating the upper oxide layer, the CNFET power management chip layer and the lower oxide layer.

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