Integrated circuit
By setting an annular area on the outer edge of the transistor array, the problem of insufficient voltage withstand the integrated circuit is solved, and a high voltage withstand and low-cost circuit design is realized, which improves the reliability and voltage withstandability of the circuit.
Patent Information
- Application Number
- CN202410164202.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-27
- Filing Date
- 2024-02-05
- Publication Date
- 2025-07-01
AI Technical Summary
The existing integrated circuits have insufficient voltage withstand capacity in high voltage applications, resulting in insufficient electrical interconnection or voltage withstand capacity between MOSFETs, reducing component performance and reliability, and increasing the number of MOSFETs to increase manufacturing costs.
A number of annular regions are provided at the outer edge of the transistor array. The annular region has a specific doping area ratio, and the doping area on the inner side is greater than the outer side, forming a protective ring to disperse the burst current and increase the withstand voltage.
The protection ring disperses the burst current, avoids circuit damage, and improves the transistor array withstand voltage to more than 1500 volts, reducing manufacturing costs.
Smart Images
Figure CN120239316A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to an integrated circuit. Specifically, the present invention relates to an integrated circuit having a plurality of guard rings disposed at the outer edge of a transistor array. Background Art
[0002] In the process of manufacturing a metal oxide semiconductor field effect transistor (MOSFET) array, a common problem is insufficient breakdown voltage, especially in high voltage applications. This problem may cause defects between the electrical interconnections or breakdown voltages of MOSFETs, and reduce the performance and reliability of the components.
[0003] To solve the problem of insufficient breakdown voltage, currently, most methods are to increase the number of MOSFETs in the MOSFET array to achieve the breakdown voltage required for the overall circuit. However, increasing the number of MOSFETs also significantly increases the manufacturing cost of the overall circuit.
[0004] In view of this, the present invention proposes an integrated circuit design with low manufacturing cost and capable of significantly improving the breakdown voltage of the circuit. Summary of the Invention
[0005] The object of the present invention is to provide a high breakdown voltage integrated circuit, which forms a plurality of annular regions at the outer edge of a transistor array, and each annular region has a certain proportion of doped area. When a surge occurs during the operation of the transistor array in the circuit, the surge current can be drained outwards through the annular regions. In this way, the transistor array can avoid being damaged by the large current and large voltage of the surge, and the breakdown voltage of the transistor array in the circuit can be significantly increased to more than 1500 volts.
[0006] To achieve the above object, the present invention discloses an integrated circuit, which includes a transistor array and a guard ring. The guard ring is formed at the outer edge (periphery) of the transistor array. The guard ring includes a plurality of annular regions, each of the annular regions has a doped area, and the doped area of a relatively inner annular region of the plurality of annular regions is larger than the doped area of a relatively outer annular region of the plurality of annular regions.
[0007] In one embodiment, the doped area of the innermost annular region of the annular regions is the total area of the innermost annular region.
[0008] In one embodiment, the ratio of the side length of the transistor array to the total width of the annular regions is less than 10.
[0009] In one embodiment, the ratio of the side length to the total width is 5:3.
[0010] In one embodiment, the plurality of annular regions are divided into an inner part and an outer part, and the width of the inner part is greater than 100 micrometers (μm).
[0011] In one embodiment, the undoped area of the inner part of the plurality of annular regions and the doped area of the outer part of the plurality of annular regions are composed of a plurality of discrete parts, and each of the discrete parts is one of a rectangle, a circle, and a polygon.
[0012] In one embodiment, when the number of the plurality of annular regions is one, the breakdown voltage of the transistor array is increased by 20% to 50%.
[0013] In one embodiment, the breakdown voltage of the transistor array increases as the total width increases.
[0014] In one embodiment, the doped area of the annular region is annular.
[0015] In one embodiment, when the number of the plurality of annular regions is one, the breakdown voltage of the transistor array is increased by 20% to 50%.
[0016] In one embodiment, the transistor array is composed of a plurality of Metal-Oxide-Semiconductor Field-Effect Transistors.
[0017] After referring to the accompanying drawings and the embodiments described hereinafter, those with ordinary technical knowledge in this technical field can understand other objectives of the present invention, as well as the technical means and embodiments of the present invention. Description of the Drawings
[0018] Figure 1 It is a schematic diagram of the integrated circuit of the present invention;
[0019] Figure 2 It is a partial cross-sectional view of the integrated circuit of the present invention;
[0020] Figure 3 It is a partial schematic diagram of the protection ring of the present invention;
[0021] Figure 4 It is a partial schematic diagram of the protection ring of the present invention;
[0022] Figure 5 It is a partial schematic diagram of the protection ring of the present invention; and
[0023] Figure 6 It is a schematic diagram of the integrated circuit of the present invention.
[0024] Description of the Reference Numerals
[0025] 1000: Integrated circuit
[0026] 1100: Transistor array
[0027] 1110: Outer edge
[0028] 1300: Protection ring
[0029] 1310: Annular region
[0030] L: Side length
[0031] W: Total width. Detailed implementation manners
[0032] The following will explain the content of the present invention through embodiments. The embodiments of the present invention are not intended to limit the present invention to be implemented in any specific environment, application, or special manner as described in the embodiments. Therefore, the description of the embodiments is only for the purpose of explaining the present invention, rather than limiting the present invention. It should be noted that in the following embodiments and drawings, elements not directly related to the present invention have been omitted and not shown, and the dimensional relationships between the elements in the drawings are only for easy understanding and are not intended to limit the actual ratio.
[0033] The first embodiment of the present invention is as Figures 1 to 5 shown. Figure 1 A schematic diagram depicting the integrated circuit 1000 of the present invention. The integrated circuit 1000 includes a transistor array 1100 and a protection ring 1300. The transistor array 1100 is composed of multiple Metal-Oxide-Semiconductor Field-Effect Transistors.
[0034] Please refer to Figure 2 and Figure 3 , Figure 2 , which depicts a partial cross-sectional view of the integrated circuit of the present invention. Figure 3 A partial schematic diagram depicting the protection ring 1300 of the present invention. The protection ring 1300 is formed on the outer edge (periphery) 1110 of the transistor array 1100, which can greatly improve the breakdown voltage of the entire transistor array 1100.
[0035] Specifically, the protection ring 1300 includes multiple annular regions 1310. The multiple annular regions 1310 are divided into an inner part 1311 and an outer part 1313, and the width of the inner part is greater than 100 micrometers (μm). The ratio of the side length L of the transistor array 1100 to the total width W of the multiple annular regions 1310 is less than 10. The optimal ratio of the side length of the transistor array 1100 to the total width of the multiple annular regions 1310 is 5:3.
[0036] Each annular region 1310 has a doped area (such as Figures 3 to 5The middle gray part), the doping area of the inner annular regions of the plurality of annular regions 1310 is larger than the doping area of the outer annular regions of the plurality of annular regions.
[0037] The plurality of doping areas can be regarded as doping concentrations. Specifically, in the process of manufacturing a metal-oxide-semiconductor field-effect transistor, P-type ions, such as positively charged ions like boron ions, aluminum ions, gallium ions, indium ions, etc., are implanted into the N-type epitaxial layer to form a P-type doped region.
[0038] Each annular region 1310 has a P-type doped region with a different doping ratio. The inner part 1311 of the annular region 1310 is formed by first determining the ratio of the undoped area of each ring and then implanting P-type ions into the remaining parts of each ring in the inner part 1311. Conversely, for the outer part 1313 of the annular region 1310, after determining the ratio of the area to be doped, P-type ions are directly implanted into the part to be doped.
[0039] The undoped area of the inner part 1311 of the plurality of annular regions 1310 and the doping area of the outer part 1313 of the plurality of annular regions are composed of a plurality of discrete parts. Each discrete part is one of a rectangle, a circle, and a polygon, as Figures 3 to 5 shown.
[0040] In short, the inner part 1311 of the annular region 1310 determines the ratio of the undoped area and selects the positions of non-doping, while the outer part 1313 of the annular region 1310 determines the ratio of the area to be doped and selects the positions to be doped.
[0041] The doping area of the innermost annular region of the plurality of annular regions 1310 is the total area of the innermost annular region. In other words, the innermost annular region among the plurality of annular regions 1310 is connected to the transistor array 1100, and the doping area of the innermost annular region is 100%.
[0042] The breakdown voltage of the transistor array 1100 increases as the total width of the plurality of annular regions 1310 increases, and the total width of the plurality of annular regions 1310 increases as the number of annular regions 1310 increases. In addition, in this embodiment, when the number of the plurality of annular regions 1310 is one, the breakdown voltage of the transistor array 1100 can be increased by twenty to fifty percent.
[0043] When a surge current appears in the circuit using the transistor array 1100, it can drift outward through the P-type doped region, causing the surge current and heat energy to conduct in the outer direction. Therefore, the integrated circuit 1000 of the present invention can improve the immediate dispersion effect and heat dissipation effect on the surge current.
[0044] The second embodiment of the present invention is as follows Figure 6 as shown. The second embodiment is an extension of the first embodiment. Different from the first embodiment, the undoped area of the inner part 1311 and the doped area of the outer part 1313 are composed of discrete parts of arbitrary shapes. In this embodiment, the doped area of the annular region 1310 is annular. When the number of the plurality of annular regions is one, the breakdown voltage of the transistor array 1100 can be increased by 20% to 50%.
[0045] In summary, for the integrated circuit of the present invention, by providing a guard ring at the outer edge of the transistor array, the doped area and the undoped area of each ring-shaped region in the guard ring have a specific ratio, and the doped area of the annular region decreases outward. Therefore, when a surge appears in the integrated circuit, the surge current can be dispersed outward through the guard ring to avoid circuit damage, and at the same time, the breakdown voltage of the overall circuit can be increased.
[0046] The above embodiments are only used to illustrate the implementation manners of the present invention and to explain the technical features of the present invention, rather than to limit the protection scope of the present invention. Any change or equivalent arrangement that can be easily completed by those skilled in the art belongs to the scope claimed by the present invention, and the scope of the claimed rights of the present invention shall be subject to the claims.
Claims
1. An integrated circuit comprising: a transistor array; a guard ring formed at an outer edge of the transistor array; in, The guard ring includes a plurality of annular regions, each of which has a doping area, and the doping area of an inner annular region of the plurality of annular regions is greater than the doping area of an outer annular region of the plurality of annular regions.
2. The integrated circuit of claim 1, wherein: The doping area of the innermost annular region of the plurality of annular regions is the total area of the innermost annular region.
3. The integrated circuit of claim 1, wherein: A ratio of a side length of the transistor array to a total width of the plurality of annular regions is less than 10.
4. The integrated circuit of claim 3, wherein: The ratio of the side length to the total width is 5:
3.
5. The integrated circuit of claim 3, wherein: The plurality of annular regions are divided into an inner portion and an outer portion, and a width of the inner portion is greater than 100 micrometers.
6. The integrated circuit of claim 5, wherein: The undoped area of the inner part of the plurality of annular regions and the doped area of the outer part of the plurality of annular regions are composed of a plurality of discrete parts, and each of the discrete parts is one of a rectangle, a circle and a polygon.
7. The integrated circuit of claim 6, wherein: When the number of the plurality of annular regions is one, the withstand voltage of the transistor array is increased by 20% to 50%.
8. The integrated circuit of claim 3, wherein: The withstand voltage of the transistor array increases as the total width increases.
9. The integrated circuit of claim 1, wherein: The doping area of each of the annular regions is annular.
10. The integrated circuit of claim 9, wherein: When the number of the plurality of annular regions is one, the withstand voltage of the transistor array is increased by 20% to 50%.
11. The integrated circuit of claim 1, wherein: The transistor array is composed of a plurality of metal oxide semiconductor field effect transistors.