Array substrate, display panel and display apparatus

Abstract

An array substrate. The array substrate comprises: a plurality of sub-pixel regions, each sub-pixel region being provided with one pixel driving circuit, and each of the multiple pixel driving circuits comprising a plurality of first-type transistors and a plurality of second-type transistors. The array substrate comprises: a base substrate, a first active film layer provided on a side of the base substrate, and a second active film layer provided on the side of the first active film layer away from the base substrate. The first active film layer comprises active layer patterns of the plurality of first-type transistors, and the second active film layer comprises active layer patterns of the plurality of second-type transistors, the film layer patterns of the sub-pixel regions in adjacent rows being mirrored, and the film layer patterns of the sub-pixel regions in adjacent columns being mirrored. The array substrate further comprises: a plurality of direct-current signal lines, the pixel driving circuits of the two columns of sub-pixel regions adjacent to one direct-current signal line sharing the direct-current signal line, and the pixel driving circuits of the two rows of sub-pixel regions adjacent to one direct-current signal line sharing the direct-current signal line.

Description

Array substrate, display panel and display device

[0001] This application claims priority to Chinese patent application No. 202311853038.9 filed on December 28, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0003] At present, OLED (Organic Light-Emitting Diode) display devices are widely used due to their self-luminescence, fast response, wide viewing angle and ability to be manufactured on flexible substrates. OLED display devices include multiple sub-pixels, each of which includes a pixel driving circuit and a light-emitting device. The pixel driving circuit drives the light-emitting device to emit light, thereby achieving display. Summary of the Invention

[0004] In one aspect, an array substrate is provided, comprising: a plurality of sub-pixel regions, each of which is provided with a pixel driving circuit, the plurality of pixel driving circuits being arranged in multiple rows and columns, each of the plurality of pixel driving circuits including a plurality of first-type transistors and a plurality of second-type transistors. The array substrate comprises: a base substrate, a first active film layer disposed on one side of the base substrate, and a second active film layer disposed on a side of the first active film layer away from the base substrate, the first active film layer including an active layer pattern for the plurality of first-type transistors, and the second active film layer including an active layer pattern for the plurality of second-type transistors. Furthermore, the film layer patterns of the sub-pixel regions in adjacent rows are mirror images, and the film layer patterns of the sub-pixel regions in adjacent columns are mirror images. The array substrate further comprises: a plurality of DC signal lines, the pixel driving circuits of the sub-pixel regions in two columns adjacent to one of the plurality of DC signal lines sharing the DC signal line, and the pixel driving circuits of the sub-pixel regions in two rows adjacent to one of the plurality of DC signal lines sharing the DC signal line.

[0005] In some embodiments, the array substrate further comprises: a shielding layer disposed between the base substrate and the first active film layer, and a second gate metal layer disposed between the first active film layer and the second active film layer, wherein the shielding layer comprises a plurality of first voltage signal line first branches and a plurality of initialization signal line first branches extending along the column direction, and the second gate metal layer comprises a plurality of first voltage signal line second branches and a plurality of initialization signal line second branches extending along the row direction. Each of the plurality of first voltage signal line second branches is connected to the plurality of first voltage signal line first branches via a via; and each of the plurality of initialization signal line second branches is connected to the plurality of initialization signal line first branches via a via.

[0006] In some embodiments, the pixel driving circuits of the two columns of sub-pixel areas adjacent to the first branch of the first voltage signal line share the first branch of the first voltage signal line; the pixel driving circuits of the two rows of sub-pixel areas adjacent to the second branch of the first voltage signal line share the second branch of the first voltage signal line.

[0007] In some embodiments, the pixel driving circuits of the two columns of sub-pixel areas adjacent to the first branch of the initialization signal line share the first branch of the initialization signal line; the pixel driving circuits of the two rows of sub-pixel areas adjacent to the second branch of the initialization signal line share the second branch of the initialization signal line.

[0008] In some embodiments, in the sub-pixel area, the first type of transistor includes: a light-emitting control transistor and a second reset transistor; the active layer pattern of the light-emitting control transistor is connected to the second branch of the first voltage signal line; the active layer pattern of the second reset transistor is connected to the second branch of the initialization signal line.

[0009] In some embodiments, the first type of transistor further includes a driving transistor, and the active layer pattern of the light emission control transistor, the active layer pattern of the driving transistor, and the active layer pattern of the second reset transistor are connected in sequence.

[0010] In some embodiments, the pixel driving circuit further includes a capacitor; the second gate metal layer further includes a second plate pattern of the capacitor. The array substrate further includes: a first gate metal layer disposed between the first active film layer and the second gate metal layer, the first gate metal layer including: a first plate pattern of the capacitor. The array substrate further includes: a first source-drain metal layer disposed between the second gate metal layer and the second active film layer, the first source-drain metal layer including a first transfer pattern, the first transfer pattern being connected to the active layer pattern of the second reset transistor through a via, and simultaneously connected to the second plate pattern of the capacitor.

[0011] In some embodiments, the array substrate further comprises: a second source-drain metal layer disposed on a side of the second active film layer away from the base substrate; and a third source-drain metal layer disposed on a side of the second source-drain metal layer away from the base substrate, wherein the second source-drain metal layer comprises a third transfer pattern, the third source-drain metal layer comprises a fourth transfer pattern, and the second active film layer further comprises a second transfer pattern. The first transfer pattern, the second transfer pattern, the third transfer pattern, and the fourth transfer pattern are sequentially connected through vias.

[0012] In some embodiments, the first gate metal layer further includes: a light emitting control signal line and a reset signal line, the light emitting control signal line passes through the active layer pattern of the light emitting control transistor, and the reset signal line passes through the active layer pattern of the second reset transistor.

[0013] In some embodiments, the blocking layer also includes: a first shading pattern; the first shading pattern is connected to the first branch of the first voltage signal line, and the orthographic projection of the driving transistor on the substrate is located within the orthographic projection of the first shading pattern on the substrate; and / or, the blocking layer also includes: a second shading pattern, the second shading pattern is connected to the first branch of the first voltage signal line, and the orthographic projection of the second reset transistor on the substrate is located within the orthographic projection of the second shading pattern on the substrate.

[0014] In some embodiments, the array substrate further comprises: a second source-drain metal layer disposed on a side of the second active film layer away from the base substrate; and a third source-drain metal layer disposed on a side of the second source-drain metal layer away from the base substrate, wherein the second source-drain metal layer comprises a plurality of first branches of second voltage signal lines extending along the row direction, and the third source-drain metal layer comprises a plurality of second branches of second voltage signal lines extending along the column direction. Each first branch of the plurality of second voltage signal lines is connected to the plurality of second branches of the second voltage signal lines via a via.

[0015] In some embodiments, the pixel driving circuits of the two columns of sub-pixel areas adjacent to the first branch of the second voltage signal line share the first branch of the second voltage signal line; the pixel driving circuits of the two columns of sub-pixel areas adjacent to the second branch of the second voltage signal line share the second branch of the second voltage signal line.

[0016] In some embodiments, in the sub-pixel region, the second type of transistor includes: a first reset transistor, and an active layer pattern of the first reset transistor is connected to a first branch of the second voltage signal line.

[0017] In some embodiments, the second type of transistor further includes a write transistor, wherein an active layer pattern of the write transistor is connected to the active layer pattern of the first reset transistor.

[0018] In some embodiments, the pixel driving circuit further includes a capacitor; the array substrate further includes: a first gate metal layer disposed between the first active film layer and the second active film layer; and a first source-drain metal layer disposed between the first gate metal layer and the second active film layer. The first gate metal layer includes: a first plate pattern of the capacitor; the first source-drain metal layer includes a fifth switching pattern. The fifth switching pattern is connected to the first plate pattern via a via, and the fifth switching pattern is connected to the active layer pattern of the write transistor via a via, thereby connecting the first plate pattern to the active layer pattern of the write transistor.

[0019] In some embodiments, the second active film layer further includes a second transfer pattern, and the third source / drain metal layer includes a data signal line and a fourth transfer pattern. The data signal line is connected to the active layer pattern of the write transistor via a first node pattern, and the fourth transfer pattern is connected to the second transfer pattern via a second node pattern. Along the row direction, the ratio of the dimension between the first node pattern and the second node pattern to the dimension of the sub-pixel region film layer pattern is greater than or equal to 30%.

[0020] In some embodiments, the array substrate further includes: a third gate metal layer disposed between the first active film layer and the second active film layer, and a fourth gate metal layer disposed between the second active film layer and the second source / drain metal layer; wherein the third gate metal layer includes a first branch line of a first scan signal line and a first branch line of a second scan signal line, and the fourth gate metal layer includes a second branch line of a first scan signal line and a second branch line of a second scan signal line, the first branch line of the first scan signal line and the second branch line of the first scan signal line pass through the active layer pattern of the first reset transistor, and the first branch line of the second scan signal line and the second branch line of the second scan signal line pass through the active layer pattern of the write transistor. The first branch line of the first scan signal line and the second branch line of the first scan signal line are electrically connected; and the first branch line of the second scan signal line and the second branch line of the second scan signal line are electrically connected.

[0021] In some embodiments, the first active film layer is a low-temperature polysilicon layer, and the second active film layer is an oxide layer.

[0022] In some embodiments, the array substrate further includes: a first planar layer disposed between the first active film layer and the second active film layer, the material of the first planar layer including an organic material, and the thickness of the first planar layer ranging from 1.5 μm to 2 μm; or, the material of the first planar layer including an inorganic material, and the thickness of the first planar layer ranging from 1.2 μm to 1.5 μm.

[0023] In another aspect, a display panel is provided, comprising: an array substrate as described in any one of the above embodiments.

[0024] In another aspect, a display device is provided, comprising: the display panel according to any one of the above embodiments, and further comprising a driver chip configured to drive the display panel to display. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0026] FIG1 is a planar structural diagram of a display device according to some embodiments of the present disclosure;

[0027] FIG2 is a planar structural diagram of a display panel provided according to some embodiments of the present disclosure;

[0028] FIG3 is another planar structural diagram of a display panel provided according to some embodiments of the present disclosure;

[0029] FIG4 is a cross-sectional structural diagram of a display panel provided according to some embodiments of the present disclosure;

[0030] FIG5 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure;

[0031] FIG6 is a timing signal control diagram of a pixel driving circuit according to some embodiments of the present disclosure;

[0032] 7 is a structural diagram of a shielding layer, a first active film layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a third gate metal layer, a second active film layer, a fourth gate metal layer, a second source-drain metal layer, and a third source-drain metal layer after being stacked according to some embodiments of the present disclosure;

[0033] 8 is a structural diagram of a shielding layer, a first active film layer, a first gate metal layer, a second gate metal layer, and a first source / drain metal layer after being stacked according to some embodiments of the present disclosure;

[0034] FIG9 is a film structure diagram of a shielding layer provided according to some embodiments of the present disclosure;

[0035] FIG10 is a film layer structure diagram of a first active film layer provided according to some embodiments of the present disclosure;

[0036] FIG11 is a structural diagram of a first type of via provided according to some embodiments of the present disclosure;

[0037] FIG12 is a film layer structure diagram of a first gate metal layer provided according to some embodiments of the present disclosure;

[0038] FIG13 is a structural diagram of a second type of via provided according to some embodiments of the present disclosure;

[0039] FIG14 is a film layer structure diagram of a second gate metal layer provided according to some embodiments of the present disclosure;

[0040] FIG15 is a structural diagram of a third type of via and a fourth type of via provided according to some embodiments of the present disclosure;

[0041] FIG16 is a film structure diagram of a first source / drain metal layer provided according to some embodiments of the present disclosure;

[0042] 17 is a cross-sectional view of the structure of the shielding layer, the first active film layer, the first gate metal layer, the second gate metal layer, and the first source and drain metal layer after being superimposed as shown in FIG. 8 , taken along the CC cross-sectional line;

[0043] FIG18 is a structural diagram of a first source-drain metal layer, a third gate metal layer, a second active film layer, a fourth gate metal layer, and a second source-drain metal layer stacked according to some embodiments of the present disclosure;

[0044] FIG19 is a film layer structure diagram of a third gate metal layer provided according to some embodiments of the present disclosure;

[0045] FIG20 is a structural diagram of a fifth type of via provided according to some embodiments of the present disclosure;

[0046] FIG21 is a film layer structure diagram of a second active film layer provided according to some embodiments of the present disclosure;

[0047] FIG22 is a film layer structure diagram of a fourth gate metal layer provided according to some embodiments of the present disclosure;

[0048] FIG23 is a structural diagram of a sixth type of via provided according to some embodiments of the present disclosure;

[0049] FIG24 is a film structure diagram of a second source / drain metal layer provided according to some embodiments of the present disclosure;

[0050] FIG25 is a structural diagram of a second source-drain metal layer, a third source-drain metal layer, an anode layer, and a light-emitting layer after being stacked according to some embodiments of the present disclosure;

[0051] FIG26 is a structural diagram of a seventh type of via provided according to some embodiments of the present disclosure;

[0052] FIG27 is a film structure diagram of a third source / drain metal layer provided according to some embodiments of the present disclosure;

[0053] FIG28 is a structural diagram of an eighth type of via provided according to some embodiments of the present disclosure;

[0054] FIG29 is a film structure diagram of an anode layer provided according to some embodiments of the present disclosure;

[0055] FIG30 is a diagram showing the film structure of a light-emitting layer according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0056] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0057] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0058] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0059] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0060] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0061] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0062] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0063] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0064] As shown in FIG1 , some embodiments of the present disclosure provide a display device. The display device provided by the embodiments of the present disclosure can be any device that displays either motion (e.g., video) or fixed (e.g., still images) and whether text or images. More specifically, it is expected that the embodiments may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0065] Specifically, as shown in FIG1 , the embodiment of the present disclosure is exemplified by taking the display device 1000 as a mobile phone.

[0066] As shown in Figures 1 and 2, a display device 1000 includes a display panel 100. The display panel 100 includes a display area AA and a peripheral area BB located on at least one side of the display area AA. The display area AA is provided with a plurality of sub-pixels 21 and a plurality of signal lines. The plurality of sub-pixels 21 are arranged in the display area AA according to a specified rule. The area where each sub-pixel 21 is located is a sub-pixel area A1. The sub-pixel 21 is the smallest unit for displaying an image in the display panel 100. Each sub-pixel 21 can display a single color, such as red, green, or blue. By adjusting the brightness of different sub-pixels 21, color superposition can achieve the display of multiple colors. As shown in Figures 3 and 4, each sub-pixel 21 includes a light-emitting device OLED and a pixel driving circuit 200 for driving the light-emitting device OLED to emit light.

[0067] For example, as shown in FIG4 , taking the display panel 100 as an OLED (Organic Light-Emitting Diode) display panel as an example, the display panel 100 includes an array substrate 10, a light-emitting device layer 40, and an encapsulation layer, which are sequentially stacked. The array substrate 10 includes multiple transistors and capacitors included in the pixel driving circuit 200, and the light-emitting device layer 40 includes multiple light-emitting devices (OLEDs). The array substrate 10 includes a base substrate 101, multiple functional layers sequentially stacked on the base substrate 101, and insulating layers located between adjacent functional layers. The functional layers may include active film layers, gate metal layers, and source / drain metal layers. The active film layers, gate metal layers, and source / drain metal layers are used to form multiple pixel driving circuits 200 in the display panel 100. The multiple pixel driving circuits 200 may be formed in the display area AA of the display panel 100. The light-emitting devices OLED are disposed on a side of the pixel driving circuit 200 away from the base substrate 101.

[0068] The pixel driving circuit 200 includes a plurality of transistors, the active layers of the plurality of transistors are located in the active film layer, the active layer of each transistor includes a first polar region, a second polar region and a channel region for connecting the first polar region and the second polar region, and the gates of the plurality of transistors are located in the gate metal layer, wherein the gate metal layer includes, for example, a plurality of signal lines, and the portion of a signal line that passes through the active layer of a certain transistor can serve as the gate of the transistor, where "passing" refers to the portion where the orthographic projections of the two on the substrate 101 overlap. When manufacturing a transistor, an active film layer can be first formed on the substrate 101 to obtain the active layer of the transistor, and then a gate metal layer can be formed on the side of the active film layer away from the substrate 101. The position where the gate metal layer overlaps with the active film layer is the position where the gate metal layer "passes" through the active layer. For example, the gate of the transistor is arranged to overlap with the channel region of the transistor.

[0069] The pixel driving circuit 200 is mainly composed of transistors. Therefore, the size of the space occupied by the transistors can determine the size of the space occupied by the pixel driving circuit 200. For example, the space occupied by the transistors includes the lateral area size parallel to the plane of the substrate 101 and the longitudinal area size in the direction perpendicular to the plane of the substrate 101. The longitudinal area size is mainly related to the thickness of the film layer included in the array substrate 10. In this disclosure, the focus is on the lateral area size of the transistors and the pixel driving circuit 200 in the plane parallel to the substrate 101. The lateral area size is the area of ​​the positive projection of the transistor on the substrate 101. Hereinafter, the area of ​​the positive projection of the transistor on the substrate 101 will be collectively referred to as the area of ​​the transistor. The same applies to the area of ​​the pixel driving circuit 200. The area of ​​the active layer of the transistor included in the pixel driving circuit 200 can affect the area of ​​the pixel driving circuit 200.

[0070] In some embodiments, the area occupied by the pixel driving circuit 200 is large, resulting in a large space occupied by the sub-pixel 21, which is not conducive to achieving a high PPI (Pixels Per Inch, pixel density) for the display panel. This is because the active layers of all transistors in the pixel driving circuit 200 are arranged in parallel, where "arranged in parallel" means that among all transistors in the pixel driving circuit 200, the orthographic projections of any two transistors on the substrate 101 do not overlap. At this time, the area of ​​the orthographic projection of the pixel driving circuit 200 on the substrate 101 is the sum of the areas of the active layers of multiple transistors in the pixel driving circuit 200, resulting in a large area of ​​the orthographic projection of the pixel driving circuit 200 on the substrate 101, thereby increasing the area occupied by the pixel driving circuit 200.

[0071] Based on this, as shown in Figure 4, some embodiments of the present disclosure provide an array substrate 10, which includes: a plurality of pixel driving circuits 200 and a plurality of signal lines. As shown in Figure 3, the plurality of pixel driving circuits 200 are arranged in multiple rows and columns. For example, the extension direction of the row is represented as the row direction X, and the extension direction of the column is represented as the column direction Y. The plurality of signal lines include data signal lines Dt and gate lines, initialization signal lines Vin, voltage signal lines, etc. For example, the gate lines include: a first scanning signal line G1, a second scanning signal line G2, a reset signal line Rst and a light-emitting control signal line EM, and the voltage signal lines include: a first voltage signal line VDD and a second voltage signal line Vre. Each data signal line Dt is electrically connected to a column of pixel driving circuits 200, and at least one gate line is electrically connected to a row of pixel driving circuits 200.

[0072] As shown in FIG4 , the array substrate 10 includes a base substrate 101 and two active film layers, wherein the two active film layers include a first active film layer 103 and a second active film layer 114 sequentially disposed on the base substrate 101, and the two active film layers are insulated from each other. The multiple transistors in the pixel driving circuit 200 are divided into multiple first-type transistors and multiple second-type transistors. The active layer patterns of the first-type transistors are located in the first active film layer 103, and the active layer patterns of the second-type transistors are located in the second active film layer 114. Furthermore, the orthographic projections of the active layer patterns of the multiple first-type transistors on the base substrate 101 at least partially overlap with the orthographic projections of the second-type transistors on the base substrate 101. Thus, by disposing the active layer patterns of the transistors in the pixel driving circuit 200 in different active film layers and overlapping the active layer patterns of the transistors in different active film layers, the total area of ​​the orthographic projections of the multiple transistors in the pixel driving circuit 200 on the base substrate 101 is reduced, thereby reducing the area occupied by the pixel driving circuit 200.

[0073] The solution of the present invention is described in detail below.

[0074] In some embodiments, the pixel driving circuit 200 in some embodiments of the present disclosure can be a 4T1C, 5T1C, 7T1C, 8T1C or 9T1C circuit, wherein T represents a transistor, and the number before T represents the number of transistors, C represents a capacitor, and the number before C represents the number of capacitors. For example, 5T1C represents 5 transistors and 1 capacitor. The following is an introduction to the pixel driving circuit 200 in 5T1C mode.

[0075] In some embodiments, as shown in Figure 5, the pixel driving circuit 200 may specifically include: a driving transistor T1, a write transistor T2, a first reset transistor T3, a second reset transistor T4, a light-emitting control transistor T5 and a capacitor Cst, and the signal lines electrically connected to the pixel driving circuit 200 include: a first scanning signal line G1, a second scanning signal line G2, an initialization signal line Vin, a reset signal line Rst, a second voltage signal line Vre, a first voltage signal line VDD, a third voltage signal line VSS, a data signal line Dt and a light-emitting control signal line EM.

[0076] Among them, the gate of the driving transistor T1 is electrically connected to the first node N1, the first electrode of the driving transistor T1 is electrically connected to the second electrode of the light-emitting control transistor T5, and the second electrode of the driving transistor T1 is electrically connected to the second node N2; the gate of the write transistor T2 is electrically connected to the second scanning signal line G2, the first electrode of the write transistor T2 is electrically connected to the data signal line Dt, and the second electrode of the write transistor T2 is electrically connected to the first node N1; the gate of the first reset transistor T3 is electrically connected to the first scanning signal line G1, the first electrode of the first reset transistor T3 is electrically connected to the second voltage signal line Vre, and the second electrode of the first reset transistor T3 is electrically connected to the first node N1.

[0077] The gate of the second reset transistor T4 is electrically connected to the reset signal line Rst, the first electrode of the second reset transistor T4 is electrically connected to the initialization signal line Vin, and the second electrode of the second reset transistor T4 is electrically connected to the second node N2; the gate of the light-emitting control transistor T5 is electrically connected to the light-emitting control signal line EM, the first electrode of the light-emitting control transistor T5 is electrically connected to the first voltage signal line VDD; the first plate of the capacitor Cst is electrically connected to the first node N1, and the second plate of the capacitor Cst is electrically connected to the second node N2.

[0078] An anode of the light emitting device OLED is electrically connected to the second node N2 , and a cathode of the light emitting device OLED is electrically connected to the third voltage signal line VSS.

[0079] Among them, the first scanning signal line G1 is used to transmit the first scanning signal g1, the second scanning signal line G2 is used to transmit the second scanning signal g2, the initialization signal line Vin is used to transmit the initialization signal, the reset signal line Rst is used to transmit the reset timing signal rst, the first voltage signal line VDD is used to transmit the first voltage signal, for example, a high-voltage DC signal, the data signal line Dt is used to transmit the data signal, the light-emitting control signal line EM is used to transmit the light-emitting control timing signal em, the third voltage signal line VSS is used to transmit the third voltage signal, for example, a low-voltage DC signal, and the second voltage signal line Vre is used to transmit the second voltage signal.

[0080] As shown in FIG5 and FIG6 , the driving process of the pixel driving circuit 200 is as follows: one frame period includes a reset phase t1 , a compensation phase t2 , a data writing phase t3 and a light emitting phase t4 .

[0081] In the reset phase t1, the first reset transistor T3 is turned on under the control of the first scan signal g1, so that the second voltage signal is written to the first node N1, thereby resetting the first node N1. After the second voltage signal is written to the first node N1, the voltage of the first node N1 is V ref The second reset transistor T4 is turned on under the control of the reset timing signal rst, so that the initialization signal is written into the anode of the OLED, which can also be represented as the second node N2, thereby resetting the anode of the light-emitting device OLED. After the initialization signal is written into the second node N2, the voltage of the second node N2 is V vin .

[0082] At this time, the driving transistor T1 is turned on, the writing transistor T2 and the light emitting control transistor T5 are in the off state, and the light emitting device OLED does not emit light.

[0083] In the compensation phase t2, the first reset transistor T3 is kept on under the control of the first scanning signal g1, the driving transistor T1 is kept on, and the light emitting control transistor T5 is turned on under the control of the light emitting control timing signal em. At this time, the voltage of the first node N1 is V ref , the voltage of the second node N2 is V vin becomes V ref -V th , where V th The threshold voltage of the driving transistor T1 is reduced, and the driving transistor T1 is turned off, thereby compensating for the threshold voltage of the driving transistor T1, avoiding changes in the driving signal generated by the driving transistor T1, and further avoiding affecting the luminous intensity of the light-emitting device OLED.

[0084] At this time, the second reset transistor T4 and the write transistor T2 are in a disconnected state, and the light emitting device OLED does not emit light.

[0085] In the data writing phase t3, the writing transistor T2 is turned on under the control of the second scanning signal g2, so that the data signal is written to the first node N1, and the voltage of the first node N1 is V data , the voltage of the second node N2 is V ref -V th becomes V ref -V th +(V data -V ref )ⅹC Cst / (C Cst +C Coled ), where C Cst is the storage capacitance of capacitor Cst, C Coled is the capacitance of OLED itself.

[0086] At this time, the driving transistor T1 is turned on, the first reset transistor T3, the second reset transistor T4 and the light emitting control transistor T5 are in a turned-off state, and the light emitting device OLED does not emit light.

[0087] In the light emitting stage t4 , the write transistor T2 is turned off under the control of the second scanning signal g2 , the first reset transistor T3 is turned off under the control of the first scanning signal g1 , and the second reset transistor T4 is turned off under the control of the reset timing signal rst.

[0088] The light emitting control transistor T5 is turned on under the control of the light emitting control timing signal em, and the driving transistor T1 remains turned on, forming a path between the first voltage signal line VDD and the light emitting device OLED, so that the light emitting device OLED emits light.

[0089] It should be noted that the first electrode of the transistor disclosed herein is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable. In other words, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source, and the second electrode is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain, and the second electrode is the source.

[0090] In the circuit provided by the embodiments of the present disclosure, nodes do not represent actual components, but represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0091] In some embodiments, as shown in FIG5 , the write transistor T2 and the first reset transistor T3 may be oxide thin film transistors, and the drive transistor T1 , the second reset transistor T4 and the light emitting control transistor T5 may be low temperature polysilicon (LTPS) thin film transistors.

[0092] The pixel driving circuit 200 adopts an LTPO (Low Temperature Polycrystalline Oxide) circuit, that is, a pixel driving circuit 200 includes both a low-temperature polycrystalline silicon (LTPS) thin film transistor and an oxide thin film transistor. The low-temperature polycrystalline silicon thin film transistor has a strong load capacity, and the oxide thin film transistor has a small off-state current and a stronger charge retention ability than the low-temperature polycrystalline silicon thin film transistor. In this way, the pixel driving circuit 200 can achieve higher charge mobility and better stability.

[0093] In some examples, both the oxide transistor and the LTPS transistor are N-type transistors, or the oxide transistor is an N-type transistor and the LTPS transistor is a P-type transistor, wherein the N-type transistor is turned on when a high voltage signal is received at the gate, and the P-type transistor is turned on when a low voltage signal is received at the gate.

[0094] It should be noted that the "high voltage signal" and "low voltage signal" mentioned above are popular terms. Generally speaking, the turn-on condition of an N-type transistor is that the gate-source voltage difference is greater than its threshold voltage, that is, the gate voltage of the N-type transistor is greater than the sum of its source voltage and its threshold voltage. The threshold voltage of the N-type transistor is a positive value, then the gate voltage signal that turns on the N-type transistor is called a high voltage signal. The turn-on condition of a P-type transistor is that the absolute value of the gate-source voltage difference is greater than its threshold voltage. The threshold voltage of the P-type transistor is a negative value, that is, the gate voltage of the P-type transistor is less than the sum of its source voltage and its threshold voltage, then the gate voltage signal that turns on the P-type transistor is called a low voltage signal. The high and low in "high voltage signal" and "low voltage signal" are relative to a reference voltage (for example, 0V).

[0095] In some other embodiments, the driving transistor T1 , the second reset transistor T4 and the light emitting control transistor T5 may be oxide thin film transistors.

[0096] The embodiments of the present disclosure are described by taking as an example that the write transistor T2 and the first reset transistor T3 are N-type oxide thin film transistors, and the drive transistor T1 , the second reset transistor T4 and the light emitting control transistor T5 are N-type low-temperature polysilicon thin film transistors.

[0097] The following describes the film layer structures included in the array substrate 10 and the arrangement of the transistors in the pixel driving circuit 200 .

[0098] In some embodiments, as shown in FIG. 4 , the array substrate 10 includes a base substrate 101 and a pixel circuit stack 20 . The pixel circuit stack 20 is disposed on the base substrate 101 .

[0099] Exemplarily, the material of the base substrate 101 may include any one of glass, metal or flexible material.

[0100] The pixel circuit stack 20 is formed with multiple pixel driving circuits 200. For example, the pixel circuit stack 20 includes: a blocking layer 121, a first buffer layer 102, a first active film layer 103, a first gate insulating layer 104, a first gate metal layer 105, a second gate insulating layer 106, a second gate metal layer 107, a first interlayer dielectric layer 108, a first source-drain metal layer 109, a first planarizing layer 110, a second buffer layer 111, a third gate metal layer 112, a third gate insulating layer 113, a second active film layer 114, a fourth gate insulating layer 115, a fourth gate metal layer 116, a second interlayer dielectric layer 117, a second source-drain metal layer 118, a second planarizing layer 119, a third source-drain metal layer 120 and a third planarizing layer 30, which are stacked in sequence.

[0101] Exemplarily, the shielding layer 121 is made of metal. Connecting a fixed potential to the shielding layer 121 can shield the influence of surrounding stray charges on the driving transistor T1 .

[0102] For example, the first buffer layer 102 and the second buffer layer 111 are prepared using PECVD (Plasma Enhanced Chemical Vapor Deposition). The materials used may be silicon nitride, silicon oxide, or silicon oxynitride, which have water and gas barrier properties. The thickness of the silicon nitride may range from 30 nm to 70 nm, for example, 50 nm, and the thickness of the silicon oxide may range from 250 nm to 350 nm, for example, 300 nm.

[0103] Exemplarily, the first active film layer 103 is obtained by an excimer laser annealing process, and its material is low-temperature polycrystalline silicon, with a thickness ranging from 30nm to 50nm, for example, 40nm; the second active film layer 114 is obtained by a PVD (Physical Vapor Deposition) process, with a thickness ranging from 30nm to 50nm, for example, 40nm, and its material can be any one of indium gallium zinc oxide or low-temperature polycrystalline oxide, for example, IGZO (Indium gallium zinc oxide) and IGZTO (Indium gallium zinc tin oxide).

[0104] Exemplarily, the material of the first gate insulating layer 104, the second gate insulating layer 106, the third gate insulating layer 113 and the fourth gate insulating layer 115 is silicon nitride, silicon oxide or silicon oxynitride, and is deposited by a PECVD process, with a thickness ranging from 100 nm to 150 nm. For example, the thickness of the first gate insulating layer 104 is 100 nm, the thickness of the second gate insulating layer 106 is 150 nm, the thickness of the third gate insulating layer 113 is 100 nm, and the thickness of the fourth gate insulating layer 115 is 150 nm.

[0105] Illustratively, the first gate metal layer 105, the second gate metal layer 107, the first source-drain metal layer 109, the third gate metal layer 112, the fourth gate metal layer 116, the second source-drain metal layer 118 and the third source-drain metal layer 120 are mainly obtained by depositing metal materials such as MO / Ti / Al / Cu (molybdenum / titanium / aluminum / copper) using a PVD process, and their thickness ranges from 300nm to 800nm.

[0106] Exemplarily, the material of the first interlayer dielectric layer 108 and the second interlayer dielectric layer 117 can be any one of silicon nitride, silicon oxide or silicon oxynitride, or a combination of any two of them, and is deposited using a PECVD process with a thickness ranging from 400 nm to 800 nm.

[0107] In some examples, the material of first planar layer 110 includes an organic material. For example, the material of first planar layer 110 can be PI (polyimide), and first planar layer 110 is formed by a spin coating process. In this case, the thickness of first planar layer 110 is greater than the thickness of second planar layer 119. The thicker first planar layer 110 can prevent signal crosstalk between the two active film layers. Exemplarily, the thickness of first planar layer 110 ranges from 1.5 microns to 2 microns.

[0108] In other embodiments, the material of the first planarization layer 110 includes an inorganic material, such as silicon oxide or silicon nitride. When the first planarization layer 110 is made of an inorganic material, the film thickness ranges from 1.2 microns to 1.5 microns. When the first planarization layer 110 is made of an inorganic material, its thickness is thinner than when it is made of an organic material. This can reduce the size of the vias in the first planarization layer 110, further improving the PPI.

[0109] For example, when the material of the first planar layer 110 is an inorganic material, the surface of the first planar layer 110 on the side close to the second planar layer 119 can be planarized by chemical mechanical polishing (CMP).

[0110] Exemplarily, the second planar layer 119 can be obtained by coating PI using a spin coating process, or by depositing silicon nitride, silicon oxide or silicon oxynitride using a PECVD process. It is mainly used to block water and oxygen and alkaline ions, and its thickness ranges from 400nm to 800nm.

[0111] In some examples, as shown in FIG. 7 , in the array substrate 10 , the film layer patterns of the adjacent row sub-pixel regions A1 are mirrored, and the film layer patterns of the adjacent column sub-pixel regions A1 are mirrored.

[0112] For example, FIG7 shows a structure diagram of the film layers of four adjacent sub-pixel regions A1 arranged in two rows and two columns after being superimposed. The two sub-pixel regions A1 in the first row are respectively the first sub-pixel region A11 and the second sub-pixel region A12, and the two sub-pixel regions A1 in the second row are respectively the third sub-pixel region A13 and the fourth sub-pixel region A14. The film layer patterns of the first sub-pixel region A11 and the second sub-pixel region A12 are mirror images in the row direction X, the film layer patterns of the third sub-pixel region A13 and the fourth sub-pixel region A14 are mirror images in the row direction X, the film layer patterns of the first sub-pixel region A11 and the third sub-pixel region A13 are mirror images in the column direction Y, and the film layer patterns of the second sub-pixel region A12 and the fourth sub-pixel region A14 are mirror images in the column direction Y.

[0113] Furthermore, as shown in Figures 8 and 10, the patterns of the film layers in adjacent row sub-pixel regions A1 are mirror images, and the patterns of the film layers in adjacent column sub-pixel regions A1 are mirror images. For example, the first active film layer 103 of the first sub-pixel region A11 and the first active film layer 103 of the second sub-pixel region A12 are mirror images in the row direction X, and the first active film layer 103 of the first sub-pixel region A11 and the first active film layer 103 of the third sub-pixel region A13 are mirror images in the column direction Y.

[0114] As shown in Figures 7 and 8, the array substrate 10 includes multiple DC signal lines, and the pixel driving circuits 200 of two columns of sub-pixel areas A1 adjacent to one DC signal line among the multiple DC signal lines share the DC signal line, and the pixel driving circuits 200 of two rows of sub-pixel areas A1 adjacent to one DC signal line among the multiple DC signal lines share the DC signal line.

[0115] 7 , the DC signal line includes: a first voltage signal line first branch line VDD1, an initialization signal line first branch line Vni1, a first voltage signal line second branch line VDD2, an initialization signal line second branch line Vni2, a second voltage signal line first branch line Vre1, and a second voltage signal line second branch line Vre2.

[0116] It should be noted that sharing means that the DC signal line is shared by the pixel driving circuits 200 of two columns or two rows of sub-pixel areas A1. A DC voltage signal line is divided into two parts along the column direction Y, and is respectively located in two adjacent columns of sub-pixel areas A1, or a DC voltage signal line is divided into two parts along the row direction X, and is respectively located in two adjacent rows of sub-pixel areas A1. For example, as shown in FIG7 , the upper half F1 of the second branch of the initialization signal line Vni2 is located in multiple sub-pixel areas A1 in the row where the first sub-pixel area A11 and the second sub-pixel area A12 are located, and the lower half F2 of the second branch of the initialization signal line Vni2 is located in multiple sub-pixel areas A1 in the row where the third sub-pixel area A13 and the fourth sub-pixel area A14 are located. The upper half F1 of the second branch of the initialization signal line Vni2 and the lower half F2 of the second branch of the initialization signal line Vni2 together constitute the complete second branch of the initialization signal line Vni2. That is, the sub-pixel area A1 includes not only the film pattern of the pixel driving circuit 200 but also a partial pattern of the signal line, a switching pattern, and the like.

[0117] By adopting a mirror-image setting of the film layer patterns of adjacent row sub-pixel areas A1 and a mirror-image setting of the film layer patterns of adjacent column sub-pixel areas A1, the DC signal lines can be shared, thereby reducing the number of DC signal lines set in the array substrate 10 and reducing wiring. It can further make the setting of adjacent pixel driving circuits 200 more compact and reduce the spacing between adjacent pixel driving circuits 200, thereby reducing the total area of ​​multiple sub-pixel areas A1, further reducing the space occupied by multiple sub-pixels 21, and helping to improve the PPI of the display panel 100.

[0118] It should be noted that the following film layer structure diagrams and structure diagrams after film layer superposition provided in the embodiments of the present disclosure are all based on the example of the arrangement of the film layers in four sub-pixel regions A1 arranged adjacently in two rows and two columns.

[0119] In some embodiments, as shown in Figures 4, 8 and 9, the array substrate 10 also includes: a shielding layer 121 arranged between the base substrate 101 and the first active film layer 103, the shielding layer 121 includes a plurality of first voltage signal lines, first branches VDD1, and a plurality of initialization signal lines, first branches Vni1, extending along the column direction Y.

[0120] It should be noted that, in the embodiments of the present disclosure, "a signal line extends along the column direction Y" means that the signal line as a whole has a tendency to extend along the column direction Y, and "a signal line extends along the row direction X" means that the signal line as a whole has a tendency to extend along the row direction X. For example, "a first branch line of the first voltage signal line VDD1" and "a first branch line of the initialization signal line Vni1" ​​extend along the column direction Y" means that "a first branch line of the first voltage signal line VDD1" and "a first branch line of the initialization signal line Vni1" ​​extend along the column direction Y"

[0121] As shown in Figures 4, 8, and 14, the array substrate 10 further includes a second gate metal layer 107 disposed between the first active film layer 103 and the second active film layer 114. The second gate metal layer 107 includes a plurality of first voltage signal line second branches VDD2 and a plurality of initialization signal line second branches Vni2 extending along the row direction X. Each of the plurality of first voltage signal line second branches VDD2 is connected to the plurality of first voltage signal line first branches VDD1 via a via, and each of the plurality of initialization signal line second branches Vni2 is connected to the plurality of initialization signal line first branches Vni1 via a via.

[0122] 4 , the following layers are sequentially arranged between the shielding layer 121 and the second gate metal layer 107: a first buffer layer 102, a first active film layer 103, a first gate insulating layer 104, a first gate metal layer 105, and a second gate insulating layer 106. A first branch line VDD1 of a first voltage signal line located in the shielding layer 121 is connected to a second branch line VDD2 of a first voltage signal line located in the second gate metal layer 107. Furthermore, a first branch line Vni1 of an initialization signal line located in the shielding layer 121 is connected to a second branch line Vni2 of an initialization signal line located in the shielding layer 121. Vias need to penetrate the first buffer layer 102, the first gate insulating layer 104, and the second gate insulating layer 106.

[0123] For example, as shown in Figures 8 and 11, the array substrate 10 includes first-type vias H1. In conjunction with Figure 4, the first-type vias H1 penetrate the first buffer layer 102, the first gate insulation layer 104, and the second gate insulation layer 106. The first-type vias H1 include: a first-type via H11 and a second-type via H12. The first branch line VDD1 of the first voltage signal line located in the shielding layer 121 and the second branch line VDD2 of the first voltage signal line located in the second gate metal layer 107 are connected via the first-type via H11. The first branch line Vni1 of the initialization signal line located in the shielding layer 121 and the second branch line Vni2 of the initialization signal line located in the second gate metal layer 107 are connected via the second-type via H12.

[0124] It can be understood that the first voltage signal line first branch line VDD1 and the first voltage signal line second branch line VDD2 are connected to form the first voltage signal line VDD, and the initialization signal line first branch line Vni1 and the initialization signal line second branch line Vni2 are connected to form the initialization signal line Vni.

[0125] By setting the first type of via H1, the second branch line VDD2 of each first voltage signal line can be connected to the first branch lines VDD1 of multiple first voltage signal lines, and the second branch line Vni2 of each initialization signal line can be connected to the first branch line Vni1 of multiple initialization signal lines. In this way, the first voltage signal line VDD used to transmit the first voltage signal and the initialization signal line Vni used to transmit the initialization signal both form a grid structure, which facilitates signal transmission, improves signal transmission efficiency, and reduces transmission voltage drop, thereby improving the uniformity of the first voltage signal and initialization signal of different sub-pixel areas A1, which is beneficial to the uniformity of light emission and reset of each pixel driving circuit 200, and improves the picture display effect. In addition, setting multiple first voltage signal lines, first branches VDD1, and multiple initialization signal lines, first branches Vni1 in the shielding layer 121 can reduce the number of wirings in other metal film layers (such as the first source-drain metal layer 109, the second source-drain metal layer 118, and the third source-drain metal layer 120), thereby reserving more space for the setting of signal lines and transfer patterns in other metal film layers, avoiding limited wiring flexibility of other metal film layers, and at the same time helping to improve the PPI of the display panel 100.

[0126] In some embodiments, as shown in Figures 7 and 8, the pixel driving circuits 200 in two columns of sub-pixel regions A1 adjacent to a first branch line of the first voltage signal line VDD1 share the first branch line of the first voltage signal line VDD1. The pixel driving circuits 200 in two columns of sub-pixel regions A1 adjacent to a first branch line of the initialization signal line Vni1 share the first branch line of the initialization signal line Vni1.

[0127] As shown in Figures 7 and 8, along the row direction X, a first branch line of the first voltage signal line VDD1 and a first branch line of the initialization signal line Vni1 are alternately arranged. The pixel driving circuits 200 in the column where the first sub-pixel area A11 and the third sub-pixel area A13 are located share a first branch line of the first voltage signal line VDD1 with the pixel driving circuits 200 in the column where the sub-pixel area A1 to their left is located. The pixel driving circuits 200 in the column where the second sub-pixel area A12 and the fourth sub-pixel area A14 are located share a first branch line of the first voltage signal line VDD1 with the pixel driving circuits 200 in the column where the sub-pixel area A1 to their right is located. Sharing the first branch line of the first voltage signal line VDD1 between pixel driving circuits 200 in adjacent columns reduces the number of wiring lines for the first branch line of the first voltage signal line VDD1, making the sub-pixel area A1 arrangement more compact and, to a certain extent, significantly saving space on the array substrate 10.

[0128] The pixel driving circuits 200 in the column where the first sub-pixel area A11 and the third sub-pixel area A13 are located share a first branch initialization signal line Vni1 with the pixel driving circuits 200 in the column where the second sub-pixel area A12 and the fourth sub-pixel area A14 are located. This allows the pixel driving circuits 200 in adjacent columns to share the first branch initialization signal line Vni1, thereby reducing the number of wiring lines for the first branch initialization signal line Vni1 and making the sub-pixel area A1 more compact. This significantly saves space on the array substrate 10.

[0129] In some embodiments, as shown in Figures 7 and 8, the pixel driving circuits 200 in two rows of sub-pixel regions A1 adjacent to a first voltage signal line second branch line VDD2 share the first voltage signal line second branch line VDD2. The pixel driving circuits 200 in two rows of sub-pixel regions A1 adjacent to an initialization signal line second branch line Vni2 share the initialization signal line second branch line Vni2.

[0130] As shown in Figures 7 and 8, along the column direction Y, a first voltage signal line, second branch line VDD2, and an initialization signal line, second branch line Vni2, are alternately arranged. The pixel driving circuits 200 in the row where the first sub-pixel area A11 and the second sub-pixel area A12 are located share a first voltage signal line, second branch line VDD2, with the pixel driving circuits 200 in the row where the sub-pixel area A1 is located above them. The pixel driving circuits 200 in the row where the third sub-pixel area A13 and the fourth sub-pixel area A14 are located share a first voltage signal line, second branch line VDD2, with the pixel driving circuits 200 in the row where the sub-pixel area A1 is located below them. Sharing the first voltage signal line, second branch line VDD2, between pixel driving circuits 200 in adjacent rows can reduce the number of wiring lines for the first voltage signal line, second branch line VDD2, and make the sub-pixel area A1 more compact, thus significantly saving space on the array substrate 10.

[0131] The pixel driving circuits 200 in the row where the first sub-pixel area A11 and the second sub-pixel area A12 are located share a second branch initialization signal line Vni2 with the pixel driving circuits 200 in the row where the third sub-pixel area A13 and the fourth sub-pixel area A14 are located. This allows the pixel driving circuits 200 in adjacent rows to share the second branch initialization signal line Vni2, thereby reducing the number of wiring lines for the second branch initialization signal line Vni2 and making the sub-pixel area A1 more compact. This significantly saves space on the array substrate 10 to a certain extent.

[0132] In some embodiments, as shown in FIG8 and FIG10 , in sub-pixel region A1, the first type of transistor includes: a light emission control transistor T5 and a second reset transistor T4. The active layer pattern of the light emission control transistor T5 is connected to the second branch line VDD2 of the first voltage signal line. The active layer pattern of the second reset transistor T4 is connected to the second branch line Vni2 of the initialization signal line.

[0133] The active layer of the first type of transistor is located in the first active film layer 103. The first active film layer 103 includes an active layer pattern for the emission control transistor T5 and an active layer pattern for the second reset transistor T4. Referring to Figure 4 , a first gate insulating layer 104, a first gate metal layer 105, and a second gate insulating layer 106 are sequentially arranged between the first active film layer 103 and the second gate metal layer 107. The active layer pattern of the emission control transistor T5 located in the first active film layer 103 is connected to the second branch line VDD2 of the first voltage signal line located in the second gate metal layer 107. Furthermore, the active layer pattern of the second reset transistor T4 located in the first active film layer 103 is connected to the second branch line Vni2 of the initialization signal line located in the second gate metal layer 107. Vias need to penetrate the first gate insulating layer 104 and the second gate insulating layer 106.

[0134] Therefore, as shown in Figures 8 and 13, the array substrate 10 includes second-type vias H2, which penetrate the first gate insulation layer 104 and the second gate insulation layer 106. The second-type vias H2 include: a first second-type via H21 and a second second-type via H22. The active layer pattern of the light-emitting control transistor T5 located in the first active film layer 103 and the second branch line VDD2 of the first voltage signal line located in the second gate metal layer 107 are connected via the first second-type via H21. The active layer pattern of the second reset transistor T4 located in the first active film layer 103 and the second branch line Vni2 of the initialization signal line located in the second gate metal layer 107 are connected via the second second-type via H22.

[0135] In some embodiments, as shown in Figures 8 and 12, the first gate metal layer 105 includes: a light emitting control signal line EM and a reset signal line Rst, the light emitting control signal line EM passes through the active layer pattern of the light emitting control transistor T5, and the reset signal line Rst passes through the active layer pattern of the second reset transistor T4.

[0136] For example, as shown in FIG8 , the emission control signal line EM passes through a portion of the active layer pattern of the emission control transistor T5 to serve as the gate of the emission control transistor T5. The emission control signal line EM is used to transmit the emission control timing signal em to the gate of the emission control transistor T5. The reset signal line Rst passes through a portion of the active layer pattern of the second reset transistor T4 to serve as the gate of the second reset transistor T4. The reset signal line Rst is used to transmit the reset timing signal rst to the gate of the second reset transistor T4.

[0137] In some embodiments, as shown in FIG8 and FIG10 , the first type of transistor further includes: a driving transistor T1 , an active layer pattern of the light emission control transistor T5 , an active layer pattern of the driving transistor T1 , and an active layer pattern of the second reset transistor T4 , which are sequentially connected.

[0138] As shown in FIG5 , the first electrode of the emission control transistor T5 is connected to the first voltage signal line VDD, the second electrode of the emission control transistor T5 is connected to the first electrode of the driving transistor T1, the second electrode of the driving transistor T1 is connected to the second electrode of the second reset transistor T4, and the first electrode of the second reset transistor T4 is connected to the initialization signal line Vin. By disposing the active layer patterns of the emission control transistor T5, the driving transistor T1, and the second reset transistor T4 on the first active film layer 103, and connecting the active layer pattern of the emission control transistor T5 to the active layer pattern of the driving transistor T1, the second electrode of the emission control transistor T5 is directly connected to the first electrode of the driving transistor T1, and the active layer pattern of the driving transistor T1 is directly connected to the active layer pattern of the second reset transistor T4, thereby directly connecting the second electrode of the driving transistor T1 to the second electrode of the second reset transistor T4.

[0139] That is to say, the first active film layer 103 is used to directly realize the electrical connection between the light-emitting control transistor T5, the driving transistor T1 and the second reset transistor T4. The connection between the transistors does not need to be connected through vias to other metal layers through the transfer pattern. This setting can reduce the setting of connecting vias and further improve PPI.

[0140] In some embodiments, as shown in Figures 4, 8 and 9, the blocking layer 121 also includes: a first shading pattern 121A, the first shading pattern 121A is connected to the first branch line VDD1 of the first voltage signal line, and the orthographic projection of the driving transistor T1 on the base substrate 101 is located within the orthographic projection of the first shading pattern 121A on the base substrate 101.

[0141] The first light-shielding pattern 121A can shield the active layer pattern of the driving transistor T1 from the side facing the substrate 101, preventing the driving transistor T1 from being affected by light or external electric fields. Furthermore, the first light-shielding pattern 121A is connected to the first branch line of the first voltage signal line VDD1, which can shield the driving transistor T1 from the effects of surrounding stray charges and improve the stability of the driving transistor T1.

[0142] In some embodiments, as shown in Figures 4, 8 and 9, the blocking layer 121 also includes: a second light-shielding pattern 121B, the second light-shielding pattern 121B is connected to the first branch line VDD1 of the first voltage signal line, and the orthographic projection of the second reset transistor T4 on the base substrate 101 is located within the orthographic projection of the second light-shielding pattern 121B on the base substrate 101.

[0143] The second light-shielding pattern 121B can shield the active layer pattern of the second reset transistor T4 from the side facing the substrate 101, preventing light or external electric fields from affecting the second reset transistor T4. Furthermore, the second light-shielding pattern 121B is connected to the first branch line VDD1 of the first voltage signal line, thereby shielding the second reset transistor T4 from the effects of surrounding stray charges and reducing the risk of leakage current in the second reset transistor T4.

[0144] In some embodiments, as shown in Figures 4, 8, 12, and 14, the pixel driving circuit 200 further includes a capacitor Cst. The array substrate 10 further includes a first gate metal layer 105 disposed between the first active film layer 103 and the second gate metal layer 107. The first gate metal layer 105 includes a first plate pattern Cst1 of the capacitor Cst. The second gate metal layer 107 also includes a second plate pattern Cst2 of the capacitor Cst.

[0145] In some examples, as shown in Figures 4, 8, 16 and 17, the array substrate 10 also includes: a first source-drain metal layer 109 arranged between the second gate metal layer 107 and the second active film layer 114, the first source-drain metal layer 109 includes a first transfer pattern M1, and the first transfer pattern M1 is connected to the active layer pattern of the second reset transistor T4 through a via, and is also connected to the second plate pattern Cst2 of the capacitor Cst.

[0146] Exemplarily, FIG16 is a film layer structure diagram of the first source-drain metal layer 109 , which includes a first switching pattern M1 for simultaneously connecting the active layer pattern of the second reset transistor T4 and the second plate pattern Cst2 of the capacitor Cst.

[0147] 8 and 17 , FIG17 is a cross-sectional view of the film layer structure diagram shown in FIG8 taken along the CC cross-sectional line. The active layer pattern of the second reset transistor T4 is located in the first active film layer 103. The first gate insulating layer 104, the first gate metal layer 105, the second gate insulating layer 106, the second gate metal layer 107 and the first interlayer dielectric layer 108 are sequentially arranged between the first active film layer 103 and the first source / drain metal layer 109. In order to achieve the connection between the first switching pattern M1 and the active layer pattern of the second reset transistor T4 and the second plate pattern Cst2 of the capacitor Cst, the via needs to penetrate the first gate insulating layer 104, the second gate insulating layer 106 and the first interlayer dielectric layer 108.

[0148] As shown in Figures 8, 15, and 17, the array substrate 10 includes third-type vias H3, which penetrate the first gate insulation layer 104, the second gate insulation layer 106, and the first interlayer dielectric layer 108. The first transfer pattern M1 is first connected to the second plate pattern Cst2 of the capacitor Cst through the third-type via H3, and then connected to the active layer pattern of the second reset transistor T4. This achieves the purpose of simultaneously connecting the first transfer pattern M1 to the active layer pattern of the second reset transistor T4 and the second plate pattern Cst2 of the capacitor Cst.

[0149] 5 , the second electrode of the driving transistor T1 is electrically connected to the second node N2, the second electrode of the second reset transistor T4 is electrically connected to the second node N2, the second plate Cst2 of the capacitor Cst is electrically connected to the second node N2, and the second node N2 is electrically connected to the anode of the light-emitting device OLED. That is, the film structure is required to achieve connection between the second electrode of the driving transistor T1, the second electrode of the second reset transistor T4, the second plate Cst2 of the capacitor Cst, and the anode of the light-emitting device OLED.

[0150] As shown in Figures 8, 10 and 17, the connection between the second electrode of the driving transistor T1 and the second electrode of the second reset transistor T4 is realized by connecting the active layer pattern of the driving transistor T1 and the active layer pattern of the second reset transistor T4. The active layer pattern of the second reset transistor T4 located on the first active film layer 103 and the second plate pattern Cst2 of the capacitor Cst located on the second gate metal layer 107 are simultaneously connected through the first switching pattern M1. Then, the first switching pattern M1 is connected to the anode of the light-emitting device OLED, so that the second electrode of the driving transistor T1, the second electrode of the second reset transistor T4, the second plate Cst2 of the capacitor Cst and the anode of the light-emitting device OLED can be connected.

[0151] Therefore, the embodiment of the present disclosure simultaneously connects the active layer pattern of the second reset transistor T4 and the second plate pattern Cst2 of the capacitor Cst through the third type of via H3 through the first transfer pattern M1, which not only reduces the setting of the vias, but also makes the capacitance area of ​​the capacitor Cst larger, so that the capacitor Cst has a larger capacitance.

[0152] The following describes the connection configuration between the active layer pattern of the second reset transistor T4 and the anode of the light emitting device OLED.

[0153] As shown in Figures 4, 18, and 25, the display panel 100 includes an anode layer 401, which includes multiple anode patterns 4011. Anode patterns 4011 serve as the anodes of the light-emitting device (OLED). Disposed sequentially between the first source / drain metal layer 109 and the anode layer 401 are a first planarization layer 110, a second buffer layer 111, a third gate metal layer 112, a third gate insulation layer 113, a second active film layer 114, a fourth gate insulation layer 115, a fourth gate metal layer 116, a second interlayer dielectric layer 117, a second source / drain metal layer 118, a second planarization layer 119, a third source / drain metal layer 120, and a third planarization layer 30. Therefore, the connection between the first transfer pattern M1 located in the first source / drain metal layer 109 and the anode pattern 4011 located in the anode layer 401 requires the provision of vias and connection patterns between the first source / drain metal layer 109 and the anode layer 401. See below for details.

[0154] In some embodiments, as shown in Figures 4, 18, 24, 25, and 27, the second active film layer 114 further includes a second transfer pattern M2, and the array substrate 10 includes a second source / drain metal layer 118 disposed on a side of the second active film layer 114 away from the base substrate 101. The second source / drain metal layer 118 includes a third transfer pattern M3. The array substrate 10 further includes a third source / drain metal layer 120 disposed on a side of the second source / drain metal layer 118 away from the base substrate 101. The third source / drain metal layer 120 includes a fourth transfer pattern M4. The first transfer pattern M1, the second transfer pattern M2, the third transfer pattern M3, and the fourth transfer pattern M4 are sequentially connected through vias.

[0155] It should be noted that, as shown in Figures 18 and 25, the fourth transfer pattern M4 is used to connect to the anode pattern 4011. Therefore, the first transfer pattern M1, the second transfer pattern M2, the third transfer pattern M3 and the fourth transfer pattern M4 are connected in sequence to realize the connection between the active layer pattern of the second reset transistor T4 and the anode of the light-emitting device OLED.

[0156] For example, referring to Figures 4 and 18, a first flat layer 110, a second buffer layer 111, a third gate metal layer 112 and a third gate insulating layer 113 are sequentially arranged between the first source / drain metal layer 109 and the second active film layer 114. The first transfer pattern M1 located in the first source / drain metal layer 109 is connected to the second transfer pattern M2 located in the second active film layer 114, and the via needs to pass through the first flat layer 110, the second buffer layer 111 and the third gate insulating layer 113.

[0157] Therefore, as shown in Figures 18 and 20, the array substrate 10 further includes fifth-type vias H5. The fifth-type vias H51 penetrate the first planar layer 110, the second buffer layer 111, and the third gate insulation layer 113. The fifth-type vias H5 include a first fifth-type via H51 and a second fifth-type via H52. The first transfer pattern M1 and the second transfer pattern M2 are connected through the first fifth-type via H51.

[0158] For example, referring to Figures 4 and 18, a fourth gate insulating layer 115, a fourth gate metal layer 116 and a second interlayer dielectric layer 117 are sequentially arranged between the second active film layer 114 and the second source-drain metal layer 118. The second transfer pattern M2 located in the second active film layer 114 is connected to the third transfer pattern M3 located in the second source-drain metal layer 118, and the via needs to pass through the fourth gate insulating layer 115 and the second interlayer dielectric layer 117.

[0159] Therefore, as shown in Figures 18 and 23, the array substrate 10 further includes sixth-type vias H6, which penetrate the fourth gate insulation layer 115 and the second interlayer dielectric layer 117. The sixth-type vias H6 include: a first sixth-type via H61, a second sixth-type via H62, and a third sixth-type via H63. The second transfer pattern M2 and the third transfer pattern M3 are connected via the first sixth-type via H61.

[0160] For example, referring to Figures 4 and 25, a second flat layer 119 is provided between the second source-drain metal layer 118 and the third source-drain metal layer 120, the third transfer pattern M3 located in the second source-drain metal layer 118 and the fourth transfer pattern M4 located in the third source-drain metal layer 120 are connected, and the via needs to pass through the second flat layer 119.

[0161] Therefore, as shown in Figures 25 and 26, the array substrate 10 further includes seventh-type vias H7, which extend through the second planar layer 119. The seventh-type vias H7 include: a first seventh-type via H71, a second seventh-type via H72, and a third seventh-type via H73. The third transfer pattern M3 and the fourth transfer pattern M4 are connected via the first seventh-type via H71.

[0162] For example, as shown in Figures 4 and 25, a third flat layer 30 is provided between the third source-drain metal layer 120 and the anode layer 401, the fourth transfer pattern M4 located in the third source-drain metal layer 120 is connected to the anode pattern 4011 located in the anode layer 401, and the via needs to pass through the third flat layer 30.

[0163] 4, 25 and 28, the array substrate 10 further includes an eighth type of via hole H8, which penetrates the third planar layer 30. The fourth transfer pattern M4 and the anode pattern 4011 are connected through the eighth type of via hole H8.

[0164] By setting the first fifth type via H51, the first sixth type via H61, the first seventh type via H71 and the eighth type via H8, the connection between the first transfer pattern M1, the second transfer pattern M2, the third transfer pattern M3, the fourth transfer pattern M4 and the anode pattern 4011 is realized, thereby realizing the connection between the second electrode of the driving transistor T1, the second electrode of the second reset transistor T4, the second electrode plate Cst2 of the capacitor Cst and the anode of the light-emitting device OLED.

[0165] In some embodiments, as shown in Figures 4, 24, 25, and 27, the array substrate 10 includes a second source-drain metal layer 118 disposed on a side of the second active film layer 114 away from the base substrate 101. The second source-drain metal layer 118 includes a plurality of second voltage signal line first branches Vre1 extending along the row direction X. The array substrate 10 also includes a third source-drain metal layer 120 disposed on a side of the second source-drain metal layer 118 away from the base substrate 101. The third source-drain metal layer 120 includes a plurality of second voltage signal line second branches Vre2 extending along the column direction Y. Each of the plurality of second voltage signal line first branches Vre1 is connected to the plurality of second voltage signal line second branches Vre2 via a via.

[0166] For example, as shown in Figures 4, 25, and 26, a second planar layer 119 is provided between the second source / drain metal layer 118 and the third source / drain metal layer 120. The array substrate 10 further includes seventh-type vias H7, which extend through the second planar layer 119. The seventh-type vias H7 include: a first seventh-type via H71, a second seventh-type via H72, and a third seventh-type via H73. The first branch of the second voltage signal line Vre1 is connected to the second branch of the second voltage signal line Vre2 via the third seventh-type via H73.

[0167] It can be understood that the first branch line Vre1 of the second voltage signal line and the second branch line Vre2 of the second voltage signal line are connected to form the second voltage signal line Vre.

[0168] By setting the No. 3 seventh type via H73, the first branch line Vre1 of each second voltage signal line can be connected to the second branch lines Vre2 of multiple second voltage signal lines. In this way, the second voltage signal line Vre used to transmit the second voltage signal forms a grid structure, which facilitates signal transmission, improves signal transmission efficiency, and reduces transmission voltage drop, thereby improving the uniformity of the second voltage signal in different sub-pixel areas A1, which is beneficial to the uniformity of reset and threshold compensation of each pixel driving circuit 200, and improves the picture display effect.

[0169] In some embodiments, as shown in FIG25 , the pixel driving circuits 200 in two rows of sub-pixel regions A1 adjacent to a first branch line of a second voltage signal line Vre1 share the first branch line of the second voltage signal line Vre1. The pixel driving circuits 200 in two columns of sub-pixel regions A1 adjacent to a second branch line of a second voltage signal line Vre2 share the second branch line of the second voltage signal line Vre2.

[0170] For example, as shown in FIG25 , the pixel driving circuits 200 in the row where the first sub-pixel area A11 and the second sub-pixel area A12 are located share a first branch line Vre1 of the second voltage signal line with the pixel driving circuits 200 in the row where the sub-pixel area A1 is located above them. The pixel driving circuits 200 in the row where the third sub-pixel area A13 and the fourth sub-pixel area A14 are located share a first branch line Vre1 of the second voltage signal line with the pixel driving circuits 200 in the row where the sub-pixel area A1 is located below them. Sharing the first branch line Vre1 of the second voltage signal line between the pixel driving circuits 200 in adjacent rows reduces the number of wiring lines for the first branch line Vre1 of the second voltage signal line, making the sub-pixel area A1 more compact, and thus significantly saving space on the array substrate 10.

[0171] The pixel driving circuits 200 in the column where the first sub-pixel area A11 and the third sub-pixel area A13 are located share a second branch line Vre2 of the second voltage signal line with the pixel driving circuits 200 in the column where the sub-pixel area A1 is located to the left of the pixel driving circuits 200. The pixel driving circuits 200 in the column where the second sub-pixel area A12 and the fourth sub-pixel area A14 are located share a second branch line Vre2 of the second voltage signal line with the pixel driving circuits 200 in the column where the sub-pixel area A1 is located to the right of the pixel driving circuits 200. Sharing the second branch line Vre2 of the second voltage signal line between the pixel driving circuits 200 in adjacent columns reduces the number of wiring lines for the second branch line Vre2 of the second voltage signal line, making the sub-pixel area A1 more compact, and thus significantly saving space on the array substrate 10.

[0172] In some embodiments, as shown in FIG. 18 and FIG. 25 , in the sub-pixel region A1 , the second type of transistor includes: a first reset transistor T3 , and an active layer pattern of the first reset transistor T3 is connected to the first branch line Vre1 of the second voltage signal line.

[0173] The active layer of the second type of transistor is located in the second active film layer 114. Therefore, the second active film layer 114 includes the active layer pattern of the first reset transistor T3. Referring to Figure 4, the second active film layer 114 and the second source / drain metal layer 118 are provided with a fourth gate insulating layer 115, a fourth gate metal layer 116, and a second interlayer dielectric layer 117, arranged in that order. The active layer pattern of the first reset transistor T3 located in the second active film layer 114 is connected to the first branch line Vre1 of the second voltage signal line located in the second source / drain metal layer 118. A via needs to penetrate the fourth gate insulating layer 115 and the second interlayer dielectric layer 117.

[0174] Therefore, as shown in Figures 18 and 23, the array substrate 10 further includes sixth-type vias H6, which penetrate the fourth gate insulation layer 115 and the second interlayer dielectric layer 117. The sixth-type vias H6 include: sixth-type via H61 (number 1), sixth-type via H62 (number 2), and sixth-type via H63 (number 3). The active layer pattern of the first reset transistor T3 located in the second active film layer 114 is connected to the first branch line Vre1 of the second voltage signal line located in the second source / drain metal layer 118 via H63 (number 3).

[0175] In some embodiments, as shown in FIG. 18 and FIG. 21 , the second type of transistor further includes a write transistor T2 , and the active layer pattern of the write transistor T2 is connected to the active layer pattern of the first reset transistor T3 .

[0176] As shown in Figure 5, the first electrode of the write transistor T2 is electrically connected to the data signal line Dt, the second electrode of the write transistor T2 is electrically connected to the first node N1, the first electrode of the first reset transistor T3 is electrically connected to the second voltage signal line Vre, and the second electrode of the first reset transistor T3 is electrically connected to the first node N1. By disposing the active layer pattern of the write transistor T2 and the active layer pattern of the first reset transistor T3 on the second active film layer 114, and connecting the active layer pattern of the write transistor T2 and the active layer pattern of the first reset transistor T3, the second electrode of the write transistor T2 and the second electrode of the first reset transistor T3 are directly connected. This arrangement can reduce the number of connection vias and further improve the PPI.

[0177] In some embodiments, as shown in Figures 4, 8, 12, and 14, the pixel driving circuit 200 further includes a capacitor Cst. The array substrate 10 further includes a first gate metal layer 105 and a second gate metal layer 107. The first gate metal layer 105 includes a first plate pattern Cst1 of the capacitor Cst, and the second gate metal layer 107 includes a second plate pattern Cst2 of the capacitor Cst.

[0178] In some examples, as shown in Figures 4, 8, 16 and 18, the array substrate 10 further includes: a first source-drain metal layer 109, the first source-drain metal layer 109 includes a fifth transfer pattern M5, the fifth transfer pattern M5 is connected to the first electrode pattern Cst1 through a via, and the fifth transfer pattern M5 is connected to the active layer pattern of the write transistor T2 through the via, so that the first electrode pattern Cst1 is connected to the active layer pattern of the write transistor T2.

[0179] 4, 8, and 12, a second gate insulating layer 106, a second gate metal layer 107, and a first interlayer dielectric layer 108 are sequentially disposed between the first gate metal layer 105 and the first source / drain metal layer 109. A first plate pattern Cst1 located in the first gate metal layer 105 is connected to a fifth transfer pattern M5 located in the first source / drain metal layer 109, and a via hole is required to penetrate the second gate insulating layer 106 and the first interlayer dielectric layer 108.

[0180] Therefore, as shown in Figures 8 and 15, the array substrate 10 includes a fourth type of via H4, which penetrates the second gate insulation layer 106 and the first interlayer dielectric layer 108. The first plate pattern Cst1 on the first gate metal layer 105 is connected to the fifth transfer pattern M5 on the first source and drain metal layer 109 through the fourth type of via H4.

[0181] 4, 16, and 18, the active layer pattern of the write transistor T2 is located in the second active film layer 114. A first planar layer 110, a second buffer layer 111, a third gate metal layer 112, and a third gate insulating layer 113 are sequentially disposed between the first source / drain metal layer 109 and the second active film layer 114. A fifth transfer pattern M5 located in the first source / drain metal layer 109 is connected to the active layer pattern of the write transistor T2 located in the second active film layer 114. A via hole needs to penetrate the first planar layer 110, the second buffer layer 111, and the third gate insulating layer 113.

[0182] Therefore, as shown in Figures 18 and 20, the array substrate 10 also includes a fifth type of via H5, and the fifth type of via H51 passes through the first flat layer 110, the second buffer layer 111 and the third gate insulation layer 113. The fifth type of via H5 includes: fifth type via No. 1 H51 and fifth type via No. 2 H52. The fifth transfer pattern M5 located in the first source and drain metal layer 109 is connected to the active layer pattern of the write transistor T2 located in the second active film layer 114 through the fifth type via No. 2 H52.

[0183] The fourth type via H4 and the second fifth type via H52 are provided to achieve connection between the first plate pattern Cst1 of the capacitor Cst and the active layer pattern of the write transistor T2.

[0184] 8 and 12 , the first plate pattern Cst1 of the capacitor Cst passes through the active layer pattern of the drive transistor T1 and also serves as the gate of the drive transistor T1. Therefore, the gate of the drive transistor T1 is connected to the active layer pattern of the write transistor T2 via the first plate pattern Cst1 of the capacitor Cst.

[0185] In some embodiments, as shown in Figures 8, 18, 25 and 27, the second active film layer 114 also includes a second transfer pattern M2, and the third source-drain metal layer 120 includes: a data signal line Dt and a fourth transfer pattern M4, the data signal line Dt is connected to the active layer pattern of the write transistor T2 through a first node pattern R1, and the fourth transfer pattern M4 is connected to the second transfer pattern M2 through a second node pattern R2.

[0186] The first node pattern R1 connecting the data signal line Dt and the active layer pattern of the write transistor T2 is described below.

[0187] 4 , 18 and 25 , the active layer pattern of the write transistor T2 is located in the second active film layer 114 , the data signal line Dt is located in the third source-drain metal layer 120 , and a fourth gate insulating layer 115 , a fourth gate metal layer 116 , a second interlayer dielectric layer 117 , a second source-drain metal layer 118 and a second planarizing layer 119 are sequentially arranged between the second active film layer 114 and the third source-drain metal layer 120 .

[0188] As shown in Figures 18, 23, and 24, the array substrate 10 further includes sixth-type vias H6, which penetrate the fourth gate insulation layer 115 and the second interlayer dielectric layer 117. The sixth-type vias H6 include: a first sixth-type via H61, a second sixth-type via H62, and a third sixth-type via H63. The second source-drain metal layer 118 includes a sixth transfer pattern M6. The active layer pattern of the write transistor T2 is connected to the sixth transfer pattern M6 via the second sixth-type via H62.

[0189] As shown in Figures 25 and 26, the array substrate 10 also includes seventh-type vias H7, which extend through the second planar layer 119. The seventh-type vias H7 include: a first seventh-type via H71, a second seventh-type via H72, and a third seventh-type via H73. The sixth transfer pattern M6 is connected to the data signal line Dt via the second seventh-type via H72.

[0190] Therefore, the active layer pattern of the write transistor T2 located in the second active film layer 114 is connected to the data signal line Dt located in the third source and drain metal layer 120 through the second sixth-category via H62, the sixth transfer pattern M6 and the second seventh-category via H72. That is, the connection pattern formed by the connected second sixth-category via H62 and the second seventh-category via H72 is the first node pattern R1.

[0191] The second node pattern R2 connecting the fourth transition pattern M4 and the second transition pattern M2 is introduced below.

[0192] 25 and 28 , the fourth transfer pattern M4 is used to connect to the anode pattern 4011. Specifically, the array substrate 10 further includes an eighth type of via H8, which penetrates the third planar layer 30. The fourth transfer pattern M4 and the anode pattern 4011 are connected via the eighth type of via H8.

[0193] As can be seen from the above description regarding the connection between the fourth transfer pattern M4 and the active layer pattern of the second reset transistor T4, the connection between the fourth transfer pattern M4 and the second transfer pattern M2 is intended to connect the active layer pattern of the second reset transistor T4 to the anode pattern 4011. The connection between the fourth transfer pattern M4 and the active layer pattern of the second reset transistor T4 can be referred to above and will not be further described here.

[0194] Therefore, from the above introduction about the connection between the fourth transfer pattern M4 and the active layer pattern of the second reset transistor T4, it can be seen that, as shown in Figures 4, 18, 24, 25 and 27, the second transfer pattern M2 is located in the second active film layer 114, the third transfer pattern M3 is located in the second source and drain metal layer 118, and the second transfer pattern M2 and the third transfer pattern M3 are connected through the first sixth type via H61; the fourth transfer pattern M4 is located in the third source and drain metal layer 120, and the third transfer pattern M3 and the fourth transfer pattern M4 are connected through the first seventh type via H71.

[0195] That is, the connection pattern formed by the connected first sixth-type via H61 and the first seventh-type via H71 is the second node pattern R2.

[0196] As shown in FIG18 , along the row direction X, the ratio of the dimension d1 between the first node pattern R1 and the second node pattern R2 to the dimension d2 of the film layer pattern in the sub-pixel area A1 is greater than or equal to 30%.

[0197] Along the row direction X, the dimension d1 between the first node pattern R1 and the second node pattern R2 can be the minimum value of the distance between the first node pattern R1 and the second node pattern R2, or can be the distance between the centers of the first node pattern R1 and the second node pattern R2 along the third direction Z, wherein the third direction Z is a direction perpendicular to the plane where the multiple rows and columns of the multiple pixel driving circuits 200 are arranged.

[0198] Exemplarily, as shown in FIG. 18 , along the row direction X, a dimension d1 between the first node pattern R1 and the second node pattern R2 is represented as a distance between centers of the first node pattern R1 and the second node pattern R2 along the third direction Z.

[0199] For example, along the row direction X, the ratio of the dimension d1 between the first node pattern R1 and the second node pattern R2 to the dimension d2 of the film layer pattern in the sub-pixel area A1 is 30%, 40%, 50%, 60%, 70%, 80%, or 90%, etc., which is not limited here.

[0200] By setting the ratio of the dimension d1 between the first node pattern R1 and the second node pattern R2 to the dimension d2 of the film layer pattern of the sub-pixel area A1 to be greater than or equal to 30% along the row direction X, it can be ensured that the first node pattern R1 and the second node pattern R2 are as far apart as possible. In other words, the writing node for the active layer pattern data signal of the writing transistor T2 is as far away as possible from the writing node for the anode voltage signal of the light-emitting device OLED, which can reduce parasitic capacitance and avoid signal crosstalk.

[0201] It should be noted that the meaning of parasitic is that the capacitance is not originally designed here, but since there is always mutual capacitance between the wirings, the mutual capacitance can be considered to be parasitic between the wirings, so it is called parasitic capacitance, also known as stray capacitance.

[0202] In some embodiments, as shown in Figures 4, 18, 19, and 22, the array substrate 10 further includes a third gate metal layer 112 disposed between the first active film layer 103 and the second active film layer 114. Specifically, the third gate metal layer 112 is disposed between the first source / drain metal layer 109 and the second active film layer 114. The array substrate 10 further includes a fourth gate metal layer 116 disposed between the second active film layer 114 and the second source / drain metal layer 118. The third gate metal layer 112 includes a first branch line G11 of a first scan signal line and a first branch line G21 of a second scan signal line. The fourth gate metal layer 116 includes a second branch line G12 of a first scan signal line and a second branch line G22 of a first scan signal line. The first branch line G11 and the second branch line G12 of the first scan signal line pass through the active layer pattern of the first reset transistor T3, while the first branch line G21 and the second branch line G22 of the second scan signal line pass through the active layer pattern of the write transistor T2. The first branch line G11 of the first scanning signal line is electrically connected to the second branch line G12 of the first scanning signal line. The first branch line G21 of the second scanning signal line is electrically connected to the second branch line G22 of the second scanning signal line.

[0203] The first branch line G11 and the second branch line G12 of the first scan signal line pass through the active layer pattern of the first reset transistor T3 to serve as the gate of the first reset transistor T3. The first branch line G11 and the second branch line G12 of the first scan signal line are electrically connected to form a first scan signal line G1. The first scan signal line G1 is used to transmit a first scan signal g1 to the gate of the first reset transistor T3. The first branch line G21 and the second branch line G22 of the second scan signal line pass through the active layer pattern of the write transistor T2 to serve as the gate of the write transistor T2. The first branch line G21 and the second branch line G22 of the second scan signal line are electrically connected to form a second scan signal line G2. The second scan signal line G2 is used to transmit a second scan signal g2 to the gate of the write transistor T2.

[0204] By setting up two branches, the first scanning signal g1 is applied to both the upper and lower sides of the active layer pattern of the first reset transistor T3, and the second scanning signal g2 is applied to both the upper and lower sides of the active layer pattern of the write transistor T2. This can enhance the strength of the scanning signal received by the transistors, increase the degree of conductivity of the channel regions of the active layer patterns of the first reset transistor T3 and the write transistor T2, and provide better control over the conduction and cutoff of the first reset transistor T3 and the write transistor T2.

[0205] As shown in FIG4 , an embodiment of the present disclosure further provides a display panel 100, which includes the array substrate 10 provided in any of the above embodiments. Therefore, the display panel 100 provided in the embodiment of the present disclosure has all the benefits of the array substrate 10 provided in any of the above embodiments, which will not be described in detail here.

[0206] In some embodiments, referring to FIG4 , FIG25 , and FIG29 , the display panel 100 further includes an anode layer 401 disposed on a side of the third source / drain metal layer 120 of the array substrate 10 away from the base substrate 101. The anode layer 401 includes a plurality of anode patterns 4011. The display panel 100 further includes a pixel defining layer 402, a light emitting layer 403, and a cathode layer disposed on a side of the anode layer 401 away from the base substrate 101. One of the anode patterns 4011 is connected to a fourth transfer pattern M4 of the third source / drain metal layer 120 via a via.

[0207] As shown in FIG4 , FIG25 and FIG28 , the anode pattern 4011 and the fourth transfer pattern M4 are connected via an eighth type of via H8 penetrating the third planar layer 30. This connects the second electrode of the driving transistor T1, the second electrode of the second reset transistor T4, the second plate Cst2 of the capacitor Cst, and the anode of the light-emitting device OLED. For details, refer to the above description and will not be repeated here.

[0208] In some embodiments, as shown in Figures 4, 25, and 30, the light-emitting layer 403 includes a plurality of light-emitting portions 4031, each of which overlaps with an anode pattern 4011. A plurality of pixel openings are formed in the pixel-defining layer 402, each of which exposes a portion of an anode pattern 4011. The light-emitting portions 4031 in the light-emitting layer 403 are disposed within the pixel openings in a one-to-one correspondence.

[0209] The cathode layer is located on a side of the pixel defining layer 402 and the light emitting layer 403 away from the array substrate 10 .

[0210] The display panel 100 also includes an encapsulation layer, which is located on the side of the cathode layer away from the array substrate 10. Exemplarily, the encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. The encapsulation layer is used to encapsulate the light-emitting device to protect the light-emitting device OLED and avoid corrosion caused by external water and oxygen.

[0211] As shown in FIG1 , some embodiments of the present disclosure provide a display device 1000 , which includes: a display panel 100 as described in any of the above embodiments; and a driver chip for driving the display panel 100 for display.

[0212] The display device may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), an in-vehicle computer, a wearable display device, or the like. The embodiments of the present disclosure do not impose any particular restrictions on the specific form of the above-mentioned display device. The display device 1000 includes the display panel 100 provided in any of the above-mentioned embodiments. Therefore, the display device 1000 provided in the embodiments of the present disclosure has all the beneficial effects of the display panel 100 provided in any of the above-mentioned embodiments, which will not be described in detail here.

[0213] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising: Multiple sub-pixel regions, each sub-pixel region is provided with a pixel driving circuit, and the multiple pixel driving circuits are arranged in multiple rows and multiple columns. Each pixel driving circuit among the multiple pixel driving circuits includes multiple first-type transistors and multiple second-type transistors; The array substrate includes: A substrate; A first active film layer disposed on one side of the substrate; the first active film layer includes active layer patterns of the multiple first-type transistors; A second active film layer disposed on the side of the first active film layer away from the substrate, the second active film layer includes active layer patterns of the multiple second-type transistors; Moreover, the film layer patterns of adjacent row sub-pixel regions are mirror-symmetrically arranged, and the film layer patterns of adjacent column sub-pixel regions are mirror-symmetrically arranged; The array substrate further includes: Multiple DC signal lines. The pixel driving circuits of two columns of the sub-pixel regions adjacent to one of the multiple DC signal lines share this DC signal line; the pixel driving circuits of two rows of the sub-pixel regions adjacent to one of the multiple DC signal lines share this DC signal line.

2. The array substrate according to claim 1, further including: A shielding layer disposed between the substrate and the first active film layer, the shielding layer includes multiple first branch lines of the first voltage signal line extending along the column direction and multiple first branch lines of the initialization signal line; A second gate metal layer disposed between the first active film layer and the second active film layer, the second gate metal layer includes multiple second branch lines of the first voltage signal line extending along the row direction and multiple second branch lines of the initialization signal line; Each of the multiple second branch lines of the first voltage signal line is connected to each of the multiple first branch lines of the first voltage signal line through a via; each of the multiple second branch lines of the initialization signal line is connected to each of the multiple first branch lines of the initialization signal line through a via.

3. The array substrate according to claim 2, wherein, The pixel driving circuits of two columns of the sub-pixel regions adjacent to one of the first voltage signal line first branch lines share this first voltage signal line first branch line; The pixel driving circuits of two rows of the sub-pixel regions adjacent to one of the first voltage signal line second branch lines share this first voltage signal line second branch line.

4. The array substrate according to claim 2 or 3, wherein, The pixel driving circuits of two columns of the sub-pixel regions adjacent to one of the initialization signal line first branch lines share this initialization signal line first branch line; The pixel driving circuits of two rows of the sub-pixel regions adjacent to one of the initialization signal line second branch lines share this initialization signal line second branch line.

5. The array substrate according to any one of claims 2 to 4, wherein, In the sub-pixel region, the first-type transistors include: a light-emitting control transistor and a second reset transistor; The active layer pattern of the light-emitting control transistor is connected to the second branch line of the first voltage signal line; the active layer pattern of the second reset transistor is connected to the second branch line of the initialization signal line.

6. The array substrate according to claim 5, wherein, The first type of transistor further includes: a driving transistor, and the active layer patterns of the light-emitting control transistor, the driving transistor, and the second reset transistor are connected in sequence; The pixel driving circuit further includes a capacitor; the second gate metal layer further includes a second electrode pattern of the capacitor; The array substrate further includes: A first gate metal layer disposed between the first active film layer and the second gate metal layer, and the first gate metal layer includes: a first electrode pattern of the capacitor; A first source-drain metal layer disposed between the second gate metal layer and the second active film layer, and the first source-drain metal layer includes a first transfer pattern, and the first transfer pattern is connected to the active layer pattern of the second reset transistor through a via, and is simultaneously connected to the second electrode pattern of the capacitor.

7. The array substrate according to claim 6, further including: A second source-drain metal layer disposed on a side of the second active film layer away from the substrate, and the second source-drain metal layer includes a third transfer pattern; A third source-drain metal layer disposed on a side of the second source-drain metal layer away from the substrate, and the third source-drain metal layer includes a fourth transfer pattern; The second active film layer further includes a second transfer pattern; The first transfer pattern, the second transfer pattern, the third transfer pattern, and the fourth transfer pattern are connected in sequence through vias.

8. The array substrate according to claim 6 or 7, wherein, The first gate metal layer further includes: a light-emitting control signal line and a reset signal line; The light-emitting control signal line passes through the active layer pattern of the light-emitting control transistor, and the reset signal line passes through the active layer pattern of the second reset transistor.

9. The array substrate according to any one of claims 6 to 8, wherein The shielding layer further includes: a first light-shielding pattern; the first light-shielding pattern is connected to the first branch of the first voltage signal line, and the orthographic projection of the driving transistor on the substrate is located within the orthographic projection of the first light-shielding pattern on the substrate; and / or, The shielding layer further includes: a second light-shielding pattern, the second light-shielding pattern is connected to the first branch of the first voltage signal line, and the orthographic projection of the second reset transistor on the substrate is located within the orthographic projection of the second light-shielding pattern on the substrate.

10. The array substrate according to any one of claims 1 to 9, further including: A second source-drain metal layer disposed on a side of the second active film layer away from the substrate, and the second source-drain metal layer includes a plurality of first branches of the second voltage signal lines extending along the row direction; A third source-drain metal layer disposed on a side of the second source-drain metal layer away from the substrate, and the third source-drain metal layer includes a plurality of second branches of the second voltage signal lines extending along the column direction; Each of the plurality of first branches of the second voltage signal lines is connected to the plurality of second branches of the second voltage signal lines through vias.

11. The array substrate according to claim 10, wherein The pixel driving circuits of two rows of the sub-pixel regions adjacent to a first branch of the second voltage signal line share the first branch of the second voltage signal line; The pixel driving circuits of two columns of the sub-pixel regions adjacent to a second branch of the second voltage signal line share the second branch of the second voltage signal line.

12. The array substrate according to claim 10 or 11, wherein, In the sub-pixel region, the second type of transistor includes: a first reset transistor; an active layer pattern of the first reset transistor is connected to the first branch of the second voltage signal line.

13. The array substrate according to claim 12, wherein, The second type of transistor further includes: a writing transistor; an active layer pattern of the writing transistor is connected to the active layer pattern of the first reset transistor.

14. The array substrate according to claim 13, wherein, The pixel driving circuit further includes a capacitor; The array substrate further includes: a first gate metal layer disposed between the first active film layer and the second active film layer, the first gate metal layer including: a first plate pattern of the capacitor; a first source-drain metal layer disposed between the first gate metal layer and the second active film layer, the first source-drain metal layer including a fifth transfer pattern; The fifth transfer pattern is connected to the first plate pattern through a via hole, and the fifth transfer pattern is connected to the active layer pattern of the writing transistor through a via hole, so that the first plate pattern is connected to the active layer pattern of the writing transistor.

15. The array substrate according to claim 13 or 14, wherein, The second active film layer further includes a second transfer pattern; The third source-drain metal layer includes: a data signal line and a fourth transfer pattern, the data signal line is connected to the active layer pattern of the writing transistor through a first node pattern, and the fourth transfer pattern is connected to the second transfer pattern through a second node pattern; Wherein, along the row direction, the ratio of the size between the first node pattern and the second node pattern to the size of the sub-pixel region film layer pattern is greater than or equal to 30%.

16. The array substrate according to any one of claims 13 to 15, further includes: a third gate metal layer disposed between the first active film layer and the second active film layer; a fourth gate metal layer disposed between the second active film layer and the second source-drain metal layer; Wherein, the third gate metal layer includes a first branch of the first scan signal line and a first branch of the second scan signal line, the fourth gate metal layer includes a second branch of the first scan signal line and a second branch of the second scan signal line, the first branch of the first scan signal line and the second branch of the first scan signal line pass through the active layer pattern of the first reset transistor, and the first branch of the second scan signal line and the second branch of the second scan signal line pass through the active layer pattern of the writing transistor; The first branch of the first scan signal line and the second branch of the first scan signal line are electrically connected; the first branch of the second scan signal line and the second branch of the second scan signal line are electrically connected.

17. The array substrate according to any one of claims 1 to 16, wherein, The first active film layer is a low-temperature polycrystalline silicon layer, and the second active film layer is an oxide layer.

18. The array substrate according to any one of claims 1 to 17 further includes: a first planarization layer disposed between the first active film layer and the second active film layer; The material of the first planarization layer includes an organic material, and the thickness range of the first planarization layer is 1.5 μm to 2 μm; or, The material of the first flat layer includes an inorganic material, and the thickness range of the first flat layer is 1.2 μm to 1.5 μm.

19. A display panel, comprising: The array substrate according to any one of claims 1 to 18; Further comprising: An anode layer disposed on the side of the third source-drain metal layer of the array substrate away from the substrate, the anode layer including a plurality of anode patterns; A pixel defining layer disposed on the side of the anode layer away from the substrate; Wherein, one anode pattern among the plurality of anode patterns is connected to one fourth transfer pattern of the third source-drain metal layer through a via hole.

20. A display device, comprising: The display panel according to claim 19; A driving chip for driving the display panel to display.

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