A chip clock correction method, circuit, system, device and storage medium

Abstract

The present invention discloses a chip clock correction method, circuit, system, device and storage medium, and relates to the field of chip technology. The present invention realizes the correction of the timer in the chip by constructing a calibration curve and several neural network models for each clock in the chip, receiving a pulse width signal from the outside once, through the pulse width signal sent between two timers, and combining the calibration curve and the neural network model. Compared with the prior art that requires an external device to send multiple pulse widths, the present invention only needs to receive a pulse width level once, which greatly reduces the hardware conditions for chip correction; a pulse width level is combined with the chip calibration curve and the neural network model, and the clocks inside the chip are adjusted to each other, which improves the speed of chip adjustment, thereby efficiently correcting the chip clock; it ensures that the chip clock will not be in an offset state for a long time, thereby ensuring the stable operation of the chip.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip clock correction method, circuit, system, device and storage medium. Background Art

[0002] MCU chips are generally configured with two clocks, a high-speed clock and a low-speed clock. During the use of the chip, the clock may be offset due to various reasons; this will affect the normal operation of the chip. Clock offset may cause timing errors in the transmission of data between registers, resulting in calculation errors, data loss or system instability. In addition, clock offset may also limit the maximum operating frequency that the chip can achieve.

[0003] In the current research on the correction of the MCU chip clock, it is necessary to re-assign the tr im register in the chip; if the tr im register is to be accurately assigned, it is necessary to send multiple pulse widths to allow the MCU to correct the deviation multiple times, which involves multiple operations of external devices other than the MCU chip, resulting in the need to increase additional correction time, thereby reducing the correction efficiency of the MCU chip clock. Therefore, the correction of the chip clock in the prior art is too complicated and the correction efficiency is low. At present, a new chip clock correction method is urgently needed to solve the defects of the prior art. Summary of the invention

[0004] The present invention provides a chip clock correction method, circuit, system, device and storage medium to solve the technical problem of how to efficiently correct the chip clock.

[0005] In order to solve the above technical problem, an embodiment of the present invention provides a chip clock correction method, which is applied to the correction of a first timer and a second timer, and specifically includes the following steps:

[0006] acquiring a second calibration curve and a plurality of neural network models for the second timer;

[0007] Inputting a preset initial pulse width signal into the first timer so that the first timer outputs a first pulse width signal;

[0008] Inputting the first pulse width signal into a second timer so that the second timer acquires a second pulse width signal;

[0009] Based on the initial pulse width signal and the second pulse width signal, obtaining a first comparison result;

[0010] Based on the first comparison result, the clock of the second timer is corrected according to the second calibration curve and a plurality of neural network models.

[0011] It can be understood that, compared with the prior art, the present invention realizes the correction of the timer in the chip by constructing a calibration curve and several neural network models for each clock in the chip, receiving a pulse width signal from the outside once, through the pulse width signal sent between two timers, and combining the calibration curve and the neural network model. Compared with the prior art that requires the external device to send multiple pulse widths, the present invention only needs to receive the pulse width level once, which greatly reduces the hardware conditions for chip correction; the pulse width level is combined with the calibration curve and neural network model of the chip once, and the clock inside the chip is adjusted to each other, which improves the speed of chip adjustment, thereby efficiently correcting the chip clock; it ensures that the chip clock will not be in an offset state for a long time, thereby ensuring the stable operation of the chip.

[0012] As a preferred solution, the obtaining of the second calibration curve and the plurality of neural network models of the second timer specifically includes:

[0013] The chip comprises: a register;

[0014] Perform simulation based on the register and the second timer to obtain a second calibration curve;

[0015] According to the second calibration curve, a first neural network model and a second neural network model are constructed.

[0016] By using the simulation data of the second timer and the register, a second calibration curve is obtained, and then a neural network model is constructed based on the second calibration curve. This can fully explore the relationship between the clock frequency of the second timer and the calibration register, so as to more accurately adjust the register and thus achieve adjustment of the second timer.

[0017] As a preferred solution, obtaining a first comparison result based on the initial pulse width signal and the second pulse width signal specifically includes:

[0018] According to the initial pulse width signal, an initial pulse width value is obtained;

[0019] According to the second pulse width signal, obtaining a second pulse width value;

[0020] The initial pulse width value and the second pulse width value are compared to obtain a first comparison result.

[0021] By receiving an initial pulse width signal from the outside once and comparing the pulse width values ​​of the pulse width signals transmitted between timers, a preliminary judgment basis is provided for the subsequent adjustment of the second clock; the signal transmission of the two timers avoids the situation in the prior art where multiple reception of external pulse width levels is required, thereby improving the correction efficiency of the chip clock.

[0022] As a preferred solution, based on the first comparison result, the clock of the second timer is corrected according to the second calibration curve and a plurality of neural network models, specifically including:

[0023] Obtaining the residual value and the rated value of the second timer;

[0024] When the first comparison result is unequal, obtaining an initial calibration value of the current register;

[0025] Determine an initial clock value based on the second calibration curve in combination with the initial calibration value;

[0026] comparing the initial calibration value and the rated value to obtain a second comparison result;

[0027] Determine a first calibration value based on the second comparison result in combination with the first neural network model or the second neural network model;

[0028] Determine a register adjustment value according to the first calibration value and in combination with the second calibration curve to adjust the register, thereby modifying the clock of the second timer;

[0029] The clock of the second timer is modified and the first comparison result is updated until the first comparison result is equal.

[0030] By combining the second correction, the first neural network model and the second neural network model according to the initial calibration value of the current register, the register is adjusted, and then the clock of the second timer is modified. The accurate register adjustment value can be efficiently calculated through the calibration curve and the neural network model, thereby achieving efficient and accurate correction of the clock of the second timer.

[0031] As a preferred solution, determining the first calibration value according to the second comparison result in combination with the first neural network model or the second neural network model specifically includes:

[0032] According to the initial calibration value, a theoretical calibration value is determined;

[0033] When the second comparison result is that the initial calibration value is lower than the rated value, the initial calibration value, the theoretical calibration value and the initial clock value are input into the first neural network model;

[0034] When the second comparison result is that the initial calibration value is higher than the rated value, the initial calibration value, the theoretical calibration value and the initial clock value are input into the second neural network model;

[0035] A first calibration value output by the first neural network model or the second neural network model is obtained according to the residual value and the rated value.

[0036] By comparing the initial calibration value with the rated value, the offset of the second timer can be determined, and then a more appropriate neural network model can be selected to obtain a predicted calibration value.

[0037] As a preferred solution, determining a register adjustment value according to the first calibration value in combination with the second calibration curve to adjust the register and thereby modify the clock of the second timer specifically includes:

[0038] Determining a forward differential clock value and a backward differential clock value of an initial calibration value according to a second calibration curve;

[0039] According to the second comparison result, the register adjustment value is determined in combination with the forward differential clock value and the backward differential clock value:

[0040]

[0041] Among them, A d is the register adjustment value, F is the first calibration value, R is the rated value, when the second comparison result is that the initial calibration value is greater than the rated value, diff is the backward differential clock value; when the second comparison result is that the initial calibration value is less than the rated value, diff is the forward differential clock value;

[0042] The register is adjusted according to the register adjustment value, thereby modifying the clock of the second timer.

[0043] The forward differential clock value and the backward differential clock value are determined by the calibration curve, and then the register adjustment value is determined, so that the register can be accurately adjusted, thereby achieving accurate adjustment of the timer clock.

[0044] Accordingly, an embodiment of the present invention provides a chip clock correction circuit, comprising: an acquisition module, a processor module and a drive module;

[0045] The signal output end of the acquisition module is electrically connected to the input end of the processor module;

[0046] The output end of the processor module is electrically connected to the control end of the drive module;

[0047] Wherein, the acquisition module is based on a second calibration curve for a second timer and a plurality of neural network models;

[0048] The processor module is used to input the initial pulse width signal into the first timer, and then input the first pulse width signal output by the first timer into the second timer, so that the second timer obtains the second pulse width signal, and then obtains a first comparison result according to the initial pulse width signal and the second pulse width signal, thereby outputting a driving instruction for the second timer;

[0049] The driving module is used to complete the correction of the clock of the second timer according to the driving instruction.

[0050] It can be understood that, compared with the prior art, this circuit realizes the correction of the timer in the chip by constructing the calibration curve and several neural network models of each clock in the chip, receiving a pulse width signal from the outside once, and sending the pulse width signal between two timers, and combining the calibration curve and the neural network model. Compared with the prior art that requires the external device to send multiple pulse widths, this circuit only needs to receive the pulse width level once, which greatly reduces the hardware conditions for chip correction; with a pulse width level combined with the calibration curve and neural network model of the chip, the chip adjustment speed is improved through the mutual adjustment of the clocks inside the chip, so as to efficiently correct the chip clock; it ensures that the chip clock will not be in an offset state for a long time, thereby ensuring the stable operation of the chip.

[0051] Accordingly, an embodiment of the present invention provides a chip clock correction system, comprising: a chip and a chip clock correction circuit as described above;

[0052] The chip includes: a first timer, a second timer and a register;

[0053] The first output terminal of the register is electrically connected to the first input terminal of the first timer;

[0054] The second output terminal of the register is electrically connected to the first input terminal of the second timer;

[0055] The third output terminal of the register is electrically connected to the input terminal of the acquisition module;

[0056] The input end of the register is electrically connected to the output end of the driving module;

[0057] The first timer and the second timer are electrically connected;

[0058] The acquisition module is used to acquire a second calibration curve of a second timer and a plurality of neural network models;

[0059] The processor module is used to input the initial pulse width signal into the first timer, and then input the first pulse width signal output by the first timer into the second timer, so that the second timer obtains the second pulse width signal, and then obtains a first comparison result according to the initial pulse width signal and the second pulse width signal, thereby outputting a driving instruction for the second timer;

[0060] The driving module is used to complete the correction of the clock of the second timer according to the driving instruction.

[0061] Accordingly, an embodiment of the present invention provides a terminal device, including:

[0062] one or more processors;

[0063] A memory, coupled to the processor, for storing one or more programs;

[0064] When the one or more programs are executed by the one or more processors, the one or more processors implement the chip clock correction method as described above.

[0065] Accordingly, an embodiment of the present invention provides a computer-readable storage medium on which a computer program is stored. The computer program is executed by a processor to implement the chip clock correction method as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1 : A flowchart of a chip clock correction method provided by an embodiment of the present invention;

[0067] Figure 2 : A connection diagram of a chip clock correction circuit provided by an embodiment of the present invention;

[0068] Figure 3 : A schematic diagram of the structure of a chip clock correction system provided by an embodiment of the present invention;

[0069] Among them, 201: acquisition module; 202: processor module; 203: drive module; 301: first timer; 302: second timer; 303: register. DETAILED DESCRIPTION

[0070] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0071] It should be noted that the chip described in the present invention refers to an MCU chip, and the MCU (Microcontroller Unit) chip is a single-chip microcomputer or a single-chip microcomputer; it is an integrated circuit chip that integrates devices such as a CPU, a memory, a timer, and a counter; the MCU chip can receive an input signal and control the operation of an external device according to the input signal. The MCU chip to be corrected by the present invention is generally configured with two clocks inside: a high-speed clock and a low-speed clock. Specifically, the general timer (GTIM) inside the MCU chip usually uses a high-speed clock (RCH); the low-power timer (LPTI M) inside the MCU chip usually uses a low-speed clock (RCL). The register of the MCU chip described in the present invention is a trim register, i.e., a calibration register, and the modification of the timer can be achieved by changing the value of the register.

[0072] In the following embodiments, the first timer and the second timer may include: when the first timer is a general timer, the second timer is a low power timer; when the first timer is a low power timer, the second timer is a general timer. Therefore, the present invention does not specifically limit the specific type of the first timer or the second timer, that is, the present invention can implement clock correction of any general timer or low power timer, and the specific implementation method is shown in the following embodiments.

[0073] Embodiment 1

[0074] Please refer to Figure 1 , is a step flow chart of a chip clock correction method provided by an embodiment of the present invention, including steps S101-S105.

[0075] Step S101: Obtain a second calibration curve and several neural network models of the second timer.

[0076] In this embodiment, the obtaining of the second calibration curve and the plurality of neural network models of the second timer specifically includes:

[0077] The chip comprises: a register;

[0078] Perform simulation based on the register and the second timer to obtain a second calibration curve;

[0079] According to the second calibration curve, a first neural network model and a second neural network model are constructed.

[0080] By using the simulation data of the second timer and the register, a second calibration curve is obtained, and then a neural network model is constructed based on the second calibration curve. This can fully explore the relationship between the clock frequency of the second timer and the calibration register, so as to more accurately adjust the register and thus achieve adjustment of the second timer.

[0081] In an optional embodiment, the performing simulation based on the register and the second timer to obtain the second calibration curve specifically includes:

[0082] Get the simulation data of the register and the second timer to get the second calibration curve. The points on the second calibration curve are (x1, y1), (x2, y2).....(x n ,y n ), wherein x1, x2, etc. are the values ​​of the tr im register, y1, y2, etc. are the clock frequencies of the second timer, wherein the simulation data of the register and the second timer refers to the simulation data obtained by the chip technicians during the design of the MCU chip.

[0083] In an optional embodiment, constructing the first neural network model and the second neural network model according to the second calibration curve refers to setting the input to [x n-1 ,x n ,y n-1 ], the output is set to y n , establish the first neural network model; set the input to [x n ,x n-1 ,y n ], the output is set to y n-1 , establish a second neural network model; the first neural network model and the second neural network model are calibration curve characteristics of the second calibration curve, which are saved in the flash of the MCU chip; the first neural network model is increasing, and the second neural network model is decreasing.

[0084] Step S102: inputting a preset initial pulse width signal into a first timer, so that the first timer outputs a first pulse width signal.

[0085] Step S103: input the first pulse width signal into a second timer, so that the second timer obtains a second pulse width signal.

[0086] Step S104: obtaining a first comparison result based on the initial pulse width signal and the second pulse width signal.

[0087] In this embodiment, obtaining a first comparison result based on the initial pulse width signal and the second pulse width signal specifically includes:

[0088] According to the initial pulse width signal, an initial pulse width value is obtained;

[0089] According to the second pulse width signal, obtaining a second pulse width value;

[0090] The initial pulse width value and the second pulse width value are compared to obtain a first comparison result.

[0091] By receiving an initial pulse width signal from the outside once and comparing the pulse width values ​​of the pulse width signals transmitted between timers, a preliminary judgment basis is provided for the subsequent adjustment of the second clock; the signal transmission of the two timers avoids the situation in the prior art where multiple reception of external pulse width levels is required, thereby improving the correction efficiency of the chip clock.

[0092] In an optional embodiment, a first timer is used to receive an initial pulse width signal of a standard length sent externally, and its length is recorded in a counter CNT of the MCU chip to obtain an initial pulse width value; then the first timer is controlled to send a first pulse width signal with a pulse width length equal to the initial pulse width value, and the second timer is used to receive it, and its length is recorded in a counter CNT of the MCU chip to obtain a second pulse width value; the initial pulse width value and the second pulse width value are compared to obtain a first comparison result. When the first comparison result is not equal, it indicates that the second timer has been offset, and the second timer needs to be corrected.

[0093] It should be noted that the use of the first timer to receive an initial pulse width signal of a standard length sent externally, wherein the standard length refers to the pulse width length that the receiver of the initial pulse width signal can receive in advance from the sender. For example, if the receiver's pin is normally at a high level, the pulse width signal sent by the external sender can be a low-level pulse width signal; recording the length in the counter CNT of the MCU chip refers to calculating the relevant pulse width length according to the following formula: counter CNT*timer clock frequency=pulse width length.

[0094] Step S105: Based on the first comparison result, the clock of the second timer is calibrated according to the second calibration curve and a plurality of neural network models.

[0095] In this embodiment, based on the first comparison result, the second timer is calibrated according to the second calibration curve and a plurality of neural network models, specifically including:

[0096] Obtaining the residual value and the rated value of the second timer;

[0097] When the first comparison result is unequal, obtaining an initial calibration value of the current register;

[0098] Determine an initial clock value based on the second calibration curve in combination with the initial calibration value;

[0099] comparing the initial calibration value and the rated value to obtain a second comparison result;

[0100] Determine a first calibration value based on the second comparison result in combination with the first neural network model or the second neural network model;

[0101] Determine a register adjustment value according to the first calibration value and in combination with the second calibration curve to adjust the register, thereby modifying the clock of the second timer;

[0102] The clock of the second timer is modified and the first comparison result is updated until the first comparison result is equal.

[0103] By combining the second correction, the first neural network model and the second neural network model according to the initial calibration value of the current register, the register is adjusted, and then the clock of the second timer is modified. The accurate register adjustment value can be efficiently calculated through the calibration curve and the neural network model, thereby achieving efficient and accurate correction of the clock of the second timer.

[0104] In this embodiment, determining the first calibration value according to the second comparison result in combination with the first neural network model or the second neural network model specifically includes:

[0105] According to the initial calibration value, a theoretical calibration value is determined;

[0106] When the second comparison result is that the initial calibration value is lower than the rated value, the initial calibration value, the theoretical calibration value and the initial clock value are input into the first neural network model;

[0107] When the second comparison result is that the initial calibration value is higher than the rated value, the initial calibration value, the theoretical calibration value and the initial clock value are input into the second neural network model;

[0108] A first calibration value output by the first neural network model or the second neural network model is obtained according to the residual value and the rated value.

[0109] By comparing the initial calibration value with the rated value, the offset of the second timer can be determined, and then a more appropriate neural network model can be selected to obtain a predicted calibration value.

[0110] In this embodiment, determining the register adjustment value according to the first calibration value in combination with the second calibration curve to adjust the register and thereby modify the clock of the second timer specifically includes:

[0111] Determining a forward differential clock value and a backward differential clock value of an initial calibration value according to a second calibration curve;

[0112] According to the second comparison result, the register adjustment value is determined in combination with the forward differential clock value and the backward differential clock value:

[0113]

[0114] Among them, A d is the register adjustment value, F is the first calibration value, R is the rated value, when the second comparison result is that the initial calibration value is greater than the rated value, diff is the backward differential clock value; when the second comparison result is that the initial calibration value is less than the rated value, diff is the forward differential clock value;

[0115] The register is adjusted according to the register adjustment value, thereby modifying the clock of the second timer.

[0116] The forward differential clock value and the backward differential clock value are determined by the calibration curve, and then the register adjustment value is determined, so that the register can be accurately adjusted, thereby achieving accurate adjustment of the timer clock.

[0117] In an optional embodiment, determining the initial clock value according to the second calibration curve in combination with the initial calibration value specifically includes: searching for the initial clock value corresponding to the point of the initial calibration value on the second correction curve according to the initial calibration value.

[0118] In an optional embodiment, the initial calibration value and the rated value are compared to obtain a second comparison result. Since the first comparison result is not equal, it means that the second comparison result will not be equal.

[0119] In an optional embodiment, determining the first calibration value according to the second comparison result in combination with the first neural network model or the second neural network model specifically includes:

[0120] When the second comparison result is that the initial calibration value is lower than the rated value, the initial calibration value (expressed as trim1), the theoretical calibration value (expressed as trim2) and the initial clock value (expressed as current RCH) are input into the first neural network model as [trim1 trim2 current RCH];

[0121] When the second comparison result is that the initial calibration value is higher than the rated value, the initial calibration value (expressed as trim1), the theoretical calibration value (expressed as trim2) and the initial clock value (expressed as current RCH) are input into the second neural network model as [trim1 trim2 current RCH];

[0122] According to the residual value and the rated value, a first calibration value (expressed as F) output by the first neural network model or the second neural network model is obtained.

[0123] In an optional embodiment, the residual value and rated value of the second timer, the rated value refers to the rated clock frequency of the timer determined by the MCU chip during design; the residual value refers to the MCU chip after the chip is taped out, in the ATE laboratory test phase, each value point of the MCU chip's tr im register is taken once, and the corresponding clock frequency value is measured. The residual value is calculated according to the following formula: residual value = ATE laboratory test phase clock frequency value - theoretical clock frequency value.

[0124] In an optional embodiment, determining the theoretical calibration value according to the initial calibration value specifically includes:

[0125] According to the random algorithm, a judgment result is obtained, wherein the judgment result is plus or minus;

[0126] When the judgment result is plus, add one unit length to the initial calibration value to obtain the theoretical calibration value;

[0127] When the judgment result is minus, the initial calibration value is subtracted by one unit length to obtain the theoretical calibration value;

[0128] The unit length mentioned refers to the unit length of the register.

[0129] In an optional embodiment, determining the forward differential clock value and the backward differential clock value of the initial calibration value according to the second calibration curve specifically includes:

[0130] Diff1=|y2-y1|,

[0131] Diff2 = |y1-y3|,

[0132] Among them, Diff1 is the forward differential clock value of the initial calibration value trim1, Diff2 is the backward differential clock value of the initial calibration value trim1; y1 is the clock value corresponding to the initial calibration value, y2 is the clock value corresponding to the initial calibration value at the next calibration value point, and y3 is the clock value corresponding to the initial calibration value at the previous calibration value point.

[0133] In an optional embodiment, the updating of the first comparison result after modifying the second timer until the first comparison result is equal specifically includes:

[0134] After modifying the second timer, controlling the first timer to re-output the first pulse width signal;

[0135] Inputting the first pulse width signal into the second timer so that the second timer can update the acquired second pulse width signal, wherein the updating of the acquired second pulse width signal includes: updating the second pulse width value recorded in the counter CNT of the MCU chip;

[0136] updating the first comparison result according to the initial pulse width signal and the current second pulse width signal;

[0137] When the first comparison result is not equal, the clock of the second timer is corrected until the first comparison result is equal.

[0138] In an optional embodiment, after completing the calibration of the second timer, the method further includes:

[0139] obtaining a first calibration curve and a plurality of neural network models for a first timer;

[0140] Inputting the third pulse width signal output by the second timer into the first timer, so that the first timer obtains the fourth pulse width signal;

[0141] Based on the initial pulse width signal and the fourth pulse width signal, obtaining a third comparison result;

[0142] Based on the third comparison result, calibrating the first timer according to the first calibration curve and a plurality of neural network models;

[0143] Among them, the several neural network models of the first timer include: a third neural network model and a fourth neural network model.

[0144] By generating a pulse width signal through the corrected second timer, the first timer can be adjusted with the help of the second timer. The adjustment of the two timers in the MCU chip can be completed at one time by receiving the external pulse width signal only once, thereby improving the adjustment efficiency of the chip clock.

[0145] This embodiment realizes the correction of the timer in the chip by constructing a calibration curve and several neural network models for each clock in the chip, receiving a pulse width signal from the outside, and sending the pulse width signal between two timers, and combining the calibration curve and the neural network model. Compared with the prior art that requires the external device to send multiple pulse widths, this embodiment only needs to receive the pulse width level once, which greatly reduces the hardware conditions for chip correction; the pulse width level is combined with the calibration curve and neural network model of the chip, and the clock inside the chip is adjusted to each other, which improves the speed of chip adjustment, thereby efficiently correcting the chip clock; it ensures that the chip clock will not be in an offset state for a long time, thereby ensuring the stable operation of the chip.

[0146] Embodiment 2

[0147] Please refer to Figure 2 , is a connection diagram of a chip clock correction circuit provided by an embodiment of the present invention, comprising: an acquisition module 201, a processor module 202 and a driving module 203;

[0148] The signal output end of the acquisition module 201 is electrically connected to the input end of the processor module 202;

[0149] The output end of the processor module 202 is electrically connected to the control end of the driving module 203;

[0150] Wherein, the acquisition module 201 is used to acquire a second calibration curve of a second timer and a plurality of neural network models;

[0151] The processor module 202 is used to input the initial pulse width signal into the first timer, and then input the first pulse width signal output by the first timer into the second timer, so that the second timer obtains the second pulse width signal, and then obtains a first comparison result according to the initial pulse width signal and the second pulse width signal, thereby outputting a driving instruction for the second timer;

[0152] The driving module 203 is used to calibrate the clock of the second timer according to the driving instruction.

[0153] This embodiment realizes the correction of the timer in the chip by constructing a calibration curve and several neural network models for each clock in the chip, receiving a pulse width signal from the outside, and sending the pulse width signal between two timers, and combining the calibration curve and the neural network model. Compared with the prior art that requires the external device to send multiple pulse widths, this embodiment only needs to receive the pulse width level once, which greatly reduces the hardware conditions for chip correction; the pulse width level is combined with the calibration curve and neural network model of the chip, and the clock inside the chip is adjusted to each other, which improves the speed of chip adjustment, thereby efficiently correcting the chip clock; it ensures that the chip clock will not be in an offset state for a long time, thereby ensuring the stable operation of the chip.

[0154] Embodiment 3

[0155] Please refer to Figure 3 , is a schematic diagram of the structure of a chip clock correction system provided by an embodiment of the present invention, comprising: a chip and a chip clock correction circuit as described above;

[0156] The chip includes: a first timer 301, a second timer 302 and a register 303;

[0157] The first output terminal of the register 303 is electrically connected to the first input terminal of the first timer 301;

[0158] The second output terminal of the register 303 is electrically connected to the first input terminal of the second timer 302;

[0159] The third output terminal of the register 303 is electrically connected to the input terminal of the acquisition module 201;

[0160] The input end of the register 303 is electrically connected to the output end of the driving module 203;

[0161] The first timer 301 and the second timer 302 are electrically connected;

[0162] The acquisition module 201 is used to acquire a second calibration curve of a second timer and a plurality of neural network models;

[0163] The processor module 202 is used to input the initial pulse width signal into the first timer, and then input the first pulse width signal output by the first timer into the second timer, so that the second timer obtains the second pulse width signal, and then obtains a first comparison result according to the initial pulse width signal and the second pulse width signal, thereby outputting a driving instruction for the second timer;

[0164] The driving module 203 is used to calibrate the clock of the second timer according to the driving instruction.

[0165] This embodiment realizes the correction of the timer in the chip by constructing a calibration curve and several neural network models for each clock in the chip, receiving a pulse width signal from the outside, and sending the pulse width signal between two timers, and combining the calibration curve and the neural network model. Compared with the prior art that requires the external device to send multiple pulse widths, this embodiment only needs to receive the pulse width level once, which greatly reduces the hardware conditions for chip correction; the pulse width level is combined with the calibration curve and neural network model of the chip, and the clock inside the chip is adjusted to each other, which improves the speed of chip adjustment, thereby efficiently correcting the chip clock; it ensures that the chip clock will not be in an offset state for a long time, thereby ensuring the stable operation of the chip.

[0166] Embodiment 4

[0167] The embodiments of the present invention provide a terminal device and a computer-readable storage medium.

[0168] The terminal device includes: one or more processors; a memory coupled to the processor and used to store one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement a chip clock correction method as described in the above embodiment.

[0169] The computer-readable storage medium stores a computer program thereon, wherein the computer program is executed by a processor to implement a chip clock correction method as described in the above embodiment.

[0170] In summary, this embodiment constructs a calibration curve and several neural network models for each clock in the chip, receives a pulse width signal from the outside once, sends a pulse width signal between two timers, and combines the calibration curve and the neural network model to achieve the correction of the timer in the chip. Compared with the prior art that requires an external device to send multiple pulse widths, this embodiment only needs to receive a pulse width level once, which greatly reduces the hardware conditions for chip correction; a pulse width level is combined with the calibration curve and neural network model of the chip, and the clocks inside the chip are adjusted to each other, which improves the speed of chip adjustment, thereby efficiently correcting the chip clock; it ensures that the chip clock will not be in an offset state for a long time, thereby ensuring the stable operation of the chip.

[0171] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It is particularly pointed out that for those skilled in the art, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of protection of the present invention.

Claims

1. A chip clock correction method, characterized in that: The method is applied to calibrate the first timer and the second timer, and specifically comprises the following steps: Obtaining a second calibration curve and several neural network models of the second timer, wherein the chip includes: a register; performing simulation based on the register and the second timer to obtain a second calibration curve; constructing a first neural network model and a second neural network model according to the second calibration curve; Inputting a preset initial pulse width signal into the first timer so that the first timer outputs a first pulse width signal; Inputting the first pulse width signal into a second timer so that the second timer acquires a second pulse width signal; Based on the initial pulse width signal and the second pulse width signal, obtaining a first comparison result; Based on the first comparison result, the clock of the second timer is corrected according to the second calibration curve and several neural network models, wherein the residual value and the rated value of the second timer are obtained; when the first comparison result is unequal, the initial calibration value of the current register is obtained; according to the second calibration curve, the initial clock value is determined in combination with the initial calibration value; the initial calibration value and the rated value are compared to obtain the second comparison result; according to the second comparison result, the first calibration value is determined in combination with the first neural network model or the second neural network model; according to the first calibration value, the register adjustment value is determined in combination with the second calibration curve to adjust the register, thereby modifying the clock of the second timer; after modifying the clock of the second timer, the first comparison result is updated until the first comparison result is equal.

2. A chip clock correction method as claimed in claim 1, characterized in that: The obtaining of a first comparison result based on the initial pulse width signal and the second pulse width signal specifically includes: According to the initial pulse width signal, an initial pulse width value is obtained; According to the second pulse width signal, obtaining a second pulse width value; The initial pulse width value and the second pulse width value are compared to obtain a first comparison result.

3. A chip clock correction method as claimed in claim 1, characterized in that: Determining the first calibration value according to the second comparison result and combining the first neural network model or the second neural network model specifically includes: According to the initial calibration value, a theoretical calibration value is determined; When the second comparison result is that the initial calibration value is lower than the rated value, the initial calibration value, the theoretical calibration value and the initial clock value are input into the first neural network model; When the second comparison result is that the initial calibration value is higher than the rated value, the initial calibration value, the theoretical calibration value and the initial clock value are input into the second neural network model; A first calibration value output by the first neural network model or the second neural network model is obtained according to the residual value and the rated value.

4. A chip clock correction method as claimed in claim 1, characterized in that: The step of determining a register adjustment value according to the first calibration value and in combination with the second calibration curve to adjust the register and thereby modify the clock of the second timer specifically includes: Determining a forward differential clock value and a backward differential clock value of an initial calibration value according to a second calibration curve; According to the second comparison result, the register adjustment value is determined in combination with the forward differential clock value and the backward differential clock value: Among them, A d is the register adjustment value, F is the first calibration value, R is the rated value, when the second comparison result is that the initial calibration value is greater than the rated value, diff is the backward differential clock value; when the second comparison result is that the initial calibration value is less than the rated value, diff is the forward differential clock value; The register is adjusted according to the register adjustment value, thereby modifying the clock of the second timer.

5. A chip clock correction circuit, characterized in that: include: Acquisition module, processor module and driver module; The signal output end of the acquisition module is electrically connected to the input end of the processor module; The output end of the processor module is electrically connected to the control end of the drive module; The acquisition module is used to acquire a second calibration curve of a second timer and several neural network models, wherein the chip includes: a register; performing simulation based on the register and the second timer to obtain a second calibration curve; and constructing a first neural network model and a second neural network model according to the second calibration curve; The processor module is used to input the initial pulse width signal into the first timer, and then input the first pulse width signal output by the first timer into the second timer, so that the second timer obtains the second pulse width signal, and then obtains a first comparison result according to the initial pulse width signal and the second pulse width signal, thereby outputting a driving instruction for the second timer; The driving module is used to complete the correction of the clock of the second timer according to the driving instruction, wherein the residual value and the rated value of the second timer are obtained; when the first comparison result is unequal, the initial calibration value of the current register is obtained; the initial clock value is determined according to the second calibration curve in combination with the initial calibration value; the initial calibration value and the rated value are compared to obtain a second comparison result; according to the second comparison result, the first calibration value is determined in combination with the first neural network model or the second neural network model; according to the first calibration value, the register adjustment value is determined in combination with the second calibration curve to adjust the register, and then the clock of the second timer is modified; after modifying the clock of the second timer, the first comparison result is updated until the first comparison result is equal.

6. A chip clock correction system, characterized in that: include: A chip and a chip clock correction circuit as claimed in claim 5; The chip includes: a first timer, a second timer and a register; The first output terminal of the register is electrically connected to the first input terminal of the first timer; The second output terminal of the register is electrically connected to the first input terminal of the second timer; The third output terminal of the register is electrically connected to the input terminal of the acquisition module; The input end of the register is electrically connected to the output end of the driving module; The first timer and the second timer are electrically connected; The acquisition module is used to acquire a calibration curve of the second timer and a plurality of neural network models; The processor module is used to input the initial pulse width signal into the first timer, and then input the first pulse width signal output by the first timer into the second timer, so that the second timer obtains the second pulse width signal, and then obtains a first comparison result according to the initial pulse width signal and the second pulse width signal, thereby outputting a driving instruction for the second timer; The driving module is used to complete the correction of the clock of the second timer according to the driving instruction.

7. A terminal device, characterized in that: include: one or more processors; A memory, coupled to the processor, for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement a chip clock correction method as described in any one of claims 1 to 4.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: The computer program is executed by a processor to implement a chip clock correction method as described in any one of claims 1 to 4.

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