Instruction processing device, system and method

Abstract

In the embodiment of the present application, an instruction processing device, system and method are provided, and the device includes: an instruction fetch module, an execution module and a write-back module, wherein the instruction fetch module is used to obtain original instruction data, and perform timing information processing on the original instruction data to obtain target instruction data; the execution module is used to read the target instruction data from the instruction fetch module, determine the queue instruction data through the emission queue, and perform operation processing on the queue instruction data to obtain the execution result and load and store; the number of emission queues is pre-configured according to the instruction type and data outflow order of the historical instruction data; the write-back module is used to write back the execution result. The present application can pre-configure different parameters according to different application scenarios, adapt to the needs of the actual market, greatly improve the adaptability and flexibility of data processing, and further improve the performance of the processor in processing data.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an instruction processing device, system and method. Background Art

[0002] With the rapid development of computer equipment, the central processing unit (CPU) is the computing and control core of a computer device. Its main function is to complete the execution of computer instructions and the processing of data. As the complexity of computing continues to increase, the performance of the CPU is becoming more and more important. Among them, the essence of the computer program running on the computer device is the execution process of instructions. In order to improve the working efficiency and performance of the CPU in the computer device, the research on how to configure and process computer instructions is particularly important.

[0003] At present, the related technology adopts the classic five-stage pipeline processor architecture, such as a microprocessor (Microprocessor without interlocked pipelined stages, MIPS), in which each pipeline stage in the architecture includes five instruction processing stages, namely instruction fetch (IF), decoding (ID), execution (EXU), memory storage (MEM), and write back (WB). Each pipeline stage is used to process different tasks in the execution process of an instruction. However, this solution can only perform operations fixedly according to the architecture and cannot adapt to the needs of the actual market. Its processing process is relatively single and one-sided, resulting in poor adaptability and flexibility. Summary of the invention

[0004] The embodiments of the present application provide an instruction processing device, system and method.

[0005] According to a first aspect of an embodiment of the present application, there is provided an instruction processing device, including:

[0006] An instruction fetch module, the instruction fetch module is used to obtain original instruction data and perform timing information processing on the original instruction data to obtain target instruction data;

[0007] An execution module, the execution module is connected to the instruction fetch module, and is used to read the target instruction data from the instruction fetch module, determine the queue instruction data through the emission queue, and perform operation processing on the queue instruction data to obtain the execution result and load and store it; the number of the emission queues is pre-configured according to the instruction type and data outflow order of the historical instruction data;

[0008] A write-back module, which is connected to the execution module and is used to write back the execution result.

[0009] In an optional embodiment of the present application, the execution module includes: a transmission unit, a queue buffer unit, and an execution unit, wherein the transmission unit is connected to the execution unit; the transmission unit includes at least two transmission queues; the execution unit includes at least two sub-execution units, each transmission queue is correspondingly connected to a sub-execution unit; each transmission queue is correspondingly connected to a queue buffer unit;

[0010] Each transmission queue is used to: determine queue instruction data corresponding to the transmission queue from the target instruction data, and send the queue instruction data to the corresponding queue buffer unit;

[0011] Each of the queue buffer units is used to: cache the queue instruction data obtained from the transmit queue and send it to the corresponding sub-execution unit;

[0012] Each of the sub-execution units is used to: perform calculations on the queue instruction data, obtain execution results, and load and store them.

[0013] In an optional embodiment of the present application, the at least two emission queues include a first emission queue and a second emission queue; the first emission queue is used to: obtain the queue instruction data from the target instruction data in a preset order, and send it to the corresponding sub-execution unit in a random order; the second emission queue is used to: obtain the queue instruction data from the target instruction data in a preset order, and send it to the corresponding sub-execution unit in the preset order.

[0014] In an optional embodiment of the present application, the second instruction emission queue includes a first instruction emission queue and a second instruction emission queue; the first instruction emission queue is used to: obtain queue instruction data of a first instruction type from the target instruction data in a preset order, and send it to the corresponding sub-execution unit in a disorderly order, and the first instruction type includes at least one of a load instruction type, a storage instruction type, a logical operation instruction type, and a floating-point instruction type; the second instruction emission queue is used to: obtain queue instruction data of a second instruction type from the target instruction data in a preset order, and send it to the corresponding sub-execution unit in a disorderly order, and the second instruction type includes a jump instruction type.

[0015] In an optional embodiment of the present application, the device also includes: a physical register, a scoreboard and a delivery unit; the physical register is used to store the execution result output by the sub-execution unit; the scoreboard is used to establish a register renaming mapping relationship for the queue instruction data and store it; the delivery unit is used to deliver the queue instruction data.

[0016] In an optional embodiment of the present application, the instruction fetch module includes an acquisition unit, a memory unit, a buffer unit, and a storage unit; the memory unit is connected to the acquisition unit and the buffer unit respectively, and the buffer unit is also connected to the storage unit; the acquisition unit is used to send an instruction data acquisition request to the memory unit; the memory unit is used to receive and respond to the instruction data acquisition request, acquire original instruction data and send it to the buffer unit; the buffer unit is used to buffer the original instruction data and send it to the storage unit; the storage unit is used to perform timing information processing on the original instruction data, obtain target instruction data and store it.

[0017] In an optional embodiment of the present application, the memory unit includes: a local storage unit and other storage units; the local storage unit is used to receive and respond to the instruction data acquisition request, obtain local original instruction data and send it to the buffer unit; the other storage units are used to receive and respond to the instruction data acquisition request, obtain other original instruction data and send it to the buffer unit.

[0018] A second aspect of the embodiments of the present application provides an instruction processing system, including the instruction processing device provided in the above embodiments.

[0019] A third aspect of the embodiments of the present application provides an instruction processing method, the method comprising:

[0020] Acquire original instruction data, and perform timing information processing on the original instruction data to obtain target instruction data;

[0021] Determine the queue instruction data through the transmission queue of the target instruction data, and perform operation processing on the queue instruction data to obtain an execution result; the number of the transmission queues is pre-configured according to the instruction type and data outflow order of the historical instruction data;

[0022] The execution result is written back.

[0023] The instruction processing device in the embodiment of the present application includes an instruction fetch module, an execution module and a write-back module. The instruction fetch module is used to obtain original instruction data and perform timing information processing on the original instruction data to obtain target instruction data. The execution module is used to read the target instruction data from the instruction fetch module, determine the queue instruction data through the emission queue of the target instruction data, and perform calculation processing on the queue instruction data to obtain the execution result and load it for storage; the number of emission queues is pre-configured according to the instruction type and data outflow order of the historical instruction data; the write-back module is used to write back the execution result. Compared with the prior art, the instruction processing device of the present application, on the one hand, obtains target instruction data by performing timing information processing on the original instruction data, can provide data guidance information for the subsequent execution module when performing calculation processing, and is adaptable to different scenarios; on the other hand, because different numbers of emission queues are pre-configured according to the instruction type and data outflow order of the historical instruction data, the queue instruction data can be accurately determined in the process of executing data calculation processing, so as to determine the execution result in a finer granularity based on different queue instruction data, and write the execution result back. It can pre-configure different parameters according to different application scenarios, adapt to the actual market needs, greatly improve the adaptability and flexibility of data processing, and further improve the performance of the processor in processing data. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0025] Figure 1 A structural diagram of a classic five-stage pipeline in the prior art provided for one embodiment of the present application;

[0026] Figure 2 A schematic diagram of the structure of an instruction processing device provided by one embodiment of the present application;

[0027] Figure 3 A schematic diagram of the structure of an instruction processing device provided by one embodiment of the present application;

[0028] Figure 4 A schematic diagram of the structure of an instruction processing device provided by one embodiment of the present application;

[0029] Figure 5 A schematic diagram of a processor structure in which a transmission queue according to an embodiment of the present application includes two first transmission queues;

[0030] Figure 6 The transmission queue provided in the embodiment of the present application includes a schematic diagram of a processor structure of three first transmission queues;

[0031] Figure 7 A schematic diagram of a processor structure in which a transmission queue provided in an embodiment of the present application includes four first transmission queues;

[0032] Figure 8 The transmission queue provided in the embodiment of the present application includes a schematic diagram of a processor structure of five first transmission queues;

[0033] Fig. 9 A schematic diagram of a processor structure in which the transmit queue provided in an embodiment of the present application includes six first transmit queues;

[0034] Fig.10 A schematic diagram of a processor structure in which a transmission queue provided in an embodiment of the present application includes seven first transmission queues;

[0035] Fig.11 A schematic diagram of a processor structure in which a transmission queue provided in an embodiment of the present application includes eight first transmission queues;

[0036] Fig.12 A flowchart of an operation instruction processing method provided for one embodiment of the present application.

[0037] Description of reference numerals:

[0038] Instruction fetch module-10; acquisition unit-11; memory unit-12; buffer unit-13; storage unit-14; execution module-20; emission unit-21; queue buffer unit-22; execution unit-23; write-back module-30; physical register-40; scoreboard-50; delivery unit-60; first emission queue-211; second emission queue-212; first sub-execution unit-231; second sub-execution unit 232; first instruction emission queue-2121; second instruction emission queue-2122. DETAILED DESCRIPTION

[0039] In the process of implementing the present application, the inventors found that the current instructions can only perform operations fixedly according to the architecture, cannot adapt to the needs of the actual market, are relatively single and one-sided, and result in poor adaptability and flexibility.

[0040] Understandably, see Figure 1As shown, the processor CPU of the related technology adopts pipeline technology, such as the classic five-stage pipeline. Each stage of the pipeline includes five instruction processing units, namely, instruction fetch (IF) unit, decoding (ID) unit, execution (EX) unit, memory access unit (MEM) unit and write back (WB) unit. Among them, the IF unit is responsible for reading instructions from the memory, the ID unit is responsible for decoding and decoding instructions, that is, identifying the instruction type, the EX unit is responsible for executing the instruction and obtaining the operation result, the MEM unit is used for memory access operations, which can be reading data from the internal or external memory, or writing the instruction result into the memory, and the WB unit is used to write the result of the instruction execution into the processor's register stack for quick access next time.

[0041] Among them, for the processor architecture, different pipelines can be divided according to different pipeline classifications. The pipeline classification can include control methods and the outflow order of tasks. For example, according to the control method, it can be divided into a synchronous pipeline architecture or a one-step pipeline architecture. For example, according to the outflow order of tasks, it can be divided into a sequential pipeline architecture or an out-of-order pipeline architecture. For different processors, the pipeline architectures used are also different. In order to improve the performance of the processor, it is usually necessary to consider multiple factors when considering the pipeline architecture, such as area, power consumption, performance, etc. However, the above-mentioned classic five-stage pipeline processor architecture can only perform fixed operations according to the architecture during instruction processing, and cannot adapt to the needs of the actual market. It is relatively single and one-sided, resulting in poor adaptability and flexibility.

[0042] In response to the above problems, the embodiments of the present application provide instruction processing devices, systems and methods. Compared with the prior art, the instruction processing device of the present application, on the one hand, obtains target instruction data by performing timing information processing on the original instruction data, can provide data guidance information for subsequent execution modules to perform calculations and processing, and is adaptable to different scenarios; on the other hand, because different numbers of emission queues are pre-configured according to the instruction type and data outflow order of historical instruction data, the queue instruction data can be accurately determined in the process of executing data calculation processing, so as to determine the execution result in a finer granularity based on different queue instruction data, and write the execution result back. It can pre-configure different parameters according to different application scenarios, adapt to the actual market needs, greatly improve the adaptability and flexibility of data processing, and further improve the performance of the processor in processing data.

[0043] The solutions in the embodiments of the present application can be implemented in various computer languages, for example, object-oriented programming language Java, interpreted scripting language JavaScript, Verilog, System Verilog and other HDL hardware description languages, etc.

[0044] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0045] See also Figure 2 , Figure 2 The structural diagram of the instruction processing device provided in the embodiment of the present application includes an instruction fetch module 10, an execution module 20 and a write-back module 30. The instruction fetch module 10 is used to obtain original instruction data and perform timing information processing on the original instruction data to obtain target instruction data; the execution module 20 is connected to the instruction fetch module 10, and is used to read the target instruction data from the instruction fetch module 10, determine the queue instruction data through the emission queue of the target instruction data, and perform operation processing on the queue instruction data to obtain the execution result and load the storage; the number of emission queues is pre-configured according to the instruction type and data outflow order of the historical instruction data; the write-back module 30 is connected to the execution module 20, and is used to write back the execution result.

[0046] It should be noted that the above-mentioned original instruction data is the instruction data that needs to be processed. The original instruction data can be obtained from a memory or other memory unit. It can be the original data that has not been segmented and processed. For example, it can be a whole segment of instruction data, which includes multiple instruction data. The multiple instruction data can be instruction data of different instruction types or instruction data of the same instruction type.

[0047] Optionally, in the process of acquiring multiple original instruction data, the original instruction data may be obtained by downloading from the cloud, or may be imported from other external devices, or may be obtained from a database or blockchain, which is not limited in this embodiment.

[0048] After acquiring the original instruction data, the instruction fetch module 10 may perform timing information processing on the original instruction data, for example, first acquiring the order of the original instruction data, then performing instruction alignment processing on the original instruction data according to the order, and performing segmentation and splicing arrangement processing on the original instruction data according to the preset instruction length to obtain multiple target instruction data. The preset instruction length may be obtained by sorting the actual instruction data and may be customized.

[0049] The instruction fetch module 10 may include a multi-level pipeline, each pipeline including a unit. The target instruction data refers to the instruction data after the original instruction data is processed with timing information. The target instruction data is complete instruction data, and each target instruction data may correspond to an instruction type, such as an operation instruction, a jump instruction, a memory access instruction, a storage instruction, etc. The number of the target instruction data may be three, four, or any other number.

[0050] The execution module 20 establishes a communication connection with the instruction fetch module 10. The execution module 20 is used to read target instruction data from the instruction fetch module 10. For example, valid instructions can be determined from the target instruction data, and then the valid instruction data can be cached to prevent timing degradation. After the cache processing, the valid target instruction data can be determined through the transmission queue to obtain queue instruction data, and the queue instruction data refers to the target instruction data that needs to be processed in each transmission queue.

[0051] It is understandable that the above-mentioned transmission queues may include multiple ones, for example, two, three, four, five, or any other number, and the number of transmission queues may be pre-configured according to the instruction type and data outflow order of the historical instruction data. The historical instruction data may be pre-acquired from a database or imported through an external device.

[0052] As an implementable manner, the historical instruction data has different instruction types, and the number of emission queues set corresponding to different instruction types is also different. The number of emission queues can be configured according to the instruction type alone. For example, when four instruction types are included, the number of emission queues can be set to four, three, or two.

[0053] As another achievable manner, the data outflow order may include a sequential outflow mode and a disordered outflow mode. The number of transmission queues set corresponding to different data outflow orders is also different. The number of transmission queues can be configured according to the data outflow order alone. For example, when the sequential outflow mode and the disordered outflow mode are included, the number of transmission queues set can be two.

[0054] As another achievable method, the number of emission queues can be configured according to the instruction type and the data outflow order. For example, when there are three instruction types and two data outflow orders, the number of emission queues set can be three. It is understandable that the number of emission queues provided in the embodiment of the present application can be customized according to the actual application scenario. For different application scenarios, a variety of different parameter configurations can be used to determine the queue instruction data corresponding to each emission queue in a more fine-grained manner, thereby accurately executing the data processing steps.

[0055] After the queue instruction data is determined, an operation is performed on it to obtain an execution result, and then loaded and stored. The above operation can include multiple operation types, and different operation processing logics can be executed for different operation types and queue instruction data.

[0056] After the execution result is obtained, the execution result may be written back to a physical register so as to facilitate subsequent calling of the execution result for data processing.

[0057] The instruction processing device in the embodiment of the present application includes an instruction fetch module, an execution module and a write-back module. The instruction fetch module is used to obtain original instruction data and perform timing information processing on the original instruction data to obtain target instruction data. The execution module is used to read the target instruction data from the instruction fetch module, determine the queue instruction data through the emission queue of the target instruction data, and perform calculation processing on the queue instruction data to obtain the execution result and load it for storage; the number of emission queues is pre-configured according to the instruction type and data outflow order of the historical instruction data; the write-back module is used to write back the execution result. Compared with the prior art, the instruction processing device of the present application, on the one hand, obtains target instruction data by performing timing information processing on the original instruction data, can provide data guidance information for the subsequent execution module when performing calculation processing, and is adaptable to different scenarios; on the other hand, because different numbers of emission queues are pre-configured according to the instruction type and data outflow order of the historical instruction data, the queue instruction data can be accurately determined in the process of executing data calculation processing, so as to determine the execution result in a finer granularity based on different queue instruction data, and write the execution result back. It can pre-configure different parameters according to different application scenarios, adapt to the actual market needs, greatly improve the adaptability and flexibility of data processing, and further improve the performance of the processor in processing data.

[0058] In an optional embodiment of the present application, please continue to refer to Figure 2 As shown, the execution module 20 includes: a transmission unit 21, a queue buffer unit 22, and an execution unit 23, wherein the transmission unit 21 is connected to the execution unit 23; the transmission unit 21 includes at least two transmission queues; the execution unit 23 includes at least two sub-execution units, each transmission queue is connected to a corresponding sub-execution unit; each transmission queue is connected to a queue buffer unit;

[0059] Each transmit queue IQ is used to: determine the queue instruction data corresponding to the transmit queue from the target instruction data, and send it to the corresponding queue buffer unit; each queue buffer unit IQBuf is used to: cache the queue instruction data obtained from the transmit queue, and send it to the corresponding sub-execution unit; each sub-execution unit is used to: perform calculations on the queue instruction data, obtain the execution results and load and store them.

[0060] It should be noted that the emission queues included in the above-mentioned emission unit may be multiple or two, the queue buffer units may be two or more, and the sub-execution units included in the execution unit may be two or three. The emission unit may include an issue list (Issue Queue, IQ), and the target instruction data obtained from the instruction fetch module is sent to different sub-execution units through the issue list (Issue Queue, IQ). The emission list includes at least two emission queues, and the number of the above-mentioned emission queues can be customized according to the actual application scenario. Different emission queues process different data.

[0061] Exemplarily, when the transmission queue includes two, for example, the first transmission queue and the second transmission queue, there are also two queue buffer units and sub-execution units, the queue buffer unit includes the first queue buffer unit and the second queue buffer unit, the sub-execution unit includes the first sub-execution unit and the second sub-execution unit, the first queue buffer unit is respectively connected to the first transmission queue and the first sub-execution unit, and the second queue buffer unit is respectively connected to the second transmission queue and the second sub-execution unit.

[0062] For example, the first emission queue can determine the first queue instruction data corresponding to the first emission queue from the target instruction data, and send it to the corresponding first queue buffer unit, the first queue buffer unit caches the first queue instruction data, and sends it to the corresponding first sub-execution unit, so that the first sub-execution unit performs operation processing on the first queue instruction data, obtains the corresponding execution result and loads and stores it. Similarly, the execution steps of the second emission queue are similar to those of the first emission queue.

[0063] In this embodiment, each transmission queue determines the corresponding queue instruction data and sends it to the corresponding queue buffer unit, and caches it through the queue buffer unit, and then runs it through the sub-execution unit, which can process multiple different data in parallel and improve data computing efficiency.

[0064] In an optional embodiment of the present application, please continue to refer to Figure 2 As shown, the at least two transmit queues include a first transmit queue 211 and a second transmit queue 212 .

[0065] The first emission queue 211 is used to obtain queue instruction data from the target instruction data in a preset order, and send it to the corresponding first sub-execution unit 231 in a random order; the second emission queue 212 is used to obtain queue instruction data from the target instruction data in a preset order, and send it to the corresponding second sub-execution unit 232 in a preset order.

[0066] It should be noted that the number of the first emission queues can be one, two or more, and the number can be customized according to the actual application scenario. The first emission queue can be understood as a sequential-in and random-out emission queue, and the corresponding queue buffer unit and sub-execution unit can be one, two or three, which is the same as the number of the first emission queue. The second emission queue can be understood as a sequential-in and sequential-out emission queue, and the corresponding queue buffer unit and sub-execution unit can be one, two or three, which is the same as the number of the second emission queue.

[0067] Specifically, the first issue queue may be an issue queue of a common instruction type, and the second issue queue may be an issue queue of a special instruction type, where the special instruction type may include a load instruction type, a store instruction type, and a jump instruction type.

[0068] In this embodiment, since the first emission queue and the second emission queue are set up, data with different outflow orders can be processed accordingly through the corresponding emission queues, so that different target instruction data can be processed accordingly in parallel, which can adapt to different application scenarios and further improve the performance of the processor in processing data.

[0069] In an optional embodiment of the present application, please continue to refer to Figure 2 As shown, the second issue queue includes a first instruction issue queue 2121 and a second instruction issue queue 2122 .

[0070] The first instruction emission queue 2121 is used to: obtain queue instruction data of a first instruction type from the target instruction data in a preset order, and send it to the corresponding sub-execution unit in a disorderly order. The first instruction type includes at least one of a load instruction type, a storage instruction type, a logical operation instruction type, and a floating-point instruction type; the second instruction emission queue 2122 is used to: obtain queue instruction data of a second instruction type from the target instruction data in a preset order, and send it to the corresponding sub-execution unit in a disorderly order. The second instruction type includes a jump instruction type.

[0071] It should be noted that the above-mentioned preset order can be the order in which instructions enter the transmission queue, and can be customized according to actual needs. The first instruction type includes a load instruction type and / or a store instruction type, and the first instruction transmission queue LSU IQ is a dedicated transmission queue for the load instruction type and / or the store instruction type. The second instruction type includes a jump instruction, and the second instruction transmission queue BJP IQ is a dedicated transmission queue for the jump instruction.

[0072] The first instruction emission queue and the second instruction emission queue are both sequential-in-sequential-out emission queues, and the first emission queue is an emission queue IQ of a common instruction type, which is sequential-in-disorder-out. The first instruction emission queue and the second instruction emission queue can cache the data of the emission queue to output to the corresponding queue buffer unit, and then perform calculation processing through the sub-execution unit, and can perform corresponding calculation processing according to different instruction types to obtain corresponding execution results.

[0073] In this embodiment, since the first instruction emission queue and the second instruction emission queue are provided according to different instruction types, data of different instruction types can be processed accordingly through the corresponding instruction emission queues, so that corresponding processing can be performed in parallel on instruction data of each different queue, which can adapt to different application scenarios and greatly improve the performance of the processor in processing data.

[0074] In an optional embodiment of the present application, see Figure 3 As shown, the above device also includes: a physical register (physical regfile) 40, a scoreboard (Score Board) 50 and a commit unit (COMMIT Table) 60.

[0075] The physical register 40 is used to store the execution result output by the sub-execution unit; the scoreboard 50 is used to establish and store the register renaming mapping relationship for the queue instruction data; and the delivery unit 60 is used to deliver the queue instruction data.

[0076] It is understandable that the physical registers may include a physical register list, which may be a list pre-customized according to actual needs, and may include multiple physical registers and attribute information of each physical register, and the attribute information of the physical register may include a physical register identifier and physical register status information. Among them, the physical register identifier is used to uniquely represent the identity information of the physical register, and the physical register status information is used to represent the current status information of the physical register, which may be a usage state and an idle state. The scoreboard is used to record the register renaming mapping relationship, and the register renaming mapping relationship is used to represent the correspondence between the physical register and the execution result.

[0077] Taking the acquisition of four queue instruction data as an example, the four queue instruction data are stored in the physical register stack (physical regfile) through the write-back module WB, and then the idle target physical register is found from the physical register list stack (physical regfilelist), and a register renaming mapping relationship between the target physical register and the four queue instruction data is established, and then the register renaming mapping relationship is stored in the scoreboard (scoreboard), and the unused tags are found from the tag queue, and then the target tags are assigned to the queue instruction data.

[0078] Finally, the queue instruction data is processed according to different instruction types, which may include general operation instructions, jump instructions and memory access instructions. Then, according to the instruction type, the corresponding data processing is performed to obtain the corresponding execution result and write it back to the physical register (physical regfile).

[0079] The delivery unit is used to perform delivery processing on the queue instruction data. It should be noted that the queue instruction data in the above pipeline is delivered, which means that the instruction is no longer in the predicted execution state. It is judged that it can be actually executed in the processor and can have an impact on the processor state. The opposite of delivery is cancellation, which means that the instruction is finally judged to need to be cancelled. Optionally, the above-mentioned delivery processing of the queue instruction data can be performed in sequence, for example, the next instruction will be delivered only after the current instruction has completed its delivery.

[0080] In this embodiment, by classifying and executing different types of instructions through corresponding execution units, the processor can execute multiple instructions in parallel within a single clock cycle, thereby significantly improving the execution speed of the instruction stream, and by delivering and processing the queue instruction information, the execution status of the instruction information can be determined in a timely manner, which facilitates effective instruction execution and improves instruction processing efficiency.

[0081] For example, see Figure 4As shown, for the instruction fetch module IF, it can include multiple pipeline steps, the first pipeline step includes the instruction fetch stage 1 (IF1 unit), wherein the IF1 unit fetches the instruction cache storage I-Cache (Instruction Cache) and the instruction local storage (Instruction Local Memory, ILM) in the memory unit according to the program counter (Program Count, PC), specifically, the IF1 unit can generate an instruction data acquisition request and send it to the memory unit, and the instruction high-speed storage I-Cache (Instruction Cache) Tag / Data RAM and the instruction local storage (Instruction Local Memory, ILM) RAM in the memory unit obtain the original instruction data; the second pipeline step includes the instruction fetch stage 2 (IF2 unit), which is the branch target buffer (Branch Target Buffer, BTB) for branch prediction; in the third pipeline, it is the Algn unit, which performs instruction alignment operations, which is from the ILM The original instruction data is obtained from the ICache, and the instruction code is obtained and selected for alignment, and then spliced ​​into a complete instruction code. At the same time, further branch prediction is performed, including RAS, branch target buffer BTB and branch history table (BHT) and other schemes. The fourth-level pipeline step includes the FB unit, which performs instruction buffer operations, which is to sort the original instruction data in time sequence, obtain the target instruction data and send it to the execution module through the IR FIFO unit. The target instruction data can be n, including the 0th to the n-1th, n>1.

[0082] Further, the number of emission queues, the number of instruction queue units, and the number of sub-execution units of the emission unit in the execution module (EX, Execution) are configurable. The emission unit may include n emission queues, a first instruction emission queue, and a second instruction emission queue. The n emission queues are OO IQ0-OO IQn-1, that is, out-of-order emission queue 0-out-of-order emission queue n-1, for example, n is 3, that is, three first emission queues are included, and the three first emission queues are OO IQ0, OO IQ1, and OO IQ2, a first instruction emission queue is a memory access emission queue IO LSU IQ, a second instruction emission queue is a sequential branch emission queue IO BJP IQ, and six corresponding instruction queue units IQBuf, a register reading unit, and an operand buffer unit. The execution units corresponding to the first instruction emission queue include: address generation unit 0 (AGU0), address generation unit 1 (AGU1), and the execution units corresponding to the first emission queue include: out-of-order instruction execution unit 0 (ALU1 MUL FMIS), out-of-order instruction execution unit 1 (ALU1 MUL The execution units corresponding to the first instruction issuance queue include: branch instruction execution unit (Branch). The instruction queue unit IQ Buf is used for instruction issuance buffering, the register reading unit is used for reading the physical register stack, and the operand buffer unit is used for operand buffering processing.

[0083] After obtaining the target instruction data from the instruction fetch module IF, the ordinary type data is sent to the corresponding queue buffer unit IQ Buf through the first transmit queue OO IQ0-OO IQn-1, and the queue instruction data of the load (Load) type and storage (Store) instruction is sent to the corresponding queue buffer unit IQBuf through the memory access transmit queue IO LSU IQ, and the jump instruction type data is sent to the corresponding queue buffer unit IQ Buf through the sequential branch transmit queue IO BJP IQ, and then the calculation is processed by each execution unit, and written back to the physical register stack (physical regfile) through the write-back port of the write-back module WB.

[0084] Optionally, the above-mentioned device may also include a memory access stage (AGU Stage), which is used to generate a corresponding address, and then load and store the execution result into the instruction buffer storage D-Cache (Instruction Cache) Tag / Data RAM and the instruction local storage (Instruction Local Memory, DLM) RAM, and finally write the write back module WB back to the physical register (physical regfile), rename the register, establish a register renaming mapping relationship and store it in the scoreboard (Score Board), and reorder the instruction data through the delivery unit COMMIT Table.

[0085] See also Figure 5-Figure 11 As shown, Figure 5 The transmission queue provided in the embodiment of the present application includes a processor structure diagram of two first transmission queues, Figure 6 The transmission queue provided in the embodiment of the present application includes a processor structure diagram of three first transmission queues, Figure 7-Figure 11 The transmission queues provided in the embodiments of the present application include, in turn, processor structure diagrams of four first transmission queues, five first transmission queues, six first transmission queues, seven transmission queues, and eight first transmission queues.

[0086] Optionally, each module in the above system can be customized according to the number of transmission queues. For example, when the number of transmission queues is large, such as four or more, the above device can be provided with a tag queue ITAGTable. The above tag queue includes multiple tags, each tag has different status information, some tags have been used, and some tags are not used. The target tag in the unused state can be found in the tag queue (ITAG Table), and then the target tag is assigned to the queue instruction data.

[0087] In this embodiment, a variety of different parameters can be customized according to different application scenarios, which can adapt to the actual market needs. That is, different numbers of transmission queues are configured so that data can be processed in parallel, which greatly improves the adaptability and flexibility of data processing and further improves the performance of the processor in processing data.

[0088] In one of the embodiments, the present application also provides a specific implementation method of the structure of the instruction fetch module, and the instruction fetch module 10 includes: an acquisition unit 11, a memory unit 12, a buffer unit 13, and a storage unit 14. The memory unit 12 is respectively connected to the acquisition unit 11 and the buffer unit 13, and the buffer unit 13 is also connected to the storage unit 14.

[0089] The acquisition unit 11 is used to send an instruction data acquisition request to the memory unit; the memory unit 12 is used to receive and respond to the instruction data acquisition request, acquire the original instruction data and send it to the buffer unit 13; the buffer unit 13 is used to buffer the original instruction data and send it to the storage unit 14; the storage unit 14 is used to process the timing information of the original instruction data, obtain the target instruction data and store it.

[0090] The memory unit may include multiple units, each of which may correspond to different types of storage units. Different types of storage units may correspond to different storage paths, for example, local storage units and other storage units may be included. The local storage unit is used to store data in the local path, and other storage units are used to store data in other paths. Other storage units may be, for example, instruction high-speed storage I-Cache (Instruction Cache), and the local storage unit may be, for example, local storage ILM (Instruction Local Memory).

[0091] Specifically, the acquisition unit can generate an instruction data acquisition request and send it to the memory unit. The memory unit is used to receive and respond to the instruction data acquisition request, call the internal interface to obtain the current original instruction data and send it to the buffer unit. The buffer unit performs branch target buffer (BTB, BranchTarget Buffer) for branch prediction on the original data, and then organizes the timing information of the original instruction data to obtain the target instruction data.

[0092] For example, please see Figure 4As shown, the instruction fetch module IF can be divided into multiple pipeline steps. The first pipeline step includes the IF1 unit, which fetches the instruction cache storage I-Cache (Instruction Cache) and the instruction local memory (Instruction Local Memory, ILM) in the memory unit according to the program counter (Program Count, PC). Specifically, IF1 can generate an instruction data acquisition request and send it to the memory unit. The instruction cache storage I-Cache (Instruction Cache) and the instruction local memory (Instruction Local Memory, ILM) in the memory unit obtain the original instruction data; the second pipeline step includes the IF2 unit, which is the branch target buffer (Branch Target Buffer, BTB) for branch prediction; in the third pipeline, there is the Algn unit, which performs instruction alignment operations, specifically, obtaining the original instruction data from ILM and ICache, obtaining the instruction code from it and selecting it for alignment, and splicing it into a complete instruction code. At the same time, further branch prediction is performed, including RAS, branch target buffer BTB and branch history table (BHT, Branch Histroy Table) and other schemes. The fourth-stage pipeline step includes the FB unit, which performs time sequence arrangement on the original instruction data, obtains the target instruction data and sends it to the execution module through the IR FIFO unit.

[0093] For example, when 16 instructions are obtained, including instructions 0-15, the instructions 0-15 can be buffered in the FB unit, and then the instruction codes are selected and aligned by the Algn unit, spliced ​​into a complete instruction code, and then the complete instruction code is stored in the instruction buffer IR FIFO unit.

[0094] In the embodiment of the present application, by obtaining the original instruction data from the memory unit and performing buffering and timing information processing in sequence, the target instruction data can be determined more accurately, providing data guidance information for subsequent data execution.

[0095] In an optional embodiment of the present application, the embodiment of the present application provides a specific implementation method of a memory unit, which includes a local storage unit and other storage units.

[0096] The local storage unit is used to receive and respond to instruction data acquisition requests, obtain local original instruction data and send it to the buffer unit; other storage units are used to receive and respond to instruction data acquisition requests, obtain other original instruction data and send it to the buffer unit.

[0097] It can be understood that the storage paths of the above-mentioned local storage unit and other storage units are different, and one or more types of original instruction data can be stored in the local storage unit, and one or more types of original instruction data can be stored in other storage units.

[0098] In this embodiment, the original instruction data can be obtained more comprehensively through the local storage unit and other storage units, so as to facilitate the subsequent more accurate determination of the target instruction data.

[0099] On the other hand, the present application embodiment also provides an instruction processing method, see Fig.12 As shown, the instruction processing method includes the following steps 201 to 203:

[0100] Step 201: Acquire original instruction data, and perform timing information processing on the original instruction data to obtain target instruction data.

[0101] Step 202: Determine the queue instruction data through the transmission queue of the target instruction data, and perform calculation processing on the queue instruction data to obtain an execution result; the number of transmission queues is pre-configured according to the instruction type of the historical instruction data and the data outflow order.

[0102] Step 203: Write back the execution result.

[0103] Among them, the process of determining the queue instruction data through the transmission queue of the target instruction data, and performing calculation processing on the queue instruction data to obtain the execution result includes: determining the queue instruction data corresponding to the transmission queue from the target instruction data; caching the queue instruction data, and performing calculation processing on the queue instruction data to obtain the execution result.

[0104] Specifically, the processor includes an instruction fetch module (IF), an execution module (EX) and a write-back module (WB). The instruction fetch module (IFU) includes a multi-stage pipeline. The first-stage pipeline step includes an IF1 unit, which fetches instructions from the instruction high-speed storage I-Cache (Instruction Cache) and the instruction local storage (Instruction Local Memory, ILM) in the memory unit according to the program counter (Program Count, PC). Specifically, the IF1 unit can generate an instruction data acquisition request and send it to the memory unit. The instruction high-speed storage I-Cache (Instruction Cache) Tag / Data RAM and the instruction local storage (Instruction Local Memory, ILM) RAM in the memory unit obtain the original instruction data; the second-stage pipeline step includes an IF2 unit, which is a branch target buffer (Branch Target Buffer, BTB) for branch prediction; in the third-stage pipeline, there is an Algn unit, which is from the ILM The original instruction data is obtained from the ICache, and the instruction code is obtained and selected for alignment, and then spliced ​​into a complete instruction code. At the same time, further branch prediction is performed, including RAS, branch target buffer BTB and branch history table (BHT) and other schemes. The fourth-level pipeline step includes the FB unit, which arranges the original instruction data in time sequence, obtains the target instruction data and sends it to the execution module through the IRFIFO unit.

[0105] Furthermore, the parameters in the execution module (EX) are configurable. The instructions obtained from the IF are sent to the corresponding queue buffer unit IQ Buf through the transmission list. The transmission list includes LSU IQ, IQ, BJP IQ, and then sent to the corresponding execution units through the queue buffer unit IQ Buf. The operations are processed by the respective execution units and written back to the physical register (physical regfile) through the write-back module WB.

[0106] Compared with the prior art, the instruction processing method in this embodiment, on the one hand, obtains target instruction data by performing timing information processing on the original instruction data, which can provide data guidance information for the subsequent execution module when performing calculation processing, and is adaptable to different scenarios; on the other hand, since different numbers of emission queues are pre-configured according to the instruction type and data outflow order of the historical instruction data, the queue instruction data can be accurately determined in the process of executing data calculation processing, so as to perform processing in parallel based on different queue instruction data to determine the execution result, and write the execution result back. It can pre-configure different parameters according to different application scenarios, adapt to the actual market needs, greatly improve the adaptability and flexibility of data processing, and further improve the performance of the processor in processing data.

[0107] On the other hand, the embodiment of the present application also provides a processing system, which includes the instruction processing device provided by the above embodiment. Compared with the prior art, the processing system of the present application, on the one hand, obtains the target instruction data by processing the original instruction data in timing information, can provide data guidance information for the subsequent execution module to perform operation processing, and is adapted to different scenarios; on the other hand, because different numbers of emission queues are pre-configured according to the instruction type and data outflow order of the historical instruction data, the queue instruction data can be accurately determined in the process of executing data operation processing, so as to facilitate parallel processing based on different queue instruction data, and write back the execution results, which can pre-configure different parameters according to different application scenarios, adapt to the needs of the actual market, greatly improve the adaptability and flexibility of data processing, and further improve the performance of the processor in processing data.

[0108] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0109] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0110] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0111] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0112] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0113] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0114] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. An instruction processing device, characterized in that: The equipment includes: An instruction fetch module, the instruction fetch module is used to obtain original instruction data and perform timing information processing on the original instruction data to obtain target instruction data; An execution module, the execution module is connected to the instruction fetch module, and is used to read the target instruction data from the instruction fetch module, determine the queue instruction data through the emission queue, and perform operation processing on the queue instruction data to obtain the execution result and load and store it; the number of emission queues is pre-configured according to the instruction type and data outflow order of the historical instruction data; the execution module at least includes an emission unit, and the emission unit includes at least two emission queues; each emission queue is used to: determine the queue instruction data corresponding to the emission queue from the target instruction data, and send it to the corresponding queue buffer unit; the at least two emission queues include a first emission queue and a second emission queue; The first emission queue is used to: obtain the queue instruction data from the target instruction data in a preset order, and send them to the corresponding sub-execution unit in a disorderly order; The second emission queue is used to obtain the queue instruction data from the target instruction data in a preset order, and send it to the corresponding sub-execution unit in the preset order; the second emission queue includes a first instruction emission queue and a second instruction emission queue; the first instruction emission queue is used to obtain queue instruction data of a first instruction type from the target instruction data in a preset order, and send it to the corresponding sub-execution unit in a disorderly order, wherein the first instruction type includes at least one of a load instruction type, a storage instruction type, a logical operation instruction type, and a floating-point instruction type; the second instruction emission queue is used to obtain queue instruction data of a second instruction type from the target instruction data in a preset order, and send it to the corresponding sub-execution unit in a disorderly order, wherein the second instruction type includes a jump instruction type; A write-back module, the write-back module is connected to the execution module, and is used to write back the execution result, including: loading and storing to the instruction buffer storage and the instruction local storage, writing the execution result back to the physical register, and renaming the register, establishing a register renaming mapping relationship and storing it in the scoreboard, and reordering the instruction data through the delivery unit.

2. The device according to claim 1, characterized in that The execution module comprises: a queue buffer unit and an execution unit, the emission unit is connected to the execution unit; the execution unit comprises at least two sub-execution units, each emission queue is correspondingly connected to a sub-execution unit; each emission queue is correspondingly connected to a queue buffer unit; Each of the queue buffer units is used to: cache the queue instruction data obtained from the transmit queue and send it to the corresponding sub-execution unit; Each of the sub-execution units is used to: perform calculations on the queue instruction data, obtain execution results, and load and store them.

3. The device according to any one of claims 1 to 2, characterized in that: The device also includes: a physical register, a scoreboard, and a delivery unit; The physical register is used to: store the execution result output by the sub-execution unit; The scoreboard is used to: establish and store a register renaming mapping relationship for the queue instruction data; The delivery unit is used to: perform delivery processing on the queue instruction data.

4. The device according to claim 1, characterized in that The instruction fetch module includes an acquisition unit, a memory unit, a buffer unit, and a storage unit; the memory unit is connected to the acquisition unit and the buffer unit respectively, and the buffer unit is also connected to the storage unit; The acquisition unit is used to send an instruction data acquisition request to the memory unit; The memory unit is used to receive and respond to the instruction data acquisition request, acquire original instruction data and send it to the buffer unit; The buffer unit is used to buffer the original instruction data and send it to the storage unit; The storage unit is used to perform timing information processing on the original instruction data to obtain and store target instruction data.

5. The device according to claim 4, characterized in that The memory unit includes: a local storage unit and other storage units; The local storage unit is used to receive and respond to the instruction data acquisition request, acquire local original instruction data and send it to the buffer unit; The other storage unit is used to receive and respond to the instruction data acquisition request, acquire other original instruction data and send it to the buffer unit.

6. A processing system comprising: An instruction processing device as claimed in any one of claims 1 to 5.

7. A command processing method, characterized in that: Applied to the instruction processing device according to any one of claims 1 to 5, the method comprises: Acquire original instruction data, and perform timing information processing on the original instruction data to obtain target instruction data; Determine the queue instruction data through the transmission queue of the target instruction data, and perform operation processing on the queue instruction data to obtain an execution result; the number of the transmission queues is pre-configured according to the instruction type and data outflow order of the historical instruction data; The execution result is written back.

8. The method according to claim 7, characterized in that The target instruction data is transmitted through a queue to determine queue instruction data, and an operation is performed on the queue instruction data to obtain an execution result, including: Determining queue instruction data corresponding to the transmit queue from the target instruction data; The queue instruction data is cached, and a calculation process is performed on the queue instruction data to obtain an execution result.

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