A high-performance, low-power semiconductor integrated circuit and its design method

Abstract

The present invention relates to the technical field of semiconductor integrated circuits, and provides a high-performance, low-power semiconductor integrated circuit and a design method thereof. The high-performance, low-power semiconductor integrated circuit comprises: a substrate, an insulating layer, a peripheral circuit and a main circuit; the insulating layer is arranged on the substrate; the peripheral circuit and the main circuit are arranged on the insulating layer; and the peripheral circuit is connected to the main circuit. The present invention can achieve a high-performance, low-power semiconductor integrated circuit through the configuration and design of the semiconductor integrated circuit, and improve the data processing speed and throughput of the integrated circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a high-performance, low-power semiconductor integrated circuit and a design method thereof. Background Art

[0002] As the use scenarios of electronic products become more diverse, higher requirements are placed on the design of electronic products and the semiconductor integrated circuits inside them. High-performance and low-power semiconductor integrated circuits are becoming increasingly important for the use of semiconductor devices.

[0003] At present, in the design of semiconductor integrated circuits, the design from the perspective of high efficiency and low power consumption is not good enough. The content of simulation test of semiconductor integrated circuits in the design process is not targeted enough, and the quality of simulation test is not high enough.

[0004] Therefore, it is necessary to provide a high-performance and low-power semiconductor integrated circuit and a design method thereof. Summary of the invention

[0005] The present invention provides a high-performance, low-power semiconductor integrated circuit and a design method thereof. By configuring and designing the semiconductor integrated circuit, a high-performance, low-power semiconductor integrated circuit can be obtained, and the data processing speed and throughput of the integrated circuit can be improved.

[0006] The present invention provides a high-performance and low-power semiconductor integrated circuit, comprising:

[0007] A substrate, an insulating layer, a peripheral circuit and a main circuit; the insulating layer is arranged on the substrate; the peripheral circuit and the main circuit are arranged on the insulating layer; and the peripheral circuit is connected to the main circuit.

[0008] Furthermore, it also includes a memory, and the peripheral circuit is connected to the memory; the memory is used to be controlled by the peripheral circuit to realize data writing and reading.

[0009] Furthermore, the main circuit includes a parallel processing control subcircuit for controlling parallel processing of writing and reading data to and from the memory via the peripheral circuit.

[0010] Furthermore, the main circuit also includes a logic gate operator subcircuit, and the logic gate operator subcircuit includes a plurality of transistors.

[0011] Furthermore, the transistor is a phototransistor, a bipolar transistor, a bipolar junction transistor or a field effect transistor.

[0012] Furthermore, the main circuit also includes a delay subcircuit; the delay subcircuit is connected to the logic gate operation subcircuit and is used to perform delay processing on the signal output from the logic gate operation subcircuit.

[0013] A design method for a high-performance, low-power semiconductor integrated circuit is applied to a high-performance, low-power semiconductor integrated circuit, comprising the following steps:

[0014] Obtaining a substrate and an insulating layer, configuring the insulating layer on the substrate, and configuring a peripheral circuit and a main circuit on the insulating layer;

[0015] Performing functional analysis on the peripheral circuit and the main circuit to obtain functional analysis data, and generating connection structure data of the peripheral circuit and the main circuit based on the functional analysis data;

[0016] According to the connection structure data, the test model is run based on the function to design the connection structure of the peripheral circuit and the main circuit.

[0017] Further, according to the connection structure data, based on the function running test model, the connection structure of the peripheral circuit and the main circuit is designed, including:

[0018] Constructing circuit device layout structure diagrams of peripheral circuits and main circuits based on connection structure data;

[0019] According to the circuit device layout structure diagram, the functional operation of the peripheral circuit and the main circuit is simulated to obtain functional operation simulation data;

[0020] Use the function to run simulation data, run the test model based on the function, and design the connection structure between the peripheral circuit and the main circuit.

[0021] Furthermore, the functional operation simulation data is used to design the connection structure between the peripheral circuit and the main circuit based on the functional operation test model, including:

[0022] Use the set model function server to obtain the function running test model;

[0023] Based on the set host computer, online debugger and online simulator, start the functional operation test model and obtain the functional operation test data;

[0024] Calibrate the functional operation simulation data and the functional operation test data to obtain functional operation correction data;

[0025] The functional operation correction data is used for designing the connection structure between the peripheral circuit and the main circuit.

[0026] Furthermore, it also includes: performing performance simulation test evaluation on the designed high-performance and low-power semiconductor integrated circuit, the specific steps are:

[0027] Configure the performance simulation test scenario according to the set performance simulation test strategy, and set the test task parameters of the performance simulation test scenario;

[0028] Edit and obtain the test script according to the performance simulation test scenario and test task parameters;

[0029] According to the test script, the heat generation of the substrate and the insulation layer, and the power consumption of the peripheral circuit and the main circuit are tested in parallel to obtain the heat generation test data and the power consumption test data;

[0030] According to the heating test data and the power consumption test data, the performance evaluation is performed using the set performance evaluation model to obtain the performance evaluation result;

[0031] According to the performance evaluation results, the periodic change analysis of the performance and the prediction analysis of the performance change are carried out to obtain the periodic change analysis data and the prediction analysis data;

[0032] Based on the periodic variation analysis data and the prediction analysis data, the performance stability of the integrated circuit is evaluated to obtain the performance stability evaluation results;

[0033] Based on the performance stability evaluation results, multiple alternative design structures of peripheral circuits and main circuits are formulated to ensure that when the performance is unstable, the alternative design structures are used to replace or adjust the connection structures of the peripheral circuits and the main circuits.

[0034] Compared with the prior art, the present invention has the following advantages and beneficial effects: through the configuration and design of semiconductor integrated circuits, high-performance and low-power semiconductor integrated circuits can be obtained, and the data processing speed and throughput of the integrated circuits can be improved.

[0035] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description and the accompanying drawings.

[0036] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0038] Figure 1 It is a schematic diagram of the structure of a high-performance and low-power semiconductor integrated circuit;

[0039] Figure 2 A schematic diagram of the steps of a design method for a high-performance and low-power semiconductor integrated circuit;

[0040] Figure 3 A schematic diagram of the method steps for designing the connection structure between the peripheral circuit and the main circuit. DETAILED DESCRIPTION

[0041] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0042] The present invention provides a high-performance and low-power semiconductor integrated circuit, such as Figure 1 As shown, including:

[0043] A substrate, an insulating layer, a peripheral circuit and a main circuit; the insulating layer is arranged on the substrate; the peripheral circuit and the main circuit are arranged on the insulating layer; and the peripheral circuit is connected to the main circuit.

[0044] The working principle of the above technical solution is: in order to realize high-efficiency and low-power semiconductor integrated circuits, the present invention proposes to use a substrate, an insulating layer, a peripheral circuit and a main circuit for configuration; first, the insulating layer is configured on the substrate; then the peripheral circuit and the main circuit are configured on the insulating layer; and the peripheral circuit is connected to the main circuit.

[0045] The beneficial effect of the above technical solution is: by adopting the solution provided in this embodiment, through the configuration and design of the semiconductor integrated circuit, a high-performance and low-power semiconductor integrated circuit can be obtained, and the data processing speed and throughput of the integrated circuit can be improved.

[0046] In one embodiment, a memory is also included, and the peripheral circuit is connected to the memory; the memory is used to be controlled by the peripheral circuit to achieve data writing and reading.

[0047] The working principle of the above technical solution is: the present invention is equipped with a memory, which is connected through a peripheral circuit; the memory is used to be controlled by the peripheral circuit to realize data writing and reading.

[0048] The beneficial effects of the above technical solution are as follows: by adopting the solution provided in this embodiment, the storage of data by the memory facilitates the realization of the functions of the integrated circuit, and the writing and reading of data can be realized through the control of the peripheral circuit.

[0049] In one embodiment, the main circuit includes a parallel processing control subcircuit for controlling parallel processing of writing and reading data to and from the memory via the peripheral circuit.

[0050] The working principle of the above technical solution is: in order to realize the parallel processing function of the integrated circuit, a parallel processing control subcircuit is set in the main circuit to realize the parallel processing of writing and reading data to the memory via the peripheral circuit.

[0051] The beneficial effect of the above technical solution is: by adopting the solution provided by this embodiment, the parallel processing function of the integrated circuit can be realized through the setting of the parallel processing control subcircuit.

[0052] In one embodiment, the main circuit further includes a logic gate operation subcircuit, and the logic gate operation subcircuit includes a plurality of transistors.

[0053] The working principle of the above technical solution is: by setting a logic gate operator circuit, the logic gate operator circuit includes a number of transistors, and the optimized layout of the logic gate can be achieved.

[0054] The beneficial effect of the above technical solution is: by adopting the solution provided by this embodiment, the optimized layout of the logic gates can be achieved through the logic gate operation sub-circuit.

[0055] In one embodiment, the transistor is a phototransistor, a bipolar transistor, a bipolar junction transistor, or a field effect transistor.

[0056] The working principle of the above technical solution is: setting the type of transistor to a phototransistor, a bipolar transistor, a bipolar junction transistor or a field effect transistor can realize the selection of devices of the logic gate operation subcircuit.

[0057] The beneficial effect of the above technical solution is: by adopting the solution provided by this embodiment, by setting different types of transistors, a basis is provided for selecting devices of the logic gate operation sub-circuit.

[0058] In one embodiment, the main circuit further includes a delay subcircuit; the delay subcircuit is connected to the logic gate operation subcircuit and is used to perform delay processing on the signal output from the logic gate operation subcircuit.

[0059] The working principle of the above technical solution is: in order to achieve control over the reduction of signal transmission delay, the present invention sets a delay subcircuit in the main circuit; the delay subcircuit is connected to the logic gate operation subcircuit, and is used to delay the signal output from the logic gate operation subcircuit.

[0060] The beneficial effect of the above technical solution is: by adopting the solution provided by this embodiment, by setting a delay sub-circuit, it is possible to achieve control over the reduction of signal transmission delay.

[0061] A design method for high-performance and low-power semiconductor integrated circuits, such as Figure 2 As shown, it is applied to a high-performance and low-power semiconductor integrated circuit, including the following steps:

[0062] Obtaining a substrate and an insulating layer, configuring the insulating layer on the substrate, and configuring a peripheral circuit and a main circuit on the insulating layer;

[0063] Performing functional analysis on the peripheral circuit and the main circuit to obtain functional analysis data, and generating connection structure data of the peripheral circuit and the main circuit based on the functional analysis data;

[0064] According to the connection structure data, the test model is run based on the function to design the connection structure of the peripheral circuit and the main circuit.

[0065] The working principle of the above technical solution is: in order to realize the design method of high-efficiency and low-power semiconductor integrated circuits, the present invention first obtains a substrate and an insulating layer, configures the insulating layer on the substrate, and configures the peripheral circuit and the main circuit on the insulating layer; then performs functional analysis on the peripheral circuit and the main circuit to obtain functional analysis data, and generates connection structure data of the peripheral circuit and the main circuit based on the functional analysis data; finally, according to the connection structure data, based on the functional operation test model, designs the connection structure of the peripheral circuit and the main circuit.

[0066] The beneficial effect of the above technical solution is: by adopting the solution provided in this embodiment, the design quality of high-efficiency and low-power semiconductor integrated circuits can be guaranteed by performing basic configuration based on the substrate and the insulating layer, and then designing the connection structure of the peripheral circuit and the main circuit.

[0067] In one embodiment, according to the connection structure data, the connection structure of the peripheral circuit and the main circuit is designed based on the function running test model, such as Figure 3 As shown, including:

[0068] Constructing circuit device layout structure diagrams of peripheral circuits and main circuits based on connection structure data;

[0069] According to the circuit device layout structure diagram, the functional operation of the peripheral circuit and the main circuit is simulated to obtain functional operation simulation data;

[0070] Use the function to run simulation data, run the test model based on the function, and design the connection structure between the peripheral circuit and the main circuit.

[0071] The working principle of the above technical solution is: in order to design the connection structure between the peripheral circuit and the main circuit, the present invention first constructs a circuit device layout structure diagram of the peripheral circuit and the main circuit according to the connection structure data; then, according to the circuit device layout structure diagram, the functional operation of the peripheral circuit and the main circuit is simulated to obtain functional operation simulation data; finally, using the functional operation simulation data and based on the functional operation test model, the connection structure of the peripheral circuit and the main circuit is designed.

[0072] The beneficial effect of the above technical solution is: by adopting the solution provided in this embodiment, the connection structure of the peripheral circuit and the main circuit is designed according to the connection structure data and combined with the functional operation simulation data, so that the scientific nature of the design can be guaranteed.

[0073] In one embodiment, the connection structure of the peripheral circuit and the main circuit is designed based on the functional operation test model by using the functional operation simulation data, including:

[0074] Use the set model function server to obtain the function running test model;

[0075] Based on the set host computer, online debugger and online simulator, start the functional operation test model and obtain the functional operation test data;

[0076] Calibrate the functional operation simulation data and the functional operation test data to obtain functional operation correction data;

[0077] The functional operation correction data is used for designing the connection structure between the peripheral circuit and the main circuit.

[0078] The working principle of the above technical scheme is: in order to utilize the function operation simulation data and design the connection structure of the peripheral circuit and the main circuit based on the function operation test model, the present invention first utilizes the set model function server to obtain the function operation test model; then based on the set host computer, online debugger and online simulator, the function operation test model is started to obtain the function operation test data; then, the function operation simulation data and the function operation test data are calibrated to obtain the function operation correction data; finally, the function operation correction data is used for the design of the connection structure of the peripheral circuit and the main circuit.

[0079] The beneficial effect of the above technical solution is: by adopting the solution provided in this embodiment, by performing calibration processing based on functional operation simulation data and functional operation test data, it is possible to ensure that functional operation correction data is obtained, and it helps to ensure the accuracy of the design of the connection structure between the peripheral circuit and the main circuit.

[0080] In one embodiment, the method further includes: performing a performance simulation test and evaluation on the designed high-performance and low-power semiconductor integrated circuit, the specific steps of which are:

[0081] Configure the performance simulation test scenario according to the set performance simulation test strategy, and set the test task parameters of the performance simulation test scenario;

[0082] Edit and obtain the test script according to the performance simulation test scenario and test task parameters;

[0083] According to the test script, the heat generation of the substrate and the insulation layer, and the power consumption of the peripheral circuit and the main circuit are tested in parallel to obtain the heat generation test data and the power consumption test data;

[0084] According to the heating test data and the power consumption test data, the performance evaluation is performed using the set performance evaluation model to obtain the performance evaluation result;

[0085] According to the performance evaluation results, the periodic change analysis of the performance and the prediction analysis of the performance change are carried out to obtain the periodic change analysis data and the prediction analysis data;

[0086] Based on the periodic variation analysis data and the prediction analysis data, the performance stability of the integrated circuit is evaluated to obtain the performance stability evaluation results;

[0087] Based on the performance stability evaluation results, multiple alternative design structures of peripheral circuits and main circuits are formulated to ensure that when the performance is unstable, the alternative design structures are used to replace or adjust the connection structures of the peripheral circuits and the main circuits.

[0088] The working principle of the above technical solution is as follows: in order to perform performance simulation test evaluation on the designed high-efficiency and low-power semiconductor integrated circuit, the present invention first configures the performance simulation test scenario according to the set performance simulation test strategy, and sets the test task parameters of the performance simulation test scenario; then, according to the performance simulation test scenario and the test task parameters, edits and obtains the test script; according to the test script, the heat generation of the substrate and the insulating layer, the power consumption of the peripheral circuit and the main circuit are tested in parallel to obtain the heat generation test data and the power consumption test data; according to the heat generation test data and the power consumption test data, the performance evaluation is performed using the set performance evaluation model to obtain the performance evaluation result; according to the performance evaluation result, the periodic change analysis of the performance and the predictive analysis of the performance change are performed to obtain the periodic change analysis data and the predictive analysis data; finally, based on the periodic change analysis data and the predictive analysis data, the performance stability of the integrated circuit is evaluated to obtain the performance stability evaluation result; based on the performance stability evaluation result, a plurality of alternative design structures of the peripheral circuit and the main circuit are formulated to ensure that when the performance is unstable, the alternative design structure is used to replace or adjust the connection structure of the peripheral circuit and the main circuit.

[0089] The beneficial effect of the above technical solution is: by adopting the solution provided in this embodiment, a performance simulation test is performed on the designed high-efficiency and low-power semiconductor integrated circuit, and based on the evaluation results, multiple alternative design structures of peripheral circuits and main circuits are formulated to ensure that when the performance is unstable, the alternative design structure is used to replace or adjust the connection structure of the peripheral circuit and the main circuit, thereby ensuring the reliability of the design of the peripheral circuit and the main circuit.

[0090] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A design method for a high-performance, low-power semiconductor integrated circuit, characterized in that: The following steps are involved: Obtaining a substrate and an insulating layer, configuring the insulating layer on the substrate, and configuring a peripheral circuit and a main circuit on the insulating layer; Performing functional analysis on the peripheral circuit and the main circuit to obtain functional analysis data, and generating connection structure data of the peripheral circuit and the main circuit based on the functional analysis data; According to the connection structure data, the test model is run based on the function to design the connection structure of the peripheral circuit and the main circuit; It also includes: conducting performance simulation test evaluation on the designed high-performance and low-power semiconductor integrated circuit, the specific steps are: Configure the performance simulation test scenario according to the set performance simulation test strategy, and set the test task parameters of the performance simulation test scenario; Edit and obtain the test script according to the performance simulation test scenario and test task parameters; According to the test script, the heat generation of the substrate and the insulation layer, and the power consumption of the peripheral circuit and the main circuit are tested in parallel to obtain the heat generation test data and the power consumption test data; According to the heating test data and the power consumption test data, the performance evaluation is performed using the set performance evaluation model to obtain the performance evaluation result; According to the performance evaluation results, the periodic change analysis of the performance and the prediction analysis of the performance change are carried out to obtain the periodic change analysis data and the prediction analysis data; Based on the periodic variation analysis data and the prediction analysis data, the performance stability of the integrated circuit is evaluated to obtain the performance stability evaluation results; Based on the performance stability evaluation results, multiple alternative design structures of peripheral circuits and main circuits are formulated to ensure that when the performance is unstable, the alternative design structures are used to replace or adjust the connection structures of the peripheral circuits and the main circuits.

2. The design method of a high-performance and low-power semiconductor integrated circuit according to claim 1, characterized in that: According to the connection structure data, the test model is run based on the function to design the connection structure of the peripheral circuit and the main circuit, including: Constructing circuit device layout structure diagrams of peripheral circuits and main circuits based on connection structure data; According to the circuit device layout structure diagram, the functional operation of the peripheral circuit and the main circuit is simulated to obtain functional operation simulation data; Use the function to run simulation data, run the test model based on the function, and design the connection structure between the peripheral circuit and the main circuit.

3. The design method of a high-performance and low-power semiconductor integrated circuit according to claim 1, characterized in that: Use the function to run simulation data, run the test model based on the function, and design the connection structure between the peripheral circuit and the main circuit, including: Use the set model function server to obtain the function running test model; Based on the set host computer, online debugger and online simulator, start the functional operation test model and obtain the functional operation test data; Calibrate the functional operation simulation data and the functional operation test data to obtain functional operation correction data; The functional operation correction data is used for designing the connection structure between the peripheral circuit and the main circuit.

4. A high-performance, low-power semiconductor integrated circuit, characterized in that: A design method for a high-performance, low-power semiconductor integrated circuit according to any one of claims 1 to 3 is designed and implemented, comprising: A substrate, an insulating layer, a peripheral circuit and a main circuit; the insulating layer is arranged on the substrate; the peripheral circuit and the main circuit are arranged on the insulating layer; the peripheral circuit is connected to the main circuit; The main circuit includes a parallel processing control subcircuit for controlling parallel processing of writing and reading data to and from the memory via the peripheral circuit.

5. The high-performance, low-power semiconductor integrated circuit according to claim 4, characterized in that: It also includes a memory, and the peripheral circuit is connected to the memory; the memory is used to be controlled by the peripheral circuit to realize data writing and reading.

6. The high-performance, low-power semiconductor integrated circuit according to claim 4, characterized in that: The main circuit also includes a logic gate operator circuit, and the logic gate operator circuit includes a plurality of transistors.

7. The high-performance, low-power semiconductor integrated circuit according to claim 4, characterized in that: The transistor is a phototransistor, a bipolar transistor or a field effect transistor.

8. The high-performance, low-power semiconductor integrated circuit according to claim 4, characterized in that: The main circuit also includes a delay subcircuit; the delay subcircuit is connected to the logic gate operation subcircuit and is used for delaying the signal output from the logic gate operation subcircuit.

Images