A fast reconstruction method of compressed sensing based on FPGA neural circuit

Abstract

This invention discloses a fast compressed sensing reconstruction method based on FPGA neural circuits, comprising the following steps: S1, establishing a compressed sensing optimization model and solving the compressed sensing optimization model using a fixed-time neural dynamics optimization model; S2, discretizing the fixed-time neural dynamics optimization model; S3, constructing an FPGA circuit; S4, based on the FPGA circuit, constructing an FPGA neural circuit consisting of an input layer, a parallel computing layer, and an output layer, and using the FPGA neural circuit to solve the discretized fixed-time neural dynamics optimization model; S5, initializing the parameters of the fixed-time neural dynamics optimization model and setting an upper bound on the convergence time; S6, using the fixed-time neural dynamics optimization model to process compressed sensing reconstruction. This invention significantly improves the reconstruction speed while ensuring the quality of the reconstructed signal, saving reconstruction time and increasing the reconstruction rate.

Description

Technical Field

[0001] The present invention relates to the field of FPGA circuit technology, and in particular to a compressed sensing fast reconstruction method based on FPGA neural circuit. Background Art

[0002] Compressed sensing is a technology that restores the original signal with sampling points far lower than the requirements of the Nyquist sampling theorem, under the premise that the sampled signal is a sparse signal. Compressed sensing technology breaks through the traditional Nyquist theorem, greatly reducing the sampling time and the number of signal transmissions, and has been widely used in medical imaging, wireless communications and other fields. In recent years, by modeling the compressed sensing reconstruction problem as a convex optimization problem, scholars have proposed many optimization algorithms for dealing with compressed sensing reconstruction problems, such as minimizing the L1 norm method, iterative threshold optimization method, and accelerated iterative threshold optimization method. The convergence time of the above algorithms strongly depends on the choice of the initial point. The computational complexity required to solve high-dimensional problems is huge, and it is not conducive to hardware implementation. Therefore, it faces many difficulties in actual deployment.

[0003] The neurodynamic optimization algorithm is an optimization algorithm that simulates the mechanism of neuronal activity and constructs a stable convergent dynamic system through the Lyapunov stability theory. As a current research hotspot in the field of artificial neural networks, the neurodynamic optimization algorithm has the characteristics of parallel computing, fast convergence, strong interpretability, and strong real-time performance. It has been widely used in the fields of robotics, image processing, and automatic control. The neurodynamic optimization algorithm with fixed-time convergence can converge to the equilibrium point in a fixed time without relying on the initial conditions. Using the neurodynamic optimization algorithm with fixed-time convergence to deal with compressed sensing problems can quickly and accurately reconstruct the original signal in a fixed time with a small amount of calculation.

[0004] Analog circuits, CPUs and other hardware devices cannot adapt well to the parallelism of the neurodynamic optimization algorithm, which affects the convergence speed. FPGA circuits are well known for their high flexibility and parallel processing capabilities. Implementing a fixed-time neurodynamic optimization algorithm on FPGA circuits to process compressed sensing reconstruction problems provides a new solution for low-energy, high-speed, and high-parallel processing of compressed sensing reconstruction problems. Summary of the invention

[0005] The purpose of the present invention is to provide a method for fast reconstruction of compressed sensing based on FPGA neural circuits to solve the technical problem of fast compressed sensing reconstruction in FPGA neural circuits.

[0006] To achieve the above object, the present invention provides the following technical solution: a compressed sensing fast reconstruction method based on FPGA neural circuit, comprising the following steps:

[0007] S1. Establish a compressed sensing optimization model and solve the compressed sensing optimization model through a fixed-time neural dynamics optimization model;

[0008] S2, discretize the fixed-time neural dynamics optimization model in S1;

[0009] S3, constructing an FPGA circuit, including a control module, a gradient module, a proximal operator module, and a computing module;

[0010] S4. Based on the FPGA circuit, an FPGA neural circuit consisting of an input layer, a parallel computing layer and an output layer is constructed, and the FPGA neural circuit is used to solve the discretized fixed-time neural dynamics optimization model;

[0011] S5, initializing the parameters of the fixed-time neural dynamics optimization model and setting the upper bound of the convergence time;

[0012] S6. Using fixed-time neural dynamics optimization model to handle compressed sensing reconstruction.

[0013] In some embodiments, by using the L1 norm to approximate the L0 norm and introducing a regularization parameter μ, the compressed sensing optimization model in S1 can be converted into a Lagrangian relaxation model based on the L1 norm:

[0014]

[0015] Where Y is the compressed low-dimensional signal, s is the reconstructed signal, θ is the perception matrix, μ is the regularization parameter, ‖·‖1 is the L1 norm, and ‖·‖ is the L2 norm.

[0016] In some embodiments, in S1, the fixed-time neural dynamics optimization model is:

[0017]

[0018] in,

[0019]

[0020] In the formula, β>0, θ1, θ2>0, 0<ω<1, χ<0 are five adjustable parameters, prox H is the proximal operator; is the gradient of the function L(x); ω is the first exponent; χ is the second exponent.

[0021] In some embodiments, S2 includes the following steps:

[0022] Initialize the parameters and set the number of iterations to k≤[T set / d]+1;

[0023] t = kd;

[0024]

[0025] k = k + 1;

[0026] Output: x k ;

[0027] Where, T set is the task time; d is the step length; prox H is the proximal operator; k is the number of iterations; ω, χ, θ1, θ2, β are adjustable parameters; Optimizing models for fixed-time neural dynamics; x k is the value of the k-th iteration formula x; t is the intermediate variable.

[0028] In some embodiments, the workflow of the FPGA circuit in S3 is:

[0029] The control module includes a finite state machine and an iteration controller, which are used to control the iteration process of the entire FPGA circuit;

[0030] The gradient module is used to calculate the gradient information and pass it to the proximal operator module to calculate the proximal operator, and then the calculation module calculates the final value of each iteration;

[0031] The calculation module determines the number of iterations and the moving distance ‖x n+1 -x n ‖ 2 Whether the preset threshold is reached is used to determine whether the iteration needs to continue. If it does not need to continue, the final value is output.

[0032] In some embodiments, the input layer of the FPGA neural circuit is responsible for inputting the compressed signal in blocks under the control of the input layer finite state machine, and the size of the block is set according to specific needs;

[0033] The parallel computing layer includes a control module and a parallel computing module, which are used to parallelly compute the compressed signal;

[0034] The output layer, under the control of the output layer finite state machine, multiplies the sparse solution with the sparse base matrix to reconstruct the original signal, adjusts the signal format and then outputs it;

[0035] The input layer, the control module and the output layer are all provided with a read-only memory, and the read-only memory is used to store the compressed signal, the perception matrix, the perception matrix transposition and the sparse matrix.

[0036] In some embodiments, in S5, the upper bound of the convergence time is:

[0037]

[0038] in,

[0039]

[0040] Where ω, χ, θ1, θ2, β are adjustable parameters; Γ is the gamma function; L f for The corresponding Lipschitz constant; τ is the proximal PL condition coefficient.

[0041] In some embodiments, the finite state machine includes an input layer finite state machine and an output layer finite state machine, the input layer finite state machine records the current signal position, when it reaches a set threshold, the input layer finite state machine jumps from a ready state to an output state, outputs the signal when a start signal is set high and a one-beat delay signal of the start signal is set low, then jumps back to the ready state, and reloads the block value;

[0042] After receiving the star signal, the output layer finite state machine jumps from the waiting state to the calculation state to reconstruct the original signal. After the calculation is completed and the cnt_pi_1 (counting signal delayed one beat signal) signal is set high, the output layer finite state machine jumps to the output state, organizes the reconstructed signal and inputs it into the random access memory RAM and returns to the waiting state.

[0043] In some embodiments, the computational expression of the proximal operator is:

[0044]

[0045] Where ‖·‖1 is the L1 norm and μ is the regularization parameter.

[0046] Compared with the prior art, the present invention has the following beneficial effects:

[0047] While ensuring the quality of the reconstructed signal, the present invention greatly improves the reconstruction speed, saves the time for reconstructing the signal, increases the rate of reconstructing the signal, greatly improves the hardware energy efficiency, and provides a new idea for embedded fast and parallel processing of large-scale compressed sensing reconstruction problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is a schematic diagram of the process of the present invention;

[0049] Figure 2 is a schematic diagram of an embodiment of the present invention;

[0050] Figure 3 This is a schematic diagram of the FPGA circuit state machine flow chart of an embodiment of the present invention;

[0051] Figure 4This is a schematic diagram of the FPGA circuit structure of an embodiment of the present invention;

[0052] Figure 5 This is a schematic diagram of the input layer finite state machine flow chart of an embodiment of the present invention;

[0053] Figure 6 This is a schematic diagram of the structure of an FPGA neural circuit according to an embodiment of the present invention;

[0054] Figure 7 This is a schematic diagram of the output layer finite state machine flow of an embodiment of the present invention;

[0055] Figure 8 This is a schematic diagram comparing the images reconstructed by the embodiment of the present invention and the 12th generation Intel i5-124500H CPU; the first row is the picture "house", and the second row is the picture "tank";

[0056] Fig. 9 The figure is a schematic diagram comparing the peak signal-to-noise ratio (PSNR), running time and operating power of compressed sensing reconstruction of a 512×512 grayscale image between an embodiment of the present invention and the 12th generation Intel i5-124500H CPU, wherein Figure (a) is a peak signal-to-noise ratio (PSNR) comparison diagram, Figure (b) is a running time comparison diagram, and Figure (c) is an operating power comparison diagram. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0058] See also Figure 1 , a fast reconstruction method of compressed sensing based on FPGA neural circuit, comprising the following steps:

[0059] S1. Establish a compressed sensing optimization model and solve the compressed sensing optimization model through a fixed-time neural dynamics optimization model;

[0060] The basic optimization modeling of the compressed sensing reconstruction problem is:

[0061] min s ‖s‖0 subject to Y=θs (1);

[0062] Where s is the sparse signal to be reconstructed, θ is the perception matrix, ‖·‖0 is the L0 norm, subjectto is the constraint condition, and Y is the compressed low-dimensional signal.

[0063] Using the L1 norm to approximate the L0 norm and the regularization parameter μ, the above expression can be converted into a Lagrangian relaxation model based on the L1 norm:

[0064]

[0065] Where Y is the compressed low-dimensional signal, s is the reconstructed signal, θ is the perception matrix, ||·||1 is the L1 norm, and ||·|| is the L2 norm.

[0066] Formula (2) can be simplified as:

[0067] min x F(x)=L(x)+H(x);

[0068] Where, L(x)=0.5||Y-θs|| 2 ; H(x) = μ||s||1;

[0069] In order to solve the compressed sensing problem of formula (2), a fixed-time neural dynamics optimization model is established:

[0070]

[0071] in,

[0072]

[0073] In the formula, β>0, θ1, θ2>0, 0<ω<1, χ<0 are five adjustable parameters, prox H is the proximal operator; ω is the first index; χ is the second index.

[0074] The proximal operator is:

[0075]

[0076] Where ||·||1 is the L1 norm and μ is the regularization parameter.

[0077] S2, discretize the fixed-time neural dynamics optimization model in S1;

[0078] Since the fixed-time neural dynamics optimization model is continuous-time, it needs to be converted into discrete form through Euler discretization before being put into application; the pseudo code for the discretization of the fixed-time neural dynamics optimization model is shown in Table 1.

[0079] Table 1 Pseudocode for discretization of fixed-time neural dynamics optimization model

[0080]

[0081] S3, constructing an FPGA circuit, including a control module, a gradient module, a proximal operator module, and a computing module;

[0082] The control module includes a finite state machine and an iteration controller, which are used to control the iteration process of the entire FPGA circuit;

[0083] The gradient module is used to calculate the gradient information and pass it to the proximal operator module to calculate the proximal operator, and then the calculation module calculates the final value of each iteration;

[0084] The calculation module determines the number of iterations and the moving distance ‖x n+1 -x n ‖ 2 Whether the preset threshold is reached is used to determine whether the iteration needs to continue. If it does not need to continue, the final value is output.

[0085] like Figure 4 As shown, the FPGA circuit of this embodiment uses 25-bit 16-bit precision fixed-point numbers for data processing, wherein FSM is a finite state machine that controls the iteration process of the FPGA circuit. The specific iteration process is as follows Figure 3 As shown. After the x_Valid signal is set high, the finite state machine reads the input signal and jumps to state 2; in state 2, the finite state machine waits for the calculation module to complete the calculation, and jumps to state 3 after the calc_ok signal is set high; in state 3, the finite state machine calls ITB to complete the iteration judgment function. If irr_tell is set low, the iteration stops and jumps to state 4 to end the iteration, otherwise it jumps back to state 2 to iterate again; in state 4, the finite state machine outputs the result and returns to state 1. ITB is an iterative controller, which judges the number of iterations and the moving distance ‖x n+1 -x n ‖ 2 Whether the preset threshold is reached or not, an iterative decision signal is output. Gradient is a gradient calculation module. Prox is the proximal operator calculation module, which implements the proximal operator function through formula (4) to calculate Calculating is a calculation update module that implements formula (3) to update the value of x.

[0086] S4. Based on the FPGA circuit, an FPGA neural circuit consisting of an input layer, a parallel computing layer and an output layer is constructed, and the FPGA neural circuit is used to solve the discretized fixed-time neural dynamics optimization model;

[0087] Since the FPGA circuit that implements the fixed-time neural dynamics optimization model cannot be used to process the high-dimensional compressed sensing reconstruction problem, in order to further expand the FPGA circuit to the compressed sensing reconstruction problem, this embodiment constructs an FPGA neural circuit consisting of an input layer, a parallel computing layer, and an output layer.

[0088] like Figure 6 As shown, the perception matrix and sparse matrix values ​​are stored in the ROM of the FPGA in advance, and the FPGA neural circuit is used to implement full hardware high-speed parallel image compression perception reconstruction.

[0089] ROM is a read-only memory used to store CompressedSignal, SensoryMatrix, SensoryMatrixtrans and SparseMatrix. InputLayer is the input layer, which is responsible for inputting the compressed image in blocks under the control of the input layer finite state machine. The size of the block can be set as needed. The state of the input layer finite state machine is as follows: Figure 5 As shown. Figure 2 As shown, the coordinates cur_height and cur_length are used to record the current pixel position. When the coordinate value reaches the set threshold, cur_height and cur_length are set to zero, and the base coordinates base_height and base_length move to point to the beginning of the next patch. The input layer finite state machine jumps from the preparation state to the output state, and outputs all the pixels of the block when the start signal is set high and the one-beat delay signal pre_flag of the start signal is set low, and then jumps back to the preparation state to reload the block value. FXPNN is a neural dynamics optimization processing layer based on the FPGA circuit expansion built in S3, in which ControlModule is the control module, ParalellCalcModule is the parallel calculation module, and OutputLayer is the output layer, which is responsible for multiplying the sparse solution with the sparse base matrix to reconstruct the original signal, adjust the signal format and output it under the control of the output layer state machine. The state of the output layer finite state machine is as follows Figure 7 As shown. After receiving the start signal, the output layer finite state machine jumps from the waiting state to the calculation state to reconstruct the original signal. After the calculation is completed and the cnt_pi_1 signal is set high, the output layer finite state machine jumps to the output state, sorts the reconstructed signal and inputs it into the random access memory RAM and returns to the waiting state. The random access memory RAM is used to cache the reconstructed signal Reconstructedsignal.

[0090] S5. Initialize the parameters of the fixed-time neural dynamics optimization model and set the upper bound of the convergence time; assume that H(x) in formula (2) is a closed convex function, L(x) is a second-order continuously differentiable function and has Where E is the identity matrix, L f for The corresponding Lipschitz constant, F(x) satisfies the proximal PL condition (Proximal Polyak-Lojasiewicz condition), and L f β<1, then according to Lyapunov fixed-time stability theory, the fixed-time neural dynamics optimization model converges to the equilibrium point within a fixed time, and the upper bound of the convergence time is:

[0091]

[0092] in,

[0093]

[0094]

[0095] Where ω, χ, θ1, θ2, and β are adjustable parameters, ω = 0.5; χ = -0.5; θ1 = θ2 = 25; β = 1; Γ is the gamma function; L f for The corresponding Lipschitz constant; τ is the proximal PL condition coefficient.

[0096] S6. Using fixed-time neural dynamics optimization model to handle compressed sensing reconstruction.

[0097] In a specific embodiment, two grayscale images named "house" and "tank" with a size of 512×512 are selected as original images. The images are uniformly divided into 4096 small blocks of 8×8, and 75% of each block is used for compressed sensing reconstruction through Gaussian random subsampling. In this embodiment, the sparse matrix is ​​taken as the discrete cosine domain basis matrix. The two images are compressed sensing reconstructed on a laptop computer with a 12th generation Intel i5-124500H CPU and an Artix-7XC7A200TXilinxFPGA running at a frequency of 50MHZ. The original image and the reconstructed image are shown in Figure 2. Figure 8 shown.

[0098] This embodiment uses the peak signal-to-noise ratio (PSNR) to measure the quality of the reconstructed image, and makes a comprehensive comparison of the image reconstruction time and the image reconstruction hardware power consumption. The results are as follows: Fig. 9 As shown. Fig. 9It can be seen that the 12th generation Intel i5-124500H CPU takes about 75 seconds to reconstruct an image, while the FPGA neural circuit only takes about 5 seconds, and the reconstruction speed is 15 times that of the 12th generation Intel i5-124500H CPU; the 12th generation Intel i5-124500H CPU operates at about 40W, while the FPGA neural circuit only requires 0.42W, which is 1.05% of the 12th generation Intel i5-124500H CPU; at the same time, the PSNR of the reconstructed images by the FPGA neural circuit is above 30, ensuring good reconstruction quality.

[0099] The above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the scope of protection of the invention.

Claims

1. A fast reconstruction method for compressed sensing based on FPGA neural circuit, characterized in that: The following steps are involved: S1. Establish a compressed sensing optimization model and solve the compressed sensing optimization model through a fixed-time neural dynamics optimization model; S2, discretize the fixed-time neural dynamics optimization model in S1; S3, constructing an FPGA circuit, including a control module, a gradient module, a proximal operator module, and a computing module; S4. Based on the FPGA circuit, an FPGA neural circuit consisting of an input layer, a parallel computing layer and an output layer is constructed, and the FPGA neural circuit is used to solve the discretized fixed-time neural dynamics optimization model; S5. Initialize the parameters of the fixed-time neural dynamics optimization model and set the upper bound of the convergence time: The upper bound of the convergence time is: in, Where ω, χ, θ1, θ2, β are adjustable parameters; Γ is the gamma function; L f for The corresponding Lipschitz constant, τ is the proximal PL condition coefficient; S6. Using fixed-time neural dynamics optimization model to handle compressed sensing reconstruction.

2. According to the method of claim 1, the compressed sensing fast reconstruction method based on FPGA neural circuit is characterized in that: In S1, the compressed sensing optimization model is: Where Y is the compressed low-dimensional signal, s is the reconstructed signal, θ is the perception matrix, μ is the regularization parameter, ‖·‖1 is the L1 norm, and ‖·‖ is the L2 norm.

3. The method for fast reconstruction of compressed sensing based on FPGA neural circuit according to claim 1, characterized in that: In S1, the fixed-time neural dynamics optimization model is: in, In the formula, β>0, θ1, θ2>0, 0<ω<1, χ<0 are five adjustable parameters, prox H is the proximal operator; is the gradient of the function L(x); ω is the first exponent; χ is the second exponent.

4. The method for fast reconstruction of compressed sensing based on FPGA neural circuit according to claim 1, characterized in that: S2 includes the following steps: Initialize the parameters and set the number of iterations to k≤[T set / d]+1; t = kd; k = k + 1; Output: x k ; Where, T set is the task time; d is the step length; prox H is the proximal operator; k is the number of iterations; ω, χ, θ1, θ2, β are adjustable parameters; Optimizing models for fixed-time neural dynamics; x k is the value of x at the kth iteration.

5. The method for fast reconstruction of compressed sensing based on FPGA neural circuit according to claim 1, characterized in that: The workflow of the FPGA circuit in S3 is: The control module includes a finite state machine and an iteration controller, which are used to control the iteration process of the entire FPGA circuit; The gradient module is used to calculate the gradient information and pass it to the proximal operator module to calculate the proximal operator, and then the calculation module calculates the final value of each iteration; The calculation module determines the number of iterations and the moving distance ‖x n+1 -x n ‖ 2 Whether the preset threshold is reached is used to determine whether the iteration needs to continue. If it does not need to continue, the final value is output.

6. The method for fast reconstruction of compressed sensing based on FPGA neural circuit according to claim 5, characterized in that: The input layer of the FPGA neural circuit is responsible for inputting the compressed signal in blocks under the control of the input layer finite state machine, and the size of the block is set according to specific needs; The parallel computing layer includes a control module and a parallel computing module, which are used to parallelly compute the compressed signal; The output layer, under the control of the output layer finite state machine, multiplies the sparse solution with the sparse base matrix to reconstruct the original signal, adjusts the signal format and then outputs it; The input layer, the control module and the output layer are all provided with a read-only memory, and the read-only memory is used to store the compressed signal, the perception matrix, the perception matrix transposition and the sparse matrix.

7. The method for fast reconstruction of compressed sensing based on FPGA neural circuit according to claim 5, characterized in that: The finite state machine comprises an input layer finite state machine and an output layer finite state machine. The input layer finite state machine records the current signal position. When it reaches a set threshold, the input layer finite state machine jumps from a ready state to an output state, outputs the signal when a start signal is set high and a one-beat delay signal of the start signal is set low, and then jumps back to the ready state to reload the block value. After receiving the start signal, the output layer finite state machine jumps from the waiting state to the calculation state, reconstructs the original signal, and after the calculation is completed and the counting signal delay signal cnt_pi_1 is set high, the output layer finite state machine jumps to the output state, organizes the reconstructed signal and inputs it into the random access memory RAM and returns to the waiting state.

8. The method for fast reconstruction of compressed sensing based on FPGA neural circuit according to claim 5, characterized in that: The calculation expression of the proximal operator is: Where ‖·‖1 is the L1 norm and μ is the regularization parameter.

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