Driving circuit, driving method, and display device

Abstract

The application provides a driving circuit, a driving method and a display device. The driving circuit comprises a driving output end, an input circuit, an output circuit and a pull-up node; the input circuit writes an input voltage into the pull-up node under the control of an input control signal; the output circuit writes a clock signal into the driving output end under the control of the potential of the pull-up node; the driving circuit further comprises a potential control circuit and a first energy storage circuit; the potential control circuit controls the communication or disconnection between a first control end and a control node under the control of the potential of the pull-up node; the first end of the first energy storage circuit is electrically connected with the control node, and the second end of the first energy storage circuit is electrically connected with the pull-up node; and the first energy storage circuit is used for storing electric energy. The application can prevent the potential of the pull-up node from being reduced in the touch stage, prevent the potential of the driving signal provided by the driving circuit from being reduced when the display stage is entered again, and avoid the generation of LH horizontal lines.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a driving circuit, a driving method and a display device. BACKGROUND

[0002] In the related art, when a TDDI (Touch and Display Driver Integration) product uses a LH (Long H) touch mode, at least one touch phase is inserted in a frame time, when entering the touch phase (referred to as entering the pit), the potential of the clock signal on all clock signal lines in the GOA (Gate On Array) circuit is set to low, the potential of the pull-up node of the in-pit row driving circuit remains high during the touch phase, and after exiting the pit, the clock signal gives the corresponding clock signal, at this time, the driving circuit continues to output the driving signal through the driving output end to perform display. However, the potential of the pull-up node of the in-pit row driving circuit is affected by transistor leakage, and the potential of the in-pit row driving circuit is reduced to a lower level in a pit time, resulting in lower output voltage of the post-pit row driving circuit, thereby causing LH horizontal lines to occur, and the position of the LH horizontal lines matches the touch pit. SUMMARY

[0003] The main purpose of the present application is to provide a driving circuit, a driving method and a display device, which solve the problem that in the prior art, the potential of the pull-up node of the in-pit row driving circuit cannot be maintained at a high level during the touch phase, thereby causing LH horizontal lines.

[0004] In one aspect, the embodiment of the present application provides a driving circuit, comprising a driving output end, an input circuit, an output circuit and a pull-up node;

[0005] The input circuit is electrically connected with the pull-up node, an input control end and an input voltage end, respectively, and is used for writing an input voltage provided by the input voltage end into the pull-up node under the control of an input control signal provided by the input control end;

[0006] The output circuit is electrically connected with the pull-up node, a clock signal line and the driving output end, respectively, and is used for writing a clock signal provided by the clock signal line into the driving output end under the control of the potential of the pull-up node;

[0007] The driving circuit further comprises a potential control circuit and a first energy storage circuit;

[0008] The potential control circuit is electrically connected with the pull-up node, a first control end and a control node, respectively, and is used for controlling the first control end to be in communication or disconnected with the control node under the control of the potential of the pull-up node;

[0009] The first end of the first energy storage circuit is electrically connected with the control node, and the second end of the first energy storage circuit is electrically connected with the pull-up node, and the first energy storage circuit is used for storing electric energy.

[0010] Optionally, the first control end is used for providing an effective voltage signal in a touch stage and providing an ineffective voltage signal in a display stage.

[0011] Optionally, the potential control circuit comprises a first transistor, and the first energy storage circuit comprises a first capacitor.

[0012] The gate of the first transistor is electrically connected with the pull-up node, the first pole of the first transistor is electrically connected with the first control end, and the second pole of the first transistor is electrically connected with the control node.

[0013] The first end of the first capacitor is electrically connected with the control node, and the second end of the first capacitor is electrically connected with the pull-up node.

[0014] Optionally, the channel width-length ratio of the first transistor is greater than or equal to 12.5 and less than or equal to 100, and the capacitance value of the first capacitor is greater than or equal to 0.5 fF and less than or equal to 4 fF.

[0015] Optionally, the driving circuit further comprises an output reset circuit.

[0016] The output reset circuit is electrically connected with the first control end, the driving output end and the first voltage end respectively, and is used for controlling the driving output end and the first voltage end to be connected or disconnected under the control of the first control signal provided by the first control end.

[0017] Optionally, the driving circuit further comprises a reset circuit and a pull-up node control circuit.

[0018] The reset circuit is electrically connected with the pull-up node, a reset control end and a reset voltage end respectively, and is used for writing the reset voltage provided by the reset voltage end into the pull-up node under the control of a reset control signal provided by the reset control end.

[0019] The pull-up node control circuit is electrically connected with the pull-up node, a pull-down node and a first voltage end respectively, and is used for controlling the pull-up node and the first voltage end to be connected or disconnected under the control of the potential of the pull-down node.

[0020] Optionally, the driving circuit further comprises a pull-down node control circuit.

[0021] The pull-down node control circuit is electrically connected with the second control end, the pull-down control node, the pull-down node, the pull-up node and the first voltage end respectively, and is used for controlling the potential of the pull-down control node under the control of the potential of the pull-up node and the second control signal provided by the second control end, and controlling the potential of the pull-down node according to the second control signal under the control of the potential of the pull-down control node and the potential of the pull-up node.

[0022] Optionally, the second control end is used for providing an effective voltage signal in a display stage and an ineffective voltage signal in a touch stage.

[0023] Optionally, the driving circuit further comprises a pull-up node reset circuit.

[0024] The pull-up node reset circuit is electrically connected with the start control end, the pull-up node and the first voltage end respectively, and is used for controlling the communication or disconnection between the pull-up node and the first voltage end under the control of the start control signal provided by the start control end.

[0025] Optionally, the driving circuit further comprises an output control circuit and a second energy storage circuit.

[0026] The output control circuit is electrically connected with the pull-down node, the driving output end and the first voltage end respectively, and is used for controlling the communication or disconnection between the driving output end and the first voltage end under the control of the potential of the pull-down node.

[0027] The second energy storage circuit is electrically connected with the pull-up node and the driving output end respectively, and is used for storing electric energy.

[0028] Optionally, the driving circuit further comprises an output reset circuit.

[0029] The output reset circuit is electrically connected with the start control end, the driving output end and the first voltage end respectively, and is used for controlling the communication or disconnection between the driving output end and the first voltage end under the control of the start control signal provided by the start control end.

[0030] Optionally, the input circuit comprises a second transistor, the reset circuit comprises a third transistor, and the pull-up node control circuit comprises a fourth transistor.

[0031] The gate of the second transistor is electrically connected with the input control end, the first pole of the second transistor is electrically connected with the input voltage end, and the second pole of the second transistor is electrically connected with the pull-up node.

[0032] The gate of the third transistor is electrically connected with the reset control end, the first pole of the third transistor is electrically connected with the pull-up node, and the second pole of the third transistor is electrically connected with the reset voltage end.

[0033] The gate of the fourth transistor is electrically connected with the pull-down node, the first pole of the fourth transistor is electrically connected with the pull-up node, and the second pole of the fourth transistor is electrically connected with the first voltage end.

[0034] Optionally, the potential control circuit comprises a first transistor.

[0035] The ratio between the channel width-length ratio of the first transistor and the channel width-length ratio of the fourth transistor is greater than or equal to 0.5 and less than or equal to 4.

[0036] Optionally, the pull-down node control circuit comprises a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor.

[0037] The gate of the fifth transistor and the first pole of the fifth transistor are both electrically connected with a second control end, and the second pole of the fifth transistor is electrically connected with a pull-down control node.

[0038] The gate of the sixth transistor is electrically connected with the pull-down control node, the first pole of the sixth transistor is electrically connected with the second control end, and the second pole of the sixth transistor is electrically connected with the pull-down node.

[0039] The gate of the seventh transistor is electrically connected with the pull-up node, the first pole of the seventh transistor is electrically connected with the pull-down control node, and the second pole of the seventh transistor is electrically connected with the first voltage end.

[0040] The gate of the eighth transistor is electrically connected with the pull-up node, the first pole of the eighth transistor is electrically connected with the pull-down node, and the second pole of the eighth transistor is electrically connected with the first voltage end.

[0041] Optionally, the pull-up node reset circuit comprises a ninth transistor.

[0042] The gate of the ninth transistor is electrically connected with a start control end, the first pole of the ninth transistor is electrically connected with the pull-up node, and the second pole of the ninth transistor is electrically connected with the first voltage end.

[0043] Optionally, the output circuit comprises a tenth transistor, and the output control circuit comprises an eleventh transistor.

[0044] The gate of the tenth transistor is electrically connected with the pull-up node, the first pole of the tenth transistor is electrically connected with a clock signal line, and the second pole of the tenth transistor is electrically connected with a driving output end.

[0045] The gate of the eleventh transistor is electrically connected with the pull-down node, the first pole of the eleventh transistor is electrically connected with the driving output end, and the second pole of the eleventh transistor is electrically connected with the first voltage end.

[0046] The second energy storage circuit comprises a second capacitor.

[0047] The first end of the second capacitor is electrically connected with the pull-up node, and the second end of the second capacitor is electrically connected with the driving output end.

[0048] Optionally, the first energy storage circuit comprises a first capacitor.

[0049] The ratio between the capacitance value of the first capacitor and the capacitance value of the second capacitor is greater than or equal to 1 / 1000 and less than or equal to 8 / 1000.

[0050] Optionally, the output reset circuit comprises a twelfth transistor.

[0051] The gate of the twelfth transistor is electrically connected with the first control end, the first pole of the twelfth transistor is electrically connected with the driving output end, and the second pole of the twelfth transistor is electrically connected with the first voltage end.

[0052] Optionally, the output reset circuit comprises a thirteenth transistor.

[0053] The gate of the thirteenth transistor is electrically connected with the start control end, the first pole of the thirteenth transistor is electrically connected with the driving output end, and the second pole of the thirteenth transistor is electrically connected with the first voltage end.

[0054] In a second aspect, an embodiment of the present application provides a driving method applied to the driving circuit, and a display period comprises a touch stage; the driving method comprises the following steps.

[0055] In the touch stage, the potential control circuit controls the communication between the first control end and the control node under the control of the potential of the pull-up node.

[0056] In a third aspect, an embodiment of the present application provides a display device comprising the driving circuit.

[0057] The driving circuit, the driving method and the display device can prevent the potential of the pull-up node from being reduced in the touch stage, prevent the potential of the driving signal provided by the driving circuit from being reduced when the display stage is entered again, and avoid the generation of LH horizontal lines. BRIEF DESCRIPTION OF DRAWINGS

[0058] Figure 1This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0059] Figure 2 This is a waveform diagram of the clock signals provided by each clock signal line within one frame in LH touch mode.

[0060] Figure 3 In related technologies, this is a timing diagram of the potential of the pull-up node of the drive circuit and the drive signal output by the drive circuit;

[0061] Figure 4 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0062] Figure 5 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0063] Figure 6 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0064] Figure 7 This is a circuit diagram of the driving circuit according to at least one embodiment of the present invention;

[0065] Figure 8 It is a waveform diagram of the potential of the pull-up node in the drive circuit of the pit in the related technology;

[0066] Figure 9 This is a waveform diagram of the potential of the pull-up node of the drive circuit in at least one embodiment of the present invention.

[0067] Figure 10 yes Figure 7 The timing diagram of at least one embodiment of the driving circuit shown;

[0068] Figure 11 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0069] Figure 12 This is a circuit diagram of the driving circuit described in at least one embodiment of the present invention. Detailed Implementation

[0070] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0071] The transistor used in all embodiments of the present application can be a thin film transistor or a field effect transistor or other devices with the same characteristics. In the embodiments of the present application, in order to distinguish the two poles of the transistor except the gate, one pole is called the first pole and the other pole is called the second pole.

[0072] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0073] As shown in FIG. 1, the driving circuit in the embodiments of the present application comprises a driving output end O1, an input circuit 101, an output circuit 102 and a pull-up node PU. Figure 1

[0074] The input circuit 101 is electrically connected with the pull-up node PU, an input control end I1 and an input voltage end VDS respectively, and is used for writing an input voltage provided by the input voltage end VDS into the pull-up node PU under the control of an input control signal provided by the input control end I1.

[0075] The output circuit 102 is electrically connected with the pull-up node PU, a clock signal line CK and the driving output end O1 respectively, and is used for writing a clock signal provided by the clock signal line CK into the driving output end O1 under the control of the potential of the pull-up node PU.

[0076] The driving circuit in the embodiments of the present application further comprises a potential control circuit 11 and a first energy storage circuit 12.

[0077] The potential control circuit 11 is electrically connected with the pull-up node PU, a first control end GCL and a control node NC respectively, and is used for controlling the communication or disconnection between the first control end GCL and the control node NC under the control of the potential of the pull-up node PU.

[0078] The first end of the first energy storage circuit 12 is electrically connected with the control node NC, and the second end of the first energy storage circuit 12 is electrically connected with the pull-up node PU, and the first energy storage circuit 12 is used for storing electric energy.

[0079] The driving circuit in the embodiments of the present application works in a display period comprising a touch phase.

[0080] ​In the touch stage, the potential control circuit 11 controls the communication between the first control end GCL and the control node NC under the control of the potential of the pull-up node PU, so as to pull up the potential of the pull-up node PU through the first energy storage circuit 12, so that the potential of the pull-up node does not decrease in the touch stage, and the potential of the driving signal provided by the driving circuit does not decrease when the display stage is entered again, avoiding the generation of LH horizontal lines.

[0081] In at least one embodiment of the present application, the first control end is used to provide an effective voltage signal in the touch stage and an ineffective voltage signal in the display stage.

[0082] In specific implementation, when the transistor controlled by the first control end and included in the potential control circuit 11 is an n-type transistor, the effective voltage signal can be a high voltage signal, and the ineffective voltage signal can be a low voltage signal.

[0083] When the transistor controlled by the first control end and included in the potential control circuit 11 is a p-type transistor, the effective voltage signal can be a low voltage signal, and the ineffective voltage signal can be a high voltage signal.

[0084] In at least one embodiment of the present application, when the transistor included in the potential control circuit 11 is an n-type transistor, in the touch stage, the GCL can provide a high-frequency square wave voltage signal, alternately outputting a first high voltage signal and a second high voltage signal, for example, the potential of the first high voltage signal can be 12V, and the potential of the second high voltage signal can be 10V.

[0085] In the display stage, the GCL outputs a low voltage signal, and the voltage value of the low voltage signal output by the GCL can be -12V, but is not limited thereto.

[0086] In at least one embodiment of the present application, in the touch stage, the clock signal line, the first control end, the second control end, the first control voltage end, the second control voltage end, the start control end and the low voltage end all output high-frequency square wave voltage signals to be consistent with the fluctuation of the touch signal on the touch electrode, thereby reducing the coupling capacitance between the touch electrode and each signal end.

[0087] In the related art, when a TDDI (Touch and Display Driver Integration) product uses a LH (Long H) touch mode, at least one touch phase is inserted in a frame time, when entering the touch phase (referred to as entering the pit), the potential of the clock signal on all clock signal lines in the GOA (Gate On Array) circuit is set to low, the potential of the pull-up node of the pit entry row driving circuit remains high during the touch phase, after exiting the pit, the respective clock signals give corresponding clock signals, at this time the driving circuit continues to output the driving signal through the driving output end to perform display. However, the potential of the pull-up node of the pit entry row driving circuit is affected by transistor leakage, and decreases to a lower level in a pit time (the pit time is the duration of the touch phase, for example, it can be about 150 μs), resulting in a lower output voltage of the post-pit row driving circuit, thereby causing LH horizontal lines to occur, and the position of the LH horizontal lines matches the Touch pit.

[0088] In the related art, the maximum feature of the TDDI product is to integrate the touch chip and the display chip into one chip, and the TDDI IC (Integrated Circuit) is usually applied to a Full in Cell product, but is not limited thereto.

[0089] The Full in Cell product is to manufacture a touch sensor array in an LCD box, and has the advantages of lighter and thinner structure, simpler process, and lower cost.

[0090] The LH touch mode is a frame-in touch driving mode, in which a frame time is divided into at least two display phases, and a touch phase is set between adjacent display phases, and in the touch phase, touch detection is performed.

[0091] For example, two touch phases can be inserted in a frame time, and touch and display are time-multiplexed.

[0092] Figure 2 The waveform of the clock signal provided by each clock signal line in a frame time in the LH touch mode.

[0093] In Figure 2 , the label CK1 is a first clock signal line, the label CK2 is a second clock signal line, the label CK3 is a third clock signal line, the label CK4 is a fourth clock signal line, the label CK5 is a fifth clock signal line, the label CK6 is a sixth clock signal line, the label CK7 is a seventh clock signal line, and the label CK8 is an eighth clock signal line.

[0094] As shown in Figure 2 , a frame time includes a first display stage TD1, a first touch stage TT1, a second display stage TD2, a second touch stage TT2 and a third display stage TD3 arranged in sequence;

[0095] In TD1, TD2 and TD3, each clock signal line provides a clock signal;

[0096] In TT1 and TT2, each clock signal line provides a high-frequency square wave voltage signal, each clock signal line provides a low voltage signal, and the voltage value of the high-frequency square wave voltage signal provided by each clock signal line can be changed between -10V and -12V, but is not limited thereto.

[0097] As shown in Figure 2 , in the first touch stage TT1 and the second touch stage TT2, each clock signal line provides a low voltage signal, and the potential of the pull-up node PU of the in-pit row driving circuit needs to be kept at a high level when entering the Touch pit, until the end of the touch time, the clock signal output, and in the touch stage, due to the long holding time of the potential of the pull-up node, the leakage is large, and the maximum leakage path is M4 in Figure 7 , after the pit, the potential of the pull-up node in the in-pit row driving circuit is lower than that of the pull-up node in the non-pit row driving circuit, so that the output voltage of the drive output end of the in-pit row driving circuit decreases, thereby causing the occurrence of horizontal lines, and the position of the horizontal lines matches the Touch pit.

[0098] As shown in Figure 3 , in the related art, assuming that the nth row driving circuit is an in-pit row driving circuit, n is an integer greater than 0, then the n+1th row driving circuit is an out-pit row driving circuit, Gn-1 is the driving signal output by the n-1th row driving circuit, Gn is the driving signal output by the nth row driving circuit, Gn+1 is the driving signal output by the n+1th row driving circuit, Gn+2 is the driving signal output by the n+2th row driving circuit, PU(n) is the pull-up node in the n th row driving circuit, and PU(n+1) is the pull-up node in the n+1th row driving circuit.

[0099] As shown in Figure 3 , in the related art, in the touch stage TT, the potential of PU(n) and the potential of PU(n+1) will decrease and cannot be well maintained at a high level.

[0100] Optionally, the potential control circuit includes a first transistor, and the first energy storage circuit includes a first capacitor;

[0101] The gate of the first transistor is electrically connected with the pull-up node, the first pole of the first transistor is electrically connected with the first control end, and the second pole of the first transistor is electrically connected with the control node.

[0102] The first terminal of the first capacitor is electrically connected to the control node, and the second terminal of the first capacitor is electrically connected to the pull-up node.

[0103] In at least one embodiment of the present invention, the channel width-to-length ratio of the first transistor is greater than or equal to 12.5 and less than or equal to 100, and the capacitance value of the first capacitor is greater than or equal to 0.5fF and less than or equal to 4fF.

[0104] like Figure 4 As shown, in Figure 1 Based on at least one embodiment of the driving circuit shown, the potential control circuit 11 includes a first transistor M1, and the first energy storage circuit includes a first capacitor C1;

[0105] The gate of the first transistor M1 is electrically connected to the pull-up node PU, the source of the first transistor M1 is electrically connected to the first control terminal GCL, and the drain of the first transistor M1 is electrically connected to the control node NC.

[0106] The first end of the first capacitor C1 is electrically connected to the control node NC, and the second end of the first capacitor C1 is electrically connected to the pull-up node PU.

[0107] exist Figure 4 In at least one embodiment of the driving circuit shown, M1 can be an n-type transistor, but is not limited thereto. In actual operation, M1 can also be a p-type transistor.

[0108] Figure 4 At least one embodiment of the driving circuit shown, when in operation,

[0109] During the touch phase, GCL provides a high voltage signal, PU has a high voltage potential, M1 is turned on, and C1 is charged with the high voltage signal provided by GCL. Through the coupling effect of C1, the potential of the pull-up node of the drive circuit in the pit is pulled up.

[0110] In practical implementation, the pull-up voltage amplitude of the pull-up node can be adjusted by the channel width-to-length ratio of M12 and the capacitance value of C1, so that the potential of the pull-up node of the in-slot drive circuit is consistent with the potential of the pull-up node of the non-in-slot drive circuit, thereby solving the problem of LH horizontal lines.

[0111] Optionally, the driving circuit described in at least one embodiment of the present invention may further include an output reset circuit;

[0112] The output reset circuit is electrically connected to the first control terminal, the drive output terminal, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the drive output terminal and the first voltage terminal under the control of the first control signal provided by the first control terminal.

[0113] In a specific implementation, the driving circuit described in at least one embodiment of the present invention may further include an output reset circuit;

[0114] During the touch phase, the output reset circuit, under the control of the first control signal provided by the first control terminal, controls the connection between the drive output terminal and the first voltage terminal to reset the potential of the drive signal provided by the drive output terminal;

[0115] During the display phase, the output reset circuit, under the control of the first control signal provided by the first control terminal, controls the disconnection between the drive output terminal and the first voltage terminal.

[0116] The driving circuit described in at least one embodiment of the present invention further includes a reset circuit and a pull-up node control circuit;

[0117] The reset circuit is electrically connected to the pull-up node, the reset control terminal, and the reset voltage terminal, respectively, and is used to write the reset voltage provided by the reset voltage terminal into the pull-up node under the control of the reset control signal provided by the reset control terminal.

[0118] The pull-up node control circuit is electrically connected to the pull-up node, the pull-down node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the pull-up node and the first voltage terminal under the control of the potential of the pull-down node.

[0119] In a specific implementation, the driving circuit may further include a reset circuit and a pull-up node control circuit. Under the control of the reset control signal, the reset circuit writes the reset voltage into the pull-up node. Under the control of the potential of the pull-down node, the pull-up node control circuit controls the connection or disconnection between the pull-up node and the first voltage terminal.

[0120] Optionally, the first voltage terminal can be a low voltage terminal, but is not limited thereto.

[0121] like Figure 5 As shown, in Figure 1 Based on at least one embodiment of the driving circuit shown, the driving circuit of at least one embodiment of the present invention may further include a pull-up node control circuit 30 and a reset circuit 31;

[0122] The reset circuit 31 is electrically connected to the pull-up node PU, the reset control terminal R1, and the reset voltage terminal VSD, respectively, and is used to write the reset voltage provided by the reset voltage terminal VSD into the pull-up node PU under the control of the reset control signal provided by the reset control terminal R1.

[0123] The pull-up node control circuit 30 is electrically connected with the pull-up node PU, the pull-down node PD and the first voltage terminal V1 respectively, and is used for controlling the communication or disconnection between the pull-up node PU and the first voltage terminal V1 under the control of the potential of the pull-down node PD.

[0124] In the display stage, the VDS can provide a high voltage signal, and the VSD can provide a low voltage signal. Figure 5 In at least one embodiment of the driving circuit shown, in the display stage, the VDS can provide a high voltage signal, and the VSD can provide a low voltage signal, in the touch stage, the VDS can provide a high frequency square wave voltage, the potential of the signal output by the VDS is a high voltage, the VSD can provide a high frequency square wave voltage, the potential of the signal output by the VSD is a high voltage, the potential of the signal provided by the VSD can be changed between 10V and 12V, and the potential of the signal provided by the VDS can be changed between 12V and 14V.

[0125] The driving circuit in at least one embodiment of the present application further comprises a pull-down node control circuit.

[0126] The pull-down node control circuit is electrically connected with the second control terminal, the pull-down control node, the pull-down node, the pull-up node and the first voltage terminal respectively, and is used for controlling the potential of the pull-down control node under the control of the potential of the pull-up node and the second control signal provided by the second control terminal, and controlling the potential of the pull-down node according to the second control signal under the control of the potential of the pull-down control node and the potential of the pull-up node.

[0127] In at least one embodiment of the present application, the driving circuit can further comprise a pull-down node control circuit, the pull-down node control circuit controls the potential of the pull-down control node under the control of the potential of the pull-up node and the second control signal, and controls the potential of the pull-down node according to the second control signal under the control of the potential of the pull-down control node and the potential of the pull-up node.

[0128] In at least one embodiment of the present application, the second control terminal can be used for providing an effective voltage signal in the display stage and providing an ineffective voltage signal in the touch stage.

[0129] In specific implementation, in the touch stage, the second control terminal provides an ineffective voltage signal, so as to ensure that the potential of the pull-down node is an ineffective voltage in the touch stage.

[0130] When the transistor with the gate electrically connected with the second control terminal comprised in the pull-down node control circuit is an n-type transistor, the effective voltage signal is a high voltage signal, and the ineffective voltage signal is a low voltage signal; when the transistor with the gate electrically connected with the second control terminal comprised in the pull-down node control circuit is a p-type transistor, the effective voltage signal is a low voltage signal, and the ineffective voltage signal is a high voltage signal.

[0131] The driving circuit described in at least one embodiment of the present invention further includes a pull-up node reset circuit;

[0132] The pull-up node reset circuit is electrically connected to the start control terminal, the pull-up node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the pull-up node and the first voltage terminal under the control of the start control signal provided by the start control terminal.

[0133] In a specific implementation, the driving circuit may further include a pull-up node reset circuit, which resets the potential of the pull-up node under the control of the start control signal provided by the start control terminal.

[0134] The driving circuit described in at least one embodiment of the present invention further includes an output control circuit and a second energy storage circuit;

[0135] The output control circuit is electrically connected to the pull-down node, the drive output terminal, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the drive output terminal and the first voltage terminal under the control of the potential of the pull-down node.

[0136] The second energy storage circuit is electrically connected to the pull-up node and the drive output terminal respectively, and is used to store electrical energy.

[0137] In a specific implementation, the driving circuit may further include an output circuit and a second energy storage circuit. The second output circuit controls the connection or disconnection between the driving output terminal and the clock signal line under the control of the potential of the pull-up node, and controls the connection or disconnection between the driving output terminal and the first voltage terminal under the control of the potential of the pull-down node. The second energy storage circuit is used to maintain the potential of the pull-up node.

[0138] The driving circuit described in at least one embodiment of the present invention further includes an output reset circuit;

[0139] The output reset circuit is electrically connected to the start control terminal, the drive output terminal, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the drive output terminal and the first voltage terminal under the control of the start control signal provided by the start control terminal.

[0140] In a specific implementation, the driving circuit may further include an output reset circuit, which can reset the potential of the driving signal provided by the driving output terminal under the control of the start control signal.

[0141] like Figure 6 As shown, in Figure 5The driving circuit in at least one embodiment of the present application further comprises a pull-down node control circuit 41 based on the driving circuit shown in at least one embodiment of the present application.

[0142] The pull-down node control circuit 41 is electrically connected with a second control end GCH, a pull-down control node PN, a pull-down node PD, the pull-up node PU and a first voltage end V1 respectively, and is used for controlling the potential of the pull-down control node PN under the control of the potential of the pull-up node PU and a second control signal provided by the second control end GCH, and controlling the potential of the pull-down node PD under the control of the potential of the pull-down control node PN and the potential of the pull-up node PU according to the second control signal.

[0143] The driving circuit in at least one embodiment of the present application further comprises a pull-up node reset circuit 42.

[0144] The pull-up node reset circuit 42 is electrically connected with a start control end S0, the pull-up node PU and the first voltage end V1 respectively, and is used for controlling the communication or disconnection between the pull-up node PU and the first voltage end V1 under the control of a start control signal provided by the start control end S0. Figure 7 The start control end S0 provides an effective potential before the beginning of a frame to reduce the noise of the pull-up node, for example, reference The noise reduction of PU is realized by controlling the M9 transistor.

[0145] The driving circuit in at least one embodiment of the present application further comprises an output control circuit 43 and a second energy storage circuit 44.

[0146] The output control circuit 43 is electrically connected with the pull-down node PD, a driving output end O1 and the first voltage end V1 respectively, and is used for controlling the communication or disconnection between the driving output end O1 and the first voltage end V1 under the control of the potential of the pull-down node PD.

[0147] The second energy storage circuit 44 is electrically connected with the pull-up node PU and the driving output end O1 respectively, and is used for storing energy.

[0148] The driving circuit in at least one embodiment of the present application further comprises an output reset circuit 45.

[0149] The output reset circuit 45 is electrically connected with a first control end GCL, the driving output end O1 and the first voltage end V1 respectively, and is used for controlling the communication or disconnection between the driving output end O1 and the first voltage end V1 under the control of a first control signal provided by the first control end GCL.

[0150] Optionally, the input circuit comprises a second transistor, the reset circuit comprises a third transistor, and the pull-up node control circuit comprises a fourth transistor.

[0151] a gate of the second transistor is electrically connected with the input control end, a first electrode of the second transistor is electrically connected with the input voltage end, and a second electrode of the second transistor is electrically connected with the pull-up node;

[0152] a gate of the third transistor is electrically connected with the reset control end, a first electrode of the third transistor is electrically connected with the pull-up node, and a second electrode of the third transistor is electrically connected with the reset voltage end;

[0153] a gate of the fourth transistor is electrically connected with the pull-down node, a first electrode of the fourth transistor is electrically connected with the pull-up node, and a second electrode of the fourth transistor is electrically connected with the first voltage end.

[0154] Optionally, the pull-down node control circuit comprises a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor;

[0155] a gate of the fifth transistor and a first electrode of the fifth transistor are electrically connected with the second control end, and a second electrode of the fifth transistor is electrically connected with the pull-down control node;

[0156] a gate of the sixth transistor is electrically connected with the pull-down control node, a first electrode of the sixth transistor is electrically connected with the second control end, and a second electrode of the sixth transistor is electrically connected with the pull-down node;

[0157] a gate of the seventh transistor is electrically connected with the pull-up node, a first electrode of the seventh transistor is electrically connected with the pull-down control node, and a second electrode of the seventh transistor is electrically connected with the first voltage end;

[0158] a gate of the eighth transistor is electrically connected with the pull-up node, a first electrode of the eighth transistor is electrically connected with the pull-down node, and a second electrode of the eighth transistor is electrically connected with the first voltage end.

[0159] Optionally, the pull-up node reset circuit comprises a ninth transistor;

[0160] a gate of the ninth transistor is electrically connected with the start control end, a first electrode of the ninth transistor is electrically connected with the pull-up node, and a second electrode of the ninth transistor is electrically connected with the first voltage end.

[0161] Optionally, the output circuit comprises a tenth transistor, and the output control circuit comprises an eleventh transistor;

[0162] a gate of the tenth transistor is electrically connected with the pull-up node, a first electrode of the tenth transistor is electrically connected with the clock signal line, and a second electrode of the tenth transistor is electrically connected with the driving output end.

[0163] The gate of the eleventh transistor is electrically connected with the pull-down node, the first pole of the eleventh transistor is electrically connected with the driving output end, and the second pole of the eleventh transistor is electrically connected with the first voltage end.

[0164] The second energy storage circuit comprises a second capacitor.

[0165] The first end of the second capacitor is electrically connected with the pull-up node, and the second end of the second capacitor is electrically connected with the driving output end.

[0166] In at least one embodiment of the present application, the first energy storage circuit comprises a first capacitor.

[0167] The ratio between the capacitance value of the first capacitor and the capacitance value of the second capacitor is greater than or equal to 1 / 1000 and less than or equal to 8 / 1000.

[0168] Optionally, the output reset circuit comprises a twelfth transistor.

[0169] The gate of the twelfth transistor is electrically connected with the first control end, the first pole of the twelfth transistor is electrically connected with the driving output end, and the second pole of the twelfth transistor is electrically connected with the first voltage end.

[0170] Optionally, the output reset circuit comprises a twelfth transistor.

[0171] The gate of the twelfth transistor is electrically connected with the start control end, the first pole of the twelfth transistor is electrically connected with the driving output end, and the second pole of the twelfth transistor is electrically connected with the first voltage end.

[0172] As shown in FIG. 1, Figure 7 As shown in FIG. 1, Figure 6 On the basis of at least one embodiment of the driving circuit shown in FIG. 1, the potential control circuit 11 comprises a first transistor M1, and the first energy storage circuit comprises a first capacitor C1.

[0173] The gate of the first transistor M1 is electrically connected with the pull-up node PU, the source of the first transistor M1 is electrically connected with the first control end GCL, and the drain of the first transistor M1 is electrically connected with the control node NC.

[0174] The first end of the first capacitor C1 is electrically connected with the control node NC, and the second end of the first capacitor C1 is electrically connected with the pull-up node PU.

[0175] The input circuit comprises a second transistor M2, the reset circuit comprises a third transistor M3, and the pull-up node control circuit comprises a fourth transistor M4.

[0176] a gate of the second transistor M2 is electrically connected with the input control end I1, a source of the second transistor M2 is electrically connected with the first control voltage end VDS, and a drain of the second transistor M2 is electrically connected with the pull-up node PU;

[0177] a gate of the third transistor M3 is electrically connected with the reset control end R1, a source of the third transistor M3 is electrically connected with the pull-up node PU, and a drain of the third transistor M3 is electrically connected with the second control voltage end VSD;

[0178] a gate of the fourth transistor M4 is electrically connected with the pull-down node PD, a source of the fourth transistor M4 is electrically connected with the pull-up node PU, and a drain of the fourth transistor M4 is electrically connected with the low voltage end VGL;

[0179] the pull-down node control circuit comprises a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and an eighth transistor M8;

[0180] a gate of the fifth transistor M5 and a source of the fifth transistor M5 are electrically connected with the second control end GCH, and a drain of the fifth transistor M5 is electrically connected with the pull-down control node PN;

[0181] a gate of the sixth transistor M6 is electrically connected with the pull-down control node PN, a source of the sixth transistor M6 is electrically connected with the second control end GCH, and a drain of the sixth transistor M6 is electrically connected with the pull-down node PD;

[0182] a gate of the seventh transistor M7 is electrically connected with the pull-up node PU, a source of the seventh transistor M7 is electrically connected with the pull-down control node PN, and a drain of the seventh transistor M7 is electrically connected with the low voltage end VGL;

[0183] a gate of the eighth transistor M8 is electrically connected with the pull-up node PU, a source of the eighth transistor M8 is electrically connected with the pull-down node PD, and a drain of the eighth transistor M8 is electrically connected with the low voltage end VGL;

[0184] the pull-up node reset circuit comprises a ninth transistor M9;

[0185] a gate of the ninth transistor M9 is electrically connected with the start control end S0, a source of the ninth transistor M9 is electrically connected with the pull-up node PU, and a drain of the ninth transistor M9 is electrically connected with the low voltage end VGL;

[0186] the output circuit comprises a tenth transistor M10, and the output control circuit comprises an eleventh transistor M11;

[0187] The gate of the tenth transistor M10 is electrically connected with the pull-up node PU, the source of the tenth transistor M10 is electrically connected with the clock signal line CK, and the drain of the tenth transistor M10 is electrically connected with the driving output end O1;

[0188] The gate of the eleventh transistor M11 is electrically connected with the pull-down node PD, the source of the eleventh transistor M11 is electrically connected with the driving output end O1, and the drain of the eleventh transistor M11 is electrically connected with the low voltage end VGL;

[0189] The second energy storage circuit includes a second capacitor C2;

[0190] The first end of the second capacitor C2 is electrically connected with the pull-up node PU, and the second end of the second capacitor C2 is electrically connected with the driving output end O1;

[0191] The output reset circuit includes a twelfth transistor M12;

[0192] The gate of the twelfth transistor M12 is electrically connected with the first control end GCL, the source of the twelfth transistor M12 is electrically connected with the driving output end O1, and the drain of the twelfth transistor M12 is electrically connected with the low voltage end VGL. Figure 7 The control ends of M12 and M1 are both electrically connected with GCL, when in the touch stage, GCL provides an effective voltage level, and at the same time, the raising of PU and the noise reduction of the driving output end O1 are realized.

[0193] In at least one embodiment of the driving circuit shown in Figure 7 In at least one embodiment of the driving circuit shown in

[0194] In at least one embodiment of the driving circuit shown in Figure 7 In at least one embodiment of the driving circuit shown in

[0195] Optionally, the ratio between the channel width-length ratio of the first transistor and the channel width-length ratio of the fourth transistor is greater than or equal to 0.5 and less than or equal to 4.

[0196] Figure 7 In at least one embodiment of the driving circuit shown in

[0197] In the input period, I1 provides a high voltage signal, M2 is on, R1 provides a low voltage signal, M3 is off, the potential of PU is high voltage, M10 is on, O1 is connected with CK; M8 is on, M7 and M8 are both on, the potential of PN is low voltage, the potential of PD is low voltage;

[0198] In the output period, I1 provides a low voltage signal, R1 provides a low voltage signal, the potential of PU is high voltage, the potential of PD is low voltage, M10 is on, O1 is connected with CK;

[0199] In the reset period, I1 provides a low voltage signal, R1 provides a high voltage signal, M3 is on, M2 is off, the potential of PU is low voltage, M5 is on, M7 is off, the potential of PN is high voltage, M6 is on, M8 is off, the potential of PD is high voltage, M4 and M11 are on, O1 outputs a low voltage signal;

[0200] In the output cutoff holding period, I1 and R1 both output a low voltage signal, M2 and M3 are both off, the potential of PU is maintained as low voltage, M5 is on, M7 is off, the potential of PN is high voltage, M6 is on, M8 is off, the potential of PD is high voltage, M4 and M11 are on, O1 outputs a low voltage signal;

[0201] In the display stage, GCL provides a low voltage signal, in the output period, the potential of PU is high voltage, M1 is on, the first end of C1 is connected with GCL, but the potential of PU can be guaranteed as high voltage due to the conduction of M2;

[0202] In the touch stage set between two display stages, GCL provides a high frequency square wave voltage signal, the potential of the voltage signal provided by GCL is high voltage, in the in-cavity row driving circuit, the potential of PU is high voltage, M1 is on, the first end of C1 is connected with GCL, so as to pull up the potential of the pull-up node PU through the first capacitor C1, so that in the touch stage, the potential of the pull-up node PU will not decrease, which will not cause the potential of the driving signal provided by the driving circuit to decrease when the display stage is entered again, thereby avoiding the generation of LH horizontal lines;

[0203] In the touch stage set between two display stages, GCL provides a high frequency square wave voltage signal, the potential of the voltage signal provided by GCL is high voltage, M12 is on, so as to control O1 to be connected with VGL, so as to guarantee that O1 outputs a low voltage signal.

[0204] Figure 7 At least one embodiment of the driving circuit shown works in the blank period between two display periods (the display period can be one frame time), S0 can provide a high voltage signal, M9 is on, so as to control the potential of PU to reset.

[0205] Figure 7 At least one embodiment of the drive circuit shown in operation, the potential of the pull-up node PU in the in-pit row drive circuit is coupled to pull up the length can be controlled by the channel width-length ratio of M1 and the size of the capacitance value of C1.

[0206] Through simulation, in the related art, the first-order voltage of the pull-up node of the non-pit row drive circuit is 10.3V, as shown in Figure 8 The first-order voltage of the pull-up node of the in-pit row drive circuit is attenuated from 10.3V to 9.2V, with an attenuation of 1.1V, and the attenuation of the potential of the pull-up node of the in-pit row drive circuit is easy to cause the occurrence of LH horizontal lines, especially under the reliability condition, the positive bias time of M10 in the in-pit row drive circuit is about 5 times or more than that of M10 in the normal row drive circuit, the positive drift of the threshold voltage of M10 in the in-pit row drive circuit is larger, resulting in the decrease of Ion (on current), and the attenuation of the potential of PU is more likely to cause the occurrence of horizontal lines. In Figure 7 At least one embodiment of the drive circuit shown in operation, the potential of the pull-up node PU in the in-pit row drive circuit is coupled to pull up the length can be controlled by the channel width-length ratio of M1 and the size of the capacitance value of C1. Figure 9 As shown in

[0207] In Figure 8 and Figure 9 , the vertical axis is the potential of the pull-up node PU, in units of V (volts), and the horizontal axis is time t, in units of S (seconds).

[0208] Figure 10 is Figure 7 the working timing diagram of at least one embodiment of the drive circuit shown.

[0209] In Figure 10 , the label CK1 is the first clock signal line, the label CK2 is the second clock signal line, the label CK3 is the third clock signal line, the label CK4 is the fourth clock signal line, the label CK5 is the fifth clock signal line, the label CK6 is the sixth clock signal line, the label CK7 is the seventh clock signal line, and the label CK8 is the eighth clock signal line.

[0210] In Figure 7In at least one embodiment of the illustrated driving circuit, the clock signal line CK can be one of CK1, CK2, CK3, CK4, CK5, CK6, CK7, and CK8.

[0211] In Figure 10 In the embodiment shown, TD1 denotes a first display stage, TT1 denotes a first touch stage, TD2 denotes a second display stage, TT2 denotes a second touch stage, and TD3 denotes a third display stage. F1 denotes a first frame time.

[0212] As shown, in the display stage, each clock signal line provides a clock signal, in the touch stage, each clock signal line provides a low voltage signal, and each clock signal line provides a high frequency square wave voltage signal, for example, the voltage value of the signal provided by each clock signal line can be changed between -12V and -10V. Figure 10 In the display stage, GCH provides a high voltage signal, for example, the voltage value of the high voltage signal provided by GCH can be 12V. In the touch stage, GCH can provide a low voltage signal, GCH provides a high frequency square wave voltage signal, for example, the voltage value of the signal provided by GCH can be changed between 12V and -10V.

[0213] In the display stage, GCL provides a low voltage signal, for example, the voltage value of the low voltage signal provided by GCL can be -12V. In the touch stage, GCL provides a high voltage signal, GCL provides a high frequency square wave voltage signal, for example, the voltage value of the signal provided by GCL can be changed between 10V and 12V.

[0214] In the display stage, VDS provides a high voltage signal, for example, the voltage value of the high voltage signal provided by VDS can be 12V. In the touch stage, VDS provides a high frequency square wave voltage signal, VDS provides a high voltage signal, for example, the voltage value of the signal provided by VDS can be changed between 12V and 14V.

[0215] In the display stage, VSD provides a low voltage signal, for example, the voltage value of the low voltage signal provided by VSD can be -12V. In the touch stage, VSD provides a high frequency square wave voltage signal, VSD provides a low voltage signal, for example, the voltage value of the signal provided by VSD can be changed between 10V and 12V.

[0216] In the display stage, VGL provides a low voltage signal, for example, the voltage value of the low voltage signal provided by VGL can be -12V. In the touch stage, VGL provides a high frequency square wave voltage signal, VGL provides a low voltage signal, for example, the voltage value of the signal provided by VGL can be changed between -12V and -10V.

[0217] In the display stage, VGL provides a low voltage signal, for example, the voltage value of the low voltage signal provided by VGL can be -12V. In the touch stage, VGL provides a high frequency square wave voltage signal, VGL provides a low voltage signal, for example, the voltage value of the signal provided by VGL can be changed between -12V and -10V.

[0218] At least one embodiment of the drive circuit shown is different from Figure 11 At least one embodiment of the drive circuit shown is different from Figure 6 At least one embodiment of the drive circuit shown is different from

[0219] The output reset circuit 45 is not electrically connected with the first control end GCL, and is electrically connected with the start control end S0. The output reset circuit 45 is used for controlling the drive output end O1 and the first voltage end V1 to be connected or disconnected under the control of a start control signal provided by the start control end S0.

[0220] Figure 12 At least one embodiment of the drive circuit shown is different from Figure 6 At least one embodiment of the drive circuit shown is different from

[0221] The gate of the M12 is electrically connected with the start control end S0.

[0222] Figure 12 At least one embodiment of the drive circuit shown is different from

[0223] The drive method provided by the embodiment of the present application is applied to the drive circuit described above, and a display period includes a touch phase. The drive method includes the following steps.

[0224] In the touch phase, the potential control circuit controls the first control end and the control node to be connected under the control of the potential of the pull-up node.

[0225] In the drive method provided by the embodiment of the present application, in the touch phase, the potential control circuit controls the first control end and the control node to be connected under the control of the potential of the pull-up node, so as to pull up the potential of the pull-up node through the first energy storage circuit, so that the potential of the pull-up node does not decrease in the touch phase, and the potential of the drive signal provided by the drive circuit does not decrease when the display phase is entered again, thereby avoiding the generation of LH horizontal lines.

[0226] The display device provided by the embodiment of the present application includes the drive circuit described above.

[0227] The above is the preferred embodiment of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements should be considered as the protection scope of the present application.

Claims

1. A driving circuit, characterized in that, This includes the drive output terminal, input circuit, output circuit, and pull-up node; The input circuit is electrically connected to the pull-up node, the input control terminal, and the input voltage terminal, respectively, and is used to write the input voltage provided by the input voltage terminal to the pull-up node under the control of the input control signal provided by the input control terminal; The output circuit is electrically connected to the pull-up node, the clock signal line and the drive output terminal respectively, and is used to write the clock signal provided by the clock signal line into the drive output terminal under the control of the potential of the pull-up node. The driving circuit also includes a potential control circuit and a first energy storage circuit; The potential control circuit is electrically connected to the pull-up node, the first control terminal, and the control node, respectively, and is used to control the connection or disconnection between the first control terminal and the control node under the control of the potential of the pull-up node. The first terminal of the first energy storage circuit is electrically connected to the control node, and the second terminal of the first energy storage circuit is electrically connected to the pull-up node. The first energy storage circuit is used to store electrical energy. The first control terminal is used to provide a valid voltage signal during the touch phase and an invalid voltage signal during the display phase; The potential control circuit includes a first transistor, and the first energy storage circuit includes a first capacitor. The gate of the first transistor is electrically connected to the pull-up node, the first terminal of the first transistor is electrically connected to the first control terminal, and the second terminal of the first transistor is electrically connected to the control node. The first terminal of the first capacitor is electrically connected to the control node, and the second terminal of the first capacitor is electrically connected to the pull-up node.

2. The driving circuit as described in claim 1, characterized in that, The channel width-to-length ratio of the first transistor is greater than or equal to 12.5 and less than or equal to 100, and the capacitance value of the first capacitor is greater than or equal to 0.5fF and less than or equal to 4fF.

3. The driving circuit as described in claim 1 or 2, characterized in that, It also includes an output reset circuit; The output reset circuit is electrically connected to the first control terminal, the drive output terminal, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the drive output terminal and the first voltage terminal under the control of the first control signal provided by the first control terminal.

4. The driving circuit as described in claim 1 or 2, characterized in that, It also includes a reset circuit and a pull-up node control circuit; The reset circuit is electrically connected to the pull-up node, the reset control terminal, and the reset voltage terminal, respectively, and is used to write the reset voltage provided by the reset voltage terminal into the pull-up node under the control of the reset control signal provided by the reset control terminal. The pull-up node control circuit is electrically connected to the pull-up node, the pull-down node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the pull-up node and the first voltage terminal under the control of the potential of the pull-down node.

5. The driving circuit as described in claim 1 or 2, characterized in that, It also includes the drop-down node control circuit; The pull-down node control circuit is electrically connected to the second control terminal, the pull-down control node, the pull-down node, the pull-up node, and the first voltage terminal, respectively. It is used to control the potential of the pull-down control node under the control of the potential of the pull-up node and the second control signal provided by the second control terminal, and to control the potential of the pull-down node according to the second control signal under the control of the potential of the pull-down control node and the potential of the pull-up node.

6. The driving circuit as described in claim 5, characterized in that, The second control terminal is used to provide a valid voltage signal during the display phase and an invalid voltage signal during the touch phase.

7. The driving circuit as described in claim 1 or 2, characterized in that, It also includes a pull-up node reset circuit; The pull-up node reset circuit is electrically connected to the start control terminal, the pull-up node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the pull-up node and the first voltage terminal under the control of the start control signal provided by the start control terminal.

8. The driving circuit as described in claim 1 or 2, characterized in that, It also includes an output control circuit and a second energy storage circuit; The output control circuit is electrically connected to the pull-down node, the drive output terminal, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the drive output terminal and the first voltage terminal under the control of the potential of the pull-down node. The second energy storage circuit is electrically connected to the pull-up node and the drive output terminal respectively, and is used to store electrical energy.

9. The driving circuit as described in claim 1 or 2, characterized in that, It also includes an output reset circuit; The output reset circuit is electrically connected to the start control terminal, the drive output terminal, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the drive output terminal and the first voltage terminal under the control of the start control signal provided by the start control terminal.

10. The driving circuit as described in claim 4, characterized in that, The input circuit includes a second transistor, the reset circuit includes a third transistor, and the pull-up node control circuit includes a fourth transistor. The gate of the second transistor is electrically connected to the input control terminal, the first terminal of the second transistor is electrically connected to the input voltage terminal, and the second terminal of the second transistor is electrically connected to the pull-up node. The gate of the third transistor is electrically connected to the reset control terminal, the first terminal of the third transistor is electrically connected to the pull-up node, and the second terminal of the third transistor is electrically connected to the reset voltage terminal. The gate of the fourth transistor is electrically connected to the pull-down node, the first terminal of the fourth transistor is electrically connected to the pull-up node, and the second terminal of the fourth transistor is electrically connected to the first voltage terminal.

11. The driving circuit as described in claim 10, characterized in that, The potential control circuit includes a first transistor; The ratio between the channel width-to-length ratio of the first transistor and the channel width-to-length ratio of the fourth transistor is greater than or equal to 0.5 and less than or equal to 4.

12. The driving circuit as described in claim 5, characterized in that, The pull-down node control circuit includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; The gate and the first terminal of the fifth transistor are both electrically connected to the second control terminal, and the second terminal of the fifth transistor is electrically connected to the pull-down control node. The gate of the sixth transistor is electrically connected to the pull-down control node, the first terminal of the sixth transistor is electrically connected to the second control terminal, and the second terminal of the sixth transistor is electrically connected to the pull-down node. The gate of the seventh transistor is electrically connected to the pull-up node, the first terminal of the seventh transistor is electrically connected to the pull-down control node, and the second terminal of the seventh transistor is electrically connected to the first voltage terminal. The gate of the eighth transistor is electrically connected to the pull-up node, the first terminal of the eighth transistor is electrically connected to the pull-down node, and the second terminal of the eighth transistor is electrically connected to the first voltage terminal.

13. The driving circuit as described in claim 7, characterized in that, The pull-up node reset circuit includes a ninth transistor; The gate of the ninth transistor is electrically connected to the start control terminal, the first terminal of the ninth transistor is electrically connected to the pull-up node, and the second terminal of the ninth transistor is electrically connected to the first voltage terminal.

14. The driving circuit as described in claim 8, characterized in that, The output circuit includes a tenth transistor, and the output control circuit includes an eleventh transistor. The gate of the tenth transistor is electrically connected to the pull-up node, the first terminal of the tenth transistor is electrically connected to the clock signal line, and the second terminal of the tenth transistor is electrically connected to the drive output terminal. The gate of the eleventh transistor is electrically connected to the pull-down node, the first terminal of the eleventh transistor is electrically connected to the drive output terminal, and the second terminal of the eleventh transistor is electrically connected to the first voltage terminal. The second energy storage circuit includes a second capacitor; The first end of the second capacitor is electrically connected to the pull-up node, and the second end of the second capacitor is electrically connected to the drive output terminal.

15. The driving circuit as described in claim 14, characterized in that, The first energy storage circuit includes a first capacitor; The ratio between the capacitance value of the first capacitor and the capacitance value of the second capacitor is greater than or equal to 1 / 1000 and less than or equal to 8 / 1000.

16. The driving circuit as described in claim 3, characterized in that, The output reset circuit includes a twelfth transistor; The gate of the twelfth transistor is electrically connected to the first control terminal, the first terminal of the twelfth transistor is electrically connected to the drive output terminal, and the second terminal of the twelfth transistor is electrically connected to the first voltage terminal.

17. The driving circuit as described in claim 9, characterized in that, The output reset circuit includes a thirteenth transistor; The gate of the thirteenth transistor is electrically connected to the start control terminal, the first terminal of the thirteenth transistor is electrically connected to the drive output terminal, and the second terminal of the thirteenth transistor is electrically connected to the first voltage terminal.

18. A driving method applied to a driving circuit as described in any one of claims 1 to 17, characterized in that, The display cycle includes a touch phase; the driving method includes: During the touch control phase, the potential control circuit controls the connection between the first control terminal and the control node under the control of the potential of the pull-up node.

19. A display device, characterized in that, Includes the drive circuit as described in any one of claims 1 to 17.

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