Semiconductor structure, image sensor, and method for manufacturing semiconductor structure

Abstract

The embodiments of the present disclosure provide a semiconductor structure, an image sensor, and a method for preparing a semiconductor structure. The semiconductor structure includes: a first substrate, including a photoelectric conversion element, a transfer transistor, and a first conductive pad, wherein the photoelectric conversion element is electrically connected to the first source-drain region of the transfer transistor, and the first conductive pad is electrically connected to the second source-drain region of the transfer transistor; a second substrate, including a readout circuit and a second conductive pad, wherein the readout circuit is electrically connected to the second conductive pad; a bonding structure, disposed between the first substrate and the second substrate, and connecting the first substrate and the second substrate so that the first conductive pad is electrically connected to the second conductive pad. The semiconductor structure provided by the embodiments of the present disclosure increases the surface area of ​​the photoelectric conversion element, improves the fill factor of the semiconductor structure, and increases the sensitivity of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a semiconductor structure, an image sensor, and a method for manufacturing the semiconductor structure. Background Art

[0002] Generally speaking, an image sensor is a device that converts light signals into electrical signals. Image sensor units primarily include charge-coupled devices (CCDs) and complementary metal-oxide semiconductor (CMOS) devices. Compared to traditional CCD sensors, CMOS image sensors offer advantages such as low power consumption, low cost, and compatibility with CMOS processes, leading to their increasing adoption.

[0003] The pixel unit of a common CMOS image sensor typically contains an active pixel structure consisting of a photodiode (PD) and four transistors (4T). Given the limited pixel unit area, the large number of transistors reduces the surface area of ​​the photodiode, which means the fill factor of the pixel unit is reduced. The fill factor is one of the important factors affecting image sensor performance. It represents the ratio of the surface area of ​​the photodiode to the total surface area of ​​the unit pixel. A large fill factor means a high ability to convert received light into electrical signals. As pixels become smaller, the proportion of the area occupied by transistors increases, further reducing the fill factor.

[0004] Therefore, how to improve the fill factor of CMOS image sensors has become a technical problem that needs to be solved urgently. Summary of the Invention

[0005] Embodiments of the present disclosure provide a semiconductor structure, an image sensor, and a method for manufacturing the semiconductor structure, which can improve the fill factor of the semiconductor structure.

[0006] In order to solve the above problems, an embodiment of the present disclosure provides a semiconductor structure, including: a first substrate, including a photoelectric conversion element, a transfer transistor and a first conductive pad, the photoelectric conversion element is electrically connected to the first source and drain region of the transfer transistor, and the first conductive pad is electrically connected to the second source and drain region of the transfer transistor; a second substrate, including a readout circuit and a second conductive pad, the readout circuit is electrically connected to the second conductive pad; a bonding structure, arranged between the first substrate and the second substrate, and connecting the first substrate and the second substrate so that the first conductive pad is electrically connected to the second conductive pad.

[0007] In one embodiment, the first substrate includes at least one photoelectric conversion element group, the photoelectric conversion element group includes a plurality of photoelectric conversion elements and a plurality of transfer transistors corresponding one-to-one to the plurality of photoelectric conversion elements, and the second source and drain regions of the plurality of transfer transistors are electrically connected to the same first conductive pad.

[0008] In one embodiment, the second source-drain region of the transfer transistor serves as a floating diffusion region; or the second substrate includes a floating diffusion region electrically connected to the second conductive pad.

[0009] In one embodiment, the transfer transistor is a vertical channel transistor, which includes: a semiconductor column, including the first source and drain region, the channel region and the second source and drain region arranged in sequence along a first direction perpendicular to the main surface of the first substrate; and a gate structure arranged on the outer side wall of the channel region of the semiconductor column.

[0010] In one embodiment, the gate structure extends along a second direction parallel to the main surface of the first substrate, and the vertical channel transistors arranged in the second direction share the same gate structure.

[0011] In one embodiment, the cross section of each of the photoelectric conversion elements is a regular hexagon, and the plurality of photoelectric conversion elements are arranged in a honeycomb shape.

[0012] In one embodiment, the photoelectric conversion element is a photodiode, a cathode of the photodiode is electrically connected to the first source-drain region of the transfer transistor, and an anode of the photodiode is electrically connected to the ground terminal.

[0013] In one embodiment, the readout circuit includes: a source follower transistor, the gate of the source follower transistor is electrically connected to the second conductive pad, and the first source-drain region of the source follower transistor is electrically connected to the power supply terminal; a selection transistor, the first source-drain region of the selection transistor is electrically connected to the second source-drain region of the source follower transistor, and the second source-drain region of the selection transistor is electrically connected to the output terminal of the readout circuit.

[0014] In one embodiment, the readout circuit further includes a reset circuit, the reset circuit includes a reset transistor, a first source-drain region of the reset transistor is electrically connected to a power supply terminal, and a second source-drain region of the reset transistor is electrically connected to the second conductive pad.

[0015] In one embodiment, the readout circuit further includes a dual conversion gain circuit, the dual conversion gain circuit including a dual conversion gain transistor and a capacitor, the first source and drain regions of the dual conversion gain transistor being electrically connected to the second conductive pad, the second source and drain regions of the dual conversion gain transistor being electrically connected to the first plate of the capacitor, and the second plate of the capacitor being electrically connected to the power supply terminal.

[0016] In one embodiment, a color filter array and a microlens array are further included. The color filter array is arranged on a side of the photoelectric conversion element away from the transfer transistor through an insulating isolation layer, and the microlens array is arranged on a side of the color filter away from the photoelectric conversion element.

[0017] In one embodiment, the color filter array includes a plurality of filter units arranged in an array, and one filter unit corresponds to one or more photoelectric conversion elements.

[0018] In one embodiment, the bonding structure includes an insulator and a conductive block, two sides of the conductive block are respectively in contact with the first conductive pad and the second conductive pad, and the insulator seals the conductive block.

[0019] An embodiment of the present disclosure further provides an image sensor, which includes the above-mentioned semiconductor structure.

[0020] An embodiment of the present disclosure also provides a method for preparing a semiconductor structure, including: providing a first substrate, the first substrate including a photoelectric conversion element, a transfer transistor and a first conductive pad, the photoelectric conversion element being electrically connected to the first source and drain region of the transfer transistor, and the first conductive pad being electrically connected to the second source and drain region of the transfer transistor; providing a second substrate, the second substrate including a readout circuit and a second conductive pad, the readout circuit being electrically connected to the second conductive pad; bonding the first substrate and the second substrate to form a bonding structure between the first substrate and the second substrate, the bonding structure connecting the first substrate and the second substrate so that the first conductive pad is electrically connected to the second conductive pad.

[0021] In one embodiment, the method for forming the first substrate includes: providing a first substrate; forming a photoelectric conversion layer on the first substrate, the photoelectric conversion layer including the photoelectric conversion element; forming a transfer transistor layer on the photoelectric conversion layer, the transfer transistor layer including the transfer transistor; and forming the first conductive pad on the transfer transistor layer.

[0022] In one embodiment, in the step of forming a transfer transistor layer on the photoelectric conversion layer, the second source and drain region of the transfer transistor serves as a floating diffusion region, or, in the step of providing a second substrate, the second substrate includes a floating diffusion region electrically connected to the second conductive pad.

[0023] In one embodiment, the step of bonding the first substrate to the second substrate includes: removing the first substrate to expose the photoelectric conversion layer; forming a color filter array and a microlens array on the photoelectric conversion layer, the color filter array being arranged on a side of the photoelectric conversion element away from the transfer transistor, and the microlens array being arranged on a side of the color filter away from the photoelectric conversion element.

[0024] In one embodiment, after the step of exposing the photoelectric conversion layer, the step further includes: dividing the photoelectric conversion layer to form a plurality of photoelectric conversion element groups, each of the photoelectric conversion element groups including a plurality of the photoelectric conversion elements and a plurality of transfer transistors corresponding one-to-one to the plurality of photoelectric conversion elements, and all the photoelectric conversion element groups including the same number of photoelectric conversion elements; forming an insulating isolation layer on the photoelectric conversion layer; and forming the color filter array on the insulating isolation layer.

[0025] In one embodiment, a method for forming the second substrate includes: providing a second substrate; forming a circuit layer on the second substrate, wherein the circuit layer includes the readout circuit; and forming the second conductive pad on the circuit layer.

[0026] In the semiconductor structure provided by the embodiment of the present disclosure, the photoelectric conversion element and the transfer transistor are arranged on the first substrate, and the readout circuit is arranged on the second substrate. The first substrate and the second substrate are electrically connected through a bonding structure to form a 3D stacked structure. Compared with the horizontal structure in which the photoelectric conversion element, the transfer transistor and the readout circuit are all distributed on the same substrate, the semiconductor structure provided by the embodiment of the present disclosure increases the surface area of ​​the photoelectric conversion element, improves the fill factor of the semiconductor structure, and increases the sensitivity of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0028] Figure 2 is a circuit diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0029] Figure 3 is a schematic diagram of the three-dimensional structure of a photoelectric conversion element and a transfer transistor in a semiconductor structure provided by an embodiment of the present disclosure;

[0030] Figure 4 is a schematic top view of a first substrate in a semiconductor structure provided by an embodiment of the present disclosure;

[0031] Figure 5 It is a schematic diagram of the arrangement of multiple photoelectric conversion elements;

[0032] Figure 6 1 is a schematic diagram of the steps of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0033] Figures 7A to 7F It is a process flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The specific embodiments of the semiconductor structure, image sensor, and method for manufacturing the semiconductor structure provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0035] Figure 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure, Figure 2 is a circuit diagram of a semiconductor structure provided by an embodiment of the present disclosure. Figure 1 and Figure 2 The semiconductor structure includes: a first substrate 100, including a photoelectric conversion element 121, a transfer transistor 131 and a first conductive pad 140, a first source and drain region SD1 (marked at Figure 7B ) is electrically connected to the first conductive pad 140 and the second source-drain region SD2 (marked at Figure 7B ) is electrically connected; the second substrate 200 includes a readout circuit 221 and a second conductive pad 230, and the readout circuit 221 is electrically connected to the second conductive pad 230; the bonding structure 300 is arranged between the first substrate 100 and the second substrate 200, and connects the first substrate 100 and the second substrate 200, so that the first conductive pad 140 is electrically connected to the second conductive pad 230.

[0036] In the semiconductor structure provided by the embodiments of the present disclosure, the photoelectric conversion element 121 and the transfer transistor 131 are disposed on a first substrate 100, and the readout circuit 221 is disposed on a second substrate 200. The first substrate 100 and the second substrate 200 are electrically connected via a bonding structure 300, forming a 3D stacked structure. Compared to a horizontal structure in which the photoelectric conversion element 121, the transfer transistor 131, and the readout circuit 221 are all distributed on the same substrate, the semiconductor structure provided by the embodiments of the present disclosure increases the surface area of ​​the photoelectric conversion element 121 and improves the fill factor of the semiconductor structure. The fill factor is one of the important factors affecting the performance of an image sensor. It represents the ratio of the surface area of ​​a photodiode to the total surface area of ​​a unit pixel. A large fill factor means a greater ability to convert received light into an electrical signal, that is, a high sensitivity.

[0037] In some embodiments, the photoelectric conversion element 121 is a photodiode, the cathode of the photodiode is electrically connected to the first source-drain region SD1 of the transfer transistor 131, and the anode of the photodiode is electrically connected to the ground terminal GND. The transfer transistor 131 can be an NMOS transistor, a PMOS transistor, or a CMOS transistor composed of an NMOS transistor and a PMOS transistor.

[0038] In some embodiments, the first substrate 100 includes a first substrate 110 (indicated by Figure 7A ), a photoelectric conversion layer 120 and a transfer transistor layer 130, wherein the photoelectric conversion layer 120 is disposed within the first substrate 110, the transfer transistor layer 130 is disposed on the photoelectric conversion layer 120, and the first conductive pad 140 is disposed on the transfer transistor layer 130. The photoelectric conversion layer 120 includes a photoelectric conversion element 121, and the transfer transistor layer 130 includes a transfer transistor 131.

[0039] In some embodiments, the first substrate 100 includes at least one photoelectric conversion element group 400, the photoelectric conversion element group 400 includes a plurality of photoelectric conversion elements 121 and a plurality of transfer transistors 131 corresponding to the plurality of photoelectric conversion elements 121, and the second source and drain regions SD2 of the plurality of transfer transistors 131 are electrically connected to the same first conductive pad 140. For example, in Figure 1 A photoelectric conversion element group 400 is schematically illustrated in the figure, which includes seven photoelectric conversion elements 121. The seven photoelectric conversion elements 121 are electrically connected to the first source-drain regions SD1 of seven transfer transistors 131 respectively, and the first source-drain regions SD1 of the seven transfer transistors 131 are electrically connected to the same first conductive pad 140.

[0040] If the second source-drain regions SD2 of the plurality of transfer transistors 131 corresponding to the same photoelectric conversion element group 400 are connected to different first conductive pads 140, then within a limited area, the surface area of ​​the first conductive pad 140 must be small. However, in the semiconductor structure provided by this embodiment of the present disclosure, the second source-drain regions SD2 of the plurality of transfer transistors 131 corresponding to the same photoelectric conversion element group 400 are electrically connected to the same first conductive pad 140. Then, within a limited area, the surface area of ​​the first conductive pad 140 is greatly increased, thereby improving the connection strength and reliability between the first conductive pad 140 and the second conductive pad 230, and reducing the difficulty of aligning the first conductive pad 140 with the second conductive pad 230.

[0041] In some embodiments, when the first substrate 100 includes multiple photoelectric conversion element groups 400, the second source-drain regions SD2 of multiple transfer transistors 131 of different photoelectric conversion element groups 400 are electrically connected to different first conductive pads 140, or the second source-drain regions SD2 of multiple transfer transistors 131 of some or all of the photoelectric conversion element groups 400 are electrically connected to the same first conductive pad 140.

[0042] In some embodiments, the second source / drain region SD2 of the transfer transistor 131 serves as a floating diffusion region FD. Alternatively, the second substrate 200 includes a floating diffusion region FD electrically connected to the second conductive pad 230. Photogenerated carriers generated within the photoelectric conversion element 121 can enter the floating diffusion region FD through the transfer transistor 131. In this embodiment, the second source / drain region SD2 of the transfer transistor 131 serves as the floating diffusion region FD.

[0043] In some embodiments, the transfer transistor 131 is a vertical channel transistor (VCT) to further reduce the area occupied by the transfer transistor 131 and improve the fill factor.

[0044] See also Figure 1 and Figure 3 ,in, Figure 3 FIG1 is a schematic diagram of the three-dimensional structure of a photoelectric conversion element 121 and a transfer transistor 131 in a semiconductor structure provided in one embodiment of the present disclosure. The transfer transistor 131 is a vertical channel transistor comprising a semiconductor pillar 1310 and a gate structure 1320. The semiconductor pillar 1310 comprises a first source / drain region SD1, a channel region CH, and a second source / drain region SD2, arranged in sequence along a first direction D1 perpendicular to the major surface of the first substrate 100. The gate structure 1320 is disposed on the outer sidewall of the channel region CH of the semiconductor pillar 1310.

[0045] The semiconductor pillars 1310 extend along a first direction D1 and are made of, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), or indium-gallium-zinc oxide. In some embodiments, the ion doping type of the first source / drain region SD1 and the second source / drain region SD2 is different from the ion doping type of the channel region CH. For example, the ion doping type of the first source / drain region SD1 and the second source / drain region SD2 is N-type, while the ion doping type of the channel region CH is P-type, or the ion doping type of the first source / drain region SD1 and the second source / drain region SD2 is P-type, while the ion doping type of the channel region CH is N-type. In some embodiments, a metal silicide layer (not shown) is further disposed at the ends of the first source / drain region SD1 and the second source / drain region SD2 to reduce the contact resistance between the first source / drain region SD1 and the photoelectric conversion element 121, and the contact resistance between the second source / drain region SD2 and the first conductive interconnect structure 500.

[0046] The gate structure 1320 includes a gate dielectric layer covering the outer sidewalls of the channel region CH of the semiconductor pillar 1310 and a gate conductive layer covering the outer sidewalls of the gate dielectric layer. In some embodiments, the gate dielectric layer also covers the outer sidewalls of the first source / drain region SD1 and the second source / drain region SD2, while the gate conductive layer only covers the outer sidewalls of the gate dielectric layer corresponding to the channel region CH. The gate dielectric layer includes, but is not limited to, a silicon oxide layer or a high-K dielectric layer, and the gate conductive layer includes, but is not limited to, a tungsten layer or a composite layer of a tungsten layer and a titanium nitride layer.

[0047] In some embodiments, the second source / drain region SD2 of the vertical transistor is electrically connected to one end of the first conductive interconnect structure 500, and the other end of the first conductive interconnect structure 500 is electrically connected to the first conductive pad 140. The first conductive interconnect structure 500 allows the first conductive pad 140 to be positioned differently without having to be positioned directly opposite the second source / drain region SD2. This allows the second source / drain regions SD2 of multiple transfer transistors 131 to be electrically connected to the same first conductive pad 140, providing high flexibility and meeting structural design requirements.

[0048] See also Figure 3 and Figure 4 ,in, Figure 4 1 is a top view of the relationship between the photoelectric conversion element, the transfer transistor and the first conductive pad of the first substrate 100 in the semiconductor structure provided by one embodiment of the present disclosure. Figure 4The middle semiconductor pillar is obscured and depicted with dashed lines. In some embodiments, the gate structure 1320 extends along a second direction D2 parallel to the main surface of the first substrate 100. Vertical channel transistors arranged in the second direction D2 share the same gate structure 1320. Multiple gate structures 1320 are arranged in intervals along a third direction D3, with an insulating isolation layer disposed between adjacent gate structures 1320 to prevent electrical conduction between adjacent gate structures 1320. The third direction D3 is parallel to the main surface of the first substrate 100 and forms an acute angle or a right angle with the second direction D2.

[0049] In some embodiments, the cross section of each photoelectric conversion element 121 is a regular hexagon, and the plurality of photoelectric conversion unit elements are arranged in a honeycomb pattern. Figure 5 is a schematic diagram of the arrangement of multiple photoelectric conversion elements 121, please refer to Figure 5 The cross-section of the photoelectric conversion element 121 is a regular hexagon, and seven photoelectric conversion elements 121 are arranged in a honeycomb pattern. These seven photoelectric conversion elements 121 constitute a photoelectric conversion element group 400. It will be understood that the seven photoelectric conversion elements 121 constituting a photoelectric conversion element group 400 is merely illustrative, and in other embodiments, other numbers of photoelectric conversion elements 121 may be configured as a photoelectric conversion element group 400, with the photoelectric conversion elements 121 in the same photoelectric conversion element group 400 being arranged in a honeycomb pattern, and different photoelectric conversion element groups 400 may also be arranged in a honeycomb pattern.

[0050] This honeycomb arrangement can increase the surface area of ​​each photoelectric conversion element 121 under the condition of limited area and a certain number of photoelectric conversion elements 121, thereby greatly improving the fill factor of the semiconductor structure.

[0051] Please continue reading Figure 1 and Figure 2 In some embodiments, the second substrate 200 includes a second substrate 210 and a circuit layer 220. The circuit layer 220 is disposed on the second substrate 210, and the second conductive pad 230 is disposed on the circuit layer 220. The circuit layer 220 includes a readout circuit 221. In some embodiments, a logic circuit (not shown in the drawings) is further disposed within the second substrate 200. The photoelectric conversion element 121 receives light and generates photocharges. The transfer transistor 131 transfers the photocharges accumulated in the photoelectric conversion element 121 to the floating diffusion region FD, and the photocharges are read out by the readout circuit 221.

[0052] In some embodiments, the second substrate 200 has at least one readout circuit 221, each readout circuit 221 is electrically connected to one second conductive pad 230, and different readout circuits 221 are electrically connected to different second conductive pads 230. For example, Figure 1Schematically depicts a readout circuit 221 , which is electrically connected to a second conductive pad 230 .

[0053] In some embodiments, the readout circuit 221 is electrically connected to the second conductive pad 230 via a second conductive interconnect structure 501. One end of the second conductive interconnect structure 501 is electrically connected to the readout circuit 221, and the other end is electrically connected to the second conductive pad 230. The second conductive interconnect structure 501 allows the second conductive pad 230 to be positioned differently without having to locate the second conductive pad 230 directly opposite the readout circuit 221. This provides high flexibility and can meet structural design requirements.

[0054] In some embodiments, the readout circuit 221 includes a source follower transistor SF and a select transistor SEL. The gate of the source follower transistor SF is electrically connected to the second conductive pad 230, and the first source-drain region SF-SD1 of the source follower transistor SF is electrically connected to the power supply terminal VDD. The first source-drain region SEL-SD1 of the select transistor SEL is electrically connected to the second source-drain region SF-SD2 of the source follower transistor SF, and the second source-drain region SEL-SD2 of the select transistor SEL is electrically connected to the output terminal OUT of the readout circuit 221. The source follower transistor SF is used to amplify the voltage change in the floating diffusion region FD, and the select transistor SEL is used to output the signal amplified by the source follower transistor SF based on the logic level of the select signal. The source follower transistor SF and the select transistor SEL can be NMOS transistors or PMOS transistors.

[0055] In some embodiments, readout circuit 221 further includes a reset circuit 600, which includes a reset transistor RG. A first source-drain region RG-SD1 of reset transistor RG is electrically connected to power supply terminal VDD, and a second source-drain region RG-SD2 of reset transistor RG is electrically connected to second conductive pad 230. Reset circuit 600 is used to reset floating diffusion region FD, thereby conducting away residual electrons from a previous signal transmission in floating diffusion region FD to prevent interference with the current signal transmission. Reset transistor RG can be an NMOS transistor or a PMOS transistor.

[0056] In some embodiments, readout circuit 221 further includes a dual conversion gain circuit 700, which includes a dual conversion gain transistor DCG and a capacitor C1. A first source-drain region DCG-SD1 of dual conversion gain transistor DCG is electrically connected to second conductive pad 230, a second source-drain region DCG-SD2 of dual conversion gain transistor DCG is electrically connected to a first plate of capacitor C1, and a second plate of capacitor C1 is electrically connected to power supply terminal VSC. When dual conversion gain transistor DCG is activated, photocharge generated in photoelectric conversion element 121 can be transferred to capacitor C1. Dual conversion gain transistor DCG can be an NMOS transistor or a PMOS transistor.

[0057] In the semiconductor structure provided by some embodiments of the present disclosure, in the signal accumulation stage, the transfer transistor 131, the source follower transistor SF and the selection transistor SEL are in the off state, and the photoelectric conversion element 121 receives light, performs photoelectric conversion, and accumulates photoelectrons; in the reset stage, the reset transistor RG and the selection transistor SEL are turned on to reset the floating diffusion area FD. At the same time, the photoelectric conversion element 121 is still receiving light to generate photoelectrons; after the reset is completed, the reset transistor RG is turned off, and the transfer transistor 131 is turned on to transfer the photoelectrons in the photoelectric conversion element 121 to the floating diffusion area FD. After the transfer is completed, the transfer transistor 131 is turned off to prevent the subsequent photoelectric conversion in the photoelectric conversion element 121 from affecting the floating diffusion area FD. At the same time, the floating diffusion area FD generates a voltage due to the photoelectrons, which controls the source follower transistor SF to turn on and amplify the voltage of the floating diffusion area FD. The selection transistor SEL outputs the signal amplified by the source follower transistor SF based on the logic level of the selection signal.

[0058] In some embodiments, the semiconductor structure further includes a color filter array (CFA) 800 and a micro lens array (MLA) 900 .

[0059] The color filter array 800 is disposed on a side of the photoelectric conversion element 121 away from the transfer transistor 131 through an insulating isolation layer, and is used to filter incident light so that the incident light is converted into monochromatic light and incident on the photoelectric conversion element 121 .

[0060] In some embodiments, the color filter array 800 includes a plurality of filter units 801 arranged in an array, with each filter unit 801 corresponding to one or more photoelectric conversion elements 121. In some embodiments, one filter unit 801 corresponds to one photoelectric conversion element 121. In other embodiments, one filter unit 801 corresponds to two or more photoelectric conversion elements 121. For example, in some embodiments, the filter unit 801 may be a red (R) filter, a green (G) filter, and a blue (B) filter, with the red (R) filter and the blue (B) filter each corresponding to one photoelectric conversion element 121, and the green (G) filter corresponding to two photoelectric conversion elements 121.

[0061] The microlens array 900 is positioned on the side of the color filter away from the photoelectric conversion element 121. It includes a plurality of microlenses 901 arranged in an array. Microlenses 901 refract incident light and direct it toward the photoelectric conversion element 121, thereby increasing the incident light intensity and enhancing the sensitivity of the semiconductor structure. In some embodiments, each filter unit 801 corresponds to a microlens 901. In other embodiments, multiple filter units 801 correspond to the same microlens 901, or one filter unit 801 corresponds to multiple microlenses 901.

[0062] In some embodiments, the bonding structure 300 includes an insulator 301 and a conductive block 302. Two sides of the conductive block 302 are in contact with the first conductive pad 140 and the second conductive pad 230, respectively. The insulator 301 seals the conductive block 302. The insulator 301 is filled between the plurality of conductive blocks 302 and between the first substrate 100 and the second substrate 200 to seal and insulate adjacent conductive blocks 302. In some embodiments, the conductive block 302 is used to electrically connect the first conductive pad 140 and the second conductive pad 230, and includes, but is not limited to, a solder block.

[0063] The present disclosure also provides an image sensor using the semiconductor structure. The image sensor may be a CMOS image sensor, which increases the surface area of ​​the photoelectric conversion element 121 within a limited area, improves the fill factor of the image sensor, and thus improves the sensitivity of the image sensor.

[0064] The disclosed embodiments also provide a method for preparing the semiconductor structure. Figure 6 This is a schematic diagram of the steps of the method for preparing a semiconductor structure according to an embodiment of the present disclosure. Figure 6The preparation method includes: step S60, providing a first substrate 100, the first substrate 100 includes a photoelectric conversion element 121, a transfer transistor 131 and a first conductive pad 140, the photoelectric conversion element 121 is electrically connected to the first source and drain region SD1 of the transfer transistor 131, and the first conductive pad 140 is electrically connected to the second source and drain region SD2 of the transfer transistor 131; step S61, providing a second substrate 200, the second substrate 200 includes a readout circuit 221 and a second conductive pad 230, and the readout circuit 221 is electrically connected to the second conductive pad 230; step S62, bonding the first substrate 100 and the second substrate 200 to form a bonding structure 300 between the first substrate 100 and the second substrate 200, the bonding structure 300 connecting the first substrate 100 and the second substrate 200 so that the first conductive pad 140 is electrically connected to the second conductive pad 230.

[0065] The method for preparing a semiconductor structure provided by an embodiment of the present disclosure bonds a first substrate 100 provided with a photoelectric conversion element 121 and a transfer transistor 131 to a second substrate 200 provided with a readout circuit 221 through a bonding structure 300 to form a 3D stacked structure. Compared with a horizontal structure in which the photoelectric conversion element 121, the transfer transistor 131 and the readout circuit 221 are all distributed on the same substrate, the semiconductor structure prepared by the method of the embodiment of the present disclosure increases the surface area of ​​the photoelectric conversion element 121 and improves the fill factor of the semiconductor structure.

[0066] Figures 7A to 7F It is a process flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure.

[0067] See also Figure 6 and Figures 7A to 7C In step S60, a first substrate 100 is provided. The first substrate 100 includes a photoelectric conversion element 121, a transfer transistor 131 and a first conductive pad 140. The photoelectric conversion element 121 is electrically connected to the first source-drain region SD1 of the transfer transistor 131, and the first conductive pad 140 is electrically connected to the second source-drain region SD2 of the transfer transistor 131.

[0068] In some embodiments, the first substrate 100 includes at least one photoelectric conversion element group 400, the photoelectric conversion element group 400 includes multiple photoelectric conversion elements 121 and multiple transfer transistors 131 corresponding one-to-one to the multiple photoelectric conversion elements 121, and the second source and drain regions SD2 of the multiple transfer transistors 131 are electrically connected to the same first conductive pad 140.

[0069] As an example, an embodiment of the present disclosure provides a method for forming a first substrate 100 .

[0070] See also Figure 7A, providing a first substrate 110 ; forming a photoelectric conversion layer 120 on the first substrate 110 , the photoelectric conversion layer 120 including a photoelectric conversion element 121 .

[0071] The first substrate 110 may be, for example, at least one of silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). The photoelectric conversion element 121 may be, for example, a photodiode.

[0072] In some embodiments, n-type doping can be performed in the p-type first substrate 110 to form an n-type doped region, thereby forming the photoelectric conversion element 121, and the depletion region of the photoelectric conversion element 121 is the contact region between the p-type first substrate 110 and the n-type doped region; or in other embodiments, p-type doping can be performed in the n-type first substrate 110 to form a p-type doped region, thereby forming the photoelectric conversion element 121, and the depletion region of the photoelectric conversion element 121 is the contact region between the n-type first substrate 110 and the p-type doped region.

[0073] In some embodiments, the cross section of each photoelectric conversion element 121 is a regular hexagon, and the plurality of photoelectric conversion units are arranged in a honeycomb pattern. Figure 5 .

[0074] See also Figure 7B A transfer transistor layer 130 is formed on the photoelectric conversion layer 120. The transfer transistor layer 130 includes a transfer transistor 131. In some embodiments, the transfer transistor 131 is formed using a method for forming a MOS transistor.

[0075] For example, if the transfer transistor 131 is a vertical channel transistor (VCT), the method for forming the transfer transistor 131 includes:

[0076] A semiconductor pillar 1310 is formed on the photoelectric conversion layer 120. The semiconductor pillar 1310 includes a first source / drain region SD1, a channel region CH, and a second source / drain region SD2, arranged in sequence along a first direction D1 perpendicular to the main surface of the first substrate 100. The first source / drain region SD1 is electrically connected to the n-type doped region or the p-type doped region of the photoelectric conversion element 121. In some embodiments, the semiconductor pillar 1310 may be doped to form the first source / drain region SD1 and the second source / drain region SD2. In some embodiments, a metal silicide layer is formed at the ends of the first source / drain region SD1 and the second source / drain region SD2, respectively, to reduce the contact resistance between the first source / drain region SD1 and the photoelectric conversion element 121, and between the second source / drain region SD2 and the first conductive interconnect structure 500. The step of forming the metal silicide layer on the second source / drain region SD2 may be performed after the step of forming the gate structure 1320.

[0077] A gate structure 1320 is formed on the outer sidewalls of the channel region CH of the semiconductor pillar 1310. The gate structure 1320 includes a gate dielectric layer covering the outer sidewalls of the channel region CH of the semiconductor pillar 1310 and a gate conductive layer covering the outer sidewalls of the gate dielectric layer.

[0078] See also Figure 7C A first conductive pad 140 is formed on the transfer transistor layer 130. The first conductive pad 140 is electrically connected to the second source-drain region SD2 of the transfer transistor 131.

[0079] In some embodiments, a first conductive interconnect structure 500 may be formed on the transfer transistor layer 130, and a first conductive pad 140 may be formed on the first conductive interconnect structure 500 to electrically connect the first conductive pad 140 to the second source / drain region SD2 of the transfer transistor 131. For example, a conductive interconnect structure layer 510 may be formed on the transfer transistor layer 130, with the first conductive interconnect structure 500 disposed therein. One end of the first conductive interconnect structure 500 is electrically connected to the second source / drain region SD2 of the transfer transistor 131, while the other end is exposed on the surface of the conductive interconnect structure layer 510. The first conductive pad 140 may be formed on the surface of the conductive interconnect structure layer 510, and the first conductive pad 140 is electrically connected to the other end of the first conductive interconnect structure 500.

[0080] See also Figure 6 and Figure 7D In step S61, a second substrate 200 is provided. The second substrate 200 includes a readout circuit 221 and a second conductive pad 230. The readout circuit 221 is electrically connected to the second conductive pad 230. In some embodiments, a logic circuit of a semiconductor structure is further provided in the second substrate 200.

[0081] As an example, an embodiment of the present disclosure provides a method for forming a second substrate 200 , including providing a second substrate 210 , forming a circuit layer 220 on the second substrate 210 , the circuit layer 220 including a readout circuit 221 , and forming a second conductive pad 230 on the circuit layer 220 .

[0082] The second substrate 210 is, for example, at least one of silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI).

[0083] In some embodiments, the second substrate 200 has at least one readout circuit 221 . Each readout circuit 221 is electrically connected to one second conductive pad 230 , and different readout circuits 221 are electrically connected to different second conductive pads 230 .

[0084] See also Figure 6 and Figure 7E In step S62 , the first substrate 100 and the second substrate 200 are bonded to form a bonding structure 300 between the first substrate 100 and the second substrate 200 . The bonding structure 300 connects the first substrate 100 and the second substrate 200 so that the first conductive pad 140 and the second conductive pad 230 are electrically connected.

[0085] In some embodiments, during the bonding process, the first conductive pad 140 and the second conductive pad 230 can be electrically connected using conductive solder. An insulating material can then be filled between the first substrate 100 and the second substrate 200 to support and further bond the first substrate 100 and the second substrate 200 and seal the conductive solder. The conductive solder includes, but is not limited to, solder and can serve as the conductive block 302 of the bonding structure 300. The insulating material includes, but is not limited to, epoxy resin and can serve as the insulator 301 of the bonding structure 300.

[0086] In some embodiments, after bonding the first substrate 100 to the second substrate 200, the step further includes thinning the second substrate 210 from the back side of the second substrate 210. After the thinning step, the readout circuit 211 is not exposed.

[0087] In some embodiments, the step of bonding the first substrate 100 to the second substrate 200 includes:

[0088] See also Figure 7F , thinning the first substrate 110 to expose the photoelectric conversion layer 120. In some embodiments, a portion of the first substrate 110 can be removed by a chemical mechanical polishing process to expose the photoelectric conversion layer 120.

[0089] In some embodiments, the photoelectric conversion layer 120 is segmented to form a plurality of photoelectric conversion element groups 400. Each photoelectric conversion element group 400 includes a plurality of photoelectric conversion elements 121 and a plurality of transfer transistors 131 corresponding one-to-one to the plurality of photoelectric conversion elements 121. All photoelectric conversion element groups 400 include the same number of photoelectric conversion elements 121. Insulating material is filled between the photoelectric conversion element groups.

[0090] See also Figure 1 A color filter array 800 and a microlens array 900 are formed on the photoelectric conversion layer 120. The color filter array 800 is arranged on the side of the photoelectric conversion element 121 away from the transfer transistor 131, and the microlens array 900 is arranged on the side of the color filter array 800 away from the photoelectric conversion element 121.

[0091] In some embodiments, before forming the color filter array 800 and the microlens array 900, the manufacturing method further includes forming an insulating isolation layer 810 on the photoelectric conversion layer 120, and forming the color filter array 800 on the insulating isolation layer 810. The insulating isolation layer 810 is used to insulate and isolate the color filter array 800 from the photoelectric conversion element 121.

[0092] In some embodiments, the color filter array 800 includes a plurality of filter units 801 arranged in an array, and one filter unit 801 corresponds to one or more photoelectric conversion elements 121 .

[0093] In some embodiments, in the step of forming the transfer transistor layer 130 on the photoelectric conversion layer 120, the second source-drain region SD2 of the transfer transistor 131 serves as the floating diffusion region FD, or, in the step of providing the second substrate 200, the second substrate 200 includes the floating diffusion region FD electrically connected to the second conductive pad 230. The photoelectric conversion element 121 receives light and generates photocharges. The transfer transistor 131 transfers the photocharges accumulated in the photoelectric conversion element 121 to the floating diffusion region FD, and the photocharges are read out by the readout circuit 221.

[0094] The semiconductor structure prepared by the method for preparing a semiconductor structure provided by the embodiment of the present disclosure increases the surface area of ​​the photoelectric conversion element 121 and improves the fill factor of the semiconductor structure.

[0095] The above is only a preferred embodiment of the present disclosure. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: A first substrate includes a photoelectric conversion element, a transfer transistor, and a first conductive pad, wherein the photoelectric conversion element is electrically connected to a first source-drain region of the transfer transistor, and the first conductive pad is electrically connected to a second source-drain region of the transfer transistor; a second substrate comprising a readout circuit and a second conductive pad, wherein the readout circuit is electrically connected to the second conductive pad; a bonding structure, disposed between the first substrate and the second substrate, and connecting the first substrate and the second substrate so that the first conductive pad is electrically connected to the second conductive pad; Wherein, the transfer transistor is a vertical channel transistor, and the vertical channel transistor includes: a semiconductor column comprising the first source-drain region, a channel region, and the second source-drain region sequentially arranged along a first direction perpendicular to a main surface of the first substrate; a gate structure, disposed on an outer sidewall of the channel region of the semiconductor column; The first substrate includes at least one photoelectric conversion element group, the photoelectric conversion element group includes multiple photoelectric conversion elements and multiple transfer transistors corresponding one-to-one to the multiple photoelectric conversion elements, and the second source and drain regions of the multiple transfer transistors are electrically connected to only one of the first conductive pads.

2. The semiconductor structure according to claim 1, wherein: The second source-drain region of the transfer transistor serves as a floating diffusion region; or, The second substrate includes a floating diffusion region electrically connected to the second conductive pad.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The cross section of each of the photoelectric conversion elements is a regular hexagon, and the plurality of photoelectric conversion elements are arranged in a honeycomb shape.

4. The semiconductor structure according to claim 1 or 2, characterized in that: The readout circuit comprises: a source follower transistor, wherein a gate of the source follower transistor is electrically connected to the second conductive pad, and a first source-drain region of the source follower transistor is electrically connected to a power supply terminal; A selection transistor is provided, wherein a first source-drain region of the selection transistor is electrically connected to a second source-drain region of the source follower transistor, and the second source-drain region of the selection transistor is electrically connected to an output terminal of the readout circuit.

5. The semiconductor structure according to claim 4, wherein: The readout circuit further includes a reset circuit, which includes a reset transistor. A first source-drain region of the reset transistor is electrically connected to a power supply terminal, and a second source-drain region of the reset transistor is electrically connected to the second conductive pad.

6. The semiconductor structure according to claim 5, wherein: The readout circuit also includes a dual conversion gain circuit, which includes a dual conversion gain transistor and a capacitor. The first source and drain regions of the dual conversion gain transistor are electrically connected to the second conductive pad, the second source and drain regions of the dual conversion gain transistor are electrically connected to the first plate of the capacitor, and the second plate of the capacitor is electrically connected to the power supply terminal.

7. The semiconductor structure according to claim 1 or 2, characterized in that: It also includes a color filter array and a microlens array. The color filter array is arranged on a side of the photoelectric conversion element away from the transfer transistor through an insulating isolation layer, and the microlens array is arranged on a side of the color filter away from the photoelectric conversion element.

8. An image sensor, characterized in that: Comprising the semiconductor structure according to any one of claims 1 to 7.

9. A method for preparing a semiconductor structure, characterized in that: include: Providing a first substrate, the first substrate comprising a photoelectric conversion element, a transfer transistor, and a first conductive pad, the photoelectric conversion element being electrically connected to a first source-drain region of the transfer transistor, and the first conductive pad being electrically connected to a second source-drain region of the transfer transistor; Providing a second substrate, the second substrate comprising a readout circuit and a second conductive pad, the readout circuit being electrically connected to the second conductive pad; Bonding the first substrate and the second substrate to form a bonding structure between the first substrate and the second substrate, wherein the bonding structure connects the first substrate and the second substrate so that the first conductive pad is electrically connected to the second conductive pad; Wherein, the transfer transistor is a vertical channel transistor, and the vertical channel transistor includes: a semiconductor column comprising the first source-drain region, a channel region, and the second source-drain region sequentially arranged along a first direction perpendicular to a main surface of the first substrate; a gate structure, disposed on an outer sidewall of the channel region of the semiconductor column; The first substrate includes at least one photoelectric conversion element group, the photoelectric conversion element group includes multiple photoelectric conversion elements and multiple transfer transistors corresponding one-to-one to the multiple photoelectric conversion elements, and the second source and drain regions of the multiple transfer transistors are electrically connected to only one of the first conductive pads.

10. The method for preparing a semiconductor structure according to claim 9, wherein: The method of forming the first substrate includes: providing a first substrate; forming a photoelectric conversion layer on the first substrate, wherein the photoelectric conversion layer includes the photoelectric conversion element; forming a transfer transistor layer on the photoelectric conversion layer, the transfer transistor layer including the transfer transistor; The first conductive pad is formed on the transfer transistor layer.

11. The method for preparing a semiconductor structure according to claim 10, wherein: In the step of forming a transfer transistor layer on the photoelectric conversion layer, the second source and drain region of the transfer transistor serves as a floating diffusion region, or, In the step of providing a second substrate, the second substrate includes a floating diffusion region electrically connected to the second conductive pad.

12. The method for preparing a semiconductor structure according to claim 10, wherein: The step of bonding the first substrate to the second substrate includes: removing the first substrate to expose the photoelectric conversion layer; A color filter array and a microlens array are formed on the photoelectric conversion layer. The color filter array is arranged on a side of the photoelectric conversion element away from the transfer transistor, and the microlens array is arranged on a side of the color filter away from the photoelectric conversion element.

13. The method for preparing a semiconductor structure according to claim 12, wherein: After the step of exposing the photoelectric conversion layer, the method further comprises: The photoelectric conversion layer is divided into a plurality of photoelectric conversion element groups, each of which includes a plurality of photoelectric conversion elements and a plurality of transfer transistors corresponding to the plurality of photoelectric conversion elements, and all the photoelectric conversion element groups include the same number of photoelectric conversion elements; forming an insulating isolation layer on the photoelectric conversion layer; The color filter array is formed on the insulating isolation layer.

Images