Topcon solar cell, preparation method thereof, photovoltaic module and photovoltaic system

Abstract

The embodiment of the application provides a kind of TOPCON solar cell and its preparation method, photovoltaic module, photovoltaic system, it is related to solar cell technical field.The preparation method includes: providing N-type silicon substrate, N-type silicon substrate has the texture structure;Form first tunneling oxide layer and first doped polysilicon layer in the front of N-type silicon substrate in turn, form second tunneling oxide layer and second doped polysilicon layer in the back of N-type silicon substrate in turn;On first doped polysilicon layer, using laser is scanned according to set pattern, forms silicon oxide layer;Remove the first doped polysilicon layer of laser non-scanning area;Form first passivation film layer in the front of N-type silicon substrate, form second passivation film layer on second doped polysilicon layer;Form front electrode in the front of N-type silicon substrate, form back electrode in the back of the N-type silicon substrate.The technical scheme of the embodiment of the application can reduce parasitic absorption loss, improve the open-circuit voltage and conversion efficiency of cell.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a TOPCON solar cell and a preparation method thereof, a photovoltaic module, and a photovoltaic system. Background Art

[0002] With the continuous development of solar cell technology, more and more photovoltaic manufacturers are beginning to deploy TOPCON (tunnel oxide passivated contact) cell technology. Traditional TOPCON solar cells use a tunnel oxide layer and a doped polysilicon layer on the back side for passivation contact. This passivation contact structure allows majority carriers to penetrate the tunnel oxide layer while blocking minority carriers, effectively achieving carrier selective transmission and significantly reducing surface recombination and metal-metal recombination in the cell.

[0003] Currently, some literature reports use a tunneling oxide layer and a doped polysilicon layer on the front of TOPCON solar cells to reduce metal recombination on the front side, thereby improving the conversion efficiency of TOPCON solar cells. However, the doped polysilicon layer has strong parasitic absorption on the front side, which to some extent limits the improvement of cell efficiency.

[0004] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Summary of the Invention

[0005] The embodiments of the present application provide a TOPCON solar cell and a preparation method thereof, a photovoltaic module, and a photovoltaic system to solve or alleviate one or more technical problems raised above.

[0006] A first aspect of an embodiment of the present application provides a method for preparing a TOPCON solar cell, comprising:

[0007] Providing an N-type silicon substrate, wherein the N-type silicon substrate has a textured structure;

[0008] forming a first tunneling oxide layer and a first doped polysilicon layer in sequence on the front surface of the N-type silicon substrate, and forming a second tunneling oxide layer and a second doped polysilicon layer in sequence on the back surface of the N-type silicon substrate;

[0009] Scanning the first doped polysilicon layer using a laser according to a set pattern to form a silicon oxide layer;

[0010] removing the first doped polysilicon layer in the area not scanned by the laser;

[0011] forming a first passivation film layer on the front surface of the N-type silicon substrate where the first doped polysilicon layer in the laser unscanned area is removed, and forming a second passivation film layer on the second doped polysilicon layer;

[0012] A front electrode is formed on the front surface of the N-type silicon substrate, and a back electrode is formed on the back surface of the N-type silicon substrate.

[0013] Optionally, when using a laser to scan according to a set pattern, the scanning speed of the laser is 300-500 mm / s, the laser power is 3-8 W, and the spot size is 60-120 um.

[0014] Optionally, the width of the set pattern is 80-150 um, and the set pattern is the same as the pattern of the front electrode.

[0015] Optionally, forming a first doped polysilicon layer on the front surface of the N-type silicon substrate includes:

[0016] depositing a first intrinsic amorphous silicon layer on the first tunnel oxide layer;

[0017] annealing the first intrinsic amorphous silicon layer to form a first polycrystalline silicon layer;

[0018] performing phosphorus diffusion processing on the first polysilicon layer to form the first doped polysilicon layer;

[0019] removing the phosphosilicate glass coated around the back and edge of the N-type silicon substrate;

[0020] Forming a second doped polysilicon layer on the back side of the N-type silicon substrate includes:

[0021] depositing a second intrinsic amorphous silicon layer on the second tunnel oxide layer;

[0022] annealing the second intrinsic amorphous silicon layer to form a second polysilicon layer;

[0023] performing a boron diffusion process on the second polysilicon layer to form a second doped polysilicon layer;

[0024] The borosilicate glass coated around the front surface and edge of the N-type silicon substrate is removed.

[0025] Optionally, removing the first doped polysilicon layer in the area not scanned by the laser comprises:

[0026] The first doped polysilicon layer in the laser unscanned area is removed by chemical cleaning, wherein the cleaning solution of the chemical cleaning method is a KOH solution with a volume fraction of 7-11%, the cleaning temperature is 35-45° C., and the cleaning time is 70-100 seconds.

[0027] Optionally, before the step of sequentially forming a second tunneling oxide layer and a second doped polysilicon layer on the back side of the N-type silicon substrate, the method further includes:

[0028] forming a mask layer on the front surface of the N-type silicon substrate;

[0029] The back side of the N-type silicon substrate is subjected to alkali polishing treatment.

[0030] Optionally, before the step of sequentially forming a first tunneling oxide layer and a first doped polysilicon layer on the front surface of the N-type silicon substrate, the method further includes:

[0031] The mask layer is removed.

[0032] Optionally, the thickness of the first tunnel oxide layer is 1-3 nm, and the thickness of the first doped polysilicon layer is 50-300 nm; and / or

[0033] The thickness of the second tunneling oxide layer is 1-3 nm, and the thickness of the second doped polysilicon layer is 50-300 nm; and / or

[0034] The thickness of the silicon oxide layer is 1-5 nm.

[0035] Optionally, forming a first passivation film layer on the front surface of the N-type silicon substrate where the first doped polysilicon layer in the laser unscanned area is removed comprises:

[0036] An aluminum oxide layer and a composite dielectric layer are sequentially formed on the front side of the N-type silicon substrate after removing the first doped polysilicon layer in the laser unscanned area. The first passivation film layer includes the aluminum oxide layer and the composite dielectric layer. The composite dielectric layer includes one or more of a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer.

[0037] Optionally, the thickness of the aluminum oxide layer is 4-10 nm; and / or

[0038] The thickness of the composite dielectric layer is 50-80 nm.

[0039] Optionally, the second passivation film layer includes one or more of a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer, and the thickness of the second passivation film layer is 60-90 nm.

[0040] A second aspect of the embodiments of the present application provides a TOPCON solar cell, which is prepared using the above-mentioned preparation method.

[0041] A third aspect of an embodiment of the present application provides a photovoltaic module, which includes the TOPCON solar cell described above.

[0042] A fourth aspect of an embodiment of the present application provides a photovoltaic system, comprising the photovoltaic assembly as described above.

[0043] The above technical solution adopted in the embodiments of the present application may have the following advantages:

[0044] When preparing a TOPCON solar cell, the above technical solution prepares a passivation contact structure formed by a tunneling oxide layer and a doped polysilicon layer on the front of the TOPCON solar cell, then removes the first doped polysilicon layer in the laser unscanned area (front non-gridline area), retaining the passivation contact structure in the laser scanned area (front gridline area), so that the front metal electrode of the prepared TOPCON solar cell does not directly contact the silicon substrate, reducing metal recombination. At the same time, by removing the first doped polysilicon layer in the laser unscanned area (front non-gridline area), parasitic absorption losses are not generated in areas outside the metallization, thereby improving the open circuit voltage and conversion efficiency of the battery. In addition, the above preparation method has a relatively simple process, requires little equipment investment, and is very suitable for mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0046] Figure 1 A flowchart of the steps of a method for preparing a TOPCON solar cell is provided in an embodiment of the present application.

[0047] Figure 2 A detailed flow chart of the steps of forming a first doped polysilicon layer on the front side of the N-type silicon substrate in an embodiment of the present application.

[0048] Figure 3 A detailed flow chart of the steps of forming a second doped polysilicon layer on the back side of the N-type silicon substrate in an embodiment of the present application.

[0049] Figure 4 Schematic diagram of the structure of the TOPCON solar cell provided in the embodiment of the present application.

[0050] Description of reference numerals:

[0051] 1. N-type silicon substrate; 2. First tunneling oxide layer; 3. First doped polysilicon layer; 4. Second tunneling oxide layer; 5. Second doped polysilicon; 6. First passivation film layer; 7. Second passivation film layer; 8. Front electrode; 9. Back electrode. DETAILED DESCRIPTION

[0052] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. In the accompanying drawings, the sizes of layers, regions, and elements and their relative sizes may be exaggerated for clarity. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be understood as limiting the present application. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other unless there is a conflict.

[0053] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that while the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another. Thus, without departing from the teachings of the present disclosure, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. Furthermore, when a second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present disclosure.

[0054] In this application, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0055] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way are interchangeable where appropriate, so that the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0056] In the present application, when it comes to a numerical interval (i.e., a numerical range), unless otherwise specified, the distribution of the optional numerical values ​​in the numerical interval is considered to be continuous, and includes the two numerical endpoints (i.e., the minimum and maximum values) of the numerical interval, and each numerical value between the two numerical endpoints. Unless otherwise specified, when the numerical interval only refers to an integer in the numerical interval, including the two endpoint integers of the numerical range, and each integer between the two endpoints, is equivalent to directly enumerating each integer. When multiple numerical ranges are provided to describe a feature or characteristic, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical range disclosed in this application should be understood to include any and all subranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, a percentage, a ratio, etc. "Numerical interval" allows broadly including quantitative intervals such as percentage intervals, ratio intervals, and ratio intervals.

[0057] Hereinafter, exemplary embodiments according to the present application will be described in more detail with reference to the accompanying drawings. It should be noted that these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0058] like Figure 1 As shown, the embodiment of the present application provides a method for preparing a TOPCON solar cell. The preparation method may include:

[0059] Step S10: providing an N-type silicon substrate having a textured structure.

[0060] In the embodiment of the present application, the provided N-type silicon substrate needs to undergo the following treatments: cleaning and texturing.

[0061] The purpose of the cleaning process is to clean the contaminants on the surface of the N-type silicon substrate. During cleaning, a wet chemical cleaning method can be used to clean the contaminants on the surface of the N-type silicon substrate.

[0062] The purpose of the texturing process is to form a velvet structure (also known as a light-trapping structure) on the surface of the N-type silicon substrate. This not only reduces the reflectivity of incident light on the solar cell surface, but also increases the effective optical path of light within the solar cell, increasing the number of internal reflections and thus reducing total reflection, thereby improving the cell's conversion efficiency.

[0063] In the embodiment of the present application, a textured structure can be formed on the surface of an N-type silicon substrate by mechanical grooving, chemical etching, plasma etching, etc. When forming the textured structure, the textured structure can be formed only on the front surface of the N-type silicon substrate, or can be formed on both the front and back surfaces of the N-type silicon substrate.

[0064] It should be noted that the front side of the N-type silicon substrate refers to the side of the TOPCON solar cell in the photovoltaic module facing the sun when the photovoltaic module is erected, and the back side of the N-type silicon substrate refers to the side of the TOPCON solar cell facing away from the sun.

[0065] As an example, the resistivity of the N-type silicon substrate is 0.4-1.6 Ω.cm (ohm.cm). During texturing, the N-type silicon substrate is textured using an alkaline solution (e.g., sodium hydroxide solution) and a texturing additive (e.g., isopropyl alcohol). After texturing, the thickness of a single side of the N-type silicon substrate is reduced to 1.5-3.0 μm (micrometers).

[0066] In step S11 , a first tunneling oxide layer and a first doped polysilicon layer are sequentially formed on the front surface of the N-type silicon substrate, and a second tunneling oxide layer and a second doped polysilicon layer are sequentially formed on the back surface of the N-type silicon substrate.

[0067] In the embodiment of the present application, the first tunnel oxide layer and the second tunnel oxide layer can be prepared by LPCVD (Low Pressure Chemical Vapor Deposition, low pressure chemical vapor deposition) method, PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition) method, PVD (Physical Vapor Deposition, physical vapor deposition) method, thermal oxidation method and the like.

[0068] The first doped polycrystalline silicon layer can first be prepared by low pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD), magnetron sputtering, RPD (reactive plasma deposition) method, ALD (atomic layer deposition) method and the like to obtain a first intrinsic amorphous silicon layer; thereafter, the first intrinsic amorphous silicon layer is further processed to obtain a first doped polycrystalline silicon layer.

[0069] The second doped polycrystalline silicon layer can first be prepared by low pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD), magnetron sputtering, RPD (reactive plasma deposition) method, ALD (atomic layer deposition) method and the like to obtain a second intrinsic amorphous silicon layer; thereafter, the second intrinsic amorphous silicon layer is further processed to obtain a second doped polycrystalline silicon layer.

[0070] As an example, when using LPCVD equipment to prepare the first tunneling oxide layer, the first intrinsic amorphous silicon layer, the second tunneling oxide layer, and the second intrinsic amorphous silicon layer, the LPCVD equipment can be used to simultaneously deposit the first tunneling oxide layer, the first intrinsic amorphous silicon layer, the second tunneling oxide layer, and the second intrinsic amorphous silicon layer on the front and back sides of the N-type silicon substrate. During the preparation process, the reaction gases used are silicon source gas (such as silane SiH4), nitrogen, and oxygen. The flow rate of the silane is 500-1800 sccm (standard cubic centimeters per minute), the flow rate of the nitrogen is 300-2000 sccm, and the flow rate of the oxygen is 100-1500 sccm. The set temperature is 570-650°C.

[0071] As another example, when other preparation methods (non-LPCVD method) are used to prepare the first tunneling oxide layer, the first intrinsic amorphous silicon layer, the second tunneling oxide layer and the second intrinsic amorphous silicon layer, the first tunneling oxide layer and the first intrinsic amorphous silicon layer can be prepared in sequence on the front side of the N-type silicon substrate, and then the second tunneling oxide layer and the second intrinsic amorphous silicon layer can be prepared in sequence on the back side of the N-type silicon substrate.

[0072] In one embodiment, the first doped polysilicon layer may be a P-type doped polysilicon layer, and correspondingly, the second doped polysilicon layer may be an N-type doped polysilicon layer.

[0073] In another embodiment, the first doped polysilicon layer may be an N-type doped polysilicon layer, and correspondingly, the second doped polysilicon layer may be a P-type doped polysilicon layer.

[0074] The doping elements for forming the P-type doped polysilicon layer may be boron, aluminum, gallium, etc. The doping elements for forming the N-type doped polysilicon layer may be phosphorus, arsenic, antimony, etc.

[0075] Step S12: Scanning the first doped polysilicon layer using a laser according to a set pattern to form a silicon oxide layer.

[0076] The set pattern is set according to actual conditions, and is preferably determined according to the pattern of the front electrode to be prepared subsequently, that is, the set pattern is preferably the same as the pattern of the front electrode to be prepared subsequently.

[0077] It should be noted that the set pattern may not be completely the same as the pattern of the front electrode.

[0078] In the embodiment of the present application, by setting the pattern to be identical to the pattern of the front electrode, a silicon oxide layer having the same pattern as the front electrode can be formed after the laser is scanned on the first doped polysilicon layer. In this way, after the first doped polysilicon layer in the area not scanned by the laser is subsequently removed, the passivation contact structure formed on the front of the TOPCON solar cell can be only present in the area corresponding to the front electrode, and no passivation contact structure is present in the area. This can effectively reduce the metal recombination in the front metallization area, thereby minimizing parasitic absorption losses and improving the open circuit voltage and conversion efficiency of the cell.

[0079] In the embodiment of the present application, the laser may be an ultraviolet nanosecond laser with a wavelength of 355 nm (nanometers).

[0080] In another embodiment, the laser may also be other lasers, as long as the laser wavelength meets a preset condition, and the preset condition may be that the laser wavelength is less than 532 nm.

[0081] In the embodiments of the present application, laser-induced oxidation is used to form the silicon oxide layer by scanning a laser according to a predetermined pattern, thereby protecting the underlying material. Specifically, when the laser is scanned according to the predetermined pattern, the energy of the laser beam is absorbed by the silicon material in the first doped polysilicon layer, causing the temperature of the local area to rise rapidly. When the temperature reaches the oxidation temperature of the silicon material, the surface of the silicon material chemically reacts with the surrounding oxygen to form a silicon oxide layer.

[0082] Step S13 , removing the first doped polysilicon layer in the area not scanned by the laser.

[0083] In the embodiment of the present application, the first doped polysilicon layer in the area not scanned by the laser can be removed by chemical cleaning.

[0084] In another embodiment, the first doped polysilicon layer in the area not scanned by the laser may be removed by ion beam etching, laser ablation or the like.

[0085] Step S14 , forming a first passivation film layer on the front surface of the N-type silicon substrate where the first doped polysilicon layer in the laser unscanned area is removed, and forming a second passivation film layer on the second doped polysilicon layer.

[0086] In an embodiment of the present application, after the removal operation of the first doped polysilicon layer in the laser unscanned area is completed, a first passivation film layer can be formed on the front surface of the N-type silicon substrate to achieve surface passivation and anti-reflection effects.

[0087] The first passivation film layer can be deposited on the front surface of the N-type silicon substrate by a PECVD method, a PVD method, an atomic layer deposition ALD method or the like.

[0088] The second passivation film layer serves as a back passivation layer, which can play the role of surface passivation and anti-reflection. The second passivation film layer can also be deposited on the back side of the N-type silicon substrate by methods such as PECVD, PVD or atomic layer deposition (ALD).

[0089] It should be noted that the order of preparing the first passivation film layer and the second passivation film layer is not limited in the embodiment of the present application. The first passivation film layer can be prepared first, and then the second passivation film layer is prepared; or the first passivation film layer can be prepared first, and then the second passivation film layer is prepared.

[0090] Step S15 , forming a front electrode on the front surface of the N-type silicon substrate, and forming a back electrode on the back surface of the N-type silicon substrate.

[0091] The front electrode can be prepared by thermal evaporation, screen printing, etc. The material of the front electrode includes but is not limited to gold (Au), silver (Ag), aluminum (Al), and copper (Cu).

[0092] The back electrode can also be prepared by thermal evaporation, screen printing, etc. The material of the back electrode includes but is not limited to gold (Au), silver (Ag), aluminum (Al), and copper (Cu).

[0093] As an example, by screen printing, metal grid lines are printed on the back side of the N-type silicon substrate to form a back electrode; and metal grid lines are printed on the front side of the N-type silicon substrate to form a front electrode.

[0094] In the embodiment of the present application, in order to improve the performance and reliability of the solar cell, a light injection process may be performed after the preparation of the electrode is completed, and after the light injection process is completed, the TOPCON solar cell is obtained.

[0095] In the embodiment of the present application, when preparing a TOPCON solar cell, after preparing a passivation contact structure formed by a tunneling oxide layer and a doped polysilicon layer on the front of the TOPCON solar cell, the first doped polysilicon layer in the laser unscanned area (the front non-gridline area) is removed, and the passivation contact structure in the laser scanned area (the front gridline area) is retained, so that the front metal electrode of the prepared TOPCON solar cell does not directly contact the silicon substrate, thereby reducing metal recombination. At the same time, by removing the first doped polysilicon layer in the laser unscanned area (the front non-gridline area), the area outside the metallization does not generate parasitic absorption losses, thereby improving the battery open circuit voltage and conversion efficiency. In addition, the above-mentioned preparation method has a relatively simple process flow, low equipment investment, and is very suitable for mass production.

[0096] In an optional embodiment, in order to achieve precise surface modification of the first doped polysilicon layer without damaging the TOPCON solar cell, the silicon oxide layer is formed. When a laser is used to scan according to a set pattern, the laser scanning speed is 300-500 mm / s (millimeters / second), the laser power is 3-8 W (watts), and the spot size is 60-120 μm (micrometers).

[0097] The scanning speed may be any value within the range of 300-500 mm / s, for example, 300 mm / s, 400 mm / s, 4500 mm / s, and 500 mm / s.

[0098] The laser power may be any value within the range of 3-8W, for example, 3W, 4W, 6W, or 8W.

[0099] The spot size can be any value within the range of 60-120um, for example, 60um, 80um, 100um, and 120um.

[0100] In an optional embodiment, in order to further reduce parasitic absorption generated in areas outside the metallization and improve the open circuit voltage and conversion efficiency of the battery, the width of the set pattern is 80-150um, and the set pattern is the same as the pattern of the front electrode.

[0101] The width of the set graphic can be any value within the range of 80-150um, for example, 80um, 100um, 120um, and 150um.

[0102] In an embodiment of the present application, by setting the width of the pattern to 80-150um and setting the pattern to be the same as the pattern of the front electrode, a silicon oxide layer having the same pattern as the front electrode can be formed after scanning by laser based on the set pattern, and the size is also slightly larger than the size of the front electrode, so that after subsequently removing the first doped polysilicon layer in the area not scanned by the laser, a passivation contact structure with the smallest possible area can be obtained, thereby increasing the area of ​​the area outside the metallization and reducing parasitic absorption losses.

[0103] In an alternative embodiment, see Figure 2 , forming a first doped polysilicon layer on the front surface of the N-type silicon substrate includes:

[0104] Step S20 , depositing a first intrinsic amorphous silicon layer on the first tunneling oxide layer.

[0105] Intrinsic amorphous silicon (ia-Si) is an amorphous silicon material that has no intentionally added dopants and is therefore neither a p-type nor an n-type semiconductor. The electrical conductivity of ia-Si is relatively low because it does not contain additional free carriers (electrons or holes).

[0106] In an embodiment of the present application, the first intrinsic amorphous silicon layer can be prepared by low-pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD), magnetron sputtering, RPD (reactive plasma deposition), ALD (atomic layer deposition) and other methods.

[0107] Step S21 , annealing the first intrinsic amorphous silicon layer to form a first polycrystalline silicon layer.

[0108] In the embodiment of the present application, by performing annealing on the first intrinsic amorphous silicon layer, the amorphous silicon layer undergoes a crystallization process, wherein the atoms of the amorphous silicon are rearranged to form a polycrystalline silicon structure.

[0109] It should be noted that the annealing temperature and annealing time have a significant impact on the crystallization rate and the final grain size. Therefore, during the annealing process, the annealing temperature and annealing time need to be reasonably controlled.

[0110] Step S22 , performing phosphorus diffusion treatment on the first polysilicon layer to form the first doped polysilicon layer.

[0111] In the embodiment of the present application, a low-pressure tube furnace may be used to perform phosphorus diffusion treatment on the first polysilicon layer to achieve phosphorus doping and form a phosphorus-doped polysilicon layer.

[0112] Step S23 , removing the phosphosilicate glass coated around the back and edge of the N-type silicon substrate.

[0113] In the embodiment of the present application, since a diffusion layer will be formed on the surface and periphery of the silicon wafer during the diffusion process, and the peripheral diffusion layer is prone to short circuit, and the surface diffusion layer will affect the subsequent passivation, after the phosphorus diffusion treatment is completed, the phosphorus silicon glass (BSG) coated on the back and edge of the N-type silicon substrate needs to be removed.

[0114] In the embodiment of the present application, chemical cleaning can be used to remove the phosphosilicate glass coated around the back and edge of the N-type silicon substrate. In one embodiment, when chemical cleaning is used to remove the phosphosilicate glass, HF (hydrofluoric acid) solution can be used to remove the phosphosilicate glass.

[0115] Accordingly, see Figure 3 , forming a second doped polysilicon layer on the back side of the N-type silicon substrate includes:

[0116] Step S30 , depositing a second intrinsic amorphous silicon layer on the second tunneling oxide layer.

[0117] In an embodiment of the present application, the second intrinsic amorphous silicon layer can also be prepared by low-pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD), magnetron sputtering, RPD (reactive plasma deposition), ALD (atomic layer deposition) and other methods.

[0118] It should be noted that the second intrinsic amorphous silicon layer and the first intrinsic amorphous silicon layer can be prepared simultaneously or separately.

[0119] Step S31 , annealing the second intrinsic amorphous silicon layer to form a second polysilicon layer.

[0120] In the embodiment of the present application, by performing annealing on the second intrinsic amorphous silicon layer, the amorphous silicon layer undergoes a crystallization process, wherein the atoms of the amorphous silicon are rearranged to form a polycrystalline silicon structure.

[0121] It should be noted that the annealing temperature and annealing time have a significant impact on the crystallization rate and the final grain size. Therefore, during the annealing process, the annealing temperature and annealing time need to be reasonably controlled.

[0122] Step S32 , performing boron diffusion treatment on the second polysilicon layer to form the second doped polysilicon layer.

[0123] In the embodiment of the present application, a tube furnace may be used to perform boron diffusion treatment on the second polysilicon layer to achieve boron doping and form a boron-doped polysilicon layer.

[0124] Step S33 , removing the borosilicate glass coated around the front surface and edges of the N-type silicon substrate.

[0125] In the embodiment of the present application, since a diffusion layer will be formed on the surface and periphery of the silicon wafer during the diffusion process, and the peripheral diffusion layer is prone to short circuit, and the surface diffusion layer will affect the subsequent passivation, after the boron diffusion treatment is completed, the borosilicate glass (PSG) coated on the front and edge of the N-type silicon substrate needs to be removed.

[0126] In the embodiment of the present application, a chemical cleaning method can be used to remove the phosphosilicate glass coated around the back and edges of the N-type silicon substrate. In one embodiment, when using a chemical cleaning method to remove the phosphosilicate glass, an HF (hydrofluoric acid) solution can be used to remove the borosilicate glass, or a mixed solution of HF and nitric acid (HNO3) can be used to remove the borosilicate glass.

[0127] The TOPCON solar cell prepared in the examples of this application adopts a back-junction cell structure. By placing the boron-doped polysilicon layer on the back of the cell, the boron-doped polysilicon layer can be prevented from growing on the velvet surface to produce large recombination. In addition, the low solid solubility of boron and the low hole mobility will result in a very high lateral resistance when the boron-doped polysilicon is used as the emitter, which in turn leads to a reduction in the fill factor. In contrast, the back-emitter structure is not very sensitive to the front lateral resistance. Therefore, the back-junction cell will have a higher cell conversion efficiency than the existing TOPCON solar cell using the positive junction cell structure.

[0128] In an optional embodiment, the removal of the first doped polysilicon layer in the area not scanned by the laser includes: removing the first doped polysilicon layer in the area not scanned by the laser by a chemical cleaning method, wherein the cleaning solution of the chemical cleaning method is a KOH solution with a volume fraction of 7-11%, the cleaning temperature is 35-45°C, and the cleaning time is 70-100 seconds.

[0129] The volume fraction of the KOH solution may be any value within the range of 7-11%, for example, 7%, 9%, 10%, or 11%.

[0130] The cleaning temperature may be any value within the range of 35-45°C, for example, 35°C, 38°C, 41°C, or 45°C.

[0131] The cleaning time may be any value within the range of 70-100 seconds, for example, 70 seconds, 80 seconds, 90 seconds, or 100 seconds.

[0132] In the embodiment of the present application, during chemical cleaning, a chain device may be used, and the N-type silicon substrate may be placed face down for cleaning.

[0133] In an embodiment of the present application, by controlling the cleaning process according to the above parameters during the cleaning process, the first doped polysilicon layer in the area not scanned by the laser can be completely removed, and the silicon oxide layer serving as a protective layer can be basically removed without removing the material protected by the silicon oxide layer serving as a protective layer.

[0134] In an optional embodiment, before the step of sequentially forming a second tunneling oxide layer and a second doped polysilicon layer on the back side of the N-type silicon substrate, the step further includes: forming a mask layer on the front side of the N-type silicon substrate; and performing alkali polishing on the back side of the N-type silicon substrate.

[0135] In the embodiment of the present application, the mask layer is used to perform alkali polishing on the back side of the N-type silicon substrate, thereby protecting the front side of the N-type silicon substrate.

[0136] The mask layer can be prepared by plasma enhanced chemical vapor deposition, thermal oxidation, ozone oxidation, or ultraviolet oxidation. The mask layer is made of silicon dioxide and has a thickness of 70-130 nm.

[0137] The thickness of the mask layer may be any value within the range of 70-130 nm, for example, 70 nm, 90 nm, 110 nm, or 130 nm.

[0138] In the embodiment of the present application, when performing alkaline polishing on the back side of the N-type silicon substrate, an alkaline solution can be used as a polishing agent to perform alkaline polishing on the back side of the N-type silicon substrate. The alkaline solution can be a strong alkaline solution such as sodium hydroxide or potassium hydroxide.

[0139] In one embodiment, in order to improve the polishing effect, an additive may be added during the alkali polishing process. The additive may be a photovoltaic wet process additive from Tuobang, such as Tuobang BP65.

[0140] As an example, after the back side of the N-type silicon substrate is subjected to alkali polishing treatment, the weight of the N-type silicon substrate is reduced by 0.15-0.30 g.

[0141] In the embodiment of the present application, a mask layer is formed on the front surface of the N-type silicon substrate before the alkali polishing treatment is performed, thereby protecting the front surface of the N-type silicon substrate.

[0142] In an optional embodiment, before the step of sequentially forming a first tunneling oxide layer and a first doped polysilicon layer on the front surface of the N-type silicon substrate, the step further includes: removing the mask layer.

[0143] In the embodiment of the present application, an HF solution may be used to remove the mask layer.

[0144] In the embodiment of the present application, before sequentially forming the first tunneling oxide layer and the first doped polysilicon layer on the front surface of the N-type silicon substrate, the mask layer serving as a protective layer is removed, thereby preventing the mask layer from affecting the performance of the TOPCON solar cell.

[0145] In an optional embodiment, the thickness of the first tunneling oxide layer is 1-3 nm, and the thickness of the first doped polysilicon layer is 50-300 nm.

[0146] The thickness of the first tunnel oxide layer includes any value within the thickness range, such as 1 nm, 2 nm, 2.5 nm, and 3 nm.

[0147] The thickness of the first doped polysilicon layer includes any value within the thickness range, for example, 50 nm, 150 nm, 200 nm, and 300 nm.

[0148] In the embodiment of the present application, by using high-quality ultra-thin silicon oxide (1-3nm) and a doped polysilicon layer of appropriate thickness (50-300nm) on the front of the battery, efficient passivation and selective carrier collection of the front are achieved, thereby improving battery performance.

[0149] In an optional embodiment, the thickness of the second tunneling oxide layer is 1-3 nm, and the thickness of the second doped polysilicon layer is 50-300 nm.

[0150] The thickness of the second tunnel oxide layer includes any value within the thickness range, such as 1 nm, 2 nm, 2.5 nm, and 3 nm.

[0151] The thickness of the second doped polysilicon layer includes any value within the thickness range, for example, 50 nm, 150 nm, 200 nm, and 300 nm.

[0152] In the embodiment of the present application, by using high-quality ultra-thin silicon oxide (1-3nm) and a doped polysilicon layer of appropriate thickness (50-300nm) on the back of the battery, efficient passivation and selective carrier collection of the back are achieved, thereby improving battery performance.

[0153] In an optional embodiment, the thickness of the silicon oxide layer is 1-5 nm.

[0154] The thickness of the silicon oxide layer includes any value within the thickness range, such as 1 nm, 3 nm, 4 nm, and 5 nm.

[0155] In an embodiment of the present application, by setting the thickness of the silicon oxide layer to 1-5 nm, the thickness of the silicon oxide layer formed by the laser-induced oxidation technology of the first doped polysilicon layer can be reduced as much as possible while ensuring the protection of the material under the silicon oxide layer, thereby improving the battery performance.

[0156] In an optional embodiment, the forming of a first passivation film layer on the front side of the N-type silicon substrate from which the first doped polysilicon layer in the laser unscanned area is removed includes: sequentially forming an aluminum oxide layer and a composite dielectric layer on the front side of the N-type silicon substrate from which the first doped polysilicon layer in the laser unscanned area is removed, the first passivation film layer including the aluminum oxide layer and the composite dielectric layer, and the composite dielectric layer including one or more of a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer.

[0157] In an embodiment of the present application, after removing the first doped polysilicon layer in the laser unscanned area, an ALD device can be used to coat an Al2O3 layer (aluminum oxide layer) on the surface of the silicon wafer to improve the passivation and impurity absorption effect of the silicon wafer surface.

[0158] In another embodiment, the aluminum oxide layer may be prepared by plasma-assisted ALD, pyrolysis deposition, delocalized PECVD, molecular beam epitaxy, or the like.

[0159] After the aluminum oxide layer is prepared, a composite dielectric layer may be deposited on the aluminum oxide layer using PECVD equipment as an anti-reflection film layer.

[0160] In another embodiment, the composite dielectric layer may be prepared by using methods such as low pressure chemical vapor deposition (LPCVD) and atomic layer deposition (ALD).

[0161] It should be noted that the aluminum oxide layer and the composite dielectric layer can be a single layer or a multilayer.

[0162] In the embodiment of the present application, the first passivation film layer is composed of an aluminum oxide layer and a composite dielectric layer, so that the passivation effect of the first passivation film layer can be improved.

[0163] In an optional embodiment, the thickness of the aluminum oxide layer is 4-10 nm.

[0164] The thickness of the aluminum oxide layer includes any value within the thickness range, such as 4 nm, 6 nm, 8 nm, and 10 nm.

[0165] In this embodiment, by setting the thickness of the aluminum oxide layer to 4-10 nm, the cost of raw materials can be saved while meeting the photoelectric conversion efficiency of the battery.

[0166] In an optional embodiment, the thickness of the composite dielectric layer is 50-80 nm.

[0167] The thickness of the composite dielectric layer includes any value within the thickness range, for example, 50 nm, 60 nm, 70 nm, and 80 nm.

[0168] In this embodiment, by setting the thickness of the composite dielectric layer to 50-80 nm, the cost of raw materials can be saved while satisfying the photoelectric conversion efficiency of the battery.

[0169] In an optional embodiment, the second passivation film layer includes one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, and the thickness of the second passivation film layer is 60-90 nm.

[0170] The thickness of the second passivation film layer includes any value within the thickness range, for example, 60 nm, 70 nm, 80 nm, and 90 nm.

[0171] In this embodiment, by setting the thickness of the second passivation film layer to 60-90 nm, the cost of raw materials can be saved while meeting the photoelectric conversion efficiency of the battery.

[0172] See Figure 4 The embodiment of the present application also provides a TOPCON solar cell, which includes an N-type silicon substrate 1, a first tunneling oxide layer 2, a first doped polysilicon layer 3, a second tunneling oxide layer 4, a second doped polysilicon 5, a first passivation film layer 6, a second passivation film layer 7, a front electrode 8 and a back electrode 9.

[0173] The TOPCON solar cell is prepared by the above-mentioned method for preparing a TOPCON solar cell.

[0174] The following TOPCON solar cells prepared by the preparation methods of the TOPCON solar cells provided in the following embodiments and the TOPCON solar cells of the relevant comparative examples are subjected to performance tests to obtain the short-circuit current Isc, open-circuit voltage Voc, fill factor FF, and photoelectric conversion efficiency PCE of the corresponding battery devices. The test results are shown in Table 1.

[0175] [Example 1]

[0176] A specific preparation method of a TOPCON solar cell is:

[0177] Step 1: Select an N-type silicon wafer and perform texturing on it using an alkaline solution and a texturing additive to obtain an N-type silicon substrate with a texturing structure. The N-type silicon has a resistivity of 0.8Ω.cm, a size of 210*210mm, and a thickness of 130um. After texturing, the single-sided thinning thickness of the N-type silicon wafer is 2.6um.

[0178] Step 2: A mask layer is deposited on the front surface of the N-type silicon substrate using a plasma enhanced chemical vapor deposition (PECVD) method. The mask layer is made of silicon dioxide and has a thickness of 90 nm.

[0179] Step 3: Perform alkali polishing on the back side of the N-type silicon substrate. During the alkali polishing, an alkali solution and an additive (Tuobang BP65) are used for alkali polishing. The N-type silicon substrate loses 0.17 g in weight after alkali polishing.

[0180] Step 4: After the alkaline polishing is completed, the front mask layer is removed using HF solution.

[0181] Step 5: Using LPCVD equipment, a tunneling oxide layer and an intrinsic amorphous silicon layer are simultaneously deposited on the front and back sides of the N-type silicon substrate. During the deposition process, a silane flow rate of 1300 sccm, a nitrogen flow rate of 1200 sccm, and an oxygen flow rate of 900 sccm are used. The temperature is set to 585° C. After the deposition is completed, the thickness of the tunneling oxide layer is 1.8 nm, and the thickness of the intrinsic amorphous silicon layer is 120 nm.

[0182] Step 6: After the tunnel oxide layer and intrinsic amorphous silicon layer are deposited on the front and back sides, the intrinsic amorphous silicon layer on the front side is annealed to form a polysilicon layer. Then, a low-pressure tube furnace is used to diffuse phosphorus into the polysilicon layer on the front side to form a phosphorus-doped polysilicon layer. Finally, an HF solution is used to remove the phosphorus-silicate glass coated on the back side and the edge.

[0183] Step 7: Anneal the intrinsic amorphous silicon layer on the back to form a polysilicon layer. Then, use a tube furnace to diffuse boron into the polysilicon layer on the back to form a boron-doped polysilicon layer. Finally, use HF solution to remove the borosilicate glass coated on the front and edges.

[0184] Step 8: Use a laser to scan the front of the N-type silicon substrate according to the set pattern to form a silicon oxide layer. Use an ultraviolet nanosecond laser with a wavelength of 355nm, a laser scanning speed of 420mm / s, a laser power of 6W, a spot size of 60um, and a pattern width of 120um.

[0185] Step 9: Use a KOH solution with a volume fraction of 8% to clean and remove the phosphorus-doped polysilicon layer in the area not scanned by the laser. The temperature is controlled at 42° C. and the cleaning time is 85 seconds.

[0186] Step 10: Deposit a first passivation film layer on the front surface of the N-type silicon substrate, including an aluminum oxide layer and a composite dielectric layer, wherein the composite dielectric layer includes a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer, the thickness of the aluminum oxide layer is 6 nm, and the thickness of the composite dielectric layer is 72 nm.

[0187] Step 11: Deposit a second passivation film layer on the back side of the N-type silicon substrate, including a silicon nitride layer and a silicon oxynitride layer, with a thickness of 83 nm.

[0188] Step 12: Print a metal electrode on the back side through screen printing to form a back electrode; and print a metal electrode on the front side to form a front electrode.

[0189] Step 13: Perform light injection processing to obtain a TOPCON solar cell, wherein the light injection intensity is 7000W / m 2 (Watts / m2), the temperature is 65℃.

[0190] [Example 2]

[0191] The TOPCON solar cell of Example 2 was prepared with reference to the preparation method of Example 1, except that step 6 of Example 2 was replaced by: after the tunneling oxide layer and the intrinsic amorphous silicon layer were deposited on the front and back sides, the intrinsic amorphous silicon layer on the front side was annealed to form a polycrystalline silicon layer, and then, boron was diffused into the polycrystalline silicon layer on the front side using a tube furnace to form a boron-doped polycrystalline silicon layer, and finally, an HF solution was used to remove the borosilicate glass coated around the back side and the edge. Step 7 of Example 2 was replaced by: annealing the intrinsic amorphous silicon layer on the back side to form a polycrystalline silicon layer, and then, phosphorus was diffused into the polycrystalline silicon layer on the back side using a low-pressure tube furnace to form a phosphorus-doped polycrystalline silicon layer, and finally, an HF solution was used to remove the phosphorus-silicon glass coated around the back side and the edge.

[0192] [Example 3]

[0193] The TOPCON solar cell of Example 3 was prepared by referring to the preparation method of Example 1, except that the width of the pattern in step 8 of Example 3 was 100 μm.

[0194] [Example 4]

[0195] The TOPCON solar cell of Example 3 was prepared by referring to the preparation method of Example 1, except that the width of the pattern in step 8 of Example 4 was 150 μm.

[0196] [Example 5]

[0197] The TOPCON solar cell of Example 5 was prepared by referring to the preparation method of Example 1, except that the width of the pattern in step 8 of Example 5 was 80 μm.

[0198] [Example 6]

[0199] The TOPCON solar cell of Example 6 was prepared by referring to the preparation method of Example 1, except that the width of the pattern in step 8 of Example 6 was 180 μm.

[0200] [Example 7]

[0201] The TOPCON solar cell of Example 7 was prepared by referring to the preparation method of Example 1, except that the cleaning time in step 9 of Example 7 was 70 seconds.

[0202] [Example 8]

[0203] The TOPCON solar cell of Example 8 was prepared by referring to the preparation method of Example 1, except that the cleaning time in step 9 of Example 8 was 100 seconds.

[0204] [Example 9]

[0205] The TOPCON solar cell of Example 9 was prepared by referring to the preparation method of Example 1, except that the cleaning time in step 9 of Example 9 was 50 seconds.

[0206] [Example 10]

[0207] The TOPCON solar cell of Example 10 was prepared by referring to the preparation method of Example 1, except that the cleaning time in step 9 of Example 10 was 120 seconds.

[0208] [Comparative Example 1]

[0209] A TOPCON solar cell of Comparative Example 1 was prepared by referring to the preparation method of Example 2, except that a tunneling oxide layer and a doped polysilicon layer were formed only on the back surface, and no tunneling oxide layer and a doped polysilicon layer were formed on the front surface.

[0210] [Comparative Example 2]

[0211] The TOPCON solar cell of Comparative Example 2 was prepared by referring to the preparation method of Example 2, except that Step 8 and Step 9 were omitted.

[0212] Table 1: Test results of battery devices

[0213]

[0214] By comparing the data of Examples 1-10 and Comparative Examples 1-2 in Table 1, it can be seen that the TOPCON solar cell prepared by the preparation method of the TOPCON solar cell in the electrical properties of the present application has better battery performance than the TOPCON solar cell prepared by the prior art. In addition, by comparing the data of Example 1, Examples 3-5 and Example 6, it can be seen that when preparing the TOPCON solar cell, when the pattern width is set to 80-150um, the TOPCON solar cell prepared has better battery performance than when the pattern width is set to greater than 150um. In addition, by comparing the data of Example 1, Examples 7-8 and Examples 9-10, it can be seen that when preparing the TOPCON solar cell, when the cleaning time is set to 70-100 seconds, the TOPCON solar cell prepared has better battery performance than when the cleaning time is set to less than 70 seconds or greater than 100 seconds.

[0215] The present application also provides a photovoltaic module (not shown) comprising a plurality of solar cells connected in series and / or in parallel, wherein at least one of the plurality of solar cells connected in series and / or in parallel is a TOPCON solar cell as described above. The plurality of solar cells connected in series form a cell string, and adjacent solar cells can be connected together by string welding.

[0216] The embodiments of the present application can provide a photovoltaic system, including the photovoltaic components in any of the above embodiments. The advantages of the above photovoltaic components are also possessed by the photovoltaic system, which will not be repeated here. The application field of the above photovoltaic system is wide, not only limited to photovoltaic power stations, such as ground power stations, rooftop power stations and water surface power stations, but also includes various equipment and devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars and solar buildings. Of course, it is understandable that the application scenarios of the photovoltaic system are not limited to this, that is, the photovoltaic system can be used in all fields that require solar energy to generate electricity. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array can be an array combination of multiple photovoltaic components. For example, multiple photovoltaic components can form multiple photovoltaic arrays. The photovoltaic array is connected to the junction box. The junction box can merge the current generated by the photovoltaic array. The merged current flows through the inverter to convert it into the alternating current required by the mains power grid and then connects to the mains power network to achieve solar power supply.

[0217] It should be noted that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are only for the convenience of describing the present application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present application. The directional terms "inside" and "outside" refer to the inside and outside relative to the outline of the component itself. For example, if the device in the drawing is inverted, the device described as "above other devices or structures" or "on top of other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Therefore, the exemplary term "above..." can include both "above..." and "below..." orientations. The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used here will be interpreted accordingly.

[0218] It should also be noted that references to "one embodiment," "another embodiment," "an embodiment," etc., in this application refer to specific features, structures, or characteristics described in conjunction with that embodiment as included in at least one embodiment generally described in this application. The appearance of the same expression in multiple places in the specification does not necessarily refer to the same embodiment. Furthermore, when a specific feature, structure, or characteristic is described in conjunction with any embodiment, it is intended that such feature, structure, or characteristic, when implemented in conjunction with other embodiments, also fall within the scope of this application.

[0219] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0220] It should also be noted that the above are only preferred embodiments of the present application and do not limit the scope of patent protection of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the scope of patent protection of the present application.

Claims

1. A method for preparing a TOPCON solar cell, characterized in that: include: Providing an N-type silicon substrate, wherein the N-type silicon substrate has a textured structure; forming a first tunneling oxide layer and a first doped polysilicon layer in sequence on the front surface of the N-type silicon substrate, and forming a second tunneling oxide layer and a second doped polysilicon layer in sequence on the back surface of the N-type silicon substrate; Scanning the first doped polysilicon layer using a laser according to a set pattern to form a silicon oxide layer; removing the first doped polysilicon layer in the area not scanned by the laser; forming a first passivation film layer on the front surface of the N-type silicon substrate where the first doped polysilicon layer in the laser unscanned area is removed, and forming a second passivation film layer on the second doped polysilicon layer; A front electrode is formed on the front surface of the N-type silicon substrate, and a back electrode is formed on the back surface of the N-type silicon substrate.

2. The preparation method according to claim 1, characterized in that When using laser to scan according to the set pattern, the scanning speed of the laser is 300-500 mm / s, the laser power is 3-8 W, and the spot size is 60-120 um.

3. The preparation method according to claim 2, characterized in that The width of the set pattern is 80-150 μm, and the set pattern is the same as the pattern of the front electrode.

4. The preparation method according to any one of claims 1 to 3, characterized in that Forming a first doped polysilicon layer on the front surface of the N-type silicon substrate includes: depositing a first intrinsic amorphous silicon layer on the first tunnel oxide layer; annealing the first intrinsic amorphous silicon layer to form a first polycrystalline silicon layer; performing phosphorus diffusion processing on the first polysilicon layer to form the first doped polysilicon layer; removing the phosphosilicate glass coated around the back and edge of the N-type silicon substrate; Forming a second doped polysilicon layer on the back side of the N-type silicon substrate includes: depositing a second intrinsic amorphous silicon layer on the second tunnel oxide layer; annealing the second intrinsic amorphous silicon layer to form a second polysilicon layer; performing a boron diffusion process on the second polysilicon layer to form a second doped polysilicon layer; The borosilicate glass coated around the front surface and edge of the N-type silicon substrate is removed.

5. The preparation method according to any one of claims 1 to 3, characterized in that The step of removing the first doped polysilicon layer in the area not scanned by the laser comprises: The first doped polysilicon layer in the laser unscanned area is removed by chemical cleaning, wherein the cleaning solution of the chemical cleaning method is a KOH solution with a volume fraction of 7-11%, the cleaning temperature is 35-45° C., and the cleaning time is 70-100 seconds.

6. The preparation method according to any one of claims 1 to 3, characterized in that Before the step of sequentially forming a second tunneling oxide layer and a second doped polysilicon layer on the back side of the N-type silicon substrate, the method further includes: forming a mask layer on the front surface of the N-type silicon substrate; The back side of the N-type silicon substrate is subjected to alkali polishing treatment.

7. The preparation method according to claim 6, characterized in that Before the step of sequentially forming a first tunneling oxide layer and a first doped polysilicon layer on the front surface of the N-type silicon substrate, the method further includes: The mask layer is removed.

8. The preparation method according to claim 1, characterized in that The thickness of the first tunneling oxide layer is 1-3 nm, and the thickness of the first doped polysilicon layer is 50-300 nm; and / or The thickness of the second tunneling oxide layer is 1-3 nm, and the thickness of the second doped polysilicon layer is 50-300 nm; and / or The thickness of the silicon oxide layer is 1-5 nm.

9. The preparation method according to claim 1, characterized in that The forming of a first passivation film layer on the front surface of the N-type silicon substrate after removing the first doped polysilicon layer in the laser unscanned area comprises: An aluminum oxide layer and a composite dielectric layer are sequentially formed on the front side of the N-type silicon substrate after removing the first doped polysilicon layer in the laser unscanned area. The first passivation film layer includes the aluminum oxide layer and the composite dielectric layer. The composite dielectric layer includes one or more of a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer.

10. The preparation method according to claim 9, characterized in that The thickness of the aluminum oxide layer is 4-10 nm; and / or The thickness of the composite dielectric layer is 50-80 nm.

11. The preparation method according to claim 1, characterized in that The second passivation film layer includes one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, and the thickness of the second passivation film layer is 60-90 nm.

12. A TOPCON solar cell, characterized in that: The invention is prepared by the preparation method according to any one of claims 1 to 11.

13. A photovoltaic module, characterized in that: The photovoltaic module includes the TOPCON solar cell according to claim 12 .

14. A photovoltaic system, characterized in that: The photovoltaic system includes the photovoltaic assembly according to claim 13.

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