Micro-optoelectronic chips, their manufacturing methods and applications

Abstract

This invention discloses a micro optoelectronic chip, its manufacturing method, and its application. The micro optoelectronic chip includes: a semiconductor structure layer comprising a first doped semiconductor layer, an active layer, and a second doped semiconductor layer sequentially stacked on a substrate; ion implantation regions distributed within the semiconductor structure layer for electrically isolating multiple optoelectronic chip structures arranged in an array within the semiconductor structure layer; isolation trenches formed within corresponding ion implantation regions, serving at least to isolate the second doped semiconductor layers of any two adjacent optoelectronic chip structures from each other; and a light-blocking structure disposed within the isolation trenches, serving at least to prevent light from propagating through the second doped semiconductor layers between any two adjacent optoelectronic chip structures. This invention can effectively eliminate optical crosstalk problems within the micro optoelectronic chip array, giving it excellent photoelectric conversion efficiency and display effect.

Description

Technical Field

[0001] This invention relates to a semiconductor optoelectronic device, specifically to a micro optoelectronic chip and its manufacturing method and application, belonging to the field of semiconductor device fabrication technology. Background Technology

[0002] Micro-LED is an ideal new micro-display technology. Through flip-chip or wafer-level bonding technology, Micro-LED arrays can be combined with active-matrix silicon display drivers to form self-emissive Micro-LED micro-display chips with high luminous efficiency and superior color performance. Compared to LCDs, self-emissive Micro-LED micro-display chips do not require backlighting, thus eliminating the need for various focusing and projection optical components, significantly reducing the size of the optical engine. Simultaneously, each Micro-LED pixel is independently switched, resulting in significantly improved luminous efficiency and dynamic contrast. Compared to OLEDs made of organic materials, gallium nitride (GaN) Micro-LEDs, made of inorganic materials, have a wider operating temperature range, can withstand higher current densities, and can achieve brightness levels of up to one million nits, tens to hundreds of times brighter than OLEDs, making them suitable for specialized applications or defense and military applications.

[0003] The current mainstream technology route for Micro-LED is to first use semiconductor micro-nano fabrication techniques such as dry etching (e.g., RIE, ECR, ICP) to fabricate Micro-LED chips of tens of micrometers or even smaller sizes based on conventional LEDs, and then combine this with mass parallel transfer technology or arraysmonolithic integration technology to achieve RGB full-color image display. However, the dry etching process leaves sidewalls at the edges of the Micro-LED chip. At the same time, high-energy etching particles bombard the material lattice and form defect dangling bonds on the material surface. Etching particles can also be injected into the material, causing sidewall damage, and the damage effect can extend several micrometers into the chip. The existence of these damages means that there are a large number of defect energy levels in the edge region of the Micro-LED chip, and dangling bonds mean increased leakage paths for charge carriers. This is unacceptable for obtaining Micro-LED micro-display devices with better optical and electrical properties. Specifically, these defects and damages significantly reduce the quantum efficiency and usable area of ​​Micro-LED devices. For example, sidewall damage results in a usable area of ​​only about 4% of the total size of a 5 μm × 5 μm Micro-LED chip. Simultaneously, sidewall damage defects form deep levels within the material, acting as nonradiative recombination centers, greatly increasing the nonradiative recombination rate and causing the peak luminous efficiency of Micro-LEDs to typically fall below 10%. Furthermore, severe optical crosstalk exists between etched Micro-LED chips, significantly impacting the micro-display effect during use. For instance, the emission of one Micro-LED pixel may cause adjacent Micro-LEDs to emit light. When a black background is required around an emitting pixel to improve contrast, the contrast of the micro-display is greatly reduced due to optical crosstalk. Moreover, the dispersion of light transport caused by optical crosstalk also significantly reduces the brightness of local Micro-LEDs.

[0004] In recent years, researchers have discovered that ion implantation isolation offers the potential to miniaturize LED light-emitting areas while effectively avoiding performance degradation caused by sidewall damage during etching processes. It also reduces the impact of trench structures on fabrication costs and potential yield rates, and promises advantages such as planarization. However, ion implantation isolation also has significant drawbacks in micro-LED array fabrication. For example, ion implantation cannot achieve true optical isolation, hindering the reduction of optical crosstalk between micro-LED devices and impacting the final display performance. Especially as micro-LED chip size and spacing decrease, the ion implantation area must also shrink accordingly. Lateral beam spread exacerbates crosstalk between adjacent micro-LED chips, further reducing color uniformity and resolution. Summary of the Invention

[0005] The main objective of this invention is to provide a micro optoelectronic chip, its manufacturing method, and its application, in order to overcome the shortcomings of the prior art.

[0006] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:

[0007] One aspect of the present invention provides a micro optoelectronic chip comprising:

[0008] Substrate;

[0009] A semiconductor structure layer disposed on the substrate, the semiconductor structure layer comprising a first doped semiconductor layer, an active layer and a second doped semiconductor layer sequentially stacked on the substrate;

[0010] Ion implantation regions and isolation trenches are distributed within the semiconductor structure layer. The ion implantation regions are used to electrically isolate multiple optoelectronic chip structures arranged in an array within the semiconductor structure layer.

[0011] An isolation trench is formed within the ion implantation region, the isolation trench being used at least to isolate the second doped semiconductor layers of any two adjacent optoelectronic chip structures from each other;

[0012] The light-blocking structure disposed within the isolation trench is at least used to prevent light from being transmitted between any two adjacent optoelectronic chip structures through the second doped semiconductor layer.

[0013] Another aspect of the present invention provides a method for fabricating a micro optoelectronic chip, comprising:

[0014] A semiconductor structure layer is formed on a substrate, the semiconductor structure layer comprising a first doped semiconductor layer, an active layer and a second doped semiconductor layer sequentially stacked on the substrate;

[0015] Ion implantation is performed on the semiconductor structure layer to form an ion implantation region within the semiconductor structure layer, thereby electrically isolating multiple optoelectronic chip structures arranged in an array within the semiconductor structure layer.

[0016] The ion implantation region is etched to form an isolation trench within the ion implantation region, thereby isolating the second doped semiconductor layers of at least two adjacent optoelectronic chip structures from each other.

[0017] A light-blocking structure is provided within the isolation trench to at least prevent light from transmitting between any two adjacent optoelectronic chip structures through the second doped semiconductor layer.

[0018] Another aspect of the present invention provides the use of the micro optoelectronic chip in the fabrication of optoelectronic devices, including but not limited to display devices, microdisplay devices, etc.

[0019] Compared with the prior art, the technical solution of the present invention realizes the fabrication of micro optoelectronic chip arrays through ion implantation, and at the same time eliminates the optical crosstalk problem between chips in the array, so that the micro optoelectronic chip array has both excellent photoelectric conversion efficiency and display effect. Attached Figure Description

[0020] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0021] Figure 1 This is a schematic diagram of a Micro-LED chip in Example 1;

[0022] Figure 2 This is a schematic diagram of the epitaxial wafer structure of a Micro-LED chip in Example 1;

[0023] Figure 3 Yes Figure 2 A schematic diagram of the device formed after ion implantation of the epitaxial wafer is shown.

[0024] Figure 4 Yes Figure 3 A schematic diagram of the device structure formed after etching and trenching the ion implantation region of the device shown.

[0025] Figure 5 Is Figure 4A schematic diagram of the structure of the device formed by filling the isolation groove with a light-blocking structure.

[0026] Figure 6 This is a schematic diagram of a Micro-LED chip in Example 3;

[0027] Figure 7 yes Figure 6 A magnified view of a portion of region A in the middle;

[0028] Figure 8 This is a test diagram of the reflectance of a dielectric layer for different wavelengths of light in Example 3;

[0029] Figure 9 This is a test diagram of the reflectivity of a dielectric layer for different wavelengths of light in Example 4;

[0030] Figure 10 This is a test diagram of the reflectivity of a dielectric layer for different wavelengths of light in Example 5. Detailed Implementation

[0031] In view of the sidewall damage and other problems existing in the formation of micro-optoelectronic chip arrays using traditional etching processes, and the optical crosstalk and other defects existing in the formation of micro-optoelectronic chip arrays using ion implantation isolation methods, the inventors, through long-term research and practice, have proposed the technical solution of this invention to reduce the impact of optical crosstalk that may affect the final display effect, while maintaining the advantage of ion implantation isolation in improving electro-optical conversion efficiency, thereby improving the photoelectric performance of the micro-optoelectronic chip array and optimizing its display effect. The technical solution of this invention will be further described in detail below.

[0032] Some embodiments of the present invention provide a micro optoelectronic chip comprising:

[0033] Substrate;

[0034] A semiconductor structure layer disposed on the substrate, the semiconductor structure layer comprising a first doped semiconductor layer, an active layer and a second doped semiconductor layer sequentially stacked on the substrate;

[0035] Ion implantation regions and isolation trenches are distributed within the semiconductor structure layer. The ion implantation regions are used to electrically isolate multiple optoelectronic chip structures arranged in an array within the semiconductor structure layer.

[0036] An isolation trench is formed within the ion implantation region, the isolation trench being used at least to isolate the second doped semiconductor layers of any two adjacent optoelectronic chip structures from each other;

[0037] The light-blocking structure disposed within the isolation trench is at least used to prevent light from being transmitted between any two adjacent optoelectronic chip structures through the second doped semiconductor layer.

[0038] In this invention, a micro optoelectronic chip array is realized by using ion implantation isolation. By opening isolation trenches in the ion implantation region and setting light-blocking structures in the isolation trenches, the miniaturization of the chip can be better realized, avoiding chip sidewall damage and dangling bonds caused by etching processes, ensuring and improving the quantum efficiency and effective usable area of ​​the chip, giving it better optical and electrical properties. At the same time, it can also effectively prevent light from being transmitted between adjacent chips in the micro optoelectronic chip array, eliminating optical crosstalk, thereby improving the display effects such as contrast and brightness of the micro optoelectronic chip array.

[0039] In one embodiment, the ion implantation region extends continuously from at least the top surface of the second doped semiconductor layer to the top surface of the active layer. The isolation trench is entirely located within the ion implantation region. The bottom surface of the isolation trench is higher than the bottom surface of the ion implantation region and is either flush with or lower than the bottom surface of the second doped semiconductor layer. The top surface of the second doped semiconductor layer is the surface of the second doped semiconductor layer furthest from the substrate. By placing the isolation trench entirely within the ion implantation region, the risk of damaging the semiconductor material due to over-etching during the fabrication of the isolation trench can be further reduced. Furthermore, the ion implantation region can electrically isolate the conductive filling material within the isolation trench from the semiconductor materials in the second doped semiconductor layer and the active layer, ensuring the normal operating performance of the device.

[0040] The implanted ions used to form the ion implantation region include, but are not limited to, H ions, F ions, N ions, or O ions.

[0041] The ion-implanted regions can be one or more. For example, on the surface of the semiconductor structure layer, the ion-implanted regions can be grid-like, with each grid surrounding a non-ion-implanted region for fabricating a photoelectric chip structure. Correspondingly, the isolation trenches can also be one or more, and for example, they can also be grid-like structures on the surface of the semiconductor structure layer.

[0042] In this invention, the ion-implanted region surrounds a corresponding non-ion-implanted region, in which a photoelectronic chip structure is formed. The dimensions of both the ion-implanted region and the photoelectronic chip structure can be determined according to actual needs. For example, the dimensions of the ion-implanted region and the photoelectronic chip structure are 1 μm to 50 μm. The dimensions of the ion-implanted region and the photoelectronic chip structure mainly refer to their dimensions in the direction parallel to the layer plane of the semiconductor structure layer, and can also be considered as their length and width or their diameter.

[0043] Furthermore, the bottom surface of the ion implantation region can be located inside the first doped semiconductor layer; the opening of the isolation trench can be disposed on the top surface of the second doped semiconductor layer, while the bottom of the trench is located inside the first doped semiconductor layer; and the light-blocking structure is at least used to prevent light from propagating between any two adjacent optoelectronic chip structures through the second doped semiconductor layer and the active layer. This design better blocks light propagation within the micro optoelectronic chip array, more thoroughly overcoming the optical crosstalk problem.

[0044] In this invention, the inner wall of the isolation trench is a certain distance from the outer wall of the corresponding ion implantation region, that is, the ion implantation region has a certain wall thickness, which can be 100 nm to 20 μm, for example.

[0045] In one embodiment, the micro optoelectronic chip further includes at least one dielectric layer, which continuously covers the sidewall of the isolation trench and is located between the sidewall of the isolation trench and the light-blocking structure; and the light-blocking structure includes a metal optical isolation layer that continuously covers the dielectric layer. By providing the dielectric layer, the sidewall of the isolation trench can be protected, and the conductive filling material within the isolation trench can be electrically isolated from the semiconductor materials in the second doped semiconductor layer and the active layer. Furthermore, the dielectric layer can prevent ion escape from the ion-implanted region when the metal optical isolation layer is fabricated using processes such as evaporation, thereby better ensuring the device's performance.

[0046] The dielectric layer is made of materials including, but not limited to, silicon oxide, silicon nitride, aluminum nitride, aluminum oxide, gallium oxide, titanium oxide, or hafnium oxide.

[0047] The metal optical isolation layer is made of materials including, but not limited to, gold, titanium, aluminum, nickel, chromium, molybdenum, or copper. Preferably, the metal optical isolation layer is formed of a metal or alloy such as Al, which possesses both excellent reflective and conductive properties. The metal optical isolation layer can be a single layer or a multilayer structure.

[0048] Preferably, the micro optoelectronic chip includes multiple dielectric layers with different refractive indices, which are at least sequentially stacked on the sidewalls of the isolation trench and combined with the ion implantation region to form a distributed Bragg reflector (DBR) structure. The definition of the distributed Bragg reflector structure is well-known in the art; it is primarily an optical thin film composed of a low-refractive-index material and a high-refractive-index material through different stacking combinations. For example, the low-refractive-index material can be, but is not limited to, SiO2, and the high-refractive-index material can be, but is not limited to, TiO2, Ta2O5, ZrO2, etc. The greater the refractive index difference between the materials, the smaller the thickness required to achieve the desired reflectivity.

[0049] Specifically, after ion implantation to form an ion implantation region in a selected area of ​​the semiconductor structure layer, the refractive index of the semiconductor material therein also changes, thereby forming a light refraction interface in conjunction with the semiconductor material in the chip. Then, by alternately stacking multiple dielectric layers with different refractive indices on the sidewall of the isolation trench, a DBR structure can be formed. This structure can achieve sidewall passivation to better ensure the electrical performance stability and long-term reliability of the optoelectronic chip. It can also work with the light-blocking structure to optically isolate and totally reflect the light emitted from the sidewall of the optoelectronic chip, allowing more light energy inside the optoelectronic chip to be emitted from the front, thereby better eliminating the problem of optical crosstalk and further improving the photoelectric conversion efficiency of the chip.

[0050] Preferably, the dielectric layer is formed of a thermally conductive medium material. For example, the coefficient of thermal expansion of the thermally conductive medium material is between that of the material constituting the metal opto-isolation layer and the material constituting the ion isolation region, and / or, the thermally conductive medium material has good bonding performance with both the material constituting the metal opto-isolation layer and the material constituting the ion isolation region. This not only facilitates the faster transfer of heat generated during chip operation but also ensures a stronger bond between the metal opto-isolation layer and the chip, preventing the metal opto-isolation layer from detaching from the chip structure due to heat generated during long-term chip operation. The thermally conductive medium material can be selected from silicon nitride, aluminum nitride, etc., but is not limited to these.

[0051] More preferably, the dielectric layer used to form the distributed Bragg reflector structure is formed of the thermally conductive dielectric material, so as to have both light reflection and heat conduction functions.

[0052] In this invention, the thickness of the dielectric layer can be 5 nm to 500 nm.

[0053] In one embodiment, the micro-optoelectronic chip further includes a thermally conductive passivation layer, which covers the surface of the semiconductor structure layer and is thermally connected to the metal opto-isolation layer. This thermally conductive passivation layer not only protects the surface of the micro-optoelectronic chip array but also forms a heat conduction path with the metal opto-isolation layer, further reducing the temperature of the micro-optoelectronic chip array and ensuring its performance and stability.

[0054] The material of the thermally conductive passivation layer includes, but is not limited to, aluminum nitride, boron nitride, or diamond.

[0055] In some cases, a localized area of ​​the thermally conductive passivation layer fills the isolation trench and comes into direct contact with the metal opto-isolation layer. Additionally, in some cases, windows may be formed on the thermally conductive passivation layer to facilitate the fabrication of electrodes that mate with the various optoelectronic chip structures.

[0056] In one embodiment, the metal optical isolation layer further extends to cover the surface of the semiconductor structure layer and forms a current spreading layer.

[0057] In this invention, the semiconductor structure layer is made of a III-V compound, preferably a III-nitride, such as Al. x In y Ga 1-x-y N, 1≥x≥0, 1≥y≥0, 1≥(1-xy)≥0. The first and second doped semiconductor layers have different conductivity types; for example, the first and second doped semiconductor layers can be N-type and P-type semiconductor layers, respectively, or vice versa. The active layer can be a multi-quantum-well layer. Furthermore, the semiconductor structure layer may also include other structural layers commonly known in the art, such as buffer layers. The materials and thicknesses of these structural layers can be selected or configured according to methods known in the art, and will not be elaborated upon here.

[0058] In this invention, the substrate may include, but is not limited to, sapphire, Si, SiC, GaN substrates, etc.

[0059] In this invention, the optoelectronic chip structure may include a Micro-LED chip structure, or it may be an LD (laser), a Mini-LED chip structure or other light-emitting semiconductor structure, and is not limited thereto.

[0060] Some embodiments of the present invention provide a method for fabricating the micro optoelectronic chip, comprising:

[0061] A semiconductor structure layer is formed on a substrate, the semiconductor structure layer including a first doped semiconductor layer, an active layer and a second doped semiconductor layer sequentially stacked on the substrate; for example, the first doped semiconductor layer, the active layer and the second doped semiconductor layer can be sequentially grown on the substrate using processes such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0062] Ion implantation is performed on the semiconductor structure layer to form ion-implanted regions within it, thereby electrically isolating multiple optoelectronic chip structures arranged in an array within the semiconductor structure layer. The implanted ions include, but are not limited to, H ions, F ions, N ions, or O ions. Generally, the ion-implanted regions surround non-ion-implanted regions, and the optoelectronic chip structures are fabricated within the non-ion-implanted regions. The dimensions of the ion-implanted and non-ion-implanted regions can be set from 1 μm to 50 μm. To improve the effective utilization area of ​​the semiconductor structure layer, the size of the non-ion-implanted regions should be as large as possible, while the size of the ion-implanted regions should be as small as possible within a reasonable range. This reasonable range should satisfy the condition that it enables electrical isolation between adjacent chip structures and facilitates the creation of isolation trenches.

[0063] The ion implantation region is etched to form an isolation trench within the ion implantation region, thereby isolating the second doped semiconductor layers of at least two adjacent optoelectronic chip structures from each other.

[0064] A light-blocking structure is provided within the isolation trench to at least prevent light from transmitting between any two adjacent optoelectronic chip structures through the second doped semiconductor layer.

[0065] In one embodiment, the manufacturing method specifically includes:

[0066] Ion implantation is performed on the semiconductor structure layer from at least the top surface of the second doped semiconductor layer, and the ion implantation depth reaches at least the top surface of the active layer, thereby forming the ion implantation region.

[0067] The ion implantation region is etched to a depth less than the ion implantation depth but at least reaching the bottom surface of the second doped semiconductor layer, thereby forming the isolation trench.

[0068] The top surface of the second doped semiconductor layer is the side of the second doped semiconductor layer away from the substrate.

[0069] In one embodiment, the manufacturing method more specifically includes:

[0070] Ion implantation is performed on the semiconductor structure layer from at least the top surface of the second doped semiconductor layer, and the ion implantation depth reaches the interior of the first doped semiconductor layer, thereby forming the ion implantation region.

[0071] The ion implantation region is etched to a depth less than the ion implantation depth, reaching the interior of the first doped semiconductor layer, thereby forming the isolation trench.

[0072] Additionally, a light-blocking structure is provided within the isolation trench to prevent light from propagating between any two adjacent optoelectronic chip structures through the second doped semiconductor layer and the active layer.

[0073] In the above embodiments of the present invention, a patterned ion implantation mask can be pre-formed on the surface of the semiconductor structure layer, and ion implantation can be performed using the mask. The ion implantation mask can be pre-fabricated and then transferred to the surface of the semiconductor structure layer, or it can be formed by coating a photoresist layer on the surface of the semiconductor structure layer and then fabricating it using photolithography or similar processes. The pattern and size of the ion implantation mask correspond to the shape and size of the ion implantation region, and can be determined according to actual needs. For example, the ion implantation region can be annular, square, or other regular or irregular shapes.

[0074] In the above embodiments of the present invention, the ion implantation region can be etched using etching processes such as RIE, ECR, and ICP to form the isolation trench. Furthermore, by setting an etching mask on the ion implantation region and using the etching mask to perform the etching operation, the position, size, and shape of the isolation trench can be controlled more precisely, avoiding damage to the sidewalls of the chip structure. Preferably, the distance between the edge of the opening on the etching mask and the edge of the ion implantation region can be controlled to 100 nm to 20 μm, thereby ensuring that the distance between the inner wall of the etched isolation trench and the outer wall of the corresponding ion implantation region is 100 nm to 20 μm. In actual production, the spacing of the high-resistivity ion implantation region can be precisely adjusted by changing the dimensions of the aforementioned ion implantation mask and etching mask, thereby flexibly defining the feature size of the chip and achieving device fabrication with dimensions ranging from several micrometers to hundreds of micrometers.

[0075] In one embodiment, the manufacturing method further includes:

[0076] At least one dielectric layer is fabricated, and the dielectric layer continuously covers the sidewall of the isolation trench.

[0077] A metallic optical isolation layer is fabricated, and the metallic optical isolation layer is made to continuously cover the dielectric layer at least continuously, so as to form the light-blocking structure.

[0078] In the above embodiments of the present invention, the dielectric layer can be grown by processes such as atomic layer deposition (ALD), and its thickness can be set to 5 nm to 500 nm.

[0079] More preferably, the fabrication method specifically includes: forming at least a plurality of alternatingly stacked dielectric layers with different refractive indices on the sidewall of the isolation trench, and combining the plurality of dielectric layers with the ion implantation region to form a distributed Bragg mirror structure.

[0080] More preferably, the dielectric layer can be formed on at least the sidewall of the isolation trench using a thermally conductive medium material, wherein the coefficient of thermal expansion of the thermally conductive medium material is between the coefficient of thermal expansion of the material constituting the metal optical isolation layer and the coefficient of thermal expansion of the material constituting the ion isolation region.

[0081] In one embodiment, a thermally conductive passivation layer is formed on the surface of the semiconductor structure layer, and the thermally conductive passivation layer is thermally connected to the metal optical isolation layer. The thermally conductive passivation layer can also be grown using processes such as atomic layer deposition (ALD). Preferably, the thermally conductive passivation layer can cover the entire surface of the semiconductor structure layer. Of course, if electrodes or the like are to be fabricated, corresponding windows can be formed in the thermally conductive passivation layer.

[0082] In one embodiment, the metal optical isolation layer can also be extended to cover the surface of the semiconductor structure layer to form a current spreading layer, which is also beneficial to improve the luminescence uniformity of the micro optoelectronic chip array.

[0083] The materials of the semiconductor structure layer, dielectric layer, metal optical isolation layer, thermally conductive dielectric material, and thermally conductive passivation layer are as described above and will not be repeated here.

[0084] The manufacturing method provided by this invention is simple and reliable, compatible with existing technologies, and can simultaneously improve the effective usable area of ​​the chip, reduce the sidewall damage effect of the material, eliminate optical crosstalk in the device, and improve the luminous efficiency of the device.

[0085] Some embodiments of the present invention also provide an optoelectronic device comprising the aforementioned micro optoelectronic chip.

[0086] Some embodiments of the present invention also provide a method for fabricating an optoelectronic device, comprising:

[0087] Fabrication of the aforementioned micro optoelectronic chip;

[0088] Furthermore, electrodes are fabricated and electrically contacted with a first doped semiconductor layer and a second doped semiconductor layer in the optoelectronic chip structure, for example, to form ohmic contacts. The electrodes include P-type electrodes and N-type electrodes.

[0089] For example, the optoelectronic device can be a Micro-LED device. Using the described fabrication method, it is possible to more conveniently, quickly, and cost-effectively fabricate Micro-LED chips with smaller size and better optical and electrical properties, and effectively improve their resolution and brightness, thereby achieving better display effects.

[0090] Furthermore, some embodiments of the present invention also provide a Micro-LED device, such as a Micro-LED display device, which includes the aforementioned micro optoelectronic chip.

[0091] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0092] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0093] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0094] In the context of this invention, the described structure of the first feature "above" the second feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0095] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0096] Example 1

[0097] Please see Figure 1 This embodiment provides a Micro-LED chip, comprising a sapphire substrate 10 and a semiconductor structure layer 11. The semiconductor structure layer includes an AlN buffer layer 111, an N-type GaN layer 112, a multi-quantum-well active layer 113, and a P-type GaN layer 114 sequentially grown on the substrate. The semiconductor structure layer includes ion-implanted regions 115 distributed along the layer plane and multiple non-ion-implanted regions. Any two adjacent non-ion-implanted regions are electrically isolated by the ion-implanted regions. Each non-ion-implanted region contains a Micro-LED chip structure 116, and each Micro-LED chip structure 116 can serve as a pixel, thereby forming a Micro-LED chip structure within the semiconductor structure layer. Simultaneously, isolation trenches 117 are formed within the ion-implanted regions to isolate the P-type GaN layer and the multi-quantum-well active layer of two adjacent Micro-LED chip structures from each other. Furthermore, light-blocking structures are provided within the isolation trenches to prevent light from propagating between two adjacent Micro-LED chip structures through the P-type GaN layer 114 and the multi-quantum-well active layer 113. The light-blocking structure includes one or more opaque metallic optical isolation layers 12, made of materials such as gold (Au), titanium (Ti), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), copper (Cu), or their alloys. The metallic optical isolation layer covers the inner wall of the isolation trench and primarily serves to block and reflect light reflected from the multi-quantum-well active layer, thus obstructing the light transmission path between adjacent Micro-LED chip structures. One or more dielectric layers 13 are disposed between the metallic optical isolation layer and the inner wall of the isolation trench. The dielectric layer materials include, but are not limited to, silicon oxide (SiO2), silicon nitride (SiN), aluminum nitride (AlN), aluminum oxide (Al2O3), gallium oxide (Ga2O3), titanium oxide (TiO2), or hafnium oxide (HfO2), with a thickness of 5 nm to 500 nm. These dielectric layers primarily passivate the inner wall of the isolation trench and electrically isolate the metallic optical isolation layer from the inner wall of the isolation trench. Preferably, the dielectric layer material can be aluminum nitride, silicon nitride, or other materials with high thermal conductivity. In some cases, the isolation trench can be completely filled using a metal optical isolation layer and a dielectric layer. More preferably, the metal optical isolation layer can be continuously extended to cover the surface of the semiconductor structure layer, thereby forming a current spreading layer to improve the efficiency and uniformity of current injection. Furthermore, a continuous thermally conductive passivation layer 14 is also covered on the surface of the semiconductor structure layer, which is in direct contact with the metal optical isolation layer. Its material can be, but is not limited to, aluminum nitride (AlN), boron nitride (BN), diamond, or a mixture thereof. This thermally conductive passivation layer not only passivates the surface of the metal optical isolation layer but also functions as a thermally conductive layer for Micro-LEDs.

[0098] Please see Figures 2-5 One method for manufacturing this Micro-LED chip includes the following steps:

[0099] S1. Using MOCVD, MBE, PECVD, etc., an AlN buffer layer 111, an N-type GaN layer 112, a multi-quantum-well active layer 113, and a P-type GaN layer 114 are sequentially grown on a sapphire substrate to obtain... Figure 2 The epitaxial wafer shown.

[0100] S2. A patterned ion implantation mask is formed using processes such as photolithography. The material of the ion implantation mask includes, but is not limited to, photoresist, silicon oxide, silicon nitride, and metal. Using this ion implantation mask as a barrier layer, ion implantation is performed on the semiconductor structure layer of the epitaxial wafer to control the area and / or shape of the light-emitting region of the Micro-LED chip structure. The ion implantation depth must penetrate at least through the P-type GaN layer, preferably reaching the interior of the N-type GaN layer 112. The implanted ion types include, but are not limited to, H ions, F ions, N ions, and O ions. The final ion implantation region 115 has a size of 1 μm to 50 μm, and the non-ion implantation region 118 has a size of 1 μm to 50 μm. From a top view, the ion implantation region 115 is preferably arranged around the non-ion implantation region 118, and each non-ion implantation region 118 is used to form a Micro-LED chip structure. The device structure finally obtained in this step is as follows: Figure 3 As shown. This step uses ion implantation for electrical isolation, which has advantages such as less damage and higher control precision compared to using etching processes for electrical isolation.

[0101] S3. An etching mask is formed on the ion implantation region 115, and vias are formed on the etching mask. The size of the vias is smaller than the size of the ion implantation region. Preferably, the distance between the edge of the via and the edge of the ion implantation region is 100 nm to 20 μm to minimize sidewall damage to the chip. Then, dry etching processes such as atomic layer etching (ALE), ion beam etching (IBE), and inductively coupled plasma etching (ICP) are used to etch the ion implantation region through the vias of the etching mask. The etching depth is less than or equal to the ion implantation depth, but preferably less than the ion implantation depth, and particularly preferably penetrates into the N-type GaN layer 112, thereby forming an isolation trench 117. The final device structure obtained in this step is as follows: Figure 4 As shown. This step, by performing dry etching within the ion implantation region, not only effectively avoids damage to the sidewalls caused by the etching process and improves photoelectric conversion efficiency, but also creates a narrower etched isolation region. In particular, it can effectively isolate the light between Micro-LED pixels and eliminate light crosstalk effects.

[0102] S4. At least one or more dielectric layers 13 are formed on the sidewalls of the isolation trench 117 using processes such as atomic layer deposition (ALD), with a thickness ranging from 5 nm to 500 nm. In some cases, the dielectric layer can completely cover the inner wall of the isolation trench 117. Further, one or more opaque metal materials are deposited on the dielectric layer to form a metallic optical isolation layer 12. This metallic optical isolation layer 12 forms a light-blocking structure, which can effectively reduce optical crosstalk between pixels. Alternatively, the metallic optical isolation layer 12 can be used to completely fill the isolation trench 117. The final device structure obtained in this step is as follows: Figure 5 As shown.

[0103] S5. A non-metallic thermally conductive material is deposited on the metallic optical isolation layer 12 to form a thermally conductive passivation layer 14, which passivates the surface of the metallic optical isolation layer 12 and also serves as a thermally conductive layer for the Micro-LED chip structure. Preferably, the thermally conductive passivation layer 14 can be continuously extended and cover the device surface, ultimately obtaining... Figure 1 The Micro-LED chip shown.

[0104] Example 2

[0105] The Micro-LED chip provided in this embodiment is basically the same as that in Embodiment 1, except that the dielectric layer is formed of aluminum nitride with high thermal conductivity, while the metal photoisolator layer is formed of aluminum. The dielectric layer serves two purposes: firstly, it passivates the sidewalls of the isolation trench and electrically isolates the metal photoisolator layer from the inner wall of the isolation trench; secondly, it acts as a transition layer between the GaN-doped ion implantation region and the metal photoisolator layer, ensuring the metal photoisolator layer is firmly bonded to the isolation trench. Simultaneously, together with the dielectric layer, it forms a heat-conducting channel, facilitating the rapid transfer of heat generated by the Micro-LED chip during operation, ensuring its operational stability, and improving its performance.

[0106] Example 3

[0107] The Micro-LED chip provided in this embodiment is basically the same as that in Embodiment 1, except that the Micro-LED chip structure is a blue LED chip structure with a center wavelength of approximately 450nm. Please also refer to... Figures 6-7 The dielectric layer 13' consists of eight pairs of TiO2 / SiO2 composite layers, with a total thickness of approximately 895.2 nm. The TiO2 and SiO2 layers are alternately stacked to form a distributed Bragg reflector structure. Each TiO2 layer is approximately 41.1 nm thick, and each SiO2 layer is approximately 70.8 nm thick. The reflectivity of this dielectric layer 13' for different wavelengths of light is as follows: Figure 8As shown, it can work with a metal optical isolation layer (such as a metal aluminum layer) to more thoroughly eliminate the problem of optical crosstalk. At the same time, it can also serve as a transition layer between the ion implantation region of GaN-doped material and the metal optical isolation layer, strengthen the bonding force between the metal optical isolation layer and the isolation trench wall, and work with the metal optical isolation layer to construct a new heat conduction channel for the Micro-LED chip.

[0108] Example 4

[0109] The Micro-LED chip provided in this embodiment is basically the same as that in Embodiment 3, except that: the Micro-LED chip structure is a green LED chip structure with a center wavelength of approximately 550 nm. The dielectric layer is an 8-pair TiO2 / SiO2 composite layer structure with a total thickness of approximately 1112.0 nm. The TiO2 and SiO2 layers are alternately stacked to form a distributed Bragg reflector structure, with each TiO2 layer approximately 46.9 nm thick and each SiO2 layer approximately 92.1 nm thick. The reflectivity of this dielectric layer for different wavelengths of light is as follows: Figure 9 As shown. This dielectric layer can also work in conjunction with the metal optical isolation layer to better eliminate optical crosstalk and enhance the heat dissipation performance of the device, thereby improving the photoelectric conversion efficiency and stability of the device.

[0110] Example 5

[0111] The Micro-LED chip provided in this embodiment is basically the same as that in Embodiment 3, except that: the Micro-LED chip structure is a red LED chip structure with a center wavelength of approximately 660nm. The dielectric layer consists of eight pairs of TiO2 / SiO2 composite layers, with a total thickness of approximately 1350.4nm. The TiO2 and SiO2 layers are alternately stacked to form a distributed Bragg reflector structure, with each TiO2 layer approximately 54.6nm thick and each SiO2 layer approximately 114.2nm thick. The reflectivity of this dielectric layer for different wavelengths of light is as follows: Figure 10 As shown. This dielectric layer can also work in conjunction with the metal optical isolation layer to better eliminate optical crosstalk and enhance the heat dissipation performance of the device, thereby improving the photoelectric conversion efficiency and stability of the device.

[0112] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A miniature optoelectronic chip, characterized in that, include: Substrate; A semiconductor structure layer disposed on the substrate, the semiconductor structure layer comprising a first doped semiconductor layer, an active layer and a second doped semiconductor layer sequentially stacked on the substrate; The ion implantation region distributed within the semiconductor structure layer extends continuously from the top surface of the second doped semiconductor layer to the top surface of the active layer, and is used to electrically isolate multiple optoelectronic chip structures arranged in an array within the semiconductor structure layer. An isolation trench is formed within the ion implantation region. The isolation trench is used to isolate the second doped semiconductor layers of any two adjacent optoelectronic chip structures from each other. The isolation trench is located entirely within the corresponding ion implantation region. At the same time, there is a gap between the inner wall of the isolation trench and the outer wall of the corresponding ion implantation region. The bottom surface of the isolation trench is higher than the bottom surface of the corresponding ion implantation region and is flush with or lower than the bottom surface of the second doped semiconductor layer. The top surface of the second doped semiconductor layer is the side of the second doped semiconductor layer away from the substrate. At least a plurality of dielectric layers continuously cover the sidewall of the isolation trench, the plurality of dielectric layers having different refractive indices, and are sequentially stacked on the sidewall of the isolation trench, and combined with the corresponding ion implantation region to form a distributed Bragg mirror structure; The light-blocking structure disposed within the isolation trench is used to at least prevent light from being transmitted between any two adjacent optoelectronic chip structures through the second doped semiconductor layer. The light-blocking structure includes at least a metal optical isolation layer continuously covering the dielectric layer.

2. The micro optoelectronic chip according to claim 1, characterized in that: The bottom surface of the ion implantation region is located inside the first doped semiconductor layer; the opening of the isolation trench is disposed on the top surface of the second doped semiconductor layer, while the bottom of the trench is located inside the first doped semiconductor layer; and the light-blocking structure is at least used to prevent light from transmitting between any two adjacent optoelectronic chip structures through the second doped semiconductor layer and the active layer.

3. The micro optoelectronic chip according to claim 1, characterized in that: The dielectric layer is made of silicon oxide, silicon nitride, aluminum nitride, aluminum oxide, gallium oxide, titanium oxide, or hafnium oxide.

4. The micro optoelectronic chip according to claim 1, characterized in that: The micro optoelectronic chip also includes a thermally conductive passivation layer, which covers the surface of the semiconductor structure layer and is thermally connected to the metal optical isolation layer.

5. The micro optoelectronic chip according to claim 1, characterized in that: The metal optical isolation layer also extends to cover the surface of the semiconductor structure layer and forms a current spreading layer.

6. The micro optoelectronic chip according to claim 1, characterized in that: The material of the metal optical isolation layer includes gold, titanium, aluminum, nickel, chromium, molybdenum, or copper.

7. The micro optoelectronic chip according to claim 1, characterized in that: The ion implantation region is arranged around the corresponding optoelectronic chip structure, and the size of the ion implantation region and the optoelectronic chip structure is 1 μm to 50 μm.

8. The micro optoelectronic chip according to claim 1, characterized in that: The implanted ions used to form the ion implantation region include H ions, F ions, N ions, or O ions.

9. The micro optoelectronic chip according to claim 1, characterized in that: The distance between the inner wall of the isolation trench and the outer wall of the corresponding ion implantation region is 100 nm to 20 μm.

10. The micro optoelectronic chip according to claim 1, characterized in that: The semiconductor structure layer is made of III-V compound.

11. The micro optoelectronic chip according to claim 10, characterized in that: The semiconductor structure layer is made of group III nitride.

12. The micro optoelectronic chip according to claim 1, characterized in that: The optoelectronic chip structure includes a Micro-LED chip structure.

13. A method for fabricating a micro optoelectronic chip, characterized in that, include: A semiconductor structure layer is formed on a substrate, the semiconductor structure layer comprising a first doped semiconductor layer, an active layer and a second doped semiconductor layer sequentially stacked on the substrate; Ion implantation is performed on the semiconductor structure layer from at least the top surface of the second doped semiconductor layer, and the ion implantation depth reaches at least the top surface of the active layer to form an ion implantation region in the semiconductor structure layer, thereby electrically isolating multiple optoelectronic chip structures arranged in an array in the semiconductor structure layer. The top surface of the second doped semiconductor layer is the side surface of the second doped semiconductor layer away from the substrate. The ion implantation region is etched to a depth less than the ion implantation depth but at least reaching the bottom surface of the second doped semiconductor layer, so as to form an isolation trench in the ion implantation region and to create a gap between the inner wall of the isolation trench and the outer wall of the ion implantation region, thereby isolating the second doped semiconductor layers of at least any two adjacent optoelectronic chip structures from each other. At least a plurality of alternating dielectric layers with different refractive indices are formed on the sidewall of the isolation trench, and the dielectric layers at least continuously cover the sidewall of the isolation trench, and the plurality of dielectric layers are combined with the ion implantation region to form a distributed Bragg mirror structure. A metal optical isolation layer is fabricated and at least continuously covers the dielectric layer to form a light-blocking structure within the isolation trench, thereby at least preventing light from transmitting between any two adjacent optoelectronic chip structures through the second doped semiconductor layer.

14. The manufacturing method according to claim 13, characterized in that, Specifically, it includes: Ion implantation is performed on the semiconductor structure layer from at least the top surface of the second doped semiconductor layer, and the ion implantation depth reaches the interior of the first doped semiconductor layer, thereby forming the ion implantation region. The ion implantation region is etched to a depth less than the ion implantation depth, reaching the interior of the first doped semiconductor layer, thereby forming the isolation trench. Furthermore, the light-blocking structure is provided within the isolation trench to prevent light from propagating between any two adjacent optoelectronic chip structures through the second doped semiconductor layer and the active layer.

15. The manufacturing method according to claim 13, characterized in that: The dielectric layer is made of silicon oxide, silicon nitride, aluminum nitride, aluminum oxide, gallium oxide, titanium oxide, or hafnium oxide.

16. The manufacturing method according to claim 13, characterized in that, Also includes: A thermally conductive passivation layer is formed on the surface of the semiconductor structure layer, and the thermally conductive passivation layer is thermally connected to the metal optical isolation layer.

17. The manufacturing method according to claim 16, characterized in that: The thermally conductive passivation layer is made of aluminum nitride, boron nitride, or diamond.

18. The manufacturing method according to claim 13, characterized in that, Also includes: The metal optical isolation layer is extended to cover the surface of the semiconductor structure layer to form a current spreading layer.

19. The manufacturing method according to claim 13, characterized in that: The material of the metal optical isolation layer includes gold, titanium, aluminum, nickel, chromium, molybdenum, or copper.

20. The manufacturing method according to claim 13, characterized in that: The ion implantation region is arranged around the corresponding optoelectronic chip structure, wherein the size of the ion implantation region and the optoelectronic chip structure is 1 μm to 50 μm.

21. The manufacturing method according to claim 13, characterized in that: The ions used in the ion implantation process include H ions, F ions, N ions, or O ions.

22. The manufacturing method according to claim 13, characterized in that: The distance between the inner wall of the isolation trench and the outer wall of the corresponding ion implantation region is 100 nm to 20 μm.

23. The manufacturing method according to claim 13, characterized in that: The semiconductor structure layer is made of III-V compound.

24. The manufacturing method according to claim 23, characterized in that: The semiconductor structure layer is made of group III nitride.

25. The manufacturing method according to claim 13, characterized in that: The optoelectronic chip structure includes a Micro-LED chip structure.

26. A Micro-LED device, characterized in that, Includes the micro optoelectronic chip according to any one of claims 1-12.

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