FPGA-based message transmission method and FPGA device

Abstract

This application provides a message transmission method and FPGA device based on FPGA. In this embodiment, the message payload is stored separately and not transmitted, avoiding the resource waste caused by each logic unit transmitting the message payload. The non-first logic unit through which the message passes only stores the message header members obtained from its corresponding processing operation in its corresponding storage space. Compared with the prior art where each logic unit has its own separate storage space for the complete message, this further saves logic resources in the FPGA, thereby ensuring the efficient operation of the FPGA.

Description

Technical Field

[0001] This application relates to the field of network communication technology, and in particular to a message transmission method and FPGA device based on FPGA. Background Technology

[0002] Currently, when using a Field Programmable Gate Array (FPGA) to transmit messages, the message passes through each logic unit in the FPGA sequentially and is processed. Each logic unit performs the corresponding processing operation on the message and then stores the complete message obtained after processing. This means that if there are too many logic units in the FPGA, a lot of additional storage resources need to be set up to buffer the messages output by each logic unit. This message transmission method inevitably occupies a lot of logic resources and affects the efficient operation of the FPGA. Summary of the Invention

[0003] In view of this, embodiments of this application provide a message transmission method and FPGA device based on FPGA, so as to save logic resources and ensure the efficient operation of FPGA when transmitting messages using FPGA.

[0004] This application provides a message transmission method based on an FPGA. The FPGA includes a message splicing unit and N logic units. Each logic unit is used to perform a corresponding processing operation. Different logic units perform different processing operations, and different logic units correspond to different storage spaces. The method includes:

[0005] When any logical unit receives a message,

[0006] If this logic unit is determined to be the first logic unit through which the message passes, the message is split into a message payload and N message header members, and the N message header members are stored in the storage space corresponding to this logic unit, and the message payload is stored in the storage space configured in this FPGA for storing message payload.

[0007] If it is determined that this logical unit is not the first logical unit through which the message passes, then the target logical unit is determined from all the logical units through which the message passes. The message header members stored in the storage space corresponding to the target logical unit are related to the processing operation performed by this logical unit. The message header members are obtained from the storage space corresponding to the target logical unit and processed according to the processing operation corresponding to this logical unit. The processed message header members are then stored in the storage space corresponding to this logical unit.

[0008] After the last logic unit through which the message passes completes its processing operation, the message splicing unit queries the memory space corresponding to each logic unit to find the message header members that meet the output requirements according to the FPGA's preset output requirements. The queryed message header members are then spliced ​​with the message payload to obtain the target message and output it.

[0009] As an example, N logic units are deployed in a predetermined order; the predetermined order is based on the functions required by the network device to which the FPGA belongs, and the processing steps performed by each logic unit.

[0010] Determining that this logical unit is the first logical unit through which the message passes includes:

[0011] If this logical unit is the first in the set sequence, then this logical unit is determined to be the first logical unit through which the message passes.

[0012] As an example, N logical units are deployed in a predetermined order; for any logical unit that is not the first in the predetermined order, the logical unit is pre-configured with at least one associated logical unit; wherein, when the logical unit performs the corresponding processing operation, it needs to base it on the processing result after the associated logical unit of the logical unit performs the corresponding processing operation.

[0013] Determining the target logical unit from the logical units through which the message passes includes:

[0014] Obtain the associated logical units that are related to this logical unit, and use the obtained associated logical units as the target logical unit.

[0015] As an example, the storage space configured in this FPGA for storing message payloads is different from the storage space corresponding to each logic unit;

[0016] The storage space configured in this FPGA for storing message payloads is managed in the form of random RAM.

[0017] The storage space corresponding to each logical unit manages the stored data in a first-in-first-out (FIFO) manner.

[0018] As an example, when the number of target logical units is greater than 1, the obtained message header members are processed according to the processing operation corresponding to this logical unit. This is executed after a set delay from the target time point corresponding to this logical unit. The target time point is the time point at which this logical unit determines the target logical unit from the logical units through which the message passes.

[0019] As an example, the message splicing unit reuses the last logical unit through which the message passes.

[0020] This application embodiment also provides an FPGA device. The FPGA includes a message splicing unit and N logic units. Each logic unit is used to perform a corresponding processing operation. Different logic units perform different processing operations and different logic units correspond to different storage spaces.

[0021] Any logical unit, used to, upon receiving a message,

[0022] If this logic unit is determined to be the first logic unit through which the message passes, the message is split into a message payload and N message header members, and the N message header members are stored in the storage space corresponding to this logic unit, and the message payload is stored in the storage space configured in this FPGA for storing message payload.

[0023] If it is determined that this logical unit is not the first logical unit through which the message passes, then the target logical unit is determined from all the logical units through which the message passes. The message header members stored in the storage space corresponding to the target logical unit are related to the processing operation performed by this logical unit. The message header members are obtained from the storage space corresponding to the target logical unit and processed according to the processing operation corresponding to this logical unit. The processed message header members are then stored in the storage space corresponding to this logical unit.

[0024] The message splicing unit is used to query the message header members that meet the output requirements from the storage space corresponding to each logic unit according to the FPGA preset output requirements after the last logic unit through which the message has completed the processing operation. The queryed message header members are then spliced ​​with the message payload to obtain the target message and output it.

[0025] As an example, N logic units are deployed in a predetermined order; the predetermined order is based on the functions required by the network device to which the FPGA belongs, and the processing steps performed by each logic unit.

[0026] Determining that this logical unit is the first logical unit through which the message passes includes:

[0027] If this logical unit is the first in the set sequence, then this logical unit is determined to be the first logical unit through which the message passes.

[0028] As an example, N logical units are deployed in a predetermined order; for any logical unit that is not the first in the predetermined order, the logical unit is pre-configured with at least one associated logical unit; wherein, when the logical unit performs the corresponding processing operation, it needs to base it on the processing result after the associated logical unit of the logical unit performs the corresponding processing operation.

[0029] Determining the target logical unit from the logical units through which the message passes includes:

[0030] Obtain the associated logical units that are related to this logical unit, and use the obtained associated logical units as the target logical unit.

[0031] As an example, the storage space configured in this FPGA for storing message payloads is different from the storage space corresponding to each logic unit;

[0032] The storage space configured in this FPGA for storing message payloads is managed in the form of random RAM.

[0033] The storage space corresponding to each logical unit manages the stored data in a first-in-first-out (FIFO) manner.

[0034] As an example, when the number of target logical units is greater than 1, the obtained message header members are processed according to the processing operation corresponding to this logical unit. This is executed after a set delay from the target time point corresponding to this logical unit. The target time point is the time point at which this logical unit determines the target logical unit from the logical units through which the message passes.

[0035] As an example, the message splicing unit reuses the last logical unit through which the message passes.

[0036] This application also provides a network device, including the FPGA device provided in the above embodiments.

[0037] As can be seen from the above technical solution, in this embodiment, the first logic unit through which the message passes splits the message into a message payload and N message header members. The message payload is stored in the storage space configured in this FPGA for storing message payloads, and the N message header members are stored in the storage space corresponding to this logic unit. For logic units other than the first one through which the message passes, a target logic unit is determined from the logic units through which the message passes. The message header members are obtained from the storage space corresponding to the target logic unit, processed according to the processing operation corresponding to this logic unit, and then stored in the storage space corresponding to this logic unit. The message splicing unit, after the last logic unit through which the message passes has completed its processing operation, queries the storage space corresponding to each logic unit to find message header members that meet the output requirements according to the FPGA's preset output requirements. The queryed message header members are then spliced ​​with the message payload to obtain the target message and output it. In this way, the message payload is stored separately and not transmitted, avoiding the resource waste caused by each logic unit transmitting the message payload.

[0038] Furthermore, the message header members obtained from the corresponding processing operation are only stored in the corresponding storage space of the non-first logic unit through which the message passes. Compared with the prior art where each logic unit is set up to store the complete message separately, this further saves logic resources in the FPGA, thereby ensuring the efficient operation of the FPGA. Attached Figure Description

[0039] Figure 1 A flowchart illustrating the method provided in the embodiments of this application;

[0040] Figure 2 A framework diagram of the implementation environment for the methods provided in the embodiments of this application;

[0041] Figure 3 A flowchart illustrating the method provided in the embodiments of this application;

[0042] Figure 4 This is a schematic diagram of the device provided in an embodiment of this application. Detailed Implementation

[0043] To enable those skilled in the art to better understand the technical solutions provided in the embodiments of this application, and to make the above-mentioned objectives, features and advantages of the embodiments of this application more apparent and understandable, the technical solutions in the embodiments of this application will be further described in detail below with reference to the accompanying drawings.

[0044] See Figure 1 , Figure 1 This is a flowchart illustrating the method provided in an embodiment of this application. As one embodiment, the process is applied to a server.

[0045] like Figure 1 As shown, the process may include the following steps:

[0046] S101, when any logic unit receives a message, if it determines that this logic unit is the first logic unit through which the message passes, it splits the message into a message payload and N message header members, stores the N message header members in the storage space corresponding to this logic unit, and stores the message payload in the storage space configured in this FPGA for storing message payload.

[0047] In this embodiment, the functions implemented by the FPGA are achieved by various logic units configured on it that implement different sub-functions (i.e., execute different processing steps). The functions that the FPGA can implement vary depending on the network device to which it belongs. Therefore, the order of the N logic units is preset according to the functions required by the network device to which the FPGA belongs and the processing steps executed by each logic unit. This allows the N logic units to be deployed in a predetermined order, with each logic unit assigned its own sequence number.

[0048] Based on the above description, the specific implementation of determining that this logical unit is the first logical unit through which the message passes is as follows: If this logical unit is the first in the set sequence, that is, if the sequence number of this logical unit is configured as 1, then this logical unit is determined to be the first logical unit through which the message passes. If this logical unit is not the first in the set sequence, for example, if the sequence number of this logical unit is configured as 2, then this logical unit is determined to be a non-first logical unit through which the message passes.

[0049] In this embodiment, the message header members include at least: protocol type, source network interconnection protocol IP address, destination IP address, source port identifier, and destination port identifier.

[0050] In this embodiment, the storage space configured in this FPGA for storing message payloads differs from the storage spaces corresponding to each logic unit. The storage space configured in this FPGA for storing message payloads manages the stored data using a random access RAM (RAM) approach. The storage space corresponding to each logic unit manages the stored data using a first-in, first-out (FIFO) approach. Managing the message header members using a FIFO approach is more conducive to pipelined message processing; that is, one message is processed per clock edge (clk).

[0051] The specific implementation of step S101 will be described in more detail in the embodiments below, and will not be repeated here.

[0052] S102, if it is determined that this logical unit is not the first logical unit through which the message passes, then the target logical unit is determined from each logical unit through which the message passes. The message header members stored in the storage space corresponding to the target logical unit are related to the processing operation performed by this logical unit. The message header members are obtained from the storage space corresponding to the target logical unit and processed according to the processing operation corresponding to this logical unit. The processed message header members are then stored in the storage space corresponding to this logical unit.

[0053] In this embodiment, after N logic units are deployed in a predetermined order, at least one logic unit associated with each non-first logic unit needs to be pre-configured. As an example, since the execution operations corresponding to each logic unit are already determined, when configuring the FPGA, it is known which logic units' processing results preceding this logic unit are needed to perform the corresponding processing operation for any non-first logic unit in the aforementioned predetermined order. Therefore, the logic units whose processing results this logic unit needs to utilize when performing the corresponding processing operation are identified as the associated logic units of this logic unit, and the relationship between this logic unit and its associated logic units is established. For example, if logic unit 2 is used to change the source IP address to an AAA IP address, and logic unit 4 also needs to process AAA IP addresses, this requires the AAA IP address in logic unit 2; therefore, logic unit 2 is designated as the associated logic unit of logic unit 4.

[0054] Based on the above description, the specific implementation of determining the target logical unit from the logical units through which the message passes in step S102 is as follows: based on the preset association relationship, obtain the associated logical units that have an association relationship with this logical unit, and take the obtained associated logical units as the target logical unit.

[0055] As a further embodiment, for any non-first-order logic unit, when configuring the FPGA, based on the corresponding processing operation of this logic unit and the processing operations corresponding to the logic units preceding this logic unit, it is possible not only to determine its association with the logic units preceding it, but also to determine from which related logic units the message header members required by the processing operation corresponding to this logic unit are obtained, and to connect them through logical connections. Therefore, during subsequent message transmission, when the message passes through this logic unit, it can obtain the message header members required by this logic unit to perform the processing operation based on the determined logical connections.

[0056] The specific implementation of step S102 will be described in more detail in the embodiments below, and will not be repeated here.

[0057] S103, the message splicing unit, after the last logic unit through which the message passes has completed its processing operation, according to the FPGA's preset output requirements, queries the memory space corresponding to each logic unit to find the message header members that meet the output requirements, splices the found message header members with the message payload to obtain the target message and outputs it.

[0058] In this embodiment, the preset output requirements of the FPGA are determined according to the specific application scenario of the FPGA, and this embodiment does not specifically limit them.

[0059] In this embodiment, the process of retrieving the message header members that meet the output requirements from the storage space corresponding to each logic unit can be implemented in many specific ways. For example, as an embodiment, the FPGA may pre-configure relevant logic units for the message splicing unit according to the output requirements, or pre-configure which related logic units the message splicing unit needs to obtain from which of the associated logic units, and connect them through logic connections. The message splicing unit obtains the required message header members from the pre-configured relevant logic units or logic connections.

[0060] The specific implementation of step S103 will be described in more detail in the embodiments below, and will not be repeated here.

[0061] This concludes the process. Figure 1 The process is shown below.

[0062] pass Figure 1 As shown in the flowchart, in this embodiment, the first logic unit through which the message passes splits the message into a message payload and N message header members. The message payload is stored in the storage space configured in this FPGA for storing message payloads, and the N message header members are stored in the storage space corresponding to this logic unit. For logic units other than the first one through which the message passes, a target logic unit is determined from the logic units through which the message passes. The message header members are obtained from the storage space corresponding to the target logic unit, processed according to the processing operation corresponding to this logic unit, and then stored in the storage space corresponding to this logic unit. The message splicing unit, after the last logic unit through which the message passes has completed its processing operation, queries the storage space corresponding to each logic unit to find message header members that meet the output requirements according to the FPGA's preset output requirements. The queryed message header members are then spliced ​​with the message payload to obtain the target message and output it. In this way, the message payload is stored separately and not transmitted, avoiding the resource waste caused by each logic unit transmitting the message payload.

[0063] Furthermore, the message header members obtained from the corresponding processing operation are only stored in the corresponding storage space of the non-first logic unit through which the message passes. Compared with the prior art where each logic unit is set up to store the complete message separately, this further saves logic resources in the FPGA, thereby ensuring the efficient operation of the FPGA.

[0064] As an example, when the number of target logical units is greater than 1, the processing of the obtained message header members according to the processing operation corresponding to this logical unit in step S102 is executed after a set delay from the target time point corresponding to this logical unit. Here, the target time point is the time point at which this logical unit determines the target logical unit from among the logical units through which the message passes.

[0065] When the number of target logic units is greater than one, the arrival times of the required header members for the corresponding processing operation of this logic unit may differ, leading to race conditions. A race condition occurs when the required header member has not arrived by the clock edge, or when an unnecessary header member arrives. Therefore, a preset time delay, such as two register clock cycles, is needed from the time the header member is retrieved. This effectively eliminates race conditions, ensuring efficient and accurate message transmission and improving signal reliability.

[0066] As an example, the message concatenation unit can also reuse the last logical unit through which the message passes (i.e., the last logical unit in the aforementioned sequence). Thus, for any non-first logical unit, upon determining that this logical unit is the last logical unit through which the message passes, after performing the corresponding processing operation, the unit queries the storage space corresponding to each logical unit to find the message header member that meets the output requirements, based on the FPGA's preset output requirements. The retrieved message header member is then concatenated with the message payload to obtain the target message, which is then output. This further saves computing resources in the FPGA and improves message transmission speed.

[0067] To illustrate the method provided in this application in more detail, the following will be combined with... Figure 3 The solution provided in this application will be described in more detail by way of specific embodiments.

[0068] In this embodiment, the message header has 5 members: message header member 0, message header member 1, message header member 2, message header member 3, and message header member 4.

[0069] FPGA pre-configuration phase: The pre-configuration phase includes the following steps:

[0070] 1. The FPGA is configured with 3 logic units. Based on the functions that the FPGA needs to implement and the processing steps of the three logic units, the three logic units are arranged in the order of logic unit A, logic unit B and logic unit C.

[0071] The storage spaces corresponding to the three logic units are managed in a FIFO (First-In, First-Out) manner. Therefore, the storage spaces configured for logic units A, B, and C are FIFO A, FIFO B, and FIFO C, respectively. The FPGA also has a storage space configured to store the message payload, which is managed in a random RAM manner and denoted as RAM1.

[0072] 2. Based on the processing steps corresponding to logical unit B, the associated logical unit of logical unit B can be determined to be logical unit A. When logical unit B executes the corresponding operation, it needs to establish logical connections between these three header members in the storage space FiFO A corresponding to logical unit B and logical unit A, based on message header member 1, message header member 3, and message header member 4 in logical unit A.

[0073] 3. Based on the processing steps corresponding to logical unit C, logical unit A, and logical unit B, the associated logical units of logical unit C can be determined to be logical units A and B. When logical unit C executes its corresponding operation, it needs to use message header member 1 and message header member 2 in logical unit A as a basis. A logical connection is established between message header member 1 in the storage space FiFO B corresponding to logical unit C and logical unit B, and a logical connection is established between message header member 2 in the storage space FiFO A corresponding to logical unit C and logical unit A.

[0074] It should be noted that the above configurations can be achieved by programming or configuration after the FPGA is manufactured.

[0075] The message transmission phase specifically includes the following steps:

[0076] 1. Logic unit A parses out the message payload and 5 message header members, stores the message payload in RAM1, and stores the 5 message header members in the storage space FiFO A corresponding to logic unit A.

[0077] 2. Logic unit B only uses message header member 1, message header member 3, and message header member 4. Therefore, message header member 1, message header member 3, and message header member 4 are retrieved from FiFO A, processed, and the resulting message header member 1, message header member 3, and message header member 4 are stored in the storage space FiFO B corresponding to logic unit B.

[0078] 3. Logic unit C only uses header member 1 and header member 2, so it extracts header member 1 from FiFO B and header member 2 from FiFO A. Starting from the extracted header member 1 and header member 2, register resources are used for two clock cycles to eliminate race conditions. After processing header member 1 and header member 2, logic unit C stores the processed header member 1 and header member 2 into the corresponding storage space FiFO C.

[0079] 4. After the logic unit C processes the message, the logic unit C extracts the message payload from RAM1 and adds the required message header members (for example, message header member 1 is obtained from FiFO C and message header member 0 is obtained from FiFO A) to complete the message splicing and obtain the target message.

[0080] In this way, storing the message payload separately and not transmitting it avoids the resource waste caused by each logic unit transmitting the message payload. The non-first logic unit that the message passes through only stores the message header members obtained from its corresponding processing operation in its corresponding memory space, further saving logic resources in the FPGA and ensuring its efficient operation. This two-step method also effectively eliminates the aforementioned race conditions, ensuring effective and accurate message transmission and improving signal reliability.

[0081] The methods provided in the embodiments of this application have been described above. The apparatus provided in the embodiments of this application is described below:

[0082] See Figure 4 , Figure 4 This is a structural diagram of the device provided in an embodiment of this application. Figure 4 As shown, the device may include: a message splicing unit and N logic units, each logic unit is used to perform a corresponding processing operation, different logic units perform different processing operations, and different logic units correspond to different storage spaces.

[0083] Any logical unit, used to, upon receiving a message,

[0084] If this logic unit is determined to be the first logic unit through which the message passes, the message is split into a message payload and N message header members, and the N message header members are stored in the storage space corresponding to this logic unit, and the message payload is stored in the storage space configured in this FPGA for storing message payload.

[0085] If it is determined that this logical unit is not the first logical unit through which the message passes, then the target logical unit is determined from all the logical units through which the message passes. The message header members stored in the storage space corresponding to the target logical unit are related to the processing operation performed by this logical unit. The message header members are obtained from the storage space corresponding to the target logical unit and processed according to the processing operation corresponding to this logical unit. The processed message header members are then stored in the storage space corresponding to this logical unit.

[0086] The message splicing unit is used to query the message header members that meet the output requirements from the storage space corresponding to each logic unit according to the FPGA preset output requirements after the last logic unit through which the message has completed the processing operation. The queryed message header members are then spliced ​​with the message payload to obtain the target message and output it.

[0087] As an example, N logic units are deployed in a predetermined order; the predetermined order is based on the functions required by the network device to which the FPGA belongs, and the processing steps performed by each logic unit.

[0088] Determining that this logical unit is the first logical unit through which the message passes includes:

[0089] If this logical unit is the first in the set sequence, then this logical unit is determined to be the first logical unit through which the message passes.

[0090] As an example, N logical units are deployed in a predetermined order; for any logical unit that is not the first in the predetermined order, the logical unit is pre-configured with at least one associated logical unit; wherein, when the logical unit performs the corresponding processing operation, it needs to base it on the processing result after the associated logical unit of the logical unit performs the corresponding processing operation.

[0091] Determining the target logical unit from the logical units through which the message passes includes:

[0092] Obtain the associated logical units that are related to this logical unit, and use the obtained associated logical units as the target logical unit.

[0093] As an example, the storage space configured in this FPGA for storing message payloads is different from the storage space corresponding to each logic unit;

[0094] The storage space configured in this FPGA for storing message payloads is managed in the form of random RAM.

[0095] The storage space corresponding to each logical unit manages the stored data in a first-in-first-out (FIFO) manner.

[0096] As an example, when the number of target logical units is greater than 1, the obtained message header members are processed according to the processing operation corresponding to this logical unit. This is executed after a set delay from the target time point corresponding to this logical unit. The target time point is the time point at which this logical unit determines the target logical unit from the logical units through which the message passes.

[0097] As one embodiment, the message splicing unit reuses the last logical unit through which the message passes. This application also provides a network device including the FPGA device provided in the above embodiment, thus completing... Figure 4 Structural description of the device shown.

[0098] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A message transmission method based on FPGA, characterized in that, The FPGA comprises a packet splicing unit and N logic units, each of which is used to perform a corresponding processing operation, different logic units perform different processing operations, and different logic units correspond to different storage spaces; the method comprises: Any logic unit, upon receiving a packet, If it is determined that the logic unit is the first logic unit via which the packet passes, the packet is split into a packet payload and N packet header members, the N packet header members are stored in the storage space corresponding to the logic unit, and the packet payload is stored in the storage space configured in the FPGA for storing packet payloads; If it is determined that the logic unit is not the first logic unit via which the packet passes, a target logic unit is determined from the logic units via which the packet passes, the storage space corresponding to the target logic unit stores packet header members related to the processing operation performed by the logic unit, packet header members are obtained from the storage space corresponding to the target logic unit and processed according to the processing operation corresponding to the logic unit, and the processed packet header members are stored in the storage space corresponding to the logic unit; The packet splicing unit, after the last logic unit via which the packet passes performs the processing operation, queries the packet header members that meet the output requirement from the storage space corresponding to each logic unit according to the output requirement preset by the FPGA, splices the obtained packet header members with the packet payload, obtains a target packet, and outputs the target packet.

2. The method of claim 1, wherein, The N logic units are arranged in a set order; the set order is set according to the function required to be implemented by the network device to which the FPGA belongs and the processing steps performed by each logic unit; The determination that the logic unit is the first logic unit via which the packet passes comprises: If the logic unit is the first one in the set order, it is determined that the logic unit is the first logic unit via which the packet passes.

3. The method of claim 1, wherein, The N logic units are arranged in a set order; for any non-first logic unit in the set order, the logic unit is preconfigured with at least one associated logic unit; when the logic unit performs the corresponding processing operation, it needs to be based on the processing result of the corresponding processing operation performed by the associated logic unit of the logic unit; The determination of the target logic unit from the logic units via which the packet passes comprises: An associated logic unit associated with the logic unit is obtained, and the obtained associated logic unit is taken as the target logic unit.

4. The method of claim 1, wherein, The storage space configured in the FPGA for storing packet payloads is different from the storage space corresponding to each logic unit; The storage space configured in the FPGA for storing packet payloads manages the stored data in a random RAM mode; The storage space corresponding to each logic unit manages the stored data in a first-in first-out FIFO mode.

5. The method of claim 1, wherein, When the number of the target logical units is greater than 1, the processing of the obtained packet header member according to the processing operation corresponding to the current logical unit is performed after a delay of a preset time length from a target time point corresponding to the current logical unit; the target time point is a time point at which the current logical unit determines the target logical unit from the logical units through which the packet passes.

6. The method of claim 1, wherein, The packet splicing unit queries the packet header member meeting the output requirement from the storage space corresponding to each logical unit after the last logical unit through which the packet passes completes the processing operation, and splices the queried packet header member with the packet payload to obtain a target packet and output the target packet.

7. An FPGA device, characterized by The FPGA comprises a packet splicing unit and N logical units, each of which is configured to perform a corresponding processing operation, different logical units perform different processing operations, and different logical units correspond to different storage spaces; Any logical unit is configured to, when receiving a packet, If it is determined that the current logical unit is the first logical unit through which the packet passes, the packet is split into a packet payload and N packet header members, the N packet header members are stored in the storage space corresponding to the current logical unit, and the packet payload is stored in the storage space configured in the FPGA for storing packet payloads; If it is determined that the current logical unit is not the first logical unit through which the packet passes, a target logical unit is determined from the logical units through which the packet passes, the packet header member stored in the storage space corresponding to the target logical unit is related to the processing operation performed by the current logical unit, the packet header member is obtained from the storage space corresponding to the target logical unit, and the obtained packet header member is processed according to the processing operation corresponding to the current logical unit, and the processed packet header member is stored in the storage space corresponding to the current logical unit; The packet splicing unit queries the packet header member meeting the output requirement from the storage space corresponding to each logical unit after the last logical unit through which the packet passes completes the processing operation, and splices the queried packet header member with the packet payload to obtain a target packet and output the target packet.

8. The apparatus of claim 7, wherein, The N logical units are arranged in a preset order; the preset order is set according to the function required to be implemented by the network device to which the FPGA belongs and the processing steps performed by each logical unit; The determination that the current logical unit is the first logical unit through which the packet passes comprises: If the current logical unit is the first one in the preset order, it is determined that the current logical unit is the first logical unit through which the packet passes; And / or, The N logical units are arranged in a preset order; for any non-first logical unit in the preset order, the logical unit is pre-configured with at least one associated logical unit; when the logical unit performs the corresponding processing operation, the processing result of the corresponding processing operation performed by the associated logical unit of the logical unit is used as a basis; The determination of the target logical unit from the logical units through which the packet passes comprises: An associated logical unit associated with the current logical unit is obtained, and the obtained associated logical unit is used as the target logical unit.

9. The apparatus of claim 7, wherein The storage space configured in the FPGA for storing the message payload is different from the storage space corresponding to each logical unit; The storage space configured in the FPGA for storing the message payload manages the stored data in a random RAM manner; The storage space corresponding to each logical unit manages the stored data in a first-in-first-out FIFO manner; And / or, When the number of the target logical units is greater than 1, the processing of the obtained message header member according to the processing operation corresponding to the current logical unit is performed after a delay of a set time length from a target time point corresponding to the current logical unit; the target time point is the time point when the current logical unit determines the target logical unit from each logical unit through which the message passes; And / or, The message splicing unit multiplexes the last logical unit through which the message passes.

10. A network device, comprising: An FPGA device as claimed in any one of claims 7 to 9.

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