Avoiding false nsn detection in flyback converters

Abstract

This document describes techniques for avoiding spurious negative sensing (NSN) detection in flyback AC-DC converters. In an exemplary embodiment, the secondary-side controller of the AC-DC converter includes a frequency detector, a negative sensing detector, and a control logic unit. The frequency detector is configured to determine the frequency of an input signal from the drain node of a synchronous rectifier (SR) circuit on the secondary side of the AC-DC converter. The negative sensing detector is configured to determine a negative voltage of the input signal. The control logic unit is configured to: enable the negative sensing detector when the frequency of the input signal rises above a frequency threshold; and turn on the SR circuit to transfer power to the secondary side of the AC-DC converter when the negative voltage of the input signal falls below a voltage threshold.

Description

[0001] priority

[0002] This application is an international application of U.S. Patent Application No. 16 / 704,975, filed December 5, 2019, which claims priority and benefit to U.S. Provisional Application No. 62 / 902,537, filed September 19, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to flyback AC-DC converters. Background Technology

[0004] An AC-DC converter converts power from an alternating current (AC) source into direct current (DC) at a specified voltage level. Typically, an AC-DC converter transfers power from an AC input coupled to the primary side of a transformer to a DC output coupled to the secondary side of the transformer. Some AC-DC converters operate in discontinuous conduction mode (DCM). In DCM mode, the converter stores power in its transformer during a conduction cycle on the primary (e.g., AC) side while the secondary (e.g., DC) side is off; the converter then transfers the stored power during a subsequent conduction cycle on the secondary side while the primary side is off.

[0005] A major problem with converters operating in DCM mode is spurious negative sensing (NSN) detection. Spurious NSN detection occurs when the secondary-side controller incorrectly interprets the resonant ringing on the primary side of the converter as a signal to turn on the secondary PS-FET to transfer power to the secondary side. However, if the secondary side is turned on while the primary side is still conducting, cross-conduction can lead to very high secondary-side currents, causing breakdown of the secondary-side transistors and diodes. Conventionally, blanking time (e.g., blanking NSN detection over a certain time interval) can be used as a solution to this problem. However, blanking time may not completely solve the problem, and unnecessary and untimely turning on of the secondary side during such blanking time, due to power being transferred through the rectifier diodes instead of the secondary PS-FET, results in power loss and reduces converter efficiency. Attached Figure Description

[0006] Figure 1 An AC-DC converter system with primary control according to an exemplary embodiment is shown.

[0007] Figure 2 A signal flow diagram for an AC-DC converter system used for primary control is shown.

[0008] Figure 3A schematic diagram of a capacitor model of a transformer in an AC-DC converter system according to some embodiments is shown.

[0009] Figure 4 A waveform diagram of the secondary side in an AC-DC converter system according to some embodiments is shown.

[0010] Figure 5 An exemplary primary control AC-DC converter system according to some embodiments is shown.

[0011] Figure 6 An exemplary method for avoiding false NSN detection in an AC-DC converter system with primary control, according to some embodiments, is shown.

[0012] Figure 7 The diagram shows simulation results for detecting high-frequency, inductor leakage ringing in an AC-DC converter system according to some embodiments.

[0013] Figure 8 An exemplary integrated circuit (IC) controller for an AC-DC converter system is shown according to some embodiments. Detailed Implementation

[0014] The following description sets forth numerous specific details, such as examples of specific systems, components, methods, etc., to provide a good understanding of various embodiments of the techniques described herein for avoiding spurious negative sensing (NSN) detection in flyback converters. However, it will be apparent to those skilled in the art that at least some embodiments can be practiced without these specific details. In other instances, well-known components, elements, or methods have not been described in detail or presented in a simple block diagram format to avoid unnecessarily obscuring the subject matter described herein. Therefore, the specific details set forth below are merely exemplary. Specific implementations may differ from these exemplary details and are still considered to be within the spirit and scope of the invention.

[0015] In the description, references to "embodiment," "one embodiment," "exemplary embodiment," "some embodiments," and "various embodiments" refer to specific features, structures, steps, operations, or characteristics described in connection with an embodiment that are included in at least one embodiment of the invention. Furthermore, the phrases "embodiment," "one embodiment," "exemplary embodiment," "some embodiments," and "various embodiments" appearing in various places in the specification do not necessarily refer to the same (one or more) embodiments.

[0016] This description includes reference to the accompanying drawings, which form part of the detailed description. The drawings illustrate embodiments according to exemplary embodiments. These embodiments, also referred to herein as “examples,” are described in sufficient detail to enable those skilled in the art to practice embodiments of the claimed subject matter described herein. Embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the claimed subject matter. It should be understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable those skilled in the art to practice, make, and / or use the subject matter.

[0017] Figure 1 An AC-DC converter 100 with primary control according to some embodiments is shown. The AC-DC converter 100 is a flyback converter that provides current isolation between an AC input 102 and a DC output 216. The AC-DC converter 100 includes a primary side 10 disposed on the AC input side of a transformer 106 and a secondary side 20 disposed on the DC output side of the transformer 106. An isolation barrier 150 with an isolation element 150a electrically isolates the primary side 10 from the secondary side 20. In primary control mode, the primary side of the transformer controls the operation of the converter because the only communication channel from the primary side to the secondary side is the voltage level provided by the transformer to the secondary side. The conduction cycles of the primary and secondary sides are typically separated by a time interval during which power stored in the transformer is transferred through rectifier diodes, resulting in higher power losses and reduced efficiency.

[0018] refer to Figure 1 The primary side 10 of the AC-DC converter 100 includes an AC input 102, a bridge rectifier 104, a transformer 106, a primary power switch (PS)-field-effect transistor (FET) 108, and a primary controller 110. The secondary side 20 includes a secondary controller 200, a synchronous rectifier (SR) circuit 210, a drain node (SR_DRAIN) 212, an output capacitor 214, and a Universal Serial Bus (USB) Type-C connector 220. On the primary side 10, the AC input 102 is configured to receive power from a power source (e.g., a wall socket). Figure 1(Not shown in the diagram) AC current. A bridge rectifier 104 is coupled between the AC input 102 and the transformer 106 to rectify the input voltage received at the AC input 102. The transformer 106 is coupled to conduct the AC current from the bridge rectifier 104 through its primary coil and primary PS-FET 108 to ground. A primary controller 110 is coupled to the gate of the PS-FET 108 to control the on-cycle and off-cycle of the transformer 106. On the secondary side 20, an SR circuit 210 is coupled between the secondary coil of the transformer 106 and the output capacitor 214. The SR circuit 210 includes a secondary PS-FET coupled in parallel with a diode, such that when the secondary PS-FET is turned on, an induced current flows to the drain node 212. The SR circuit 210 is configured to charge the output capacitor 214 (during successive on-cycles and off-cycles) so that the output capacitor can provide a stable voltage to the DC output 216. The DC output 216 is coupled to a power connector 220. Secondary controller 200 is coupled to drain node 212 of SR circuit 210 to sense the voltage (and its changes) on drain node. Secondary controller 200 is also coupled to the gate of secondary PS-FET in SR circuit 210 to turn SR circuit on and off based on voltage peak, negative voltage, and zero voltage crossover points sensed on drain node 212 (e.g., during corresponding on and off cycles).

[0019] A key element in determining the efficiency of an AC-DC converter (e.g., converter 100) is the operation of the secondary PS-FET switch (e.g., PS-FET 210) that controls the operating cycle of the SR circuit (e.g., SR circuit 210). In primary control mode, the secondary-side controller (e.g., controller 200) depends entirely on the voltage level of the drain node of the SR circuit (e.g., SR_DRAIN 212) because there is no other communication channel from the primary side (10) to the secondary side (20). In a typical operating scenario, the voltage at the SR_DRAIN node drops below -0.2V to instruct the secondary controller to turn on the secondary PS-FET. When the voltage at the SR_DRAIN node returns to 0V, the secondary-side controller detects this zero-voltage crossover and turns off the secondary PS-FET.

[0020] False NSN detection is a major problem for the secondary-side controller operating in a primary-controlled AC-DC converter environment. This false NSN detection occurs during resonant ringing when the converter operates in discontinuous conduction mode (DCM). During this resonant ringing, the voltage at the SR_DRAIN node of the SR circuit may drop below -200mV. This is incorrectly interpreted by the secondary-side controller as a valid NSN detection event, causing the secondary-side controller to turn on the secondary PS-FET of the SR circuit. This, in turn, leads to efficiency losses due to the unnecessary turn-on of the SR circuit, discharging the output load capacitor to ground. Furthermore, if the primary-side controller simultaneously turns on the primary PS-FET, cross-conduction occurs, where both the primary and secondary sides are turned on simultaneously. However, this cross-conduction can result in very high secondary-side currents, which can cause breakdown of diodes and transistor components in the SR circuit. Conventionally, blanking time can be used as a solution to this problem (e.g., blanking the NSN detection within a certain time interval). However, using this blanking time reduces the converter's efficiency because the secondary PS-FET is not turned on during this time, while the diodes in the SR circuit will carry peak current, resulting in power loss.

[0021] Figure 2 This is an exemplary signal diagram illustrating a false NSN detection problem (e.g., for an AC-DC converter with primary control operating in DCM mode). When the primary side is on (primary on-cycle), the primary PS-FET is on, the secondary PS-FET is off, and a primary current 105 flows through the primary winding of the transformer. When the secondary side is on (secondary on-cycle), the primary PS-FET is off, the secondary PS-FET is on, and a secondary current 211 flows to the drain node of the SR circuit. Figure 2 As shown, the primary conduction period and the secondary conduction period are separated by a blanking time interval of 107 in a conventional manner.

[0022] When the primary side is turned on, a leakage ringing event 109a occurs on the SR_DRAIN signal 213. A real NSN event 205a can be detected based on the output NSN signal (NSN_OUT) 205 at the end of the blanking interval 107 when the voltage on the SR_DRAIN signal 213 drops to approximately -0.7V. After the blanking interval 107, the primary side is turned off and the secondary side is turned on. The detection of the real NSN event 205a drives the control signal SR_DRV 209 high, which turns on the secondary PS-FET. As a result, the voltage on the SR_DRAIN signal rises and eventually crosses 0V. When this occurs, a zero-crossing detection (ZCD) event 207a can be detected based on the control signal ZCD_OUT 207, and the control signal SR_DRV 209 is driven low to turn off the secondary PS-FET. However, after ZCD event 207a, the voltage on SR_DRAIN signal 209 continues to rise and resonant ringing 213a occurs on it. This causes a false NSN detection event 205b to be detected on SR_DRAIN signal 213 based on NSN_OUT signal 205. The detection of this (false) NSN event 205b is used to drive control signal SR_DRV 209 high, which unnecessarily (i.e., incorrectly) turns on the secondary PS-FET.

[0023] To prevent such false turn-on of the secondary PS-FET, the techniques described herein provide methods for detecting real, genuine turn-on events on the primary side and avoiding spurious NSN detections. For example, the techniques described herein provide methods for detecting high-frequency ringing on the secondary-side SR drain node, which only occurs when the primary-side PS-FET is truly turned on. See below for more details. Figure 3 and Figure 4 As described, this ringing frequency is much higher than the resonant ringing frequency caused by spurious NSN events. Therefore, an AC-DC converter configured according to the technology described herein can distinguish between real and spurious NSN detection events.

[0024] Figure 3 A schematic diagram of the capacitor model of the transformer in an AC-DC converter is shown. Figure 3In the diagram, transformer 301 is shown coupled to parasitic element 303, which causes parasitic ringing at the SR_DRAIN node of the SR circuit on the secondary side. For example, the inter-winding capacitance of transformer 301 and the capacitances of different components connected to the AC-DC converter can be collectively modeled as parasitic capacitance Clump. The leakage energy from the primary side to the secondary side due to imperfect coupling is shown as leakage inductance Lleak. Whenever the primary PS-FET switch is turned on, leakage inductance Lleak and parasitic capacitance Clump create oscillatory behavior (e.g., inductor ringing) at the SR_DRAIN node. The frequency of inductor ringing, flek, is expressed as the following equation (1):

[0025]

[0026] Similarly, whenever the energy in the transformer becomes zero, a resonant ringing occurs at the SR_DRAIN node on the secondary side. The frequency of this resonant ringing, fdcm, is expressed by the following equation (2):

[0027]

[0028] Where Lp is the inductance of the primary coil of the transformer.

[0029] Typically, the leakage inductance Lleak is very small compared to the primary inductance Lp (e.g., less than 2%). Therefore, based on equations (1) and (2), it can be observed that the leakage frequency flek of the inductor ringing is very high compared to the resonant ringing frequency fdcm. The technique described herein utilizes the significant difference between the leakage frequency flek and the resonant ringing frequency fdcm to detect real primary-side turn-on events and distinguish between real and spurious NSN detection events. This is achieved in... Figure 4 As shown in the figure, Figure 4 The waveform of the voltage signal at the drain node (SR_DRAIN) of the SR circuit on the secondary side of the AC-DC converter is shown. Figure 4 As shown, the frequency of the inductor leakage ringing 401 is much higher than the frequency of the resonant ringing 403.

[0030] According to the technique described herein, the ringing frequency on the SR_DRAIN node of the SR circuit is measured in each cycle on the secondary side of the AC-DC converter. When the measured frequency is significantly higher than the expected resonant frequency (e.g., at least above a threshold amount), a signal is generated to enable NSN detection on the SR_DRAIN node. This effectively distinguishes real NSN events from spurious NSN events, thereby eliminating spurious turn-on of the secondary PS-FET.

[0031] Figure 5A converter 100 configured according to the technology described herein for avoiding spoofed NSN detection events is shown (e.g., such as...). Figure 1 AC-DC converter 100). Figure 5 In this embodiment, AC-DC converter 100 is a flyback converter that provides current isolation between AC input 102 and DC output 216. Converter 100 is a primary-controlled AC-DC converter operating in DCM mode. Various components of converter 100 may be disposed on one or more substrates (e.g., as a printed circuit board, PCB) enclosed in a suitable housing and coupled to each other. For example, in some embodiments, AC-DC converter 100 may be a power converter disposed within an electronic device. In other embodiments, AC-DC converter may be a standalone power supply for a portable electronic device.

[0032] refer to Figure 5 The converter 100 includes a primary side 10, an isolation barrier 150, and a secondary side 20. The primary side 10 controls the operation of the converter 100 because the only communication channel from the primary side 10 to the secondary side 20 is the voltage level provided to the secondary side by the transformer 106.

[0033] Among other components, the primary side 10 of converter 100 includes an AC input 102, a bridge rectifier 104, a transformer 106, a primary PS-FET 108, and a primary controller 110. The AC input 102 is configured to couple to a power source (e.g., a wall socket) that provides an AC voltage in the range of 85V to 265V. The bridge rectifier 104 is coupled to receive the input voltage from the AC input 102 and provide a rectified output voltage (VIN) to the primary winding of transformer 106. The primary winding of transformer 106 is coupled to conduct current from bridge rectifier 104 to ground through the primary PS-FET 108. The PS-FET 108 is a power switch, which may be implemented as one or more metal-oxide-semiconductor field-effect transistors (MOSFETs) or other suitable high-voltage / power semiconductor devices. The primary controller 110 is coupled to the gate of the PS-FET 108 to control the on and off cycles of transformer 106. In some embodiments, the primary controller 110 may be implemented as a single-chip integrated circuit (IC) controller fabricated on a semiconductor die. In other embodiments, the main controller 110 may be a single-chip IC fabricated as a system-on-a-chip (SoC). In still other embodiments, the main controller 110 may be a multi-chip module encapsulated in a single semiconductor package.

[0034] An isolation barrier 150, including isolation element 150a, is disposed between the primary side 10 and the secondary side 20 to electrically isolate the primary side from the secondary side. Isolation element 150a is an electronic circuit coupled to one or more input pins of the primary controller 110, coupled to the VBUS_IN line on the secondary side 20, and coupled to one or more output pins of the secondary controller 200. Isolation element 150a is configured to provide non-current feedback signals to the primary controller 110 to control the voltage level output on the VBUS line by the transformer 106.

[0035] For example, in some embodiments, isolation element 150a may be an opto-isolator circuit. The opto-isolator circuit includes a light-emitting element (e.g., a light-emitting diode (LED)) and a photosensitive element (e.g., a phototransistor). The LED has an anode coupled to the VBUS_IN line on the secondary side 20 via a voltage divider and a cathode directly coupled to the error amplifier output (EA_OUT) pin of the secondary controller 200. The cathode of the LED is also coupled to a feedback (FB) pin and a constant current compensation (CC_COMP) pin of the secondary controller 200 via one or more resistor-capacitor networks. The phototransistor of the opto-isolator circuit is coupled to an input pin of the primary controller 110 and is configured (e.g., within a suitable housing) to receive a light signal emitted from the LED. In operation, the secondary controller 200 uses the output signal from its EA_OUT pin to drive the LED to provide a light feedback signal regarding the voltage on the VBUS_IN line. The light feedback signal is provided to the primary controller 110 via the phototransistor in the opto-isolator element 150a. The primary controller 110 uses the received feedback signal to control the length of the conduction cycle of the primary side 10, thereby controlling the level of the voltage output from the secondary coil of the transformer 106 to the VBUS_IN line on the secondary side 20.

[0036] In another example, in some embodiments, isolation element 150a may be a pulse transformer circuit. The pulse transformer circuit includes a pulse transformer coupled between the pulse width modulation drive (PWM_DRV) pin of the secondary controller 200 and the input pin of the primary controller 110. The signal output on the PWM_DRV pin of the secondary controller 200 reflects the voltage on the VBUS_IN line on the secondary side 20. In operation, the signal output on the PWM_DRV pin is provided to the primary coil of the pulse transformer, which induces a corresponding signal (to the secondary coil of the pulse transformer), which is provided as a feedback signal to the primary controller 110. The primary controller 110 uses the pulse width of the received feedback signal to operate the primary PS-FET 108 and control the length of the on-cycle of the primary side 10, thereby controlling the level of the voltage output through the secondary coil of the transformer 106 to the VBUS_IN line on the secondary side 20.

[0037] Among other components, the secondary side 20 of converter 100 includes a secondary controller 200, a synchronous rectifier (SR) circuit 210, a drain node (SR_DRAIN) 212, and an output capacitor 214. The SR circuit 210 is coupled between the secondary winding of transformer 106 and the output capacitor 214. The SR circuit 210 includes a secondary PS-FET coupled in parallel with a diode, such that when the secondary PS-FET is turned on, induced current flows to the drain node 212. The secondary PS-FET in the SR circuit 210 is a power switch, which can be implemented as one or more MOSFETs or other suitable high-voltage / power semiconductor devices. The drain node 212 of the SR circuit 210 is coupled to an input pin (e.g., terminal) 201 of the secondary controller 200, and the gate of the secondary PS-FET in the SR circuit is coupled to an output pin 209 of the secondary controller.

[0038] Secondary controller 200 is configured to sense the voltage (and its changes) at drain node 212. Secondary controller 200 is also configured to control the gate of the secondary PS-FET of SR circuit 210 by providing a control signal (SR_GDRV) on its output pin 209. In some embodiments, secondary controller 200 may be implemented as a single-chip IC controller fabricated on a semiconductor die. In other embodiments, secondary controller 200 may be a single-chip IC fabricated as a system-on-a-chip (SoC). In still other embodiments, secondary controller 200 may be a multi-chip module encapsulated in a single semiconductor package.

[0039] Under the control of the secondary controller 200, the SR circuit 210 operates to charge the output capacitor 214 during successive on and off cycles. The output capacitor 214 is configured to act as a filter to provide a DC voltage to the DC output 216. For example, during the on-cycle of the primary side 10 and the off-cycle of the secondary side 20 (e.g., when PS-FET 108 is closed and the secondary PS-FET in the SR circuit 210 is open), a magnetic field is established in the transformer 106, while the current on the primary side 10 increases linearly. During the off-cycle of the primary side 10 and the on-cycle of the secondary side 20 (e.g., when PS-FET 108 is open and the secondary PS-FET in the SR circuit 210 is closed), the magnetic field established in the transformer 106 begins to collapse, and a current is induced in the secondary coil of the transformer as power is transferred to the output capacitor 214. During the secondary-side conduction cycle, the current in the secondary side 20 remains stable but gradually decreases until it reaches a point where the current flowing through the drain node 212 is essentially zero. In this way, the output capacitor 214 is charged in successive cycles to provide a stable DC voltage to the DC output 216.

[0040] DC output 216 is coupled to supply DC voltage to electronic devices or other loads. For example, in some embodiments, the nominal DC voltage supplied on DC output 216 may be in the range of 3.3V (or 5V) to 20V. Furthermore, in some embodiments, DC output 216 may be coupled as an internal power supply for electronic devices. In other embodiments, DC output 216 may be coupled to a power connector (…). Figure 5 (not shown) for use in providing power to portable electronic devices. In one such embodiment (e.g., as...) Figure 1 As shown), the power connector can be a USB Type-C connector (220) configured according to the USB Type-C specification. The USB Type-C specification defines a Type-C receptacle, a Type-C plug, and a Type-C cable, which can support USB communication and power delivery (PD) through protocols defined in various revisions / versions of the USB-PD specification. According to the USB Type-C specification, the Type-C connector port (e.g., a Type-C receptacle or Type-C plug) provides VBUS power lines, DP (D+) and DM (D-) data lines, and a GND ground return line, etc. In addition, the Type-C connector port provides two configuration channel lines (CC1 and CC2) for discovering, configuring, and managing connections via the Type-C cable. Figure 1As shown in the embodiment, the USB Type-C connector 220 provides a VBUS line (VBUS_IN), a GND line, CC1 and CC2 lines, and DP and DM data lines. The VBUS_IN line is coupled to a corresponding input pin of the secondary controller 200 to provide a power signal (VBUS_IN), while the GND line is coupled to a corresponding pin of the secondary controller to provide a control signal (SR_VSS) from the source node of the SR circuit 210. The VBUS_IN line includes a power switch, which is implemented as an on / off semiconductor device controlled by a control signal (VBUS_CTRL) provided from an output pin of the secondary controller 200. The CC1, CC2, DP, and DM lines of the USB Type-C connector 220 are coupled to corresponding pins of the secondary controller 200.

[0041] Return to reference Figure 5 The secondary controller 200 in the AC-DC converter 100 is configured, according to the techniques described herein, to avoid spurious NSN detection. The secondary controller 200 includes a control logic unit 208 coupled to receive power from an external source via a power pin (VDDD). As used herein, a "logic unit" refers to a block of hardware having one or more circuits, including various electronic components configured to process analog and / or digital signals and perform one or more operations in response to control signals(s). Examples of such electronic components include, but are not limited to, transistors, diodes, resistors, capacitors, inductors, logic gates, and various circuits thereof. The control logic unit 208 is coupled to provide a control signal (SR_GDRV) to the SR circuit 210 via pin 209. The control signal SR_GDRV is applied to the gate of the PS-FET in the SR circuit 210 to turn the SR circuit on and off. The control logic unit 208 may also include circuitry for receiving a high-frequency clock signal, which serves as a reference to determine when the frequency of a signal from the SR_DRAIN node 212 is higher than a predetermined frequency threshold.

[0042] The secondary controller 200 also includes a frequency detector 202, a negative voltage detector 204, and a zero voltage detector 206, which are coupled to the SR_DRAIN node 212 via pin 201. A voltage divider with an 8K external resistor and a 2K internal resistor is coupled at input pin 201 to generate a voltage divider input signal (SR_SNS), which is provided to the frequency detector 202, the negative voltage detector 204, and the zero voltage detector 206. The output terminals of the frequency detector 202, the negative voltage detector 204, and the zero voltage detector 206 are coupled to the control logic unit 208.

[0043] Frequency detector 202 (also known as a "peak detector") is a circuit that includes diode 202a, reference capacitor 202b, high-speed comparator 202c, and digital counter 202d. Frequency detector 202 may also include a control terminal coupled to receive an enable signal from control logic unit 208. Figure 5 (Not shown in the diagram). Reference capacitor 202b is coupled between diode 202a and the non-inverting terminal of comparator 202c. The inverting terminal of comparator 202c is coupled to receive the SR_SNS input signal from SR_DRAIN node 212. Diode 202a is also coupled to receive the SR_SNS input signal. Counter 202d may be a register or other element suitable for storing digital counts. Frequency detector 202 is configured to detect the peak point of any oscillating signal on SR_DRAIN node 212, and the difference between two consecutive peaks can be used to determine the frequency of the oscillation. For example, comparator 202c outputs a high signal to counter 202d, and control logic unit 208 uses the count stored in counter 202d to determine the frequency of the SR_SNS input signal from SR_DRAIN node 212.

[0044] In some embodiments, the secondary controller 200 may include hardware components that can operate in both primary control mode and secondary control mode. In secondary control mode, the AC-DC converter 100 also includes electronic components (e.g., an opto-isolator circuit with light-emitting diodes and phototransistors, or a PWM circuit with a pulse width modulation (PWM) ramp generator and pulse transformer) that provide a non-current feedback path to the primary controller 110, allowing the secondary controller 200 to pass control signals to the primary controller and control its operation. In such embodiments, to implement either primary or secondary control operation mode of the secondary controller 200, the control logic unit 208 is configured to provide an enable signal (SR_ONLY) 203 to a switch coupled to diode 202a. In primary control mode, the control logic unit 208 continuously applies the SR_ONLY enable signal 203 to the switch, thus continuously providing the SR_SNS input signal to the frequency detector 202.

[0045] The negative sensing detector 204 is a circuit that includes a comparator 204. The inverting terminal of the comparator 204 is coupled to receive the SR_SNS input signal from the SR_DRAIN node 212. The non-inverting terminal of the comparator 204 is coupled to a finely adjustable voltage reference source (e.g., at -70mV or below). The negative sensing detector 204 may also include a control terminal coupled to receive an enable signal from the control logic unit 208. Figure 5(Not shown in the diagram). The output of the negative sensing detector 204 is coupled to provide an output signal to the control logic unit 208. For example, the negative sensing detector 204 is configured to provide a high output signal when the negative voltage of the SR_SNS input signal drops below a certain voltage threshold (e.g., -200mV).

[0046] Zero-voltage detector 206 is a circuit that includes comparator 206. The non-inverting terminal of comparator 206 is coupled to receive the SR_SNS input signal from SR_DRAIN node 212. The inverting terminal of comparator 206 is coupled to a zero-voltage reference source, Vgnd_sense (e.g., at 0V). Zero-voltage detector 206 may also include a control terminal coupled to receive an enable signal from control logic unit 208. Figure 5 (Not shown in the diagram). The output of zero-voltage detector 206 is coupled to provide an output signal to control logic unit 208. For example, zero-voltage detector 206 is configured to provide a high output signal when the voltage of the SR_SNS input signal reaches 0V from a previous negative voltage value.

[0047] In operation according to the technique described herein, frequency detector 202 and control logic unit 208 measure the ringing frequency at SR_DRAIN node 212 of SR circuit 210 in each cycle on the secondary side 20 of converter 100. When the measured frequency is higher than a frequency threshold (e.g., ten times the expected resonant frequency, or 10*fdcm), control logic unit 208 enables negative sensing detector 204. For example, control logic unit 208 may apply an enable signal to negative sensing detector 204 or (e.g., if the negative sensing detector is configured for continuous operation) may simply turn on the output of the negative sensing detector. In this way, negative sensing detector 204 is only turned on after high-frequency (e.g., inductor leakage) ringing is detected at SR_DRAIN node 212, thereby indicating a true turn-on event for master controller 110. When enabled, negative sensing detector 204 operates to sense a negative voltage from the SR_SNS input signal from SR_DRAIN node 212. When the negative voltage of the SR_SNS input signal drops below a certain voltage threshold (e.g., -200mV), the negative sensing detector 204 outputs a high signal to the control logic unit 208. In response, the control logic unit 208 turns on the secondary PS-FET of the SR circuit 210 to transfer power to the secondary side 20 of the converter 100. Thereafter (e.g., after turning on the SR circuit), the control logic unit 208 disables the negative sensing detector 204 (and / or its output signal). When the voltage on the SR_DRAIN node 212 returns from its previous negative voltage level to 0V, the zero-voltage detector 206 detects the zero-crossing event and outputs a high signal to the control logic unit 208. In response, the control logic unit 208 turns off the PS-FET switch in the SR circuit 210 by applying the appropriate control signal SR_GDRV to the output pin 209. However, because the negative sensing detector 204 is disabled before and during the zero-crossing event, the detection of a possible (false) NSN event by the negative sensing detector is avoided.

[0048] Figure 6 A method 600 for avoiding false NSN detection in an AC-DC converter with primary control, according to an exemplary embodiment, is shown. Figure 6 The operation of method 600 is described as consisting of a frequency detector, an NSN detector, and a control logic unit (e.g., frequency detector 202, negative sensing detector 204, and...). Figure 5 The control logic unit 208) executes the method. However, it should be noted that various implementations and embodiments may use various and potentially different hardware components to perform the operation of method 600. Therefore, the following description of method 600 is considered illustrative rather than restrictive.

[0049] According to the technique described herein, method 600 is performed based on the input signal from the drain node of the SR circuit on the secondary side of the AC-DC converter operated in DCM mode under primary control.

[0050] In operation 602, the control logic unit in the secondary controller of the AC-DC converter resets the frequency counter to 0. In operation 604, the control logic unit enables the frequency detector and routes the output of the frequency detector to the frequency counter. In some embodiments, the secondary controller may include hardware components that can operate in both primary and secondary control modes. In such embodiments, the primary control mode is enabled within the secondary controller prior to operations 602 and 604. For example, the control logic unit may continuously apply enable signals to the frequency detector to ensure that the secondary controller receives input signals from the drain node of the SR circuit.

[0051] In operation 606, the control logic unit disables its NSN detector. For example, the control logic unit may apply a disable signal to the NSN detector. If the NSN detector is configured for continuous operation, the control logic unit may shut down its circuitry that receives output signals from the NSN detector.

[0052] In operation 608, the frequency detector determines the frequency of the input signal received from the drain node of the SR circuit, and the control logic unit continuously monitors the output of the frequency detector. For example, the control logic unit can be configured to continuously receive the output signal from the peak detection comparator in the frequency detector. When the output of the peak detection comparator is low, the control logic unit proceeds to operation 606 to disable the NSN detector. However, when the output of the peak detection comparator is high, in operation 610, the control logic unit samples the output from the frequency counter (e.g., at a sampling frequency of 1 MHz).

[0053] In operation 612, the control logic unit compares the sampling frequency with a frequency threshold. According to the techniques described herein, the frequency threshold is based on the expected resonant frequency of the input signal from the drain node of the SR circuit. In some embodiments, the frequency threshold may be equal to ten times the expected resonant frequency (e.g., 10 * fdcm), but it should be noted that different frequency thresholds may be used in various embodiments depending on the specific type of converter and the circuitry therein.

[0054] If the control logic unit determines in operation 612 that the sampling frequency is not greater than the frequency threshold, the control logic unit resets the frequency counter to 0 in operation 614, and then continues to operation 606 to disable the NSN detector.

[0055] If, in operation 612, the control logic unit determines that the sampling frequency is greater than a frequency threshold, then the control logic unit determines that a genuine on-event has been detected on the primary side of the AC-DC converter. The control logic unit then proceeds to operation 616 to enable the NSN detector. For example, in response to determining that the sampling frequency is greater than the frequency threshold, the control logic unit may apply an enable signal to the NSN detector to turn it on. If the NSN detector is configured for continuous operation, then in operation 616, in response to determining that the sampling frequency is greater than the frequency threshold, the control logic unit may activate its circuitry for receiving the output signal from the NSN detector.

[0056] In operation 618, the control logic unit monitors the output signal from the NSN detector. If the output signal from the NSN detector is low, the control logic unit returns to operation 616 to ensure that the NSN detector remains enabled.

[0057] If, in operation 618, the control logic unit detects that the output signal from the NSN detector is high, it determines that the voltage of the input signal from the drain node of the SR circuit has dropped below a certain voltage threshold (e.g., -200mV). This instructs the control logic unit to turn on the SR circuit. Therefore, in operation 620, the NSN detector output signal is provided to the internal hardware circuitry of the control logic unit (e.g., synthesized RTL), which applies an enable signal to the gate of the PS-FET in the SR circuit to turn it on. Furthermore, in response to detecting a high level output signal from the NSN detector, the control logic unit proceeds to operation 614 to reset the frequency counter to 0, and then performs operation 606 to disable the NSN detector.

[0058] In this way, the NSN detector is only enabled after a genuine on-time event is detected on the primary side of the AC-DC converter, and remains disabled the rest of the time. Operating the NSN detector in this manner ensures that spurious NSN events are avoided.

[0059] Figure 7 A simulation result diagram for detecting high-frequency ringing is shown. The top portion of the diagram shows inductor leakage ringing on the SR_DRAIN input signal when the primary side of the AC-DC converter is turned on. The bottom portion of the diagram shows the output signal from the peak detection comparator of the frequency detector according to the technique described herein. As shown in the bottom portion of the diagram, the output signal from the peak detector can be used to detect inductor leakage ringing oscillating at 17.2 MHz on the SR_DRAIN signal.

[0060] The technique described herein provides a method for detecting genuine turn-on events on the primary side of an AC-DC converter, thereby improving efficiency and avoiding spurious turn-on of the PS-FET in the SR circuit on the secondary side of the converter. This is achieved by detecting high-frequency inductor leakage ringing at the drain node of the SR circuit, which occurs whenever the PS-FET on the primary side is turned on. This inductor leakage ringing occurs at a frequency much higher than the resonant ringing caused by spurious NSN events. Furthermore, by detecting genuine turn-on events on the primary side, the technique described herein does not require a blanking time for NSN turn-off detection. The technique described herein also provides improved operational reliability, as no cross-conduction will occur since the secondary PS-FET will not be turned on during spurious NSN events. Additionally, based on the actual primary turn-on detection signal, a feedforward scheme can be enabled on the secondary side of the converter to sense the VIN voltage supplied to the transformer on the primary side of the converter. This voltage information, in turn, can be used to modify internal parameters to further optimize converter efficiency.

[0061] Figure 8 An exemplary semiconductor device configured according to the technique used to avoid spoofed NSN detections described herein is shown. Figure 8 In the illustrated embodiment, device 800 is a single-chip IC controller fabricated on a semiconductor die. In another example, IC controller 800 may be a single-chip IC fabricated as a system-on-a-chip (SoC). In other embodiments, IC controller 800 may be a multi-chip module encapsulated in a single semiconductor package. In various operational contexts, IC controller 800 can be used as... Figure 1 and Figure 5 The secondary controller 200 in the AC-DC converter system 100.

[0062] refer to Figure 8 The IC controller 800 includes a CPU subsystem 802, peripheral interconnects 814, system resources 816, input / output (I / O) subsystem 818, USB-PD subsystem 820, and various terminals (e.g., pins) configured to receive and transmit signals.

[0063] CPU subsystem 802 includes one or more CPUs (Central Processing Units) 804, flash memory 806, SRAM (Static Random Access Memory) 808, and ROM (Read-Only Memory) 810 coupled to system interconnect 812. CPU 804 is a suitable processor that can operate in an IC or SoC device. Flash memory 806 is non-volatile memory (e.g., NAND flash, NOR flash, etc.) configured to store data, programs, and / or other firmware instructions. Flash memory 806 is tightly coupled within CPU subsystem 802 to improve access time. SRAM 808 is volatile memory configured to store data and firmware instructions accessed by CPU 804. ROM 810 is read-only memory (or other suitable storage medium) configured to store boot routines, configuration parameters, and other firmware parameters and settings. System interconnect 812 is a system bus (e.g., a single-level or multi-level high-performance bus, or AHB) configured as an interface for coupling various components of CPU subsystem 802 to each other, and as a data and control interface between various components of CPU subsystem and peripheral interconnect 814.

[0064] Peripheral interconnect 814 is a peripheral bus (e.g., a single-level or multi-level AHB) that provides the primary data and control interface between CPU subsystem 102 and its peripheral devices and other resources (e.g., system resource 816, I / O subsystem 818, and USB-PD subsystem 820). Peripheral interconnect 814 may include various controller circuitry (e.g., direct memory access or DMA controllers) that can be programmed to transfer data between peripheral blocks without burdening CPU subsystem 802. In various embodiments, each component of the CPU subsystem and the peripheral interconnect may differ depending on the choice or type of CPU, system bus, and / or peripheral bus.

[0065] System resource 816 includes various electronic circuits that support the operation of IC controller 800 in its various states and modes. For example, system resource 816 may include a power subsystem with analog and / or digital circuitry required for each controller state / mode (e.g., sleep control circuitry, wake-up interrupt controller (WIC), power-on reset (POR), voltage and / or current reference (REF) circuitry, etc.). In some embodiments, the power subsystem may also include circuitry that allows IC controller 800 to draw power from and / or supply power to external sources having several different voltage and / or current levels, and supports controller operation in several power states 817 (e.g., active state, sleep state, and deep sleep state with clock off). Furthermore, in some embodiments, CPU subsystem 802 may be optimized for low-power operation with extensive clock gating and may include various internal controller circuitry that allows the CPU to operate in various power states 817. For example, the CPU may include a wake-up interrupt controller configured to wake the CPU from a sleep state, thereby allowing power to be turned off when the IC chip is in a sleep state. System resource 816 may also include a clock subsystem with analog and / or digital circuitry for clock generation and clock management, such as clock control circuitry, watchdog timer (WDT) circuitry, internal low-speed oscillator (ILO) circuitry, and internal master oscillator (IMO) circuitry. System resource 816 may also include analog and / or digital circuitry blocks that provide reset control and support external reset (XRES).

[0066] The I / O subsystem 818 includes several different types of I / O blocks and subsystems. For example, the I / O subsystem 818 includes a GPIO (General Purpose Input / Output) block 818a, a TCPWM (Timer / Counter / Pulse Width Modulation) block 818b, and an SCB (Serial Communication Block) 818c. The GPIO 818a includes analog and / or digital circuitry configured to implement various functions, such as pull-up / pull-down, input threshold selection, input and output buffer enable / disable, and multiplexing signals connected to various I / O pins. The TCPWM 818b includes analog and / or digital circuitry configured to implement timers, counters, pulse width modulators, decoders, and various other analog / mixed-signal elements configured to operate on input / output signals. The SCB 818c includes analog and / or digital circuitry configured to implement various serial communication interfaces, such as I... 2 C. SPI (Serial Peripheral Interface), UART (Universal Asynchronous Receiver / Transmitter), CAN (Controller Area Network) interface, CXPI (Clock Extended Peripheral Interface), etc.

[0067] The USB-PD subsystem 820 provides an interface to power connectors such as USB Type-C ports. As used herein, "USB-PD subsystem" refers to one or more logic blocks and other analog / digital hardware circuitry that can be controlled by firmware and configured and operable to perform functions and meet the requirements specified in at least one version of the USB-PD specification. The USB-PD specification defines a standard protocol designed to enable the full functionality of USB-enabled devices by providing more flexible power delivery and data communication via a single USB Type-C cable through a USB Type-C port. The USB-PD specification also describes the architecture, protocols, power behaviors, parameters, and cable routing necessary for managing power delivery over a USB Type-C cable (e.g., up to 5A of current at up to 20V for a total power of up to 100W). The USB-PD specification also defines requirements for a power delivery contract (PD contract) that can be negotiated between a pair of USB-enabled devices. The PD contract can specify the power levels and power delivery directions that the two devices can accommodate and can be dynamically renegotiated (e.g., without unplugging the devices).

[0068] In other circuitry, the USB-PD subsystem 820 may include: one or more analog-to-digital converters (ADCs) for converting various analog signals into digital signals; an error amplifier (ERROR AMP) for controlling the supply voltage applied to the VBUS line for each PD contract; a current sensing amplifier (CSA) and overvoltage protection (OVP) circuitry for providing overcurrent and overvoltage protection on the VBUS line with configurable thresholds and response times; a communication channel PHY (CC BB PHY) logic unit for supporting communication on the Type-C communication channel (CC) line; a charge detector logic block (CHRG DET) connected to the DP and DM lines for detecting conventional battery chargers conforming to various standards and proprietary battery charging specifications; at least two die-on discharge (VBUS DISCH) circuitry capable of discharging the VBUS line voltage to any range within a programmable voltage level range; one or more gate drivers (GATE DRV) for controlling the power switch that turns on and off the power supply through the VBUS line; and a high-voltage regulator (HV). REG), which is used to convert the power supply voltage to the precise voltage (e.g., 3-5V) required to power the IC controller 800; and the short-circuit protection block (SCP), which is used to perform additional short-circuit detection across an external resistor coupled to the ground return path.

[0069] According to the techniques described herein for avoiding spurious NSN detection, the USB-PD subsystem 820 includes an SR sensing logic block (SR SENSE) and an SR driver logic block (SR DRV). According to the techniques described herein, the SR sensing logic block includes: a frequency detector for determining the frequency of an input signal from the drain node of the SR circuit of the AC-DC converter; a negative sensing detector for providing a high output signal when the negative voltage at the drain node of the SR circuit drops below a certain voltage threshold; and a ZCD detector for providing a high output signal when the voltage at the drain node of the SR circuit reaches 0V from a previous negative voltage value. The SR driver logic block includes a control logic unit configured to drive the gate of the PS-FET of the SR circuit based on signals from the frequency detector, the negative sensing detector, and the ZCD detector, according to the techniques described herein.

[0070] The various embodiments of the techniques described herein for avoiding spurious NSN detection in flyback AC-DC converters may include a variety of operations. These operations may be performed and / or controlled by hardware components, digital hardware and / or firmware, and / or combinations thereof. As used herein, the term “coupled to” may mean a direct connection or an indirect connection via one or more intermediate components. Any signal provided via various on-die buses may be time-multiplexed with other signals and provided via one or more common on-die buses. Furthermore, interconnections between circuit components or blocks may be represented as buses or single signal lines. Each bus may alternatively be one or more single signal lines, and each of the single signal lines may alternatively be a bus.

[0071] Some embodiments can be implemented as a computer program product that may include instructions stored on a non-transitory computer-readable medium (e.g., volatile memory and / or non-volatile memory). These instructions may be used to program and / or configure one or more devices, including a processor (e.g., CPU) or its equivalents (e.g., processing core, processing engine, microcontroller, etc.), such that, when executed by the processor or its equivalents, the instructions cause the devices(s) to perform the operations described herein for the USB-C power architecture. The computer-readable medium may also include one or more mechanisms for storing or transferring information in a machine-readable form (e.g., software, processing applications, etc.), such as a device or computer. Non-transitory computer-readable storage media may include, but are not limited to, electromagnetic storage media (e.g., floppy disks, hard disks, etc.), optical storage media (e.g., CD-ROMs), magneto-optical storage media, read-only memory (ROM), random access memory (RAM), erasable programmable memory (e.g., EPROM and EEPROM), flash memory, or another now-known or later-developed medium suitable for storing information.

[0072] Although the operations of the circuits and blocks herein are shown and described in a specific order, in some embodiments, the order of operations of each circuit / block may be changed, so that certain operations can be performed in reverse order or that certain operations can be performed at least partially simultaneously and / or in parallel with other operations. In other embodiments, instructions or sub-operations of different operations may be performed in an intermittent and / or alternating manner.

[0073] The invention has been described in the foregoing specification with reference to specific exemplary embodiments thereof. However, it will be apparent that various modifications and alterations can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

Claims

1. An integrated circuit (IC) controller for the secondary side of an AC-DC converter, the integrated circuit controller comprising: A terminal for receiving input signals from the drain node of the synchronous rectifier (SR) circuit on the secondary side of the AC-DC converter; A frequency detector configured to determine the frequency of the input signal from the drain node of the synchronous rectifier circuit; A negative sensing detector is configured to determine the negative voltage of the input signal from the drain node of the synchronous rectifier circuit; as well as The control logic unit is configured as follows: When the frequency of the input signal rises above a frequency threshold, the negative sensing detector is activated; and When the negative voltage of the input signal drops below a voltage threshold, the synchronous rectifier circuit is turned on to transfer power to the secondary side of the AC-DC converter.

2. The integrated circuit controller according to claim 1, wherein, The control logic unit is configured to detect that the primary side of the AC-DC converter is turned on when the frequency of the input signal rises above the frequency threshold.

3. The integrated circuit controller according to claim 1, wherein, The control logic unit is configured to disable the negative sensing detector when the negative voltage of the input signal drops below the voltage threshold.

4. The integrated circuit controller of claim 1 further includes a zero-voltage detector, the zero-voltage detector being configured to output a high signal when the voltage of the input signal rises above 0V.

5. The integrated circuit controller according to claim 4, wherein, The control logic unit is configured to shut down the synchronous rectifier circuit in response to receiving a high signal from the zero-voltage detector.

6. The integrated circuit controller according to claim 1, wherein, The AC-DC converter is configured to operate in discontinuous conduction mode (DCM).

7. The integrated circuit controller according to claim 1, wherein, The AC-DC converter is configured to operate in primary control mode.

8. The integrated circuit controller according to claim 7, wherein, The control logic unit is configured to apply an enable signal to operate the frequency detector in the primary control mode.

9. A method of operating a secondary-side controller for an AC-DC converter in discontinuous conduction mode (DCM), the method comprising: Receives input signals from the drain node of the synchronous rectifier (SR) circuit on the secondary side of the AC-DC converter; Determine the frequency of the input signal from the drain node of the synchronous rectifier circuit; When the frequency of the input signal rises above a frequency threshold, the following operations are performed: Determine the negative voltage of the input signal; as well as When the negative voltage of the input signal drops below a voltage threshold, the synchronous rectifier circuit is turned on to transfer power to the secondary side of the AC-DC converter.

10. The method of claim 9, further comprising: When the frequency of the input signal rises above the frequency threshold, the primary side of the AC-DC converter is detected to be turned on.

11. The method of claim 9, further comprising: When the negative voltage of the input signal drops below the voltage threshold, the determination of the negative voltage of the input signal is disabled.

12. The method according to claim 9, further comprising: When the frequency of the input signal is at or below the frequency threshold, the determination of the negative voltage of the input signal is abandoned.

13. The method of claim 9, further comprising: Detect when the input signal rises above 0V; as well as In response to the detection that the input signal has risen above 0V, the synchronous rectifier circuit is turned off.

14. The method of claim 9, further comprising: Enable the determination of the frequency of the input signal.

15. An alternating current (AC) to direct current (DC) converter system configured to operate in discontinuous conduction mode (DCM), the system comprising: A transformer, which is coupled to receive rectified AC input; A primary-side integrated circuit (IC) controller is coupled to control the operation of the transformer; A connector that couples to an output capacitor that provides DC output; A synchronous rectifier (SR) circuit is coupled between the output capacitor and the transformer; as well as A secondary-side integrated circuit controller, coupled to control the operation of the synchronous rectifier circuit, wherein the secondary-side integrated circuit controller includes: Terminals, which are coupled to receive input signals from the drain node of the synchronous rectifier circuit; A frequency detector configured to determine the frequency of the input signal from the drain node of the synchronous rectifier circuit; A negative sensing detector, configured to determine the negative voltage of the input signal from the drain node of the synchronous rectifier circuit; and The control logic unit is configured as follows: When the frequency of the input signal rises above a frequency threshold, the negative sensing detector is activated; and When the negative voltage of the input signal drops below a voltage threshold, the synchronous rectifier circuit is turned on to transfer power to the output capacitor.

16. The system according to claim 15, wherein, The secondary-side integrated circuit controller further includes a zero-voltage detector configured to output a high signal when the voltage of the input signal rises above 0V, and wherein the control logic unit is further configured to shut down the synchronous rectifier circuit in response to receiving the high signal from the zero-voltage detector.

17. The system according to claim 15, wherein, The rectified AC input is generated from an AC voltage in the range of 85V to 265V.

18. The system according to claim 15, wherein, The DC output provides a nominal DC voltage in the range of 3.3V to 20V.

19. The system according to claim 15, wherein, The connector is a Universal Serial Bus (USB) Type-C connector.

20. The system according to claim 15, wherein, The system is one of the following: Power converters installed within electronic devices; and Power converters for portable electronic devices.

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