Chip-level protocol stack computing task offloading method and device for thread network border router

Abstract

A chip-level protocol stack computing task offloading method and device for a Thread network border router, the method comprising: (1) the data link layer to the network layer of the protocol stack of the host chip is divided into 5 different levels, numbered from top to bottom as 1 to 5; (2) for the protocol stack divided in step (1), when sending a data packet, the task passing time in the 5 levels of the host chip and the task passing time in the radio frequency chip are recorded in the case of no computing task offloading; (3) the necessity of offloading is judged according to the time recorded in step (2); (4) if it is judged in step (3) that offloading is not needed, the task does not perform computing task offloading this time, and if it is judged in step (3) that offloading is needed, the best offloading point is found through an overhead function and offloading is performed. The protocol stack part computing task is dynamically migrated between two chips through chip-level optimization, the network signal unpacking and flow control computing actions are performed, the network traffic processing capacity per unit time is improved, and a larger scale robust stable adaptive network is formed.

Description

TECHNICAL FIELD

[0001] The present application provides a chip-level protocol stack computing task offloading method for a Thread network border router. TECHNICAL BACKGROUND

[0002] Thread network is a wireless network protocol based on IPv6 designed for low-power Internet of Things devices. It is based on IEEE 802.15.4 wireless technology and uses 6LoWPAN technology to adapt to low-bandwidth, low-power wireless network environments. The features of Thread network include easy deployment and maintenance, communication security, stability and reliability, low power consumption, scalability, and bidirectional communication service discovery and connection.

[0003] An important role in Thread network is the border router, which can forward information between Thread network and non-Thread network (such as Wi-Fi). It also undertakes the function of configuring Thread network for external connection and access.

[0004] The current mainstream Thread border router uses the design idea of RCP (radio co-processor), that is, the physical layer is deployed in the radio frequency chip, and the physical layer above is deployed in the main control chip, and one main control chip can connect multiple radio frequency chips. When the main control chip is connected to a large number of radio frequency chips at the same time and there is a large amount of network traffic, the computational task load in the main control chip needs to be processed, resulting in an increase in end-to-end delay. SUMMARY

[0005] In order to solve the problem that the Spinel layer transmission rate between the main control chip and the radio frequency chip becomes a performance bottleneck, the present application provides a chip-level protocol stack computing task offloading method for a Thread network border router.

[0006] In a low-load case, the Thread protocol core runs in the main control chip. Due to the strong performance of the main control chip, the network layer can use more complex routing algorithms to ensure the delay of data transmission. When the network traffic increases, the computing power of Spinel and the main control chip encounters a bottleneck. At this time, the main control chip will try to offload part of the protocol stack computing task to the radio frequency chip. Whether to offload the computing task and the specific offloaded computing task will be evaluated according to the offloading overhead. If the overhead of task offloading is acceptable, the main control chip will migrate part of the protocol in the Thread protocol core to the radio frequency chip for running.

[0007] The application provides a chip-level protocol stack computing task offloading method for a Thread network border router, comprising the following steps:

[0008] (1) The data link layer to the network layer of the protocol stack located in the master chip are divided into 5 different layers, numbered from top to bottom as 1 to 5.

[0009] (2) For the protocol stack divided in step (1), when sending a data packet, the time for the task to pass through the stack in the 5 layers of the master chip and the time for the task to pass through the stack in the radio frequency chip are recorded in the case of no computing task offloading.

[0010] (3) The necessity of offloading is judged according to the time recorded in step (2).

[0011] (4) If it is judged in step (3) that offloading is not needed, the task is not offloaded this time. If it is judged in step (3) that offloading is needed, the best offloading point is found through an overhead function and offloading is performed.

[0012] For the time recording in step (2), the following steps are included:

[0013] (2.1) In a message sending cycle, the time is recorded at the in-stack and out-stack of each protocol stack of the master chip, and the time is recorded at the in-stack and out-stack of the radio frequency chip.

[0014] (2.2) For the time recorded in (2.1), the difference between the out-stack time and the in-stack time is calculated to obtain the time t 1,p for the task to pass through the stack in the 5 layers of the master chip, where p∈{0,1,2,3,4,5}, when p≠0, t 1,p is the processing time of the pth protocol stack on the master processor; when p=0, t 1,0 represents the execution time of the master processor other than the above-mentioned 5 protocol stack layers.

[0015] (2.3) For the time recorded in (2.1), the difference between the out-stack time and the in-stack time is calculated to obtain the time t 2,0 for the task to pass through the stack in the radio frequency chip.

[0016] For the necessity of offloading in step (3), the following steps are included:

[0017] (3.1) The sum of the master processor computing time and the transmission delay between the two processors is calculated, and the time sum is:

[0018]

[0019] Where n is the number of coprocessors. ò(x) represents the amount of data transferred between the main processor and coprocessors in each operation; it is only a function of the partition point x. v3 is the data transfer rate between the main processor and coprocessors, which is a constant value during the execution of a set of tasks.

[0020] (3.2) Compare the t calculated in step (3.1) with the t obtained in step (2.3). 2,0 The size of the variable. If the former is larger, uninstallation is deemed necessary; otherwise, uninstallation is not required. When uninstallation is required, the following applies:

[0021]

[0022] Finding the optimal unloading point in step (4) includes the following steps:

[0023] (4.1) In each task execution, the overall time is minimized when the sum of the main control chip's calculation time and the spinel transmission delay is exactly equal to the RF chip's calculation time. The formula is:

[0024]

[0025] Here, x is the protocol stack offload point, determining the task allocation between the main processor and the coprocessor, where x∈{0,1,2,3,4}. Specifically, the protocol stack partitioning point x is located above the protocol stack partitioning point in the original RCP design, ensuring that protocol stack layers with sequence numbers less than or equal to x are completed on the main control chip, while protocol stack layers with sequence numbers greater than x are completed on the RF chip. The original protocol stack partitioning point was defined as x0.t 2,p This is the processing time of the p-th protocol stack of the coprocessor, where p∈{1,2,3,4,5}, and this value is determined by t. 1,p It is calculated from the main processor processing speed v1 and the coprocessor processing speed v2.

[0026] (4.2) For the formula in step (4.1), t on the right side of the equation 2p It's about t 1,p The function is v1, v2, therefore the above expression can be simplified to:

[0027]

[0028] (4.3) Regarding the formula in step (4.2), since the partition points are not continuous but discrete in actual partitioning, it may not be possible to find such an x ​​that makes the above equation completely true. Therefore, the difference function E(x) is calculated:

[0029]

[0030] (4.3) According to the difference function in step (4.3), traverse x and find the x that makes the difference function E(x) take the smallest value. This is the best unloading point.

[0031] (4.4) Based on the optimal offload point found in step (4.3), a portion of the protocol stack of the main control chip is offloaded to multiple RF chips connected to the main control chip. That is, the protocol stack above point x is calculated and run by the main control chip, and the protocol stack below point x is run by the RF chips.

[0032] A second aspect of the present invention relates to a chip-level protocol stack computation task offloading device for Thread network border routers, comprising a memory and one or more processors, wherein the memory stores executable code, and the one or more processors execute the executable code to implement the chip-level protocol stack computation task offloading method for Thread network border routers of the present invention.

[0033] A third aspect of the invention relates to a computer-readable storage medium having a program stored thereon that, when executed by a processor, implements the chip-level protocol stack computation task offloading method for Thread-oriented network boundary routers of the present invention.

[0034] To address the issue of excessive end-to-end latency in high-volume network traffic scenarios, this invention proposes a scheme that dynamically migrates network signal decapsulation and flow control calculations between two chips by optimizing the protocol stack computation tasks in the network coprocessor architecture at the chip level. This scheme consists of three stages: the first stage records the stack migration time on both the main control chip and the RF chip; the second stage determines whether unloading is necessary; and the third stage finds the most appropriate unloading point to minimize the overall system time.

[0035] The advantages of this invention are: the protocol stack computation tasks are optimized at the chip level, and the decapsulation and flow control calculations of network signals are dynamically migrated between two chips. This improves the network traffic processing capacity per unit time, forming a larger-scale, robust, stable, and adaptive network. Attached Figure Description

[0036] Figure 1 This is a flowchart of the method of the present invention. Detailed Implementation

[0037] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0038] Example 1

[0039] Reference Figure 1This invention provides a chip-level protocol stack computing task offloading method for Thread network boundary routers, comprising the following steps:

[0040] (1) First, the unloadable part of the protocol stack located in the main control chip is divided into 5 different levels according to its implementation function and unloadability, numbered from 1 to 5 from top to bottom.

[0041] (2) For the protocol stack divided in step (1), when the data packet is sent, the stack crossing time of the task in the five levels of the main control chip and the stack crossing time in the radio frequency chip are recorded without unloading the computing task.

[0042] (3) Based on the time recorded in step (2), determine the necessity of unloading according to formula (1).

[0043] (4) If it is determined in step (3) that uninstallation is required, the optimal uninstallation point is found by formula (2) and uninstallation is performed.

[0044] The time recording in step (2) includes the following steps:

[0045] (2.1) During a message sending cycle, the time is recorded at the push and pop points of each protocol stack of the main control chip, and the time is recorded at the push and pop points of the radio frequency chip.

[0046] (2.2) For the time recorded in (2.1), calculate the difference between the pop time and the push time to obtain the stack passage time t of the task in the five levels of the main control chip. 1,p Where p∈{0,1,2,3,4,5}, when p≠0, t 1,p t is the processing time of the p-th protocol stack on the main processor; when p=0, t 1,0 This indicates the execution time of the main processor outside of the five protocol stack layers mentioned above, under the original partitioning method.

[0047] (2.3) For the time recorded in (2.1), calculate the difference between the pop-out time and the push-in time to obtain the time t of the task passing through the stack in the RF chip. 2,0 .

[0048] The determination of the necessity of uninstallation in step (3) includes the following steps:

[0049] (3.1) Calculate the sum of the main processor's computation time and the transmission delay between the two processors. This sum is:

[0050]

[0051] Where n is the number of coprocessors. ò(x) represents the amount of data transferred between the main processor and coprocessors in each operation; it is only a function of the partition point x. v3 is the data transfer rate between the main processor and coprocessors, which is a constant value during the execution of a set of tasks.

[0052] (3.2) Compare the t calculated in step (3.1) with the t obtained in step (2.3). 2,0 The size of the variable. If the former is larger, uninstallation is deemed necessary; otherwise, uninstallation is not required. When uninstallation is required, the following applies:

[0053]

[0054] Finding the optimal unloading point in step (4) includes the following steps:

[0055] (4.1) In each task execution, the overall time is minimized when the sum of the main control chip's calculation time and the spinel transmission delay is exactly equal to the RF chip's calculation time. The formula is:

[0056]

[0057] Here, x is the protocol stack offload point, determining the task allocation between the main processor and the coprocessor, where x∈{0,1,2,3,4}. Specifically, the protocol stack partitioning point x is located above the protocol stack partitioning point in the original RCP design, ensuring that protocol stack layers with sequence numbers less than or equal to x are completed on the main control chip, while protocol stack layers with sequence numbers greater than x are completed on the RF chip. The original protocol stack partitioning point was defined as x0.t 2,p This is the processing time of the p-th protocol stack of the coprocessor, where p∈{1,2,3,4,5}, and this value is determined by t. 1,p It is calculated from the main processor processing speed v1 and the coprocessor processing speed v2.

[0058] (4.2) For the formula in step (4.1), t on the right side of the equation 2p It's about t 1,p The function is v1, v2, therefore the above expression can be simplified to:

[0059]

[0060] (4.3) Regarding the formula in step (4.2), since the partition points are not continuous but discrete in actual partitioning, it may not be possible to find such an x ​​that makes the above equation completely true. Therefore, the difference function E(x) is calculated:

[0061]

[0062] (4.3) According to the difference function in step (4.3), traverse x and find the x that makes the difference function E(x) take the smallest value. This is the best unloading point.

[0063] (4.4) Based on the optimal offload point found in step (4.3), a portion of the protocol stack of the main control chip is offloaded to multiple RF chips connected to the main control chip. That is, the protocol stack above point x is calculated and run by the main control chip, and the protocol stack below point x is run by the RF chips.

[0064] Example 2

[0065] This embodiment relates to a chip-level protocol stack computing task offloading device for Thread network border routers, including a memory and one or more processors. The memory stores executable code, and when the one or more processors execute the executable code, they are used to implement the chip-level protocol stack computing task offloading method for Thread network border routers of the present invention.

[0066] Example 3

[0067] This embodiment relates to a computer-readable storage medium storing a program that, when executed by a processor, implements the chip-level protocol stack computation task offloading method for Thread-oriented network boundary routers of the present invention.

[0068] The embodiments described in this specification are merely examples of implementations of the inventive concept. The scope of protection of this invention should not be considered as limited to the specific forms stated in the embodiments. The scope of protection of this invention also extends to equivalent technical means that can be conceived by those skilled in the art based on the inventive concept.

Claims

1. A chip-level protocol stack computation task offloading method for Thread network boundary routers, characterized by comprising the following steps: (1) The protocol stack located on the main control chip is divided into 5 different levels, numbered 1 to 5 respectively; (2) For the protocol stack divided in step (1), when the data packet is sent, the stack crossing time of the task in the five protocol stack layers of the main control chip and the stack crossing time of the task in the radio frequency chip are recorded without unloading the computing task. (3) Calculate the sum of the computation time of the main control chip and the data transmission delay between the main control chip and the coprocessor; compare the sum of the computation time and the data transmission delay with the stack-through time of the task in the RF chip; if the former is larger, unloading is required, otherwise unloading is not required; (4) If it is determined in step (3) that unloading is not required, then the task will not be unloaded in this step; if it is determined in step (3) that unloading is required, then the optimal unloading point is found through the overhead function and unloading is performed; the specific steps for finding the optimal unloading point are as follows: (4.1) In each task execution, the overall time is minimized when the sum of the main control chip's calculation time and the spinel transmission delay is exactly equal to the RF chip's calculation time; The formula is: Where x is the protocol stack offload point, determining the task allocation between the main control chip and the coprocessor, x∈{0,1,2,3,4}; specifically, the protocol stack partitioning point x is located above the protocol stack partitioning point of the original RCP design, so that protocol stack levels with sequence numbers less than or equal to x are completed on the main control chip, and protocol stack levels with sequence numbers greater than x are completed on the RF chip; the original protocol stack partitioning point is defined as x0; t 2,p It is the processing time of the p-th protocol stack of the coprocessor, where p∈{1,2,3,4,5}, determined by t. 1,p The processing speed v1 of the main control chip and the processing speed v2 of the coprocessor are calculated; t 2,0 This refers to the stack-through time of the task within the RF chip. (4.2) For the formula in step (4.1), t on the right side of the equation 2,p It's about t 1,p The function is v1, v2, therefore the above expression can be simplified to: (4.3) Regarding the formula in step (4.2), since the partition points are not continuous but discrete in actual partitioning, it may not be possible to find such an x ​​that makes the above equation completely true. Therefore, the difference function E(x) is calculated: (4.4) Based on the difference function in step (4.3), iterate through x to find the x that minimizes the value of the difference function E(x), which is the optimal unloading point; (4.5) Based on the optimal unloading point found in step (4.4), a portion of the protocol stack of the main control chip is unloaded to multiple radio frequency chips connected to the main control chip; that is, the protocol stack above point x is calculated and run by the main control chip, and the protocol stack below point x is run by the radio frequency chips.

2. The method according to claim 1, characterized in that: Step (2) involves recording the stack-through time of the task in the five protocol stack layers of the main control chip and the stack-through time in the RF chip. The specific steps are as follows: (2.1) In a message sending cycle, the time is recorded at the push and pop points of each protocol stack layer of the main control chip, and the time is recorded at the push and pop points of the radio frequency chip. (2.2) For the push and pop times recorded in (2.1) at each protocol stack level of the main control chip, calculate the difference between the pop time and the push time to obtain the task's stack-through time t in the five levels of the main control chip. 1,p Where p∈{0,1,2,3,4,5}, when p≠0, t 1,p This refers to the processing time of the p-th protocol stack on the main control chip. When p = 0, t 1,0 This indicates the execution time of the main control chip outside of the five protocol stack layers mentioned above, under the original division method; (2.3) For the push and pop times recorded in (2.1) on the RF chip, calculate the difference between the pop time and the push time to obtain the task's stack-through time t in the RF chip. 2,0 .

3. The method according to claim 1, characterized in that: Step (3) involves calculating the sum of the computation time of the main control chip and the data transmission delay between the main control chip and the coprocessor, specifically as follows: Where n is the number of coprocessors; ò(x) represents the amount of data transfer between the main processor and the coprocessors in each step, which is only a function of the partition point x; v3 is the speed at which data is transferred between the main processor and the coprocessors, which is a constant value during the execution of a set of tasks.

4. A chip-level protocol stack computing task offloading device for Thread network boundary routers, characterized in that, The device includes a memory and one or more processors, wherein the memory stores executable code, and the one or more processors execute the executable code to implement the chip-level protocol stack computing task offloading method for a Thread-oriented network boundary router as described in any one of claims 1-3.

5. A computer-readable storage medium, characterized in that, It stores a program that, when executed by a processor, implements the chip-level protocol stack computing task offloading method for Thread-oriented network boundary routers as described in any one of claims 1-3.

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