Layout structure and array structure of semiconductor devices, layout structure of integrated circuits

Abstract

The embodiments of the present disclosure disclose a layout structure and array structure of a semiconductor device, and a layout structure of an integrated circuit, wherein the layout structure of the semiconductor device includes: multiple first active areas, all extending along a first direction; two gate connection structures, arranged along the first direction, each gate connection structure including 2N interconnected first gates and 2N second gates; the first gate corresponds to the first active area; N is a positive integer; 2N third gates; wherein the N third gates are located between the two gate connection structures and correspond to the N second gates of each of the two gate connection structures; the remaining N third gates are located on a side of a gate connection structure away from the other gate connection structure, and correspond to the remaining N second gates of a gate connection structure; the second gate and the third gate both extend along a second direction; and the second direction is perpendicular to the first direction.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a layout structure and array structure of a semiconductor device, and a layout structure of an integrated circuit. Background Art

[0002] In semiconductor devices, such as dynamic random access memory (DRAM), word lines can be used as conductive lines to transmit the gate voltage required to drive one or more transistors in a memory cell. The transistors can operate in response to the potential state of the word lines, allowing the DRAM to write data to or read data from the memory cell through the transistors.

[0003] As chip size and capacity increase, the line delay caused by such wordlines can be considered one of the most important delay factors limiting the operating speed of dynamic random access memory. To minimize the line delay of such wordlines, a device has been developed to divide a long main wordline (MWL) into multiple sub-wordlines (SWL) and a sub-wordline driver (SWD) to drive each sub-wordline. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a layout structure and array structure of a semiconductor device, and a layout structure of an integrated circuit. In one aspect, embodiments of the present disclosure provide a layout structure of a semiconductor device, comprising: a plurality of first active regions, all extending along a first direction;

[0005] Two gate connection structures are arranged along the first direction, each of the gate connection structures includes 2N interconnected first gates and 2N second gates; the first gates correspond to the first active area; N is a positive integer;

[0006] 2N third gates; wherein, N third gates are located between the two gate connection structures and correspond to the N second gates of each of the two gate connection structures; the remaining N third gates are located on a side of one gate connection structure away from the other gate connection structure, and correspond to the remaining N second gates of the one gate connection structure; the second gate and the third gate both extend along a second direction; the second direction is perpendicular to the first direction.

[0007] In one embodiment, the 2N first gates of each of the gate connection structures are physically connected;

[0008] The 2N second gates of each gate connection structure are connected to one end of the 2N first gates; or the 2N second gates of each gate connection structure are connected to both ends of the plurality of first gates.

[0009] In one embodiment, the two gate connection structures include a first gate connection structure and a second gate connection structure;

[0010] The 2N second gates of the first gate connection structure and the second gate connection structure are all connected to one end of the 2N first gates of the corresponding gate connection structure;

[0011] The 2N second gates of the first gate connection structure and the second gate connection structure each include a first portion and a second portion; the first portion is the N second gates close to the first gate, and the second portion is the N second gates away from the first gate;

[0012] The distance between the first portion of the first gate connection structure and the first portion of the second gate connection structure along the first direction is a first distance; the distance between the second portion of the first gate connection structure and the second portion of the second gate connection structure along the first direction is a second distance.

[0013] In one embodiment, the first distance is greater than the second distance;

[0014] The N third gates are located between the first portion of the first gate connection structure and the first portion of the second gate connection structure; the remaining N third gates are located on one side of the second portion of the first gate connection structure or on one side of the second portion of the second gate connection structure.

[0015] In one embodiment, the first distance is smaller than the second distance;

[0016] The N third gates are located between the second portion of the first gate connection structure and the second portion of the second gate connection structure; the remaining N third gates are located on one side of the first portion of the first gate connection structure or on one side of the first portion of the second gate connection structure.

[0017] In one embodiment, the first part and the second part of the 2N second gates each include two directly connected second gates; the N third gates include two spaced-apart third gates; and both ends of the two directly connected second gates and both ends of the two spaced-apart third gates are substantially flush along the first direction.

[0018] In one embodiment, the projection shapes of the first gate on the plane where the first active area is located include a U-shape or an inverted U-shape; the 2N first gates include a third part and a fourth part; the third part is the N first gates close to the second gate, and the fourth part is the N first gates away from the second gate; the projection shapes of the first gates in the third part and the first gates in the fourth part on the plane where the first active area is located are different.

[0019] In one embodiment, the projection shapes of the second gate and the third gate on the plane where the first active region is located are both rectangles.

[0020] In one embodiment, a side line of the first gate in the third part along the second direction is substantially flush with a side line of the second gate in the first part along the second direction; a side line of the first gate in the fourth part along the second direction is substantially flush with a side line of the second gate in the second part along the second direction.

[0021] In one embodiment, the distance between the N third gates and the corresponding N second gates of the first gate connection structure along the first direction is a third distance, and the distance between the N third gates and the corresponding N second gates of the second gate connection structure along the first direction is a fourth distance;

[0022] The distance between the remaining N third gates and the corresponding N second gates of the adjacent gate connection structures in the two gate connection structures along the first direction is a fifth distance;

[0023] The third distance is equal to the fourth distance; the fourth distance is equal to the fifth distance.

[0024] In one embodiment, the size of the first gate along the first direction is greater than the size of the second gate along the first direction;

[0025] A size of the second gate along the first direction is equal to a size of the third gate along the first direction.

[0026] In one embodiment, the 2N first gates in the two gate connection structures are parallel and both ends are substantially flush along the first direction;

[0027] The 2N second gates in the two gate connection structures are parallel and both ends are substantially flush along the first direction.

[0028] In one embodiment, the transistor corresponding to the first gate includes a PMOS transistor; the transistor corresponding to the second gate and the transistor corresponding to the third gate both include NMOS transistors.

[0029] In one embodiment, the layout structure of the semiconductor device further includes a plurality of second active regions; the plurality of second active regions correspond to the second gate and the third gate.

[0030] On the other hand, an embodiment of the present disclosure provides an array structure of semiconductor devices, including: a layout structure of multiple semiconductor devices as described in the above embodiments of the present disclosure.

[0031] In one embodiment, the layout structures of the plurality of semiconductor devices are arranged along a first direction; and the structural arrangement of the layout structure of each semiconductor device in the layout structures of the plurality of semiconductor devices is the same.

[0032] In one embodiment, both ends of the layout structure of the plurality of semiconductor devices are substantially flush along the first direction.

[0033] On the other hand, an embodiment of the present disclosure provides a layout structure of an integrated circuit, comprising: an array structure of one or more semiconductor devices as described in the above embodiments of the present disclosure; and

[0034] A plurality of sub-word lines; each of the sub-word lines is connected to an active area corresponding to a first gate and an active area corresponding to a second gate in a gate connection structure through a first via hole.

[0035] In one embodiment, the layout structure of the integrated circuit further includes a plurality of main word lines; each of the main word lines is connected to all the first gates and all the second gates in one of the gate connection structures through a second via.

[0036] In one embodiment, the integrated circuit is a dynamic random access memory.

[0037] The layout structure of the semiconductor device provided by the embodiment of the present disclosure includes multiple first active areas, two gate connection structures, and 2N third gates, wherein each gate connection structure includes 2N interconnected first gates and 2N second gates; wherein, by arranging N third gates between the two gate connection structures, and making the N third gates correspond to the N second gates of each of the two gate connection structures, and arranging the remaining N third gates on a side of a gate connection structure away from the other gate connection structure, and making the remaining N third gates correspond to the remaining N second gates in the adjacent gate connection structure, it is possible to allow two adjacent gate connection structures to share a group of third gates, thereby reducing the number of third gates in the layout structure of the semiconductor device, reducing the area of ​​the semiconductor device, and improving the integration of the device; in addition, it can be understood that, when the total area of ​​the layout structure of the semiconductor device remains unchanged, by reducing the number of third gates, at least the size of the second gate and the remaining third gates can be increased, that is, the size of the channel in the transistor corresponding to the second gate and the third gate is increased, thereby improving the hot carrier effect and reducing the subthreshold leakage current (Ioff) and gate-induced drain leakage current (GIDL). Drain Leakage), improving the reliability of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1a A schematic diagram of a partial circuit of a memory provided in an embodiment of the present disclosure;

[0039] Figure 1b A schematic diagram of the layout structure of a semiconductor device with a sub-word line driver provided in an embodiment of the present disclosure;

[0040] Figure 2 A circuit diagram of a sub-word line driver provided in an embodiment of the present disclosure;

[0041] Figure 3a Schematic diagram of the circuit structure of the sub-word line driver provided in an embodiment of the present disclosure under a first working condition;

[0042] Figure 3b Schematic diagram of the circuit structure of the sub-word line driver provided in the embodiment of the present disclosure under the second working condition;

[0043] Figure 3c Schematic diagram of the circuit structure of the sub-word line driver provided in the embodiment of the present disclosure under the third working condition;

[0044] Figure 4 The circuit structure provided in the embodiment of the present disclosure in which two sub-word lines are respectively connected to two NTK_SV2 transistors is improved to a circuit structure in which two sub-word lines are commonly connected to one NTK_SV2 transistor;

[0045] Figure 5 A schematic diagram of the layout structure of a semiconductor device provided in an embodiment of the present disclosure;

[0046] Figure 6 A schematic diagram of the layout structure of another semiconductor device provided in an embodiment of the present disclosure;

[0047] Figure 7 A schematic diagram of a layout structure of another semiconductor device provided in an embodiment of the present disclosure;

[0048] Figure 8 for Figure 5 An enlarged schematic diagram corresponding to 2N first gates in the first gate connection structure;

[0049] Figure 9 for Figure 5 An enlarged schematic diagram corresponding to the first gate connection structure;

[0050] Figure 10 A schematic diagram of the layout structure of multiple semiconductor devices provided in an embodiment of the present disclosure;

[0051] Figure 11 Schematic diagram of the layout structure of multiple sub-word lines provided in an embodiment of the present disclosure.

[0052] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0053] To make the technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although the accompanying drawings show exemplary implementation methods of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0054] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0055] It will be understood that the meanings of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” not only means being “on” something with no intervening features or layers (i.e., directly on something), but also includes being “on” something with intervening features or layers.

[0056] Furthermore, for ease of description, spatially relative terms such as "on," "over," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0057] In the embodiments of the present disclosure, the term "substrate" refers to the material onto which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0058] In the disclosed embodiments, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is smaller than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (in which interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0059] In the embodiments of the present disclosure, the terms "first," "second," etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0060] The layout structure of the semiconductor device involved in the embodiments of the present disclosure is at least a portion of the final device structure that will be used in subsequent manufacturing processes. Here, the final device may include a memory, including but not limited to a dynamic random access memory. The following description uses the dynamic random access memory as an example and is not intended to limit the scope of the present disclosure.

[0061] With the development of dynamic random access memory technology, the architecture of memory cell array has changed from 8F 2 Go to 6F 2 Then go to 4F 2 However, regardless of 8F 2 Still 4F 2 Dynamic random access memory (DRAM) is an array architecture consisting of multiple memory cells. Each memory cell can be composed of a transistor and a capacitor controlled by the transistor. That is, dynamic random access memory has a 1 transistor (T) and 1 capacitor (C) (1T1C) architecture. Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0062] Figure 1a Schematic diagram of a memory using a 1T1C architecture provided in an embodiment of the present disclosure; Figure 1a As shown, the drain of the transistor T is electrically connected to the bit line (BL), the source of the transistor T is electrically connected to one of the electrode plates of the capacitor C, the other electrode plate of the capacitor C can be connected to a reference voltage, which can be a ground voltage or other voltage, and the gate of the transistor T is connected to the word line (WL); the voltage applied by the word line WL controls the conduction or cut-off of the transistor T, and the bit line BL is used to perform a read or write operation on the transistor T when the transistor T is turned on.

[0063] Figure 1b FIG. 1 is a schematic diagram of a layout of a semiconductor device with a sub-word line driver provided in an embodiment of the present disclosure. Figure 1b As shown, the dynamic random access memory may include at least one memory cell array (CA) and a circuit for controlling the cell array including a main word line. Figure 1b A plurality of memory cell arrays CA are shown, and each memory cell array CA may include at least one bit line sense amplifier (BLSA) and at least one sub-word line driver SWD.

[0064] Each memory cell array CA may include a plurality of memory cells arranged in an array shape for storing data. The memory cell array may include a plurality of sub-word lines SWL, each of which may be coupled to a plurality of memory cells, the plurality of sub-word lines may be sequentially and successively arranged above the memory cell array, and the plurality of sub-word lines may be connected to a main word line MWL.

[0065] As previously mentioned, to minimize the line delay of a main word line, a method has been developed to divide a long main word line and its driver into multiple sub-word lines, and to use multiple sub-word line drivers to drive each of the sub-word lines. A sub-word line driver can selectively drive one or more sub-word lines in response to a main word line drive signal. In this case, the main word line drive signal can represent a memory cell drive signal transmitted via the main word line.

[0066] exist Figure 1b In the embodiment of the present invention, the sub-word line driver can be divided into an even sub-word line driver circuit SWD (EVEN) arranged along one side of the memory cell array and an odd sub-word line driver circuit SWD (ODD) arranged along the opposite side relative to the memory cell array. The even sub-word line driver circuit can drive one or more even sub-word lines, and the odd sub-word line driver circuit can drive one or more odd sub-word lines. It can be understood that the even sub-word line driver circuit and the odd sub-word line driver circuit have a basically similar structure, and the even sub-word line driver circuit and the odd sub-word line driver are collectively referred to as sub-word line drivers below. The sense amplifier can sense and amplify the cell data of the associated memory cell array. The sense amplifier can be arranged along the other side of the memory cell array.

[0067] Figure 2 FIG. 1 shows a circuit diagram of a sub-word line driver in one embodiment. Figure 2 As shown, the sub-wordline driver SWD is used to drive four sub-wordlines SWL and includes four P-type metal-oxide-semiconductor (PMOS) transistors and four N-type metal-oxide-semiconductor (NMOS) transistors. The gates of the four PMOS transistors and the four NMOS transistors are interconnected to form the main wordline MWL. Each sub-wordline SWL includes a PMOS transistor and an NMOS transistor, wherein the PMOS transistor and the NMOS transistor can be formed into an inverter to control the switching state of the target sub-wordline. The transistor control voltage VPP turns the sub-wordline on, or controls the voltage VKK to turn the sub-wordline off.

[0068] It should be noted that the sub-word line driver may also include another NMOS transistor connected to a group of PMOS transistors and NMOS transistors. The other NMOS transistor may be a noise suppression unit (Noise Killer). The noise suppression unit may be used to input a VKK voltage to other sub-word lines to turn them off when a certain sub-word line is turned on, so as to prevent affecting the signal of turning on the sub-word line.

[0069] However, the sub-word line driver SWD is prone to causing leakage current that causes static power consumption. This leakage current includes subthreshold leakage current between the source and drain and gate-induced drain leakage current occurring in the gate-drain overlap region. Especially for short-channel devices, the phenomenon of hot carrier injection (HCI) effect is more serious. When the channel length is small, increasing the drain terminal voltage will make the source and drain depletion regions closer and closer (punch-through), causing the electric field to pass from the drain to the source, thereby increasing the electrons injected into the channel from the source terminal, resulting in increased leakage current.

[0070] Exemplary, reference Figure 3a 、 Figure 3b 、 Figure 3c , Figure 3a 、 Figure 3b 、 Figure 3c The following table shows the different working conditions of three sub-word line drivers SWD. Figures 3a-3c H is high level and L is low level: Figure 3a In the first working condition shown, the PMOS transistor (PTK_SV) is in the off state, the NMOS transistor (NTK_SV1) is in the on state, the other NMOS transistor (NTK_SV2) is in the off state, and the corresponding sub-word line SWL is in the off state. Figure 3b In the second working condition shown, the PMOS transistor (PTK_SV) is in the off state, the NMOS transistor (NTK_SV1) is in the on state, another NMOS transistor (NTK_SV2) is in the on state, and the corresponding sub-word line SWL is in the off state. Figure 3c In the third working condition shown, the PMOS transistor (PTK_SV) is in the on state, the NMOS transistor (NTK_SV1) is in the off state, the other NMOS transistor (NTK_SV2) is in the off state, and the corresponding sub-word line SWL is in the on state. Figure 3a and Figure 3b Under the working conditions shown in FIG, it is very easy to cause the PMOS transistor (PTK_SV) to generate a gate-induced drain leakage current GIDL, and Figure 3c Under the working conditions shown in FIG, a subthreshold leakage current (Ioff) is easily induced.

[0071] Based on this, in order to solve one or more of the above problems, the present disclosure provides a circuit structure of a semiconductor device, referring to Figure 4 , Figure 4The circuit structure provided in the embodiment of the present disclosure in which two sub-word lines are respectively connected to two NTK_SV2 transistors is improved to a circuit structure in which two sub-word lines are commonly connected to one NTK_SV2 transistor; wherein, in the improved circuit structure, two sub-word lines (WL-A and WL-B) are commonly connected to one NTK_SV2 transistor. In this way, the number of NTK_SV2 transistors in the sub-word line driver can be reduced, a larger area can be saved, and the integration of semiconductor devices can be improved; at the same time, the channel length of the remaining transistors (PMOS (PTK_SV), NMOS (NTK_SV1), NMOS (NTK_SV2)) can be increased, the hot carrier effect of the NMOS transistors (NTK_SV1, NTK_SV2) can be reduced, and the subthreshold leakage current and gate-induced drain leakage current can be reduced.

[0072] The embodiment of the present disclosure further provides a layout structure of a semiconductor device corresponding to the circuit structure of the above-mentioned semiconductor device, wherein the layout structure of the semiconductor device includes: a plurality of first active regions, each extending along a first direction;

[0073] Two gate connection structures are arranged along the first direction, each of the gate connection structures includes 2N interconnected first gates and 2N second gates; the first gates correspond to the first active area; N is a positive integer;

[0074] 2N third gates; wherein, N third gates are located between the two gate connection structures and correspond to the N second gates of each of the two gate connection structures; the remaining N third gates are located on a side of one gate connection structure away from the other gate connection structure, and correspond to the remaining N second gates of the one gate connection structure; the second gate and the third gate both extend along a second direction; the second direction is perpendicular to the first direction.

[0075] Here and below, to facilitate description of the disclosed embodiments, the first direction refers to the extension direction of the first active region; each of the multiple first active regions extends in the same first direction; the second direction refers to a direction perpendicular to the first direction and parallel to the plane in which the first active regions are located. In some specific examples, the first direction can be represented as the Y-axis direction in the accompanying drawings; the second direction can be represented as the X-axis direction in the accompanying drawings; and the plane in which the first active regions are located can be represented as the XOY plane in the accompanying drawings.

[0076] refer to Figure 5 , Figure 5This is a schematic diagram of the layout structure of a semiconductor device provided in an embodiment of the present disclosure; wherein, the layout structure of the semiconductor device may include multiple first active areas 401, multiple second active areas 402, and multiple gate connection structures 50, wherein the number of first gates 501 and second gates 502 in each gate connection structure 50 is the same, the first gates 501 and the second gates 502 represent different types of transistors, and the types of transistors represented by the first gates 501 and the second gates 502 can be interchanged. For example, the transistor corresponding to the first gate may include a PMOS transistor; the transistor corresponding to the second gate may include an NMOS transistor; or the transistor corresponding to the first gate may include an NMOS transistor; the transistor corresponding to the second gate may include a PMOS transistor. Here, the first active area 401 corresponds to the first gate 501, and part of the second active area 402 corresponds to the second gate 502.

[0077] In some embodiments, the 2N first gates of each of the gate connection structures are physically connected; the 2N second gates of each of the gate connection structures are connected to one end of the 2N first gates; or, the 2N second gates of each of the gate connection structures are connected to both ends of the multiple first gates.

[0078] Here, the term "physical connection" can be understood as a direct connection between the connected objects through contact or through a connection structure such as a metal wire or metal via, with no other non-connected connection objects interposed between the physically connected objects. In other words, the 2N first gates of each gate connection structure are directly connected along the second direction, and the 2N second gates of each gate connection structure are directly connected along the second direction. The directly connected 2N second gates can both be disposed at one end of the directly connected 2N first gates, or the directly connected 2N second gates can be split into two parts, with the two parts being disposed at each end of the physically connected 2N first gates.

[0079] Exemplary, reference Figure 5 In each gate connection structure, 2N first gates directly connected are formed on the right side, and 2N second gates directly connected are formed on the left side, that is, the 2N first gates are arranged on the right side of the 2N second gates.

[0080] Exemplary, reference Figure 6 , Figure 6This is a schematic diagram of the layout structure of another semiconductor device provided in an embodiment of the present disclosure; in each gate connection structure, the 2N directly connected first gates are formed in the middle, N of the 2N second gates are directly connected and formed on the left, and the remaining N second gates are directly connected and formed on the right, that is, the 2N second gates are respectively arranged at both ends of the 2N first gates. The specific connection structure of the first and second gates can be selected according to actual needs.

[0081] In some embodiments, the 2N first gates in the two gate connection structures are parallel and both ends are substantially flush along the first direction; the 2N second gates in the two gate connection structures are parallel and both ends are substantially flush along the first direction.

[0082] Exemplary, reference Figure 5 , N=2, the two gate connection structures include a first gate connection structure 50a and a second gate connection structure 50b; the four first gates 501 in the first gate connection structure 50a and the four first gates 501 in the second gate connection structure 50b are all parallel, and the two ends of the four first gates 501 in the first gate connection structure 50a and the two ends of the four first gates 501 in the second gate connection structure 50b are all substantially flush along the Y-axis direction, as indicated by the dotted line AA". The substantially flush includes non-flatness within the actual allowable manufacturing error range standard. The four second gates 502 in the first gate connection structure 50a and the four second gates 502 in the second gate connection structure 50b are all parallel, and the two ends of the four second gates 502 in the first gate connection structure 50a and the two ends of the four second gates 502 in the second gate connection structure 50b are all substantially flush along the Y-axis direction, as indicated by the dotted line BB".

[0083] The layout structure of the semiconductor device also includes multiple third gates 503, part of the second active area 402 also corresponds to the third gate 503, and the third gate 503 and the first gate 501 represent the same type of transistor; wherein, the multiple third gates 503 can all be arranged between the two gate connection structures, or all be arranged on the side of one gate connection structure away from the other gate connection structure, or part of the third gate 503 can be arranged between the two gate connection structures, and the remaining part of the third gate is arranged on the side of one gate connection structure away from the other gate connection structure.

[0084] In the embodiment of the present disclosure, N third gates 503 out of the 2N third gates 503 are arranged between two gate connection structures, and the remaining N third gates 503 are arranged on the side of one gate connection structure away from the other gate connection structure. At this time, the N third gates 503 correspond to the N second gates of each of the two gate connection structures; the remaining N third gates correspond to the remaining N second gates in an adjacent gate connection structure.

[0085] In some embodiments, the two gate connection structures include a first gate connection structure and a second gate connection structure; the 2N second gates of the first gate connection structure and the second gate connection structure are all connected to one end of the 2N first gates of the corresponding gate connection structure; the 2N second gates of the first gate connection structure and the second gate connection structure each include a first part and a second part; the first part is the N second gates close to the first gate, and the second part is the N second gates away from the first gate; the distance between the first part of the first gate connection structure and the first part of the second gate connection structure along the first direction is a first distance; the distance between the second part of the first gate connection structure and the second part of the second gate connection structure along the first direction is a second distance.

[0086] Exemplary, reference Figure 5 The 2N second gates of the first gate connection structure 50a are all connected to one end of the 2N first gates of the first gate connection structure 50a; wherein the 2N second gates in the first gate connection structure 50a include a first portion 502-1 and a second portion 502-2, wherein the first portion 502-1 comprises the N second gates close to the first gate 501, and the second portion 502-2 comprises the N second gates away from the first gate 501. The 2N second gates of the second gate connection structure 50b are all connected to one end of the 2N first gates of the second gate connection structure 50b; wherein the 2N second gates in the second gate connection structure 50b include a first portion 502-3 and a second portion 502-4, wherein the first portion 502-3 comprises the N second gates close to the first gate 501, and the second portion 502-4 comprises the N second gates away from the first gate 501.

[0087] The distance between the first portion 502-1 of the second gate of the first gate connection structure 50a and the first portion 502-3 of the second gate of the second gate connection structure 50b along the Y-axis direction is a first distance L1; the distance between the second portion 502-2 of the second gate of the first gate connection structure 50a and the second portion 502-4 of the second gate of the second gate connection structure 50b along the Y-axis direction is a second distance L2. In some specific embodiments, the first distance L1 may be greater than the second distance L2 in the layout structure of the semiconductor device (e.g., Figure 5 The two gate connection structures of the layout structure shown in FIG include a first gate connection structure 50a and a second gate connection structure 50b). In some specific embodiments, the first distance L1 may be smaller than the second distance L2 (eg, Figure 5 The two gate connection structures of the layout structure shown in FIG. 5 include a first gate connection structure 50 c and a second gate connection structure 50 b .

[0088] In some embodiments, the first distance is greater than the second distance; the N third gates are located between the first portion of the first gate connection structure and the first portion of the second gate connection structure; and the remaining N third gates are located on one side of the second portion of the first gate connection structure or on one side of the second portion of the second gate connection structure.

[0089] Exemplary, reference Figure 5 , the 2N third gates 503 include a first portion 503-1 and a second portion 503-2, wherein the first portion 503-1 and the second portion 503-2 each include N third gates; when the first distance L1 is greater than the second distance L2, as Figure 5 The two gate connection structures of the layout structure 50 shown include a first gate connection structure 50a and a second gate connection structure 50b, the first part 503-1 of the 2N third gates 503 is arranged between the first part 502-1 of the second gate of the first gate connection structure 50a and the first part 502-3 of the second gate of the second gate connection structure 50b, and the second part 503-2 of the 2N third gates 503 is arranged on one side of the second part 502-2 of the second gate of the first gate connection structure 50a (away from the side of the second gate connection structure 50b). In other examples, the second part 503-2 of the 2N third gates 503 can also be arranged on one side of the second part 502-4 of the second gate of the second gate connection structure 50b (away from the side of the first gate connection structure 50a).

[0090] In some embodiments, the first distance is smaller than the second distance; the N third gates are located between the second portion of the first gate connection structure and the second portion of the second gate connection structure; and the remaining N third gates are located on one side of the first portion of the first gate connection structure or on one side of the first portion of the second gate connection structure.

[0091] Exemplary, reference Figure 5 The two gate connection structures of the layout structure 50 include a first gate connection structure 50c and a second gate connection structure 50b. The first portion 503-1 of the 2N third gates 503 is arranged on one side of the first portion 502-3 of the second gate of the second gate connection structure 50b (a side away from the first gate connection structure 50c). In other examples, the first portion 503-1 of the 2N third gates 503 may also be arranged on one side of the first portion 502-1 of the second gate of the first gate connection structure 50c (a side away from the second gate connection structure 50b). Figure 5 (not shown), the second portion 503-2 of the 2N third gates 503 is disposed between the second portion 502-2 of the second gate of the first gate connection structure 50c and the second portion 502-4 of the second gate of the second gate connection structure 50b. In this way, the third gate can be shared between the two gate connection structures, thereby achieving the goal of reducing the area while ensuring the integrity of the circuit structure of the semiconductor device.

[0092] In some embodiments, reference Figure 5 、 Figure 6 The second gate 502 and the third gate 503 in the first gate connection structure 50a and the second gate connection structure 50b extend along the Y-axis direction, and the projection shapes of the second gate 502 and the third gate 503 on the plane where the first active area is located are in the shape of a "one"; in other words, in some embodiments, the projection shapes of the second gate and the third gate on the plane where the first active area is located include rectangles. For example, referring to Figure 5 The projection shapes of the second gates (502-1, 502-2, 502-3, 502-4) and the third gates (503-1 and 503-2) on the plane where the first active region is located all include rectangles.

[0093] In other embodiments, reference Figure 7 , Figure 7This is a schematic diagram of the layout structure of another semiconductor device provided in an embodiment of the present disclosure; wherein the second gate 502 in the first gate connection structure 50a and the second gate connection structure 50b both extend along the Y-axis direction, and the third gate 503 in the first gate connection structure 50a and the second gate connection structure 50b has a projection shape of a "C" or a mirrored "C" on the plane where the first active region is located. The plane where the first active region is located is the XOY plane shown in the accompanying drawings. In this way, when the total area of ​​the layout structure of the semiconductor device is constant, the projection shape of the third gate 503 on the plane where the first active region is located is a "I" shape. Compared with the C-shaped projection shape of the third gate 503 on the plane where the first active region is located, the size of the second gate and / or the third gate in the Y-axis direction can be increased, thereby increasing the size of the second active region in the Y-axis direction, thereby increasing the size of the channel in the Y-axis direction, thereby improving the hot carrier effect, reducing the subthreshold leakage current Ioff and the gate-induced drain leakage current, and improving the reliability of the semiconductor device. In addition, since the size of the channel in the Y-axis direction is increased, the process of forming a shallowly doped drain (LDD) region in the transistor can be omitted, thereby reducing the number of process steps and lowering the process cost.

[0094] In some embodiments, a size of the first gate along the first direction is greater than a size of the second gate along the first direction; a size of the second gate along the first direction is equal to a size of the third gate along the first direction.

[0095] Exemplary, reference Figure 6 The first gate has a size R1 along the Y-axis, the second gate has a size R2 along the Y-axis, and the third gate has a size R3 along the Y-axis, where R1>R2 and R2=R3. In some specific embodiments, R1=0.42 μm, R2=0.375 μm, and R3=0.375 μm.

[0096] In some other embodiments, the size of the first gate along the first direction is greater than the size of the second gate along the first direction; the size of the second gate along the first direction is greater than and equal to the size of the third gate along the first direction.

[0097] Exemplary, reference Figure 7 The first gate has a size R4 along the Y-axis, the second gate has a size R5 along the Y-axis, and the third gate has a size R6 along the Y-axis, where R4>R5>R6. In some specific embodiments, R4=0.416μm, R5=0.27μm, and R6=0.257μm.

[0098] It should be understood that the projection shape of the third gate 503 on the plane where the first active region is located is an "I"-shaped layout structure (refer to Figure 5 、 Figure 6 , at this time R1>R2, R2=R3), compared with the projection shape of the third gate 503 on the plane where the first active region is located, the layout structure is "C" shaped (reference Figure 7 , at this time R4>R5>R6), in some embodiments, the sizes of the second gate 502 and the third gate 503 along the first direction are significantly increased, for example, the size of the second gate along the Y-axis direction is increased from 0.27μm to 0.375μm, and the size of the third gate along the Y-axis direction is increased from 0.257μm to 0.375μm, wherein the size of the second gate along the Y-axis direction and the size of the third gate along the Y-axis direction are the same as the channel size of the transistor to which they belong. In other words, changing the projection shape of the third gate on the plane where the first active area is located from a "I" shape to a "C" shape can save the area of ​​the semiconductor device. In this way, the size of the second gate and / or the third gate along the first direction can be increased, thereby increasing the size of the second active area 402 corresponding to the second gate and / or the third gate along the first direction, thereby increasing the size of the channel corresponding to the second gate and / or the third gate along the first direction, thereby improving the hot carrier effect, reducing the subthreshold leakage current and the gate-induced drain leakage current, and improving the reliability of the semiconductor device.

[0099] In some embodiments, the first and second parts of the 2N second gates each include two directly connected second gates; the N third gates include two spaced-apart third gates; and both ends of the two directly connected second gates and both ends of the two spaced-apart third gates are substantially flush along the first direction.

[0100] Exemplary, reference Figure 5 , N=2, the first gate connection structure 50a includes four second gates, wherein the second gates of the first portion 502-1 include two second gates, and the second gates of the second portion 502-2 include two second gates, and the two second gates in each portion are directly connected. The two third gates 503-1 corresponding to the second gates of the first portion 502-1 are separated, that is, there is a gap between the two third gates, and the two third gates are not connected. Here, the ends of the two third gates 503-1 with the gap are substantially flush with the ends of the two directly connected second gates 502-1 along the Y-axis direction, as indicated by the dotted lines BB" and CC". Similarly, the two third gates 503-2 corresponding to the second gates of the second portion 502-2 are also separated, and the ends of the two third gates 503-2 with the gap are substantially flush with the ends of the two directly connected second gates 502-2 along the Y-axis direction, as indicated by the dotted lines DD" and EE".

[0101] In some embodiments, the projection shapes of the first gate on the plane where the first active area is located include a "U" shape or an inverted "U" shape; the 2N first gates in the layout structure of the semiconductor device include a third part and a fourth part; the third part is the N first gates close to the second gate, and the fourth part is the N first gates away from the second gate; the projection shapes of the first gates in the third part and the first gates in the fourth part on the plane where the first active area is located are different.

[0102] refer to Figure 5 、 Figure 8 , Figure 8 for Figure 5 The enlarged schematic diagram of the 2N first gates in the first gate connection structure 50a is shown, where N=2; wherein the 2N first gates include the third portion 501-1 and the fourth portion 501-2. The number of first gates in the third portion 501-1 and the fourth portion 501-2 can be the same, both N, where N is a positive integer. The projection shapes of the first gates in the third portion 501-1 and the first gates in the fourth portion 501-2 on the plane where the first active region is located are different. For example, refer to Figure 8 The projection of the first gate in the third portion 501-1 onto the plane where the first active region is located is an inverted U-shape, and the projection of the first gate in the fourth portion 501-2 onto the plane where the first active region is located is also a U-shape. In other examples, the projection of the first gate in the third portion 501-1 onto the plane where the first active region is located can be a U-shape, and the projection of the first gate in the fourth portion 501-2 onto the plane where the first active region is located can be an inverted U-shape.

[0103] In other embodiments, the projection shape of the first gate on the plane where the first active area is located may also include an "I" shape. In this case, the projection shapes of the first gate in the third part and the first gate in the fourth part on the plane where the first active area is located may be the same.

[0104] In some embodiments, a side line of the first gate in the third portion along the second direction is substantially flush with a side line of the second gate in the first portion along the second direction; a side line of the first gate in the fourth portion along the second direction is substantially flush with a side line of the second gate in the second portion along the second direction.

[0105] refer to Figure 5 、 Figure 9 , Figure 9 for Figure 5 The enlarged schematic diagram corresponding to the first gate connection structure 50a; Figure 9As can be seen, the first gate 501-1 in the third portion is along a side a1 in the X-axis direction, and the second gate 502-1 in the first portion is along a side a2 in the X-axis direction, and a1 and a2 are substantially aligned. The first gate 501-2 in the fourth portion is along a side a3 in the X-axis direction, and the second gate 502-2 in the second portion is along a side a4 in the X-axis direction, and a3 and a4 are substantially aligned.

[0106] In some embodiments, the distance between the N third gates and the corresponding N second gates of the first gate connection structure along the first direction is a third distance, and the distance between the N third gates and the corresponding N second gates of the second gate connection structure along the first direction is a fourth distance; the distance between the remaining N third gates and the corresponding N second gates of the adjacent gate connection structures in the two gate connection structures along the first direction is a fifth distance; the third distance is equal to the fourth distance; and the fourth distance is equal to the fifth distance.

[0107] refer to Figure 5 、 Figure 6 The distance between one of the first-part third gates 503-1 and one of the first-part second gates 502-1 of the first gate connection structure 50a along the Y-axis direction is a third distance S1, the distance between one of the first-part third gates 503-1 and one of the first-part second gates 502-1 of the second gate connection structure 50b along the Y-axis direction is a fourth distance S2, and the distance between one of the second-part third gates 503-2 and one of the second-part second gates 502-2 of the first gate connection structure 50a along the Y-axis direction is a fifth distance S3. Here, the third distance S1 = the fourth distance S2 = the fifth distance S3.

[0108] Based on this, the layout structure of the semiconductor device provided in the embodiment of the present disclosure includes multiple first active areas, two gate connection structures, and 2N third gates, wherein each gate connection structure includes 2N interconnected first gates and 2N second gates; wherein, by arranging N third gates between the two gate connection structures, and making the N third gates correspond to the N second gates of each of the two gate connection structures, and arranging the remaining N third gates on the side of one gate connection structure away from the other gate connection structure, and making the remaining N third gates correspond to the remaining N second gates in the adjacent gate connection structure; in this way, two adjacent gate connection structures can share a group of third gates, thereby reducing the number of third gates in the layout structure of the semiconductor device, reducing the area of ​​the semiconductor device, and improving the integration of the device; in addition, it can be understood that, when the total area of ​​the layout structure of the semiconductor device remains unchanged, by reducing the number of third gates, at least the size of the second gate and the remaining third gates can be increased, that is, the size of the channel in the transistor corresponding to the second gate and the third gate is increased, thereby improving the hot carrier effect, reducing the subthreshold leakage current and the gate-induced drain leakage current, and improving the reliability of the semiconductor device.

[0109] An embodiment of the present disclosure further provides an array structure of semiconductor devices, comprising: a layout structure of multiple semiconductor devices as described in the above embodiments of the present disclosure.

[0110] In some embodiments, the layout structures of the plurality of semiconductor devices are arranged along a first direction; and the structural arrangement of the layout structure of each semiconductor device in the layout structures of the plurality of semiconductor devices is the same.

[0111] Figure 10 FIG2 shows a partial schematic diagram of the array structure of the semiconductor device in the embodiment of the present disclosure. Figure 10 , the array structure 60 of semiconductor devices may include a plurality of ( Figure 10 5) layout structures 50 of semiconductor devices arranged along the Y-axis direction are shown. Each semiconductor device layout structure 50 includes a first gate connection structure 50a and a second gate connection structure 50b arranged along the Y-axis direction. The arrangement of the first gate connection structure 50a, the second gate connection structure 50b, and the third gate in each of the layout structures of the multiple semiconductor devices is the same. Here, the multiple first gate connection structures 50a and the second gate connection structures 50b in the array structure 60 of semiconductor devices are arranged at intervals. Here, the same arrangement can be understood as the positional relationship and size between the first gate connection structure, the second gate connection structure, and the third gate are the same, which is similar to copying the layout structure of a semiconductor device, and the layout structures of the multiple copied semiconductor devices are arranged in sequence along the first direction.

[0112] It should be noted that the layout structure of the semiconductor device may include a variety of arrangements, such as Figure 10 The first structure P1, second structure P2, third structure P3, and fourth structure P4 are shown in FIG. The first structure P1 and the second structure P2 are mirror-symmetrical; the third structure P3 and the fourth structure P4 are mirror-symmetrical. The layout structure of each semiconductor device in the aforementioned layout structure of multiple semiconductor devices is arranged in the same manner. It can be understood that the array structure of semiconductor devices includes multiple first structures P1 arranged along the first direction, or multiple second structures P2 arranged along the first direction, or multiple third structures P3 arranged along the first direction, or multiple fourth structures P4 arranged along the first direction.

[0113] In some embodiments, both ends of the layout structure of the plurality of semiconductor devices are substantially flush along the first direction. Figure 10 Both ends of the layout structure 50 of the three semiconductor devices are flush along the Y-axis direction, refer to the dotted lines FF" and GG".

[0114] An embodiment of the present disclosure also provides a layout structure of an integrated circuit, comprising: an array structure of one or more semiconductor devices as described in the above embodiments of the present disclosure; and a plurality of sub-word lines; each of the sub-word lines is connected to an active area corresponding to a first gate and an active area corresponding to a second gate in a gate connection structure through a first via.

[0115] Exemplary, reference Figure 11 The layout structure of the integrated circuit includes an array structure of semiconductor devices and multiple sub-wordlines SWL. Each sub-wordline is connected to a first gate 501 and a second gate 502 in a gate connection structure (50a or 50b) through a first via 601. Here, each first gate connection structure 50a or each second gate connection structure 50b includes four first gates and four second gates. Based on this, each first gate connection structure 50a or each second gate connection structure 50b can be connected to four sub-wordlines through the first vias 601. In other words, the layout structure 1100 of the integrated circuit includes eight sub-wordlines (such as SWL-1, SWL-2, SWL-3, SWL-4, SWL-5, SWL-6, SWL-7, and SWL-8). Each sub-wordline is connected to two first vias 601, and is respectively connected to a first gate 501 and a second gate 502 in a gate connection structure through the two first vias 601.

[0116] In some embodiments, the layout structure of the integrated circuit further comprises a plurality of main word lines; each of the main word lines is connected to all first gates and all second gates in one of the gate connection structures through a second via. Figure 11 , one main word line is connected to one gate connection structure, that is, one main word line passes through the second via hole ( Figure 11 The main word line (not shown) is connected to the four first gates and the four second gates in each first gate connection structure 50a or each second gate connection structure 50b. In other words, each main word line may include four sub-word lines (e.g., SWL-1, SWL-2, SWL-3, and SWL-4).

[0117] In some embodiments, the integrated circuit is a dynamic random access memory.

[0118] It should also be noted that, under different operating conditions, the sub-threshold leakage current and the gate-induced drain leakage current of the sub-word line driver formed by adopting the layout structure of the semiconductor device in the above embodiment of the present disclosure are reduced.

[0119] The scope of protection of the present disclosure is not limited to this. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A layout structure of a semiconductor device, characterized in that: include: A plurality of first active regions, all extending along a first direction; Two gate connection structures are arranged along the first direction, each of the gate connection structures includes 2N interconnected first gates and 2N second gates; the first gates correspond to the first active area; N is a positive integer; 2N third gates; wherein, N third gates are located between the two gate connection structures adjacent to each other along the first direction, and correspond to the N second gates of the two gate connection structures, and the devices corresponding to the N third gates are respectively electrically connected to the devices corresponding to the N second gates of the two adjacent gate connection structures; the remaining N third gates are located on a side of one gate connection structure away from the other gate connection structure, and correspond to the remaining N second gates of the one gate connection structure; the second gate and the third gate both extend along the second direction; the second direction is perpendicular to the first direction.

2. The layout structure of the semiconductor device according to claim 1, wherein: 2N first gates of each of the gate connection structures are physically connected; The 2N second gates of each gate connection structure are connected to one end of the 2N first gates; or the 2N second gates of each gate connection structure are connected to both ends of the plurality of first gates.

3. The layout structure of the semiconductor device according to claim 2, wherein: The two gate connection structures include a first gate connection structure and a second gate connection structure; The 2N second gates of the first gate connection structure and the second gate connection structure are all connected to one end of the 2N first gates of the corresponding gate connection structure; The 2N second gates of the first gate connection structure and the second gate connection structure each include a first portion and a second portion; the first portion is the N second gates close to the first gate, and the second portion is the N second gates away from the first gate; The distance between the first portion of the first gate connection structure and the first portion of the second gate connection structure along the first direction is a first distance; the distance between the second portion of the first gate connection structure and the second portion of the second gate connection structure along the first direction is a second distance.

4. The layout structure of the semiconductor device according to claim 3, wherein: The first distance is greater than the second distance; The N third gates are located between the first portion of the first gate connection structure and the first portion of the second gate connection structure; the remaining N third gates are located on one side of the second portion of the first gate connection structure or on one side of the second portion of the second gate connection structure.

5. The layout structure of the semiconductor device according to claim 3, wherein: The first distance is smaller than the second distance; The N third gates are located between the second portion of the first gate connection structure and the second portion of the second gate connection structure; the remaining N third gates are located on one side of the first portion of the first gate connection structure or on one side of the first portion of the second gate connection structure.

6. The layout structure of the semiconductor device according to claim 3, wherein: The first and second parts of the 2N second gates each include two directly connected second gates; the N third gates include two spaced-apart third gates; both ends of the two directly connected second gates and both ends of the two spaced-apart third gates are substantially flush along the first direction.

7. The layout structure of the semiconductor device according to claim 3, wherein: The projection shapes of the first gate on the plane where the first active area is located include a U-shape or an inverted U-shape; the 2N first gates include a third part and a fourth part; the third part is the N first gates close to the second gate, and the fourth part is the N first gates away from the second gate; the projection shapes of the first gates in the third part and the first gates in the fourth part on the plane where the first active area is located are different.

8. The layout structure of the semiconductor device according to claim 7, wherein: The projection shapes of the second gate and the third gate on the plane where the first active region is located are both rectangles.

9. The layout structure of the semiconductor device according to claim 8, wherein: A side line of the first gate in the third part along the second direction is substantially flush with a side line of the second gate in the first part along the second direction; a side line of the first gate in the fourth part along the second direction is substantially flush with a side line of the second gate in the second part along the second direction.

10. The layout structure of the semiconductor device according to claim 1, wherein: The distance between the N third gates and the corresponding N second gates of the first gate connection structure along the first direction is a third distance, and the distance between the N third gates and the corresponding N second gates of the second gate connection structure along the first direction is a fourth distance; The distance between the remaining N third gates and the corresponding N second gates of the adjacent gate connection structures in the two gate connection structures along the first direction is a fifth distance; The third distance is equal to the fourth distance; the fourth distance is equal to the fifth distance.

11. The layout structure of the semiconductor device according to claim 1, wherein: The size of the first gate along the first direction is greater than the size of the second gate along the first direction; A size of the second gate along the first direction is equal to a size of the third gate along the first direction.

12. The layout structure of the semiconductor device according to claim 1, wherein: The 2N first gates in the two gate connection structures are parallel and both ends thereof are substantially flush along the first direction; The 2N second gates in the two gate connection structures are parallel and both ends are substantially flush along the first direction.

13. The layout structure of the semiconductor device according to claim 1, wherein: The transistor corresponding to the first gate includes a PMOS transistor; the transistor corresponding to the second gate and the transistor corresponding to the third gate both include NMOS transistors.

14. The layout structure of the semiconductor device according to claim 1, wherein: The layout structure of the semiconductor device further includes a plurality of second active regions; the plurality of second active regions correspond to the second gate and the third gate.

15. An array structure of semiconductor devices, characterized in that: include: A layout structure of a plurality of semiconductor devices according to any one of claims 1 to 14.

16. The array structure of semiconductor devices according to claim 15, characterized in that: The layout structures of the plurality of semiconductor devices are arranged along a first direction; and the structural arrangement of the layout structure of each semiconductor device in the layout structures of the plurality of semiconductor devices is the same.

17. The array structure of semiconductor devices according to claim 16, wherein: Both ends of the layout structure of the plurality of semiconductor devices are substantially flush along the first direction.

18. A layout structure of an integrated circuit, characterized in that: include: An array structure of one or more semiconductor devices according to any one of claims 15 to 17; as well as a plurality of sub-word lines; Each of the sub-word lines is connected to an active region corresponding to a first gate and an active region corresponding to a second gate in a gate connection structure through a first via hole.

19. The layout structure of the integrated circuit according to claim 18, wherein: The layout structure of the integrated circuit further includes a plurality of main word lines; each of the main word lines is connected to all the first gates and all the second gates in one of the gate connection structures through a second via.

20. The layout structure of the integrated circuit according to claim 18, wherein: The integrated circuit is a dynamic random access memory.

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