Semiconductor structure and method for forming the same

Abstract

The present disclosure relates to a semiconductor structure and a method for forming the same. The semiconductor structure includes: a supporting substrate; an array structure located on the supporting substrate, including a plurality of active rows spaced apart along a first direction, each active row including a plurality of active columns spaced apart along a second direction, and the active columns in two adjacent active rows along the first direction are staggered; a first signal line structure located on the supporting substrate, including a plurality of first signal lines spaced apart along the first direction and extending along the second direction, each first signal line electrically connecting the active columns in two adjacent active rows; a second signal line structure located above the first signal line structure, including a plurality of second signal lines spaced apart along the second direction and extending along the first direction, each second signal line electrically connecting the plurality of active columns aligned along the first direction. The present disclosure simplifies the manufacturing process of the semiconductor structure and improves the performance of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers. It consists of multiple active pillars, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to a word line, the source is electrically connected to a bit line, and the drain is electrically connected to a capacitor. The word line voltage on the word line can control the on and off of the transistor, thereby allowing data stored in the capacitor to be read or written through the bit line.

[0003] To meet the demands of increasing storage density and shrinking active pillar size, the active pillars in semiconductor structures such as DRAM have evolved from a 6F2 structure to a 4F2 structure, where F represents the minimum feature size. However, the 4F2 structure presents significant challenges in forming signal lines (such as word lines or bit lines) due to the small size of the active pillars and the narrow spacing between adjacent active pillars. Furthermore, the capacitive coupling effect between adjacent signal lines is strong, limiting further improvements in semiconductor structure performance.

[0004] Therefore, how to improve the performance of semiconductor structures, increase the yield of semiconductor structures, and simplify the manufacturing process of semiconductor structures is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which are used to improve the performance of the semiconductor structure, increase the yield of the semiconductor structure, and simplify the manufacturing process of the semiconductor structure.

[0006] According to some embodiments, the present disclosure provides a semiconductor structure comprising:

[0007] a supporting substrate;

[0008] An array structure, located on the top surface of the support substrate, comprising a plurality of active rows spaced apart along a first direction, each of the active rows comprising a plurality of active pillars spaced apart along a second direction, the active pillars in two adjacent active rows along the first direction being staggered, the first direction and the second direction being parallel to the top surface of the support substrate, and intersecting the first direction;

[0009] a first signal line structure, located above the support substrate, comprising a plurality of first signal lines arranged at intervals along the first direction and extending along the second direction, each of the first signal lines electrically connecting the active pillars in two adjacent active rows along the first direction;

[0010] The second signal line structure is located above the first signal line structure and includes a plurality of second signal lines arranged at intervals along the second direction and extending along the first direction, each of the second signal lines being electrically connected to the plurality of active pillars aligned and arranged along the first direction.

[0011] In some embodiments, the plurality of active rows in the array structure are arranged in sequence along the first direction, the active pillars in the plurality of odd-numbered active rows are aligned and arranged along the first direction, and the active pillars in the plurality of even-numbered active rows are aligned and arranged along the first direction.

[0012] In some embodiments, the first signal line is a word line, the first signal line structure is a word line structure, the second signal line is a bit line, and the second signal line structure is a bit line structure.

[0013] In some embodiments, further comprising:

[0014] The first isolation layer is located between two word lines adjacent to each other along the first direction, and an air gap is formed in the first isolation layer.

[0015] In some embodiments, along a third direction, a top surface of the air gap is higher than a top surface of the word line, and a bottom surface of the air gap is lower than a bottom surface of the word line. The third direction is perpendicular to the top surface of the support substrate.

[0016] In some embodiments, the interval width between two active rows electrically connected to the same word line along the first direction is a first width, the width of the first isolation layer along the first direction is a second width, and the first width is smaller than the second width.

[0017] In some embodiments, the active pillar comprises:

[0018] channel area;

[0019] The source region and the drain region are distributed on opposite sides of the channel region along the third direction, the first signal line is distributed around the periphery of the channel region, the second signal line is electrically connected to the source region, and the third direction is perpendicular to the top surface of the supporting substrate.

[0020] In some embodiments, the first signal line is distributed around the entire periphery of the channel region; or,

[0021] A portion of the sidewall of the channel region is covered by the first signal line, and another portion of the sidewall of the channel region is directly covered by the first isolation layer.

[0022] In some embodiments, it further includes:

[0023] a capacitor contact structure extending along the third direction and electrically connected to the drain region;

[0024] A capacitor is electrically connected to the capacitor contact structure, and the active region and the capacitor are located on opposite sides of the capacitor contact structure along the third direction.

[0025] According to some other embodiments, the present disclosure further provides a method for forming a semiconductor structure, comprising the following steps:

[0026] forming an array structure, the array structure comprising a plurality of active rows spaced apart along a first direction, each of the active rows comprising a plurality of active pillars spaced apart along a second direction, the active pillars extending along a third direction, the active pillars in two adjacent active rows along the first direction being staggered, the first direction and the second direction both being perpendicular to the third direction, and the first direction intersecting the second direction;

[0027] forming a first signal line structure, the first signal line structure comprising a plurality of first signal lines spaced apart along the first direction and extending along the second direction, each of the first signal lines electrically connecting the active pillars in two adjacent active rows along the first direction;

[0028] A second signal line structure is formed above the first signal line structure, the second signal line structure including a plurality of second signal lines arranged at intervals along the second direction and extending along the first direction, each of the second signal lines being electrically connected to a plurality of the active pillars aligned and arranged along the first direction.

[0029] In some embodiments, the specific steps of forming the array structure include:

[0030] providing a growth substrate;

[0031] The growth substrate is etched to form the array structure, wherein the plurality of active rows in the array structure are sequentially arranged along the first direction, the active pillars in the plurality of odd-numbered active rows are aligned and arranged along the first direction, and the active pillars in the plurality of even-numbered active rows are aligned and arranged along the first direction.

[0032] In some embodiments, the active pillar includes a channel region, and a source region and a drain region distributed on opposite sides of the channel region along the third direction; the specific steps of forming the first signal line structure include:

[0033] forming a first dielectric layer on the remaining growth substrate, wherein the first dielectric layer continuously covers the source regions of all the active pillars in the array structure;

[0034] forming a word line material layer on the first dielectric layer, wherein the word line material layer is continuously distributed around the channel regions of all the active pillars in the array structure;

[0035] The word line material layer is etched to form a plurality of word line grooves extending along the second direction and arranged at intervals along the first direction, wherein the word line grooves separate the word line material layer into a plurality of word lines arranged at intervals along the first direction, and the word lines are used as the first signal lines, and the plurality of word lines arranged at intervals along the first direction are used as the first signal line structure.

[0036] In some embodiments, the specific steps of forming the word line material layer on the first dielectric layer include:

[0037] forming a gate dielectric layer on the first dielectric layer and surrounding the channel region and the drain region in the active pillar;

[0038] A word line material is deposited on the first dielectric layer to form the word line material layer which continuously covers the entire surface of the gate dielectric layer and surrounds the periphery of the channel region.

[0039] In some embodiments, before etching the word line material layer, the following steps are further included:

[0040] A plurality of capacitor contact structures are formed and electrically connected to the drain regions in the plurality of active pillars in a one-to-one correspondence.

[0041] In some embodiments, the specific steps of forming a plurality of capacitor contact structures electrically connected to the drain regions in the plurality of active pillars in a one-to-one correspondence include:

[0042] forming a second dielectric layer covering the word line material layer, wherein the top surface of the drain region is exposed to the surface of the second dielectric layer;

[0043] growing a first metal silicide material on the drain region to form a first metal silicide layer;

[0044] A first conductive contact layer is formed on the first metal silicide layer, and the first conductive contact layer and the first metal silicide layer serve together as the capacitor contact structure.

[0045] In some embodiments, the specific steps of forming a plurality of word line trenches extending along the second direction and spaced apart along the first direction include:

[0046] connecting the second dielectric layer and the supporting substrate;

[0047] removing the remaining growth substrate to expose the first dielectric layer;

[0048] The first dielectric layer and the word line material layer are etched to form the word line trench that penetrates the word line material layer and extends into the second dielectric layer.

[0049] In some embodiments, the specific steps of forming the word line trench penetrating the word line material layer and extending into the second dielectric layer include:

[0050] The first dielectric layer, the word line material layer and the gate dielectric layer are etched to form the word line trench, wherein the width of the word line trench along the first direction is greater than the spacing width of the two active rows electrically connected to the same word line along the first direction.

[0051] In some embodiments, after forming a plurality of word line trenches extending along the second direction and spaced apart along the first direction, the method further includes the following steps:

[0052] A dielectric material is filled in the word line trench to form a first isolation layer with an air gap.

[0053] In some embodiments, the specific steps of forming the second signal line structure include:

[0054] A plurality of bit lines extending along the first direction and spaced apart along the second direction are formed on the first dielectric layer, and the bit lines are used as the second signal lines, and the plurality of bit lines spaced apart along the second direction are used as the second signal line structure.

[0055] In some embodiments, the specific steps of forming a plurality of bit lines extending along the first direction and spaced apart along the second direction on the first dielectric layer include:

[0056] growing a second metal silicide material on the source region to form a plurality of bit line contact layers electrically connected one-to-one with the plurality of source regions in the plurality of active pillars;

[0057] A bit line conductive layer is formed to continuously cover the plurality of bit line contact layers spaced apart along the first direction, and the bit line contact layer and the bit line conductive layer are used together as the bit line.

[0058] Some embodiments of the present disclosure provide semiconductor structures and methods for forming them, electrically connecting all active pillars in two adjacent active rows via a first signal line. This, on the one hand, can increase the etching window when forming the first signal line, simplifying the manufacturing process of the semiconductor structure; on the other hand, it can increase the spacing between two adjacent first signal lines, thereby reducing the capacitive coupling effect between adjacent first signal lines, improving the performance of the semiconductor structure, and increasing the yield of the semiconductor structure. Some embodiments of the present disclosure use the method for forming a 6F2 array structure to form active pillars in a 4F2 array structure, which can further reduce the size of the semiconductor structure and increase the storage density of the semiconductor structure while improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Attachment Figure 1 is a schematic top view of a semiconductor structure in a specific embodiment of the present disclosure;

[0060] Attachment Figure 2 It is attached Figure 1 Schematic diagram of the cross section at the AA position;

[0061] Attachment Figure 3 It is attached Figure 1 Schematic diagram of the cross section at the mid-BB position;

[0062] Attachment Figure 4 It is attached Figure 1 Schematic diagram of the cross section at the mid-CC position;

[0063] Attachment Figure 5 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure;

[0064] Attachment Figure 6 -Attached Figure 30 It is a schematic diagram of the main process structure in the process of forming a semiconductor structure according to a specific embodiment of the present disclosure. DETAILED DESCRIPTION

[0065] The specific embodiments of the semiconductor structure and the method for forming the same provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0066] This embodiment provides a semiconductor structure. Figure 1 is a top view schematic diagram of a semiconductor structure in a specific embodiment of the present disclosure, Figure 2 It is attached Figure 1 Schematic diagram of the cross section at the AA position, attached Figure 3 It is attached Figure 1 Schematic diagram of the cross section of the BB position, attached Figure 4 It is attached Figure 1 Schematic diagram of the cross section at the CC position. Figures 1-4As shown, the semiconductor structure includes:

[0067] Support substrate 20;

[0068] An array structure, located on the top surface of the support substrate 20, includes a plurality of active rows 15 spaced apart along a first direction D1, each of the active rows 15 includes a plurality of active pillars 10 spaced apart along a second direction D2, the active pillars 10 in two adjacent active rows 15 along the first direction D1 being staggered, the first direction D1 and the second direction D2 being parallel to the top surface of the support substrate 20, and the first direction D1 intersecting the second direction D2;

[0069] a first signal line structure, located above the support substrate 20, comprising a plurality of first signal lines arranged at intervals along the first direction D1 and extending along the second direction D2, each of the first signal lines electrically connecting the active pillars 10 in two adjacent active rows 15 along the first direction D1;

[0070] The second signal line structure is located above the first signal line structure, and includes a plurality of second signal lines arranged at intervals along the second direction D2 and extending along the first direction D1, each of the second signal lines being electrically connected to the plurality of active pillars 10 aligned and arranged along the first direction D1.

[0071] The semiconductor structure described in this specific embodiment may be, but is not limited to, a DRAM. The following description will be made by taking the semiconductor structure being a DRAM as an example. The supporting substrate 20 may be, but is not limited to, a silicon substrate. The present specific embodiment will be described by taking the supporting substrate 20 being a silicon substrate as an example. In other embodiments, the supporting substrate 20 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI. The supporting substrate 20 is used to support the device structure above it. The array structure includes a plurality of active pillars 10 arranged at intervals along the first direction D1 and the second direction D2. The plurality of active pillars 10 arranged at intervals along the second direction D2 constitute an active row 15. The plurality of active rows 15 are arranged at intervals along the first direction D1. The staggered arrangement of the active pillars 10 in two adjacent active rows 15 along the first direction D1 means that, for two adjacent active rows 15 along the first direction D1, a projection of the active pillars 10 in one active row 15 in a plane formed by the intersection of the first direction D1 and a third direction D3 does not overlap or only partially overlaps with a projection of the active pillars 10 in the other active row 15 in a plane formed by the intersection of the first direction D1 and the third direction D3. The third direction D3 is perpendicular to the top surface of the support substrate 20.

[0072] In this embodiment, by staggering the active pillars 10 in two adjacent active rows 15 along the first direction D1, the facing area between the active pillars 10 in the two adjacent active rows 15 can be reduced, thereby reducing the capacitive coupling effect between the two adjacent active pillars 10 along the first direction D1, thereby improving the performance of the semiconductor structure. Furthermore, in this embodiment, a first signal line electrically connects the active pillars 10 in two adjacent active rows 15 along the first direction D1, thereby reducing the number of first signal lines within the semiconductor structure and increasing the spacing between adjacent first signal lines. This not only reduces the difficulty in forming the first signal lines but also reduces the capacitive coupling effect between adjacent first signal lines, thereby further improving the electrical performance of the semiconductor structure. Each second signal line electrically connects a plurality of active pillars 10 aligned along the first direction D1. That is, two adjacent active pillars 10 along the first direction D1 are each electrically connected to two second signal lines, thereby enabling addressing of the active pillars 10 via one first signal line and one second signal line.

[0073] In some embodiments, the plurality of active rows 15 in the array structure are arranged in sequence along the first direction D1, the active pillars in the plurality of odd-numbered active rows 15 are aligned and arranged along the first direction D1, and the active pillars in the plurality of even-numbered active rows 15 are aligned and arranged along the first direction D1.

[0074] For example, all the odd-numbered active rows 15 in the array structure are aligned along the first direction D1, and all the even-numbered active rows 15 are also aligned along the first direction D1. The active pillars 10 in the odd-numbered active rows 15 and the active pillars 10 in the adjacent even-numbered active rows 15 are staggered, so that all the active pillars 10 in the array structure are arranged in a hexagonal array, thereby further increasing the storage density of the semiconductor structure and contributing to further miniaturization of the size of the semiconductor structure.

[0075] In some embodiments, the first signal line is a word line 11, the first signal line structure is a word line structure, the second signal line is a bit line 14, and the second signal line structure is a bit line structure. In other embodiments, the first signal line is a bit line, the first signal line structure is a bit line structure, the second signal line is a word line, and the second signal line structure is a word line structure.

[0076] In some embodiments, the semiconductor structure further comprises:

[0077] The first isolation layer 12 is located between two adjacent word lines 11 along the first direction D1. The first isolation layer 12 has an air gap 22 therein, thereby utilizing the low dielectric constant of air to further enhance the electrical isolation between adjacent word lines 11. In one example, the material of the first isolation layer 12 can be an oxide material (e.g., silicon dioxide).

[0078] In order to further enhance the electrical isolation effect between adjacent word lines 11, in some embodiments, along the third direction D3, the top surface of the air gap 22 is higher than the top surface of the word line 11, and the bottom surface of the air gap 22 is lower than the bottom surface of the word line 11, and the third direction D3 is perpendicular to the top surface of the supporting substrate 20.

[0079] In some embodiments, the spacing width between the two active rows 15 electrically connected to the same word line 11 along the first direction D1 is a first width, the width of the first isolation layer 12 along the first direction D1 is a second width, and the first width is smaller than the second width to increase the distance between the two adjacent word lines 11 along the first direction D1.

[0080] In some embodiments, the active pillar comprises:

[0081] channel area;

[0082] The source region and the drain region are distributed on opposite sides of the channel region along the third direction D3, the first signal line is distributed around the periphery of the channel region, the second signal line is electrically connected to the source region, and the third direction D3 is perpendicular to the top surface of the supporting substrate 20.

[0083] In some embodiments, the first signal line is distributed around the entire periphery of the channel region to enhance the control performance of the first signal line on the active pillar; or,

[0084] A portion of the sidewall of the channel region is covered with the first signal line, and another portion of the sidewall of the channel region is directly covered with the first isolation layer 12 , so as to further increase the interval width between adjacent first signal lines.

[0085] In some embodiments, the semiconductor structure further comprises:

[0086] a capacitor contact structure extending along the third direction D3 and electrically connected to the drain region;

[0087] A capacitor is electrically connected to the capacitor contact structure, and the active region and the capacitor are located on opposite sides of the capacitor contact structure along the third direction D3.

[0088] Specifically, if Figures 1-4As shown, the top surface of the supporting substrate 20 includes a plurality of the capacitor contact structures electrically connected to the plurality of active pillars 10 in a one-to-one correspondence. The capacitor contact structure includes a first conductive contact layer 26 located on the supporting substrate 20, and a first metal silicide layer 25 located on the first conductive contact layer 26. One end of the first metal silicide layer 25 is in contact and electrically connected with the first conductive contact layer 26, and the other end is in contact and electrically connected with the drain region in the active pillar 10, thereby reducing the contact resistance between the capacitor and the drain region. In one example, the material of the first conductive contact layer 26 can be a metal material such as metal tungsten, and the material of the first metal silicide layer 25 is cobalt silicon. The second dielectric layer 21 covers the surface of the capacitor contact structure and the top surface of the supporting substrate 20. In one example, the material of the second dielectric layer 21 can be a nitride material, such as silicon nitride. The gate dielectric layer 13 is distributed at least around the periphery of the channel region in the active pillar 10, and the word line 11 (i.e., the first signal line) covers the surface of the gate dielectric layer 13, thereby forming a GAA (Gate-All-Around) structure. The first dielectric layer 27 covers the surface of the gate dielectric layer 13 and the word line 11. In one example, the material of the first dielectric layer 27 can be an oxide material (e.g., silicon dioxide). The bit line 14 (i.e., the second signal line) includes a bit line contact layer 23 that is electrically connected to the source region in the active pillar 10, and a bit line conductive layer 24 located on the bit line contact layer 23 and electrically connected to the bit line contact layer 23, so as to reduce the contact resistance between the source region and the bit line. In one example, the material of the bit line contact layer 23 can be a metal silicide material (e.g., cobalt silicon), and the material of the bit line conductive layer 24 can be a metal material (e.g., metal tungsten).

[0089] This embodiment also provides a method for forming a semiconductor structure. Figure 5 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure, Figure 6 -Attached Figure 30 This is a schematic diagram of the main process structure in the process of forming a semiconductor structure in the specific embodiment of the present disclosure. The schematic diagram of the semiconductor structure formed in this specific embodiment can be found in Figures 1-4 .like Figure 1-Figure 30 As shown, the method for forming the semiconductor structure includes the following steps:

[0090] Step S51: forming an array structure, the array structure comprising a plurality of active rows 61 spaced apart along a first direction D1, each of the active rows 61 comprising a plurality of active pillars 10 spaced apart along a second direction D2, the active pillars 10 extending along a third direction D3, the active pillars 10 in two adjacent active rows 61 along the first direction D1 being staggered, the first direction D1 and the second direction D2 being perpendicular to the third direction D3, and the first direction D1 intersecting the second direction D2, as shown in FIG. Figure 6 and Figure 7 As shown, wherein the Figure 6 is a top view schematic diagram of the array structure (the mask layer is not shown), Figure 7 yes Figure 6 Schematic cross-sectional view of the DD position (showing the mask layer);

[0091] Step S52: forming a first signal line structure, the first signal line structure including a plurality of first signal lines arranged at intervals along the first direction D1 and extending along the second direction D2, each of the first signal lines electrically connecting the active pillars 10 in two adjacent active rows 61 along the first direction D1;

[0092] In step S53, a second signal line structure is formed above the first signal line structure, wherein the second signal line structure includes a plurality of second signal lines arranged at intervals along the second direction D2 and extending along the first direction D1, and each of the second signal lines is electrically connected to the plurality of active pillars 10 aligned and arranged along the first direction D1.

[0093] In some embodiments, the specific steps of forming the array structure include:

[0094] Providing a growth substrate 60;

[0095] The growth substrate 60 is etched to form the array structure, wherein the plurality of active rows 61 in the array structure are sequentially arranged along the first direction D1, the active pillars 10 in the plurality of odd-numbered active rows 61 are aligned and arranged along the first direction D1, and the active pillars 10 in the plurality of even-numbered active rows 61 are aligned and arranged along the first direction D1.

[0096] Specifically, a first mask layer 70 and a second mask layer 71 located above the first mask layer 70 are sequentially deposited on the growth substrate 60, and the first mask layer 70 and the second mask layer 71 are used together as the mask layer for forming the array structure. Then, the first mask layer 70 and the second mask layer 71 are patterned to form a first etching window exposing the growth substrate 60. In one example, the material of the first mask layer 70 can be an oxide material (such as silicon dioxide), and the material of the second mask layer 71 is a polysilicon material. The growth substrate 60 is etched downward along the first etching window to form a plurality of first grooves 72 that do not penetrate the growth substrate 60 along the third direction D3. The plurality of first grooves 72 separate the growth substrate 60 into a plurality of active pillars 10, such as Figure 6 and Figure 7 As shown. A plurality of active pillars 10 arranged at intervals along the second direction D2 form an active row 61. The active pillars 10 in the odd-numbered active rows 61 are aligned along the first direction D1, and the active pillars 10 in the even-numbered active rows 61 are aligned along the first direction D1, so that all the active pillars 10 in the array structure are arranged in a hexagonal array, thereby further increasing the storage density of the semiconductor structure and facilitating further miniaturization of the semiconductor structure.

[0097] In some embodiments, the active pillar 10 includes a channel region, and a source region and a drain region distributed on opposite sides of the channel region along the third direction; the specific steps of forming the first signal line structure include:

[0098] A first dielectric layer 27 is formed on the remaining growth substrate 60. The first dielectric layer 27 continuously covers the source regions of all the active pillars 10 in the array structure. Figure 9 As shown;

[0099] A word line material layer 110 is formed on the first dielectric layer 27. The word line material layer 110 is continuously distributed around the channel regions of all the active pillars 10 in the array structure. Figure 12 and Figure 13 As shown, Figure 13 is a schematic top view after the word line material layer 110 is formed (the mask layer is not shown). Figure 12 yes Figure 13 Schematic cross-sectional view of the DD position (showing the mask layer);

[0100] The word line material layer 110 is etched to form a plurality of word line trenches 260 extending along the second direction D2 and arranged at intervals along the first direction D1. The word line trenches 260 separate the word line material layer 110 into a plurality of word lines 11 arranged at intervals along the first direction D1, and the word lines 11 are used as the first signal lines, and the plurality of word lines 11 arranged at intervals along the first direction D1 are used as the first signal line structure. Figure 26 shown.

[0101] In some embodiments, the specific steps of forming the word line material layer 110 on the first dielectric layer 27 include:

[0102] A gate dielectric layer 13 is formed on the first dielectric layer 27 and is distributed around the channel region and the drain region in the active pillar 10. Figure 10 As shown;

[0103] The word line material is deposited on the first dielectric layer 27 to form the word line material layer 110 that continuously covers the entire surface of the gate dielectric layer 13 and surrounds the periphery of the channel region. Figure 12 and Figure 13 shown.

[0104] Specifically, after forming the array structure, an oxide material such as silicon dioxide is deposited on the remaining growth substrate 60 to form the first dielectric layer 27. Figure 8 The first dielectric layer 27 is etched back so that the top surface of the remaining first dielectric layer 27 after etching is lower than the bottom surface of the channel region in the active pillar 10, as shown. Figure 9 Next, a thermal oxidation process or an in-situ water vapor generation process is used to form the gate dielectric layer 13 covering the sidewalls of the active pillar 10 exposed above the first dielectric layer 27 and the sidewalls of the second mask layer 71, as shown. Figure 10 Afterwards, a word line material such as metal tungsten is deposited on the first dielectric layer 27 to form the word line material layer 110 that continuously covers the first dielectric layer 27, the plurality of gate dielectric layers 13 and the top surface of the second mask layer 71, as shown. Figure 11 The word line material layer 110 is etched back so that the top surface of the word line material layer 110 is lower than the top surface of the active pillar 10, as shown. Figure 12 and Figure 13 In one example, the top surface of the word line material layer 110 remaining after etching back is flush with the top surface of the channel region in the active pillar 10. Then, a dielectric material such as silicon nitride is deposited on the word line material layer 110 to form the second dielectric layer 21, as shown in FIG. Figure 14 As shown, the word line material layer 110 is prevented from being affected by the external environment.

[0105] In some embodiments, before etching the word line material layer 110 , the following steps are further included:

[0106] A plurality of capacitor contact structures are formed and electrically connected to the drain regions in the plurality of active pillars 10 in a one-to-one correspondence.

[0107] In some embodiments, the specific steps of forming a plurality of capacitor contact structures electrically connected to the drain regions in the plurality of active pillars 10 in a one-to-one correspondence include:

[0108] A second dielectric layer 21 is formed to cover the word line material layer 110, and the top surface of the drain region is exposed to the surface of the second dielectric layer 21. Figure 16 As shown;

[0109] A first metal silicide material is grown on the drain region to form a first metal silicide layer 25, such as Figure 18 As shown;

[0110] A first conductive contact layer 26 is formed on the first metal silicide layer 25, and the first conductive contact layer 26 and the first metal silicide layer 25 serve together as the capacitor contact structure. Figure 20 and Figure 21 As shown, Figure 21 is a schematic top view after the capacitor contact structure is formed, Figure 20 yes Figure 21 Schematic cross-section of the middle DD position.

[0111] Specifically, after forming the second dielectric layer 21, a planarization process such as chemical mechanical polishing is used to remove the second mask layer 71, part of the gate dielectric layer 13 and part of the second dielectric layer 21 to expose the first mask layer 70. Figure 15 Afterwards, the second mask layer 71 is removed to form a second trench 160 exposing the drain region in the active pillar 10, as shown. Figure 16 In one example, during the process of removing the second mask layer 71, a portion of the second dielectric layer 21 is also removed to increase the width of the second trench 160 for subsequently forming the capacitor contact structure, thereby further simplifying the manufacturing process of the semiconductor structure. A metal material such as metal cobalt is deposited in the second trench 160 to form a first metal layer 170, as shown in FIG. Figure 17 Afterwards, the active pillar 10 and the first metal layer 170 are heat-treated, and the excess first metal layer 170 is removed to form the first metal silicide layer 25 and the third trench 180 located above the first metal silicide layer 25, as shown. Figure 18Afterwards, a conductive material such as metal tungsten is deposited in the third trench 180 to form an initial first conductive contact layer 190, as shown. Figure 19 The initial first conductive contact layer 190 is etched back to remove the initial first conductive contact layer 190 covering the top surface of the second dielectric layer 21, and the remaining initial first conductive contact layer 190 is used as the first conductive contact layer 26, as shown. Figure 20 shown.

[0112] In some embodiments, the specific steps of forming a plurality of word line trenches 260 extending along the second direction D2 and spaced apart along the first direction D1 include:

[0113] connecting the second dielectric layer 21 and the supporting substrate 20;

[0114] removing the remaining growth substrate 60 to expose the first dielectric layer 27;

[0115] The first dielectric layer 27 and the word line material layer 110 are etched to form the word line trench 260 penetrating the word line material layer 110 and extending into the interior of the second dielectric layer 21. Figure 26 shown.

[0116] In some embodiments, the specific steps of forming the word line trench 260 penetrating the word line material layer 110 and extending into the second dielectric layer 21 include:

[0117] The first dielectric layer 27, the word line material layer 110 and the gate dielectric layer 13 are etched to form the word line trench 260, and the width of the word line trench 260 along the first direction D1 is greater than the spacing width of the two active rows 61 electrically connected to the same word line 11 along the first direction D1.

[0118] In one example, after forming the capacitor contact structure, the second dielectric layer 21 and the support substrate 20 are bonded to form a bonding structure, such as Figure 22 Afterwards, the bonding structure is flipped, as shown in Figure 23 The remaining growth substrate 60 is removed by chemical mechanical polishing or other processes to expose the first dielectric layer 27, as shown. Figure 24 Next, a third mask layer 250 is formed on the first dielectric layer 27, and the third mask layer 250 has a second etching window 251 exposing the first dielectric layer 27, as shown. Figure 25The first dielectric layer 27, the word line material layer 110, the gate dielectric layer 13 and the second dielectric layer 21 are etched downward in a self-aligned manner along the second etching window 251 to form the word line trench 260. The plurality of word line trenches 260 separate the word line material layer 110 into a plurality of independent word lines 11, as shown. Figure 26 shown.

[0119] In another example, in order to further simplify the process of the semiconductor structure, after forming the capacitor contact structure, it is necessary to first form a plurality of capacitors corresponding to the plurality of capacitor contacts and a capacitor connection line corresponding to the plurality of capacitors, one end of the capacitor connection line being electrically connected to the capacitor contact structure and the other end being electrically connected to the capacitor. Next, a covering layer is formed covering the capacitor connection line, the capacitor, and the second dielectric layer 21. Then, the covering layer and the supporting substrate 20 are bonded to form a bonding structure. Thereafter, the bonding structure is flipped over, and the word line trench 260 is formed by an etching process.

[0120] In some embodiments, after forming a plurality of word line trenches 260 extending along the second direction D2 and spaced apart along the first direction D1, the following steps are further included:

[0121] Fill the word line trench 260 with dielectric material to form a first isolation layer 12 with an air gap 22. Figure 27 and Figure 28 As shown, Figure 27 is a schematic top view after the first isolation layer 12 is formed, Figure 28 yes Figure 27 Schematic diagram of the cross section at the mid-BB position.

[0122] In some embodiments, the specific steps of forming the second signal line structure include:

[0123] A plurality of bit lines 14 extending along the first direction D1 and spaced apart along the second direction D2 are formed on the first dielectric layer 27 , and the bit lines 14 serve as the second signal lines, and the plurality of bit lines 14 spaced apart along the second direction D2 serve as the second signal line structure.

[0124] In some embodiments, the specific steps of forming a plurality of bit lines 14 extending along the first direction D1 and spaced apart along the second direction D2 on the first dielectric layer 27 include:

[0125] Growing a second metal silicide material on the source region to form a plurality of bit line contact layers 23 electrically connected to the plurality of source regions in the plurality of active pillars 10 one by one;

[0126] A bit line conductive layer 24 is formed to continuously cover the plurality of bit line contact layers 23 spaced apart along the first direction D1, and the bit line contact layer 23 and the bit line conductive layer 24 are used together as the bit line 14. Figures 1-4 shown.

[0127] Specifically, after forming the first isolation layer 12, metal silicon is deposited on the first dielectric layer 27 to form the second metal layer 290 in contact with the active pillar 10. Figure 29 Afterwards, the second metal layer 290 and the active pillar 10 are heat-treated to form the bit line contact layer 23, and after removing the excess second metal layer 290, the result is as shown below. Figure 30 The structure shown. In one example, the material of the second metal layer 290 is cobalt, and the material of the bit line contact layer 23 is cobaltized silicon. Subsequently, a conductive material such as tungsten is deposited on the bit line contact layer 23 to form the bit line conductive layer 24 that continuously covers the plurality of bit line contact layers 23 spaced apart along the first direction D1. In one example, the material of the bit line conductive layer 24 is a metal material such as tungsten.

[0128] This embodiment is described by taking the first signal line as a word line and the second signal line as a bit line as an example. In other embodiments, the first signal line may also be a bit line, and correspondingly, the second signal line may be a word line.

[0129] Some embodiments of this specific embodiment provide semiconductor structures and methods for forming them, electrically connecting all active pillars in two adjacent active rows via a first signal line. This, on the one hand, can increase the etching window when forming the first signal line, simplifying the manufacturing process of the semiconductor structure; on the other hand, it can increase the spacing between two adjacent first signal lines, thereby reducing the capacitive coupling effect between adjacent first signal lines, improving the performance of the semiconductor structure, and increasing the yield of the semiconductor structure. Some embodiments of this specific embodiment utilize the method for forming a 6F2 array structure to form active pillars in a 4F2 array structure, which can further reduce the size of the semiconductor structure and increase the storage density of the semiconductor structure while improving the performance of the semiconductor structure.

[0130] The above is only a preferred embodiment of the present disclosure. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: a supporting substrate; An array structure, located on the top surface of the support substrate, comprising a plurality of active rows spaced apart along a first direction, each of the active rows comprising a plurality of active pillars spaced apart along a second direction, the active pillars in two adjacent active rows along the first direction being staggered, the first direction and the second direction being parallel to the top surface of the support substrate, and intersecting the first direction; a first signal line structure, located above the supporting substrate, comprising a plurality of first signal lines arranged at intervals along the first direction and extending along the second direction, each of the first signal lines electrically connecting the active pillars in two adjacent active rows along the first direction; a second signal line structure, located above the first signal line structure, comprising a plurality of second signal lines arranged at intervals along the second direction and extending along the first direction, each of the second signal lines being electrically connected to a plurality of the active pillars aligned and arranged along the first direction; The first signal line is a word line, and the first signal line structure is a word line structure; the second signal line is a bit line, and the second signal line structure is a bit line structure; a first isolation layer, located between two adjacent word lines along the first direction, wherein the first isolation layer has an air gap; The interval width between the two active rows electrically connected to the same word line along the first direction is a first width, the width of the first isolation layer along the first direction is a second width, and the first width is smaller than the second width.

2. The semiconductor structure according to claim 1, wherein: The multiple active rows in the array structure are arranged in sequence along the first direction, the active pillars in the multiple odd-numbered active rows are aligned and arranged along the first direction, and the active pillars in the multiple even-numbered active rows are aligned and arranged along the first direction.

3. The semiconductor structure according to claim 1, wherein: In a third direction, a top surface of the air gap is higher than a top surface of the word line, and a bottom surface of the air gap is lower than a bottom surface of the word line. The third direction is perpendicular to the top surface of the support substrate.

4. The semiconductor structure according to claim 1, wherein: The active pillar comprises: channel area; The source region and the drain region are distributed on opposite sides of the channel region along a third direction, the first signal line is distributed around the periphery of the channel region, the second signal line is electrically connected to the source region, and the third direction is perpendicular to the top surface of the supporting substrate.

5. The semiconductor structure according to claim 4, wherein: The first signal line is distributed around the entire periphery of the channel region; or, A portion of the sidewall of the channel region is covered by the first signal line, and another portion of the sidewall of the channel region is directly covered by the first isolation layer.

6. A method for forming a semiconductor structure, characterized in that: The steps include: forming an array structure, the array structure comprising a plurality of active rows spaced apart along a first direction, each of the active rows comprising a plurality of active pillars spaced apart along a second direction, the active pillars extending along a third direction, the active pillars in two adjacent active rows along the first direction being staggered, the first direction and the second direction both being perpendicular to the third direction, and the first direction intersecting the second direction; forming a first signal line structure, the first signal line structure comprising a plurality of first signal lines spaced apart along the first direction and extending along the second direction, each of the first signal lines electrically connecting the active pillars in two adjacent active rows along the first direction; forming a second signal line structure located above the first signal line structure, the second signal line structure comprising a plurality of second signal lines arranged at intervals along the second direction and extending along the first direction, each of the second signal lines being electrically connected to a plurality of the active pillars aligned and arranged along the first direction; The first signal line is a word line, and the first signal line structure is a word line structure; the second signal line is a bit line, and the second signal line structure is a bit line structure; forming a first isolation layer, wherein the first isolation layer is located between two word lines adjacent to each other along the first direction, and an air gap is formed in the first isolation layer; The interval width between the two active rows electrically connected to the same word line along the first direction is a first width, the width of the first isolation layer along the first direction is a second width, and the first width is smaller than the second width.

7. The method for forming a semiconductor structure according to claim 6, wherein: The specific steps of forming the array structure include: providing a growth substrate; The growth substrate is etched to form the array structure, wherein the plurality of active rows in the array structure are sequentially arranged along the first direction, the active pillars in the plurality of odd-numbered active rows are aligned and arranged along the first direction, and the active pillars in the plurality of even-numbered active rows are aligned and arranged along the first direction.

8. The method for forming a semiconductor structure according to claim 7, wherein: The active pillar includes a channel region, and a source region and a drain region distributed on opposite sides of the channel region along the third direction; the specific steps of forming the first signal line structure include: forming a first dielectric layer on the remaining growth substrate, wherein the first dielectric layer continuously covers the source regions of all the active pillars in the array structure; forming a word line material layer on the first dielectric layer, wherein the word line material layer is continuously distributed around the channel regions of all the active pillars in the array structure; The word line material layer is etched to form a plurality of word line grooves extending along the second direction and arranged at intervals along the first direction, wherein the word line grooves separate the word line material layer into a plurality of word lines arranged at intervals along the first direction, and the word lines are used as the first signal lines, and the plurality of word lines arranged at intervals along the first direction are used as the first signal line structure.

9. The method for forming a semiconductor structure according to claim 8, wherein: The specific steps of forming a word line material layer on the first dielectric layer include: forming a gate dielectric layer on the first dielectric layer and surrounding the channel region and the drain region in the active pillar; A word line material is deposited on the first dielectric layer to form the word line material layer which continuously covers the entire surface of the gate dielectric layer and surrounds the periphery of the channel region.

10. The method for forming a semiconductor structure according to claim 9, wherein: Before etching the word line material layer, the method further includes the following steps: forming a second dielectric layer covering the word line material layer, wherein the top surface of the drain region is exposed to the surface of the second dielectric layer; growing a first metal silicide material on the drain region to form a first metal silicide layer; A first conductive contact layer is formed on the first metal silicide layer, and the first conductive contact layer and the first metal silicide layer serve together as a capacitor contact structure.

11. The method for forming a semiconductor structure according to claim 10, wherein: The specific steps of forming a plurality of word line trenches extending along the second direction and spaced apart along the first direction include: connecting the second dielectric layer and the supporting substrate; removing the remaining growth substrate to expose the first dielectric layer; The first dielectric layer, the word line material layer, and the gate dielectric layer are etched to form the word line trench, wherein the width of the word line trench along the first direction is greater than the spacing width along the first direction between the two active rows electrically connected to the same word line, thereby forming the word line trench that penetrates the word line material layer and extends into the interior of the second dielectric layer.

12. The method for forming a semiconductor structure according to claim 9, wherein: After forming a plurality of word line trenches extending along the second direction and spaced apart along the first direction, the method further includes the following steps: A dielectric material is filled in the word line trench to form a first isolation layer with an air gap.

13. The method for forming a semiconductor structure according to claim 12, wherein: The specific steps of forming the second signal line structure include: growing a second metal silicide material on the source region to form a plurality of bit line contact layers electrically connected one-to-one with the plurality of source regions in the plurality of active pillars; A bit line conductive layer is formed to continuously cover the plurality of bit line contact layers arranged at intervals along the first direction, the bit line contact layer and the bit line conductive layer are used together as the bit line, the bit line is used as the second signal line, and the plurality of bit lines arranged at intervals along the second direction are used as the second signal line structure.

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